Uniform voltage drop across an array of memory devices

Abstract

An array of PCM devices and techniques for their fabrication are provided, each having an integrated resistor formed during heater patterning to equalize voltage drops across the PCM device. The PCM device includes at least one PCM cell containing a phase change material disposed over a heater and at least one resistor in series with the at least one PCM cell, the at least one resistor comprising the same combination of materials as the heater. Methods for forming the memory array and the PCM device are also provided.

Description

[Technical Field]

[0001] The present invention relates to arrays of memory devices, such as phase change memory (PCM) devices, and more particularly to arrays of PCM devices having integrated resistors formed during heater patterning to equalize voltage drops across the PCM devices, and techniques for their fabrication. [Background technology]

[0002] Chalcogenides are an emerging class of electronic materials that exhibit switching, memory, logic, and processing functions. One type of chalcogenide memory device utilizes the wide range of resistance values available in the active chalcogenide material as the principle of memory operation; each resistance value corresponds to a different structural state of the chalcogenide material. One or more states can be selected and used to define an operational memory state.

[0003] Chalcogenide materials exhibit crystalline states or phases as well as amorphous states or phases. Different structural states of chalcogenide materials differ in the relative proportions of crystalline and amorphous phases in a given volume or region of the chalcogenide material. A range of resistivity values is defined by the SET and RESET states of the chalcogenide material. The SET state is a low-resistivity structural state whose electrical properties are primarily dominated by the crystalline portion of the chalcogenide material. The RESET state is a high-resistivity structural state whose electrical properties are primarily dominated by the amorphous portion of the chalcogenide material.

[0004] Chalcogenide memory devices can be implemented in arrays of resistive memory cells. However, as these memory cell arrays grow larger, there can be a large difference between the line resistance of the first memory cell and the line resistance of the last memory cell. This resistance difference can lead to a large voltage drop across the memory cells, affecting read and write performance.

[0005] Therefore, techniques for achieving uniform voltage drops across a crossbar array of memory cells are desirable. Summary of the Invention

[0006] The present invention provides an array of PCM devices and techniques for their fabrication that have integrated resistors formed during heater patterning to equalize voltage drops across the PCM devices. In one aspect of the invention, a PCM device is provided that includes at least one PCM cell comprising a phase change material disposed on a heater, and at least one resistor in series with the at least one PCM cell, the at least one resistor comprising the same combination of materials as the heater.

[0007] In another aspect of the present invention, a memory array is provided, the memory array including a first set of metal lines, a second set of metal lines, and PCM devices between the first set of metal lines and the second set of metal lines, each of the PCM devices including a PCM cell including a phase change material disposed on a heater and a resistor in series with the PCM cell, the resistor including the same combination of heater and material, and the PCM cell is at an intersection of the first set of metal lines and the second set of metal lines.

[0008] In yet another aspect of the present invention, a method of forming a PCM device is provided, the method including simultaneously forming a heater and a resistor on a bottom electrode from the same combination of materials, forming a phase change material on the heater, and forming a top electrode on the phase change material, wherein the bottom electrode, heater, phase change material, and top electrode form a PCM cell.

[0009] A more complete understanding of the present invention, as well as further features and advantages of the present invention, will be obtained by reference to the following detailed description and drawings. [Brief explanation of the drawings]

[0010] [Figure 1] 1 illustrates a memory array of phase change memory (PCM) devices, each PCM device including a PCM cell and an integrated series resistor according to one embodiment of the present invention. [Figure 2] 1 is a cross-sectional view illustrating an exemplary PCM cell according to one embodiment of the present invention. [Figure 3] FIG. 2 is a top-down diagram illustrating an exemplary integrated series resistor according to one embodiment of the present invention. [Figure 4] FIG. 1 is a cross-sectional view illustrating a first metal layer Mx including a first metal line in an interlayer dielectric (ILD) formed on a substrate, at least one bottom electrode formed in a second ILD above the first metal line, and a lithography stack including a hardmask layer, an organic planarizing layer (OPL), an antireflective coating (ARC), and a patterned photoresist formed on the second ILD, in accordance with one embodiment of the present invention. [Figure 5] FIG. 1 is a top-down view illustrating patterned photoresist, where the photoresist is patterned with the footprints and locations of the heater and integrated series resistor, according to one embodiment of the present invention. [Figure 6] 1A-1C are cross-sectional views illustrating a pattern transferred from a patterned photoresist to a hard mask layer according to one embodiment of the present invention. [Figure 7]FIG. 1 is a top-down view illustrating a hard mask layer including a (first) pattern corresponding to the footprint and location of a heater and a (second) pattern corresponding to the footprint and location of an integrated series resistor, according to one embodiment of the present invention. [Figure 8] 1A-1C are cross-sectional views illustrating the same combination of materials, alternating layers of a first material and a second material, deposited simultaneously in a first pattern and a second pattern, according to one embodiment of the present invention. [Figure 9] FIG. 2 is a cross-sectional view illustrating a layer of first material and a layer of second material polished to form a heater and an integrated series resistor according to one embodiment of the present invention. [Figure 10] FIG. 10 is a top down view illustrating a defined heater and integrated series resistor according to one embodiment of the present invention. [Figure 11] FIG. 1 is a cross-sectional view illustrating a phase change material layer deposited on a hard mask layer, a top electrode layer deposited on the phase change material layer, and a (second) hard mask layer deposited on the top electrode layer, in accordance with one embodiment of the present invention. [Figure 12] 3A-3C are cross-sectional views illustrating a second hard mask layer, a top electrode layer, and a phase change material layer patterned to form a PCM cell, according to one embodiment of the present invention. [Figure 13] FIG. 1 is a top-down view illustrating a PCM cell above a heater and an integrated series resistor adjacent to the PCM cell, according to one embodiment of the present invention. [Figure 14] 1 is a cross-sectional view illustrating a conformal encapsulation layer deposited over a PCM cell and an integrated series resistor according to one embodiment of the present invention. [Figure 15] FIG. 10 is a cross-sectional view illustrating a third ILD deposited on an encapsulation layer embedding a PCM cell and an integrated series resistor, according to one embodiment of the present invention. [Figure 16]FIG. 10 is a cross-sectional view illustrating a first interconnect and a second interconnect of a second metal layer Mx+1 formed in a third ILD, whereby the first interconnect connects a PCM cell to an integrated series resistor and the second interconnect functions to contact an opposite end of the integrated series resistor and interconnect the integrated series resistor to a second metal line, according to one embodiment of the present invention. [Figure 17] FIG. 1 is a top-down view illustrating a first interconnect interconnecting a PCM cell to an integrated series resistor and a second interconnect contacting the opposite end of the integrated series resistor, according to one embodiment of the present invention. [Figure 18] FIG. 10 is a cross-sectional view illustrating a third metal layer Mx+2 including a second metal line in a fourth ILD formed above a second metal layer Mx+1, whereby the second metal line contacts a second interconnect, in accordance with one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0011] As given above, large arrays of resistive memory cells, such as chalcogenide phase change memory (PCM) memory cells, can experience significant resistance differences from the first memory cell to the last along a given metal line, which can cause significant and undesirable voltage drops between memory cells, thereby affecting read and write performance.

[0012] Advantageously, provided herein are PCM memory cell arrays and techniques for their fabrication that have integrated series resistors with tunable lengths formed during heater patterning (i.e., at the heater height) to achieve uniform voltage drops across the PCM devices. As described in more detail below, materials such as tantalum nitride (TaN), titanium nitride (TiN), and silicon nitride (SiN) can be utilized to reduce the area of the series resistor by one to two orders of magnitude, potentially improving process margins. Furthermore, reduced resistor size can improve parasitic inductance and capacitance.

[0013] FIG. 1 illustrates a memory array 100 of PCM devices 101 in accordance with the present technology. As shown in FIG. 1, each PCM device 101 includes a PCM cell 102 and an associated integrated series resistor 300. The PCM devices 101 reside between two sets of metal lines. That is, the memory array 100 includes a first metal line 104 that resides below the PCM devices 101 and a second metal line 106 that resides above the PCM devices 101. In this exemplary embodiment, the first metal line 104 is oriented orthogonal to the second metal line 106. A PCM cell 102 resides at each intersection of the first metal line 104 and the second metal line 106.

[0014] For illustrative purposes, a cross-sectional view of one of the PCM cells 102 is shown in Figure 2. As shown in Figure 2, each PCM cell 102 includes a PCM stack 200 sandwiched between a bottom electrode 202 and a top electrode 204. The PCM stack 200 has a heater 206 in direct physical contact with a phase change material 208. That is, in the exemplary embodiment shown in Figure 2, the heater 206 is below the phase change material 208, such that the heater 206 is disposed on the bottom electrode 202, the phase change material 208 is disposed on the heater 206, and the top electrode 204 is disposed on the phase change material 208. With this configuration, the heater 206 is sometimes referred to herein as the "bottom heater."

[0015] As described in detail below, in accordance with this technique, a hard mask 210 is disposed on the top electrode 204, and an encapsulation layer 212 is disposed on the PCM stack 200, the hard mask 210, and the top electrode 204. Interconnects 1602 (see also FIG. 16 , described below) extend through the hard mask 210 and the encapsulation layer 212 and are in direct physical contact with the top electrode 204. Note that certain structures, which will be described in detail below, have been omitted from FIG. 2 solely for purposes of clarity and ease of depiction. For example, surrounding dielectrics have been omitted.

[0016] A wide variety of materials can be employed as the phase change material 208 in accordance with the present technology. Nearly all materials are phase change materials, in the sense that they can exist in amorphous and crystalline forms, including metals, semiconductors, and insulators. However, only a small group of materials possess the properties that make them technologically useful phase change materials, such as high on / off resistance ratios, fast switching times, and good data retention. According to an exemplary embodiment, the phase change material 208 is a chalcogenide, i.e., the phase change material 208 includes at least one chalcogenide element. Generally, chalcogenides are elements from Group 16 of the Periodic Table of Elements, such as sulfur (S), selenium (Se), or tellurium (Te), or combinations thereof. In one exemplary embodiment, phase change material 208 is a chalcogenide alloy including the element Te (chalcogen) combined with at least one other element, such as antimony (Sb) and / or germanium (Ge), to form the alloy Sb2Te3, GeTe, or Ge2Sb2Te5 (GST), or combinations thereof. However, the present technology is not limited to the use of only chalcogenides as phase change material 208. For example, phase change material 208 may alternatively include a III-V semiconductor material (such as gallium antimonide (GaSb)) and / or a Ge-Sb based alloy. Additionally, elements such as silver (Ag), indium (In), nitrogen (N), and / or bismuth (Bi) can be added to phase change material 208 to optimize its properties.

[0017] During operation of the memory array 100, the heater 206 is employed to generate heat (by resistive heating) that is used to switch the phase change material 208 between two states: a low-resistivity crystalline state and a high-resistivity amorphous state. As shown in FIG. 2 , the heater 206 is formed from a combination of alternating first and second materials, e.g., a layer of first material 206a, a layer of second material 206b, a layer of first material 206c, a layer of second material 206d, etc. According to an exemplary embodiment, the first material is a material with a relatively high resistivity, such as tantalum nitride (TaN) and / or silicon nitride (SiN), and the second material is a material with a relatively low resistivity, such as titanium nitride (TiN). For example, TaN and / or SiN provide a high resistivity that allows for a reduced series resistor area, and TiN provides good thermal conductivity for the phase change material 208.

[0018] Furthermore, as will be described in more detail below, according to the present technique, the heater 206 is formed simultaneously with the integrated series resistor. In other words, the series resistor is formed at the height of the heater 206 during patterning of the heater 206. Therefore, the first material / second material combination selected should consider both the need for resistive heating and the heat conduction by the heater 206 to the phase change material 208, in addition to providing the necessary resistance for the series resistor. As will become apparent from the following description, by forming the heater 206 simultaneously with the integrated series resistor, the heater 206 and the integrated series resistor 300 include the same combination of materials.

[0019] For example, a series resistor 300 formed in accordance with the present techniques is illustrated in Figure 3. As shown in Figure 3, similar to the heater 206, the resistor 300 is formed from a combination of alternating first materials (such as TaN and / or SiN) and second materials (such as TiN), e.g., layer 306a of first material, layer 306b of second material, layer 306c of first material, layer 306d of second material, etc.

[0020] As will become apparent from the following description, a resistor 300 is associated with each of the PCM cells 102. That is, the resistor 300 connects each of the PCM cells 102 in series with one of the metal lines 106. According to an exemplary embodiment, the resistor 300 has a serpentine shape, as shown in FIG. 3, whereby at least a portion of the resistor 300 curves back and forth along the x and y directions. Employing such a serpentine shape advantageously allows for a reduced series resistance area.

[0021] Additionally, as emphasized above, the resistor 300 has an adjustable length to provide a uniform voltage drop across the PCM cells 102. For example, the length L of the resistor 300 can be varied during patterning to change the resistance of the resistor 300 of the corresponding PCM cell 102. Increasing the length L of the resistor 300 increases the resistance of the resistor 300, and vice versa. By way of example only, and referring to FIG. 3 , the length L of the resistor 300 can be increased / decreased by increasing / decreasing the number of loops 302 of the resistor 300 and / or by increasing / decreasing the width w and / or height h of the loops 302. Each of these techniques will increase / decrease the length of the path that the programming voltage must traverse to reach the PCM cell 102 from the corresponding metal line 106.

[0022] In general, the length L selected for resistor 300 depends on the location of the PCM device 101 and corresponding PCM cells 102 in the memory array 100. For example, referring back to FIG. 1 , the placement of PCM cells 102 along a particular metal line 106 will naturally result in some PCM cells 102 being located closer to the programming voltage source V than others. In conventional array designs, there is a significant difference in the line resistance of the cells closest to the voltage source V and the cells farthest from the voltage source V. As a result, voltage drops often occur between cells, which can affect read and write performance.

[0023] Advantageously, in accordance with the present technique, series resistors 300 of variable length, and therefore variable resistivity, are employed to adjust the resistance of the PCM device 101 as a function of their distance from a voltage source V. Thus, a uniform voltage drop can be engineered between the PCM device 101 and PCM cells 102. For example, referring to FIG. 1 , PCM cells 102a, 102b, 102c, and 102d are arranged along the same metal line 106, with PCM cell 102a closest to voltage source V, PCM cell 102d farther from voltage source V, and PCM cells 102b and 102c located between PCM cells 102a and 102d. Series resistors 300a, 300b, 300c, and 300d of different lengths L1, L2, L3, and L4 connect PCM cells 102a, 102b, 102c, and 102d, respectively, to metal line 106. According to an exemplary embodiment, L1>L2>L3>L4. In this case, the resistances of resistors 300a>300b>300c>300d, respectively. Viewed another way, the resistance value is adjusted (by the lengths of resistors 300a, 300b, 300c, and 300d) to gradually decrease as PCM cells 102a, 102b, 102c, and 102d are further from the voltage source. This adjustable process creates equal resistance in each of the PCM cells 102a, 102b, 102c, and 102d, thereby allowing for equal voltage drops between the PCM cells 102a, 102b, 102c, and 102d during operation.

[0024] An exemplary method for fabricating a PCM device having an integrated series resistor formed during heater patterning will now be described with reference to FIGS. 4-18. FIGS. 4-18 illustrate cross-sectional and top-down views of a cross section 110 (see FIG. 1) of a memory array 100 containing one of the PCM devices 101 (i.e., a PCM cell 102 and associated integrated series resistor 300). Furthermore, as will become apparent from the following discussion, FIG. 1 provides a basic illustration of components, such as the PCM cell 102, integrated series resistor 300, and corresponding metal lines 104 and 106, without depicting surrounding structures, such as dielectrics, interconnects, etc. This is done solely for ease and clarity of illustrating these elements of the present technology. However, structures not shown in FIG. 1 will be described in detail in the following figures and discussion. Additionally, as will be described in more detail below, the integrated series resistor 300 is formed simultaneously with and adjacent to the heater 206 of the PCM cell 102. 1 is merely for the purpose of illustrating that the integrated series resistor 300 is connected in series between the PCM cell 102 and the metal line 106, and that the integrated series resistor 300 may have different lengths, but does not imply that the integrated series resistor 300 necessarily has such an orientation.

[0025] As shown in FIG. 4 , the process begins with forming a first metal layer Mx on a substrate 402. According to an exemplary embodiment, the substrate 402 is a bulk semiconductor wafer, such as bulk silicon (Si), bulk germanium (Ge), bulk silicon germanium (SiGe), and / or a bulk III-V semiconductor wafer. Alternatively, the substrate 402 can be a semiconductor-on-insulator (SOI) wafer. An SOI wafer includes an SOI layer separated from an underlying substrate by a buried insulator. When the buried insulator is an oxide layer, it is referred to herein as a buried oxide or BOX (buried oxide). The SOI layer can include any suitable semiconductor, such as Si, Ge, SiGe, or a III-V semiconductor, or a combination thereof. The substrate 402 can already have pre-built structures, such as transistors, diodes, capacitors, resistors, interconnects, wiring, etc. See, for example, the selector transistor 404. Each transistor includes a source (S) and a drain (D) interconnected by a channel, and a gate (G) that controls the flow of electrons in the channel.

[0026] To form the first metal layer Mx, an interlayer dielectric (ILD) 406 is first deposited on the substrate 402. Suitable ILD 406 materials include, but are not limited to, nitride materials such as silicon nitride (SiN), oxide materials such as silicon oxide (SiOx), organosilicate glass (SiCOH), or ultra-low-κ interlayer dielectric (ULK-ILD) materials, e.g., those having a dielectric constant κ of less than 2.7, or combinations thereof. For comparison, the dielectric constant κ of silicon dioxide (SiO2) is 3.9. Suitable ultra-low-κ dielectric materials include, but are not limited to, porous organosilicate glass (pSiCOH). Processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) can be employed to deposit the ILD 406 on the substrate 402.

[0027] Next, a metallization process is employed to form first metal lines 104 in ILD 406. As explained above in connection with the description of FIG. 1, first metal lines 104 reside in memory array 100 below PCM cells 102. Note that similar structures are similarly numbered in the description and figures. In the exemplary embodiment illustrated in FIG. 4, conductive vias 408 connect metal lines 104 to transistors 404. By way of example only, a so-called “dual damascene process” may be employed to form metal lines 104 and conductive vias 408. Generally, a dual damascene process involves first patterning features, such as trenches and / or vias, in a dielectric and then filling the features with a metal or combination of metals to form metal lines and / or conductive vias, respectively. When trenches are formed before vias, this process is also referred to herein as a trench-first dual damascene process. Conversely, when vias are formed before trenches, this process is also referred to herein as a via-first dual damascene process.

[0028] Suitable metals for the metal lines 104 and conductive vias 408 include, but are not limited to, copper (Cu), cobalt (Co), ruthenium (Ru), or tungsten (W), or combinations thereof. Processes such as evaporation, sputtering, or electrochemical plating can be employed to deposit the metal in the feature. After deposition, metal overburden can be removed using processes such as chemical-mechanical polishing (CMP). Prior to depositing the metal in the feature, a conformal barrier layer 407 can be deposited in the feature to line the feature. The use of such a barrier layer helps prevent the metal from diffusing into the surrounding dielectric. Suitable barrier layer materials include, but are not limited to, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), or titanium nitride (TiN), or combinations thereof. Additionally, a seed layer (not shown) can be deposited in the feature to line the feature prior to depositing the contact metal. The seed layer facilitates plating of the metal into the features.

[0029] Next, the heater 206 and the integrated series resistor 300 are formed above the first metal layer Mx. As provided above, the heater 206 is disposed on the bottom electrode 202. To form the bottom electrode 202, a capping layer 410 is deposited on the ILD 406, an ILD 412 is deposited on the capping layer 410, and at least one bottom electrode 202 is formed in the ILD 412 above the metal line 104. See FIG. 4. Suitable materials for the capping layer 410 include, but are not limited to, nitride materials such as SiN, silicon oxynitride (SiON), or silicon oxycarbonitride (SiOCN), or combinations thereof. Processes such as CVD, ALD, or PVD can be employed to deposit the capping layer 410 on the ILD 406. According to an exemplary embodiment, the capping layer 410 has a thickness ranging from about 2 nanometers (nm) to about 5 nm, and therebetween.

[0030] ILD 412 may also be referred to as the "second ILD" to distinguish it from ILD 406, which may also be referred to herein as the "first ILD." Suitable materials for ILD 412 include, but are not limited to, oxide materials such as SiOx, SiCOH, or ULK-ILD materials such as pSiCOH, or combinations thereof. Processes such as CVD, ALD, or PVD may be employed to deposit ILD 412 on capping layer 410.

[0031] Next, a metallization process is employed to form at least one bottom electrode 202 in the ILD 412 above the metal lines 104. In the exemplary embodiment illustrated in FIG. 4, a conductive via 414 connects the bottom electrode 202 to the metal lines 104. By way of example only, the bottom electrode 202 and conductive via 414 may be formed using a dual damascene process. As provided above, a dual damascene process involves first patterning features, such as trenches and / or vias, in a dielectric and then filling the features with a metal or combination of metals (e.g., Cu, Co, Ru, and / or combinations thereof) using a process such as evaporation, sputtering, or electrochemical plating to form the metal lines and / or conductive vias, respectively. After deposition, the metal overburden may be removed using a process such as CMP. Prior to depositing metal in the feature, a conformal barrier layer 413 (e.g., Ta, TaN, Ti, or TiN, or a combination thereof) may be deposited in the feature to line the feature and prevent the metal from diffusing into the surrounding dielectric. Additionally, prior to depositing the contact metal, a seed layer (not shown) may be deposited in the feature to line the feature and facilitate plating of the metal into the feature.

[0032] Next, a lithography stack 416 is formed on the ILD 412 above the at least one bottom electrode 202 to pattern the heater 206 and the integrated series resistor 300. As shown in Figure 4, the lithography stack 416 includes a hard mask layer 418 (e.g., SiN), an organic planarization layer (OPL) 420 disposed on the hard mask layer 418, an antireflective coating (ARC) 422 disposed on the OPL 420, and a patterned photoresist 424 disposed on the ARC 422.

[0033] Photoresist 424 is patterned with the footprints and locations of heater 206 and integrated series resistor 300. For example, as shown in Figure 5 (a top-down view of the structure from viewpoint A (see Figure 4)), photoresist 422 includes a pattern 502 corresponding to the footprint and location of heater 206 and a pattern 504 corresponding to the footprint and location of integrated series resistor 300.

[0034] Lithography and etching techniques are then employed to transfer the patterns 502 / 504 from the photoresist 424 to the hardmask layer 418, after which any remaining OPL 420, ARC 422, and photoresist 424 are removed. See Figure 6. A directional (anisotropic) etching process, such as reactive ion etching (RIE), may be employed to pattern the hardmask layer 418.

[0035] The hard mask layer 418 is now patterned with the footprints and locations of the heater 206 and the integrated series resistor 300. For example, as shown in Figure 7 (a top-down view of the structure from viewpoint B (see Figure 6)), the hard mask layer 418 includes a (first) pattern 702 corresponding to the footprint and location of the heater 206 and a (second) pattern 704 corresponding to the footprint and location of the integrated series resistor 300.

[0036] According to an exemplary embodiment, the heater 206 and the integrated series resistor 300 are formed from the same combination of alternating first and second materials. As emphasized above, the first material is preferably a relatively high-resistivity material such as TaN and / or SiN, and the second material is preferably a relatively low-resistivity material such as TiN. For example, with reference to FIG. 8 , a layer 802 of a first material is conformally deposited on the hard mask layer 418, lining the patterns 702 / 704. According to an exemplary embodiment, the layer 802 has a thickness ranging from about 2 nanometers (nm) to about 10 nm and therebetween. Next, a layer 804 of a second material is conformally deposited on the layer 802. According to an exemplary embodiment, the layer 804 has a thickness ranging from about 2 nm to about 10 nm and therebetween. A layer 806 of a first material is conformally deposited above the layer 802 and on the layer 804. According to an exemplary embodiment, layer 806 has a thickness ranging from about 2 nm to about 10 nm and therebetween. Finally, a layer 808 of a second material is deposited over layer 806 to fill the remainder of patterns 702 and / or 704. Processes such as CVD, ALD, or PVD may be employed to deposit each of layers 802, 804, 806, and 808.

[0037] It should be noted that the first material / second material combination shown in FIG. 8 is merely one exemplary embodiment for forming the heater 206 and integrated series resistor 300 according to the present technique, and other configurations are contemplated herein. For example, to reduce manufacturing complexity, one or more of layers 802, 804, 806, and 808 may be omitted from the design. Furthermore, the thickness stacking of deposited layers 802-808 may result in portions of patterns 702 and 704 being fully filled before depositing subsequent layers. For example, according to an alternative embodiment, the layer of first material 806 may instead fill the remainder of pattern 702 before depositing the layer of second material 808. In that case, after polishing (see below), the heater 206 will not include the layer of second material 808.

[0038] Next, layers 802, 804, 806, and 808 are polished down to hard mask layer 418 using a process such as chemical mechanical polishing (CMP). See FIG. 9. As shown in FIG. 9, by polishing layers 802, 804, 806, and 808, heater 206 and integrated series resistor 300 are separately defined. To be consistent with the numbering used above, the portions of layers 802, 804, 806, and 808 that form heater 206 will be referred to as 206a, 206b, 206c, and 206d, respectively, and the portions of layers 802, 804, 806, and 808 that form integrated series resistor 300 will be referred to as 306a, 306b, 306c, and 306d, respectively. Notably, as is now apparent from the process described above, heater 206 and integrated series resistor 300 are formed from the same combination of the same (first and second) materials. Furthermore, as shown in FIG. 9, this process results in the top surfaces of the heater 206 and the integrated series resistor 300 becoming coplanar.

[0039] Figure 10 is a top-down view of this structure (from viewpoint C (see Figure 9)). As shown in Figure 10, heater 206 and integrated series resistor 300 are defined here. Based on the configuration of layers 802, 804, 806, and 808, heater 206 includes a layer of first material 206a, a layer of second material 206b, a layer of first material 206c, and a layer of second material 206d, and integrated series resistor 300 includes a layer of first material 306a, a layer of second material 306b, a layer of first material 306c, and a layer of second material 306d.

[0040] The remainder of the PCM cell 102 is then built up on the heater 206. To do so, a phase change material layer 1102 is deposited over the heater 206 and integrated series resistor 300 and on the hard mask layer 418, a top electrode layer 1104 is deposited on the phase change material layer 1102, and a hard mask layer 1106 is deposited on the top electrode layer 1104. See FIG. 11 . Hard mask layer 1106 is sometimes referred to herein as the “second hard mask layer” to distinguish it from the “first” hard mask layer 418.

[0041] According to an exemplary embodiment, phase change material layer 1102 is formed from a chalcogenide material, i.e., phase change material layer 1102 contains at least one chalcogen element, such as S, Se, or Te, or a combination thereof. In one exemplary embodiment, phase change material layer 1102 is formed from a chalcogenide alloy including the element Te (chalcogen) combined with at least one other element, such as Sb or Ge, to form the alloy SbTe, GeTe, or GeSbTe, or a combination thereof. However, as emphasized above, the present technology is not limited to using only chalcogenide-based phase change materials. For example, according to an alternative embodiment, phase change material layer 1102 is formed from a III-V semiconductor material (such as gallium antimonide (GaSb)) and / or a Ge-Sb-based alloy. Additional elements, such as Ag, In, N, or Bi, or a combination thereof, can be optionally added to the phase change material to optimize its properties. Processes such as CVD, PVD, or molecular beam epitaxy (MBE) can be employed to deposit phase change material layer 1102 on hard mask layer 418. Of course, the specific target (PVD) or precursor (CVD) in the deposition process will depend on the particular phase change material being formed. For example, if PVD is used to deposit GeSbTe, the most common source is a GeSbTe target. Separate elemental targets for Ge, Sb, and Te can also be used by adjusting the flux from each target to achieve the desired composition. According to an exemplary embodiment, phase change material layer 1102 has a thickness ranging from about 10 nm to about 20 nm and therebetween.

[0042] Suitable materials for the top electrode layer 1104 include, but are not limited to, TiN, TaN, Ru, or W, or combinations thereof. Processes such as evaporation or sputtering may be employed to deposit the top electrode layer 1104 on the phase change material layer 1102. According to an exemplary embodiment, the top electrode layer 1104 has a thickness ranging from about 5 nm to about 10 nm and therebetween.

[0043] Suitable materials for the hard mask layer 1106 include, but are not limited to, nitride hard mask materials such as SiN. Processes such as CVD, ALD, or PVD may be employed to deposit the hard mask layer 1106 on the top electrode layer 1104. According to an exemplary embodiment, the hard mask layer 1106 has a thickness ranging from about 5 nm to about 15 nm and therebetween.

[0044] Next, lithography and etching techniques are used to pattern the hard mask layer 1106, the top electrode layer 1104, and the phase change material layer 1102. See FIG. 12 . As described above, the lithography process generally includes forming a lithography stack (e.g., OPL / ARC / photoresist), transferring a pattern from the photoresist, etc. For brevity, the description of the steps associated with forming and patterning the lithography stack will not be repeated here, but it should be understood that these steps are performed in the same manner as described above. As shown in FIG. 12 , the patterned portion of the hard mask layer 1106 forms a hard mask 210 with the footprint and location of the PCM cell 102. Next, in a similar manner as described above, the hard mask 210 is used to pattern the underlying phase change material layer 1102 and top electrode layer 1104 to form the phase change material 208 and top electrode 204 of the PCM cell 102, respectively. As highlighted above and as shown in FIG. 12, the PCM cell 102 and the integrated series resistor 300 together form the PCM device 101.

[0045] Figure 13 is a top-down view of the structure (from viewpoint D (see Figure 12)). As shown in Figure 13, the PCM cell 102 (of which only the hard mask 210 is visible from the top-down view) now resides above the heater 206 (not visible in the top-down view). An integrated series resistor 300 resides adjacent to the PCM cell 102 (and the heater 206 below it).

[0046] Next, a conformal encapsulation layer 212 is deposited on the hard mask layer 418, covering the PCM cell 102 and the integrated series resistor 300. See FIG. 14. The encapsulation layer 212 functions to protect the exposed surface of the phase change material 208 along the sidewalls of the PCM cell 102. Suitable materials for the encapsulation layer 212 include, but are not limited to, nitride materials such as SiN, SiON, or SiOCN, or combinations thereof. Processes such as CVD, ALD, or PVD may be employed to deposit the encapsulation layer 212. According to an exemplary embodiment, the encapsulation layer 212 has a thickness ranging from about 2 nm to about 5 nm, and therebetween.

[0047] Next, a second metal layer Mx+1 is fabricated above the hard mask layer 418 to interconnect the PCM cell 102 with the integrated series resistor 300 and provide a means for accessing the integrated series resistor 300 via the metal line 106. To form the second metal layer Mx+1, an ILD 1502 is first deposited on the encapsulation layer 212 to bury the PCM cell 102 and the integrated series resistor 300. See FIG. 15 . The ILD 1502 is sometimes referred to herein as the “third ILD” to distinguish it from the “first” ILD 406 and the “second” ILD 412. Suitable materials for the ILD 1502 include, but are not limited to, oxide materials such as SiOx, SiCOH, or ULK-ILD materials such as pSiCOH, or combinations thereof. Processes such as CVD, ALD, or PVD may be employed to deposit the ILD 1502 on the encapsulation layer 212. After deposition, the ILD 1502 is polished using a process such as CMP.

[0048] Next, a metallization process is employed to form at least a first interconnect 1602 and a second interconnect 1604 in the ILD 1502. See FIG. 16. By way of example only, the interconnects 1602 and 1604 may be formed using a dual damascene process. As provided above, a dual damascene process involves first patterning features such as trenches and / or vias, and then filling the features with a metal or combination of metals (e.g., Cu, Co, Ru, or W, or combinations thereof) using a process such as evaporation, sputtering, or electrochemical plating to form metal lines and / or conductive vias, respectively. In this case, the features are patterned not only in the encapsulation layer 212 but also in the ILD 1502 and, in the case of the interconnect 1602, through the hard mask 210 on top of the PCM cell 102. After deposition, the metal overburden may be removed using a process such as CMP. Prior to depositing metal into the feature, a conformal barrier layer 1601 (e.g., Ta, TaN, Ti, or TiN, or a combination thereof) may be deposited in and lining the feature to prevent the metal from diffusing into the surrounding dielectric. Additionally, prior to depositing the contact metal, a seed layer (not shown) may be deposited in and lining the feature to facilitate plating of the metal into the feature.

[0049] 16, interconnect 1602 contacts both PCM cell 102 (via top electrode 204) and one (first) end of integrated series resistor 300. In this manner, interconnect 1602 interconnects PCM cell 102 to integrated series resistor 300. Interconnect 1604 contacts the other (second) end (opposite the first end) of integrated series resistor 300. As will be explained in more detail below, interconnect 1604 functions to interconnect integrated series resistor 300 to metal line 106.

[0050] Figure 17 is a top-down view of the structure (from viewpoint E (see Figure 16)). As shown in Figure 17, interconnect 1602 interconnects PCM cell 102 (of which only hard mask 210 is present in the top-down view) to a first end of integrated series resistor 300. Interconnect 1604 resides above and contacts the second / opposite end of integrated series resistor 300. For clarity, encapsulation layer 212 and ILD 1502 are not included in this illustration.

[0051] Next, a third metal layer Mx+2 is fabricated above the second metal layer Mx+1. To that end, a capping layer 1802 is first deposited on the ILD 1502 covering the interconnects 1602 and 1604. See FIG. 18 . The capping layer 1802 may also be referred to herein as the “second capping layer” to distinguish it from the “first” capping layer 410. Suitable materials for the capping layer 1802 include, but are not limited to, nitride materials such as SiN, SiON, or SiOCN, or combinations thereof. Processes such as CVD, ALD, or PVD may be employed to deposit the capping layer 1802 on the ILD 1502. According to an exemplary embodiment, the capping layer 1802 has a thickness ranging from about 2 nm to about 5 nm, and therebetween.

[0052] Next, ILD 1804 is deposited on capping layer 1802 above interconnects 1602 and 1604. ILD 1804 is sometimes referred to herein as the “fourth ILD” to distinguish it from “first” ILD 406, “second” ILD 412, and “third” ILD 1502. Suitable materials for ILD 1804 include, but are not limited to, oxide materials such as SiOx, SiCOH, or ULK-ILD materials such as pSiCOH, or combinations thereof. Processes such as CVD, ALD, or PVD can be employed to deposit ILD 1804 on capping layer 1802. After deposition, ILD 1804 is polished using a process such as CMP.

[0053] Next, a metallization process is employed to form second metal line 106 in ILD 1804. As discussed above in connection with the description of FIG. 1 , second metal line 106 resides in memory array 100 above PCM cell 102. In the exemplary embodiment illustrated in FIG. 18 , conductive via 1806 connects metal line 106 to interconnect 1604. As provided above, interconnect 1604 contacts the end of integrated series resistor 300 opposite interconnect 1602 / PCM cell 102. With this configuration, resistor 300 therefore resides in series with metal line 106 and PCM cell 102.

[0054] By way of example only, a so-called “dual damascene process” may be employed to form the metal lines 106 and conductive vias 1806. As provided above, a dual damascene process involves first patterning a feature, such as a trench or via, or both, and then filling the feature with a metal or combination of metals (e.g., Cu, Co, Ru, or W, or a combination thereof) using a process such as evaporation, sputtering, or electrochemical plating to form the metal lines or conductive vias, or both, respectively. In this case, the feature is patterned not only in the capping layer 1802 but also in the ILD 1804 as well. After deposition, the metal overburden may be removed using a process such as CMP. Before depositing the metal in the feature, a conformal barrier layer 1805 (e.g., Ta, TaN, Ti, or TiN, or a combination thereof) may be deposited in the feature to line it and prevent the metal from diffusing into the surrounding dielectric. Additionally, a seed layer (not shown) may be deposited in the feature prior to contact metal deposition to line the feature and facilitate plating of the metal into the feature.

[0055] In a PCM device 101, the resistance difference between the two states of a PCM cell 102 (i.e., when the phase change material 208 is in an amorphous state or a crystalline state) can vary by several orders of magnitude. The use of an integrated series resistor 300 allows for fine tuning of the resistance value. For example, as described above, the length of the integrated series resistor 300 can be adjusted based on the position of the corresponding PCM device 101 in the memory array 100.

[0056] During programming of the memory array 100, a SET operation is used to program one or more of the PCM cells 102 to a low-resistance structural state that represents a data value, such as a logic "1" or a logic "0." As provided above, the SET state is a low-resistance structural state in which the electrical properties are primarily dominated by the crystalline portion of the phase-change material. The data value may be read from the memory array 100 during a read operation. A subsequent RESET operation is then used to return the PCM cells 102 to their previous high-resistance structural state. As provided above, the RESET state is a high-resistance structural state in which the electrical properties are primarily dominated by the amorphous portion of the phase-change material.

[0057] The heater 206 is employed to generate heat (via resistive heating) that is used to switch the phase change material 208 between a low-resistance crystalline state and a high-resistance amorphous state. To change the PCM cell 102 from an amorphous state to a crystalline state, a SET programming voltage pulse is applied to the heater 206 to heat the phase change material 208 above its crystallization temperature for a sufficiently long time. As a result, the phase change material 208 aligns itself in a crystalline state during that heating period. To change the phase change material 208 from a crystalline state to an amorphous state, a RESET programming voltage pulse is applied to the heater 206 to heat the phase change material 208 above its melting point and then stopped (quenched). This action leaves the phase change material 208 in an amorphous state without having time to rearrange itself into an ordered state. Both the crystallization temperature and melting point will vary depending on the particular phase change material employed.

[0058] During programming, as described above, there is a drop in the SET / RESET programming voltage pulse applied to PCM cells 102 located along the same metal line. However, the integrated series resistors 300 can be adjusted to different lengths to account for the difference in distance from the programming voltage source. This allows the voltage drop to be uniform across the PCM cells 102.

[0059] According to an exemplary embodiment, the PCM cell 102 is read by applying a lower read voltage pulse for a shorter time period compared to the SET / RESET programming voltage pulse. For example, the read voltage pulse can be smaller than either the SET programming voltage pulse or the RESET programming voltage pulse. Furthermore, the read voltage is applied for a time shorter than the SET time or the RESET time. For example, the read time can be less than half the RESET time, and the read voltage pulse can be less than half the SET programming voltage pulse. Furthermore, the RESET programming voltage pulse can be more than twice the SET programming voltage pulse, and the SET time can be two, three, five, or more times the RESET time.

[0060] While illustrative embodiments of the present invention have been described herein, it is to be understood that the invention is not limited to those precise embodiments, and that various other changes and modifications can be made by those skilled in the art without departing from the scope of the invention.

Claims

1. 1. A phase change memory (PCM) device comprising: at least one PCM cell comprising a phase change material disposed on a heater; at least one resistor in series with the at least one PCM cell, the at least one resistor having the same combination of materials as the heater; an interconnect contacting both a top electrode of the at least one PCM cell and an end of the at least one resistor; Equipped with the length and resistance of the resistors being a function of the distance of each of the PCM devices from a voltage source; A phase change memory (PCM) device, wherein a top surface of the heater is flush with a top surface of the at least one resistor.

2. The PCM device of claim 1 , wherein the heater is below the phase change material of the at least one PCM cell.

3. 3. A PCM device according to claim 1 or 2, wherein said same combination of materials comprises alternating layers of a first material and a second material.

4. 4. The PCM device of claim 3, wherein the first material is selected from the group consisting of tantalum nitride (TaN) and silicon nitride (SiN), and the second material comprises titanium nitride (TiN).

5. The PCM device of claim 1 or 2, wherein the phase change material comprises a chalcogenide alloy.

6. The at least one PCM cell a lower electrode on which the heater is disposed; a top electrode disposed on the phase change material; 3. The PCM device of claim 1 or 2, further comprising:

7. 3. The PCM device of claim 1, further comprising an encapsulation layer disposed over the at least one PCM cell, along sidewalls of the phase change material, and over the at least one resistor.

8. 8. The PCM device of claim 7, wherein the encapsulation layer comprises a material selected from the group consisting of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), and combinations thereof.

9. a first set of metal wires; a second set of metal wires; and PCM devices between the first set of metal lines and the second set of metal lines, each PCM device comprising a PCM cell comprising a phase change material disposed on a heater and a resistor in series with the PCM cell, the resistor comprising the same combination of material as the heater, and the PCM cell being at an intersection of the first set of metal lines and the second set of metal lines; an interconnect contacting both the PCM cell and an end of the resistor; Equipped with the length and resistance of the resistors being a function of the distance of each of the PCM devices from a voltage source; A memory array wherein a top surface of the heater is flush with a top surface of the resistor.

10. 10. The memory array of claim 9, wherein the first set of metal lines are oriented orthogonal to the second set of metal lines.

11. 10. The memory array of claim 9, wherein the resistor has a serpentine shape whereby at least a portion of the resistor curves back and forth along the x and y directions.

12. 10. The memory array of claim 9, wherein the length and resistance of the resistor depends on the position of the PCM cell in the memory array to provide a uniform voltage drop across the PCM device.

13. 10. The memory array of claim 9, wherein said same combination of materials comprises alternating layers of a first material and a second material, said first material being selected from the group consisting of TaN and SiN, and said second material comprising TiN.

14. 10. The memory array of claim 9, wherein the phase change material comprises a chalcogenide alloy, the chalcogenide alloy comprising Te in combination with an element selected from the group consisting of Sb, Ge, and combinations thereof.

15. 1. A method of forming a PCM device, comprising: simultaneously forming the heater and resistor on the bottom electrode from the same combination of materials; forming a phase change material on the heater; forming a top electrode on the phase change material; wherein the bottom electrode, the heater, the phase change material, and the top electrode comprise a PCM cell, the PCM device comprising an interconnect contacting both the PCM cell and an end of the resistor, the length and resistance of the resistor being a function of the distance of each of the PCM devices from a voltage source, and the top surface of the heater being flush with the top surface of the resistor.

16. the same combination of materials includes alternating layers of a first material and a second material; forming at least a first pattern and a second pattern in a hard mask layer, the first pattern corresponding to the heater and the second pattern corresponding to the resistor; simultaneously depositing the alternating layers of the first material and the second material in the first pattern and in the second pattern; polishing the alternating layers of the first material and the second material to form the heater and the resistor, wherein after polishing, a top surface of the heater is flush with a top surface of the resistor; 16. The method of claim 15, further comprising:

17. 17. The method of claim 16, wherein the first material is selected from the group consisting of TaN and SiN, and the second material comprises TiN.

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