DFS-based cycle detection in the Pregel model

Abstract

A method, system, and computer program product for reducing memory consumption in a depth-first search (DFS)-based cycle detection process for detecting n-long cycles in the Pregel model are presented. The method includes generating a graph including a plurality of vertices and edges connecting the plurality of vertices, starting a cycle from a first vertex of the plurality of vertices, setting the ID of the first vertex to a path and the first vertex as a target vertex, and repeating the following n-1 times: sending the path to an out-edge starting from the first vertex, forwarding the path n-1 times through the out-edges with subsequent received vertices, discovering a vertex before returning to the target vertex, adding the ID of the discovered vertex to the path, and setting the discovered vertex as the target vertex, such that n=n-1, where n is the number of iterations.

Description

[Technical Field]

[0001] The present invention relates generally to cycle detection in directed graphs, and more particularly to depth-first search (DFS) based cycle detection in the Pregel model. [Background technology]

[0002] Many practical computing problems involve large graphs. Typical examples include web graphs and various social networks. These graphs can sometimes have billions of vertices and trillions of edges, making efficient processing of them challenging. Graph algorithms often have poor memory access locality, very low per-vertex processing, and varying degrees of parallelism over the course of execution. Furthermore, distributing the graph across many machines exacerbates the locality problem and increases the probability of machine failure during the computation. Summary of the Invention

[0003] According to one embodiment, a method for reducing memory consumption in a depth-first search (DFS)-based cycle detection process for detecting n-length cycles on the Pregel model is provided. The method includes generating a graph including a plurality of vertices and edges connecting the plurality of vertices, starting a cycle from a first vertex of the plurality of vertices, setting the identification (ID) of the first vertex to a path and the first vertex as a target vertex, and repeating the following n-1 times: sending the path to an out-edge starting from the first vertex, forwarding the path n-1 times through the out-edges with subsequent received vertices, discovering a vertex before returning to the target vertex, adding the ID of the discovered vertex to the path, and setting the discovered vertex as the target vertex such that n=n-1, where n is the number of iterations.

[0004] According to another embodiment, a method for reducing memory consumption in cycle detection processing is provided, which includes employing a depth-first search (DFS) approach to detect n-long cycles on the Pregel model by generating a graph including a plurality of vertices and edges connecting the plurality of vertices, starting a cycle at a first vertex of the plurality of vertices, setting the identity (ID) of the first vertex as a path and the first vertex as a target vertex, and repeating the DFS process n−1 times, where n is the number of iterations.

[0005] A computer program product for reducing memory consumption in a depth-first search (DFS)-based cycle detection process for detecting n-long cycles on the Pregel model is presented. The computer program product includes a computer-readable storage medium having program instructions embodied therein, the program instructions being executable by a computer to cause the computer to perform the following operations: generate a graph including a plurality of vertices and edges connecting the plurality of vertices; start a cycle from a first vertex of the plurality of vertices; set the ID of the first vertex to a path and the first vertex as a target vertex; and repeat the following n-1 times: send the path to an out-edge starting from the first vertex; forward the path n-1 times via the out-edges with subsequent received vertices; find one vertex before returning to the target vertex; add the ID of the found vertex to the path; and set the found vertex as the target vertex so that n=n-1, where n is the number of iterations.

[0006] It should be noted that exemplary embodiments have been described with reference to different subject matters. In particular, some embodiments have been described with reference to method-type claims, while other embodiments have been described with reference to apparatus-type claims. However, those skilled in the art will understand from the above and following description that, unless otherwise notified, in addition to any combination of features belonging to one type of subject matter, any combination between features relating to different subject matters, in particular any combination between features of method-type claims and features of apparatus-type claims, is also considered to be described within this document.

[0007] These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.

[0008] The present invention is provided in more detail in the description of preferred embodiments with reference to the following figures. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is an exemplary directed graph in which all 4-long cycles containing vertices 0 and 6 are detected in the first iteration, according to one embodiment of the present invention. [Figure 2] 2 is the exemplary directed graph of FIG. 1 where a second iteration is performed to find an ID, according to one embodiment of the present invention. [Figure 3] 3 is the exemplary directed graph of FIG. 2 where a third iteration is performed to find the ID, according to one embodiment of the present invention. [Figure 4] 4 is the exemplary directed graph of FIG. 3 where a fourth iteration is performed to find the ID, according to one embodiment of the present invention. [Figure 5] 5 is the exemplary directed graph of FIG. 4 where a fifth iteration is performed to find the ID, according to one embodiment of the present invention. [Figure 6] 6 is the example directed graph of FIG. 5 where a sixth iteration is performed to find the ID, according to one embodiment of the present invention. [Figure 7] 7 is the exemplary directed graph of FIG. 6 where the seventh iteration is performed to find the ID, according to one embodiment of the present invention. [Figure 8] 8 is the example directed graph of FIG. 7 where the eighth iteration is performed to find the ID, according to one embodiment of the present invention. [Figure 9] 9 is the exemplary directed graph of FIG. 8 where the ninth iteration is performed to find the ID, according to one embodiment of the present invention. [Figure 10] 10 is the exemplary directed graph of FIG. 9 where the tenth iteration is performed to find the ID, according to one embodiment of the present invention. [Figure 11] 11 is the exemplary directed graph of FIG. 10 where the 11th iteration is performed to find the ID, according to one embodiment of the present invention. [Figure 12] FIG. 2 is a block / flow diagram of an exemplary method for applying depth-first search (DFS) based cycle detection in the Pregel model, according to one embodiment of the present invention. [Figure 13] FIG. 1 is a block / flow diagram of an exemplary cloud computing environment, according to one embodiment of the present invention. [Figure 14] FIG. 2 is a schematic diagram of an exemplary abstraction model layer, according to one embodiment of the present invention. [Figure 15] FIG. 1 is a block / flow diagram of a practical application for applying depth-first search (DFS) based cycle detection in the Pregel model, according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0010] Throughout the drawings, the same or similar reference numbers represent the same or similar elements.

[0011] An exemplary embodiment according to the present invention provides cycle detection based on depth-first search (DFS) in the Pregel model. Graph learning is defined as a type of machine learning that utilizes graph-based features to add rich context to data by first linking that data together as a graph structure and then deriving features from different metrics on the graph. Various graph features can be defined using a set of graph analytics, such as connectivity, centrality, community detection, and pattern matching. Graph features can also be combined with non-graph features (e.g., features related to the attributes of specific data points). Once a set of features, including graph features and non-graph features, is defined, the problem can be formulated as a supervised machine learning problem (assuming label data is provided). However, if label data is not provided, the problem becomes an unsupervised machine learning problem, and methods such as clustering and outlier detection can be applied.

[0012] Nevertheless, to address the distributed processing of large-scale graphs, the Pregel model was built as a scalable and fault-tolerant platform with an application programming interface (API) flexible enough to express any graph algorithm. The Pregel model is a programming model that implements bulk synchronous parallel processing for graph analysis.

[0013] The high-level structure of a Pregel program is inspired by the variant's bulk-synchronous parallel processing model. A Pregel computation involves a series of iterations called supersteps. During a superstep, the framework invokes a user-defined function, conceptually in parallel, for each vertex. This function specifies an action for a single vertex V and a single superstep S. This function can read messages sent to V in superstep S-1, send messages to other vertices that will receive them in superstep S+1, and modify the state of V and its outgoing edges. Messages are typically sent along outgoing edges, but messages can be sent to any vertex whose identifier is known.

[0014] The vertex-centric approach is reminiscent of MapReduce, where users focus on local actions, processing each item independently, and the system composes these actions to scale the computation to large datasets.By design, this model is suitable for distributed implementation, i.e., it does not expose a mechanism for discovering the execution order within a superstep; all communication is from superstep S to superstep S+1.

[0015] The synchronicity of this model makes it easy to reason about program semantics when implementing the algorithm, and ensures that Pregel programs are inherently free from deadlocks and data races common in asynchronous systems. In principle, with sufficient parallel slack, the performance of Pregel programs should compare favorably with that of asynchronous systems. Because there are more vertices in a graph computation than there are machines, users should be able to balance machine loads such that synchronization between supersteps does not introduce excessive latency.

[0016] The Pregel model employs a breadth-first search (BFS) approach. BFS is an algorithm for traversing or searching a tree or graph data structure. BFS starts from the root of the tree (or any node in the graph, sometimes called the "search key") and searches all adjacent nodes at the current depth before moving on to the node at the next depth. However, existing Pregel model cycle detection algorithms require many messages because they employ the BFS approach. In other words, the total number of messages increases exponentially based on the number of iterations. As a result, while the Pregel model is easier to develop through parallelization, existing Pregel model cycle detection algorithms require too many messages because they use BFS.

[0017] Exemplary embodiments of the present invention disclose a method and system that alleviates such problems by employing a depth-first search (DFS) approach. DFS is an algorithm for traversing or searching a tree or graph data structure. The algorithm starts from a root node (in the case of a graph, some arbitrary node is selected as the root node) and searches as far as possible along each branch before backtracking. In this way, employing a DFS approach can significantly reduce the number of messages in each iteration when detecting cycles.

[0018] While the present invention is described in terms of certain exemplary architectures, it should be understood that other architectures, structures, substrate materials, and process features and steps / blocks can vary within the scope of the present invention. Note that for clarity, certain features may not be shown in every figure. This is not intended to be construed as a limitation of the particular embodiment, or of the illustrations, or of the scope of the claims.

[0019] Various illustrative embodiments of the present invention are described below. In the interest of clarity, not all features of an actual implementation are described herein. Of course, it will be understood that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developer's particular goals, including compliance with system- and business-related constraints, which will vary from implementation to implementation. Moreover, it will be understood that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this invention.

[0020] FIG. 1 is an exemplary directed graph in which all 4-long cycles containing vertices 0 and 6 are detected in the first iteration, according to one embodiment of the present invention.

[0021] The input to a Pregel computation is a directed graph, where each vertex is uniquely identified by a string vertex identifier. Each vertex is associated with a modifiable user-defined value. Directed edges are associated with their source vertex, and each edge contains a modifiable user-defined value and a target vertex identifier. A Pregel computation includes an input, when the graph is initialized, followed by a series of supersteps separated by global synchronization points until the algorithm terminates, terminating with an output.

[0022] Within each superstep, vertices perform computations in parallel, each executing the same user-defined function that represents the logic of a given algorithm. Vertices can change their own state or the state of their outgoing edges, receive messages sent in the previous superstep, send messages to other vertices (to be received in the next superstep), or change the topology of the graph. Edges are not first-class objects in this model and have no associated computation.

[0023] The termination of the algorithm is based on all vertices voting to stop. In superstep 0, all vertices are in the active state, and all active vertices participate in the computation of any given superstep. A vertex deactivates itself by voting to stop. This means that unless there is an external trigger, the vertex has no more work to do, and the Pregel framework will not execute the vertex in subsequent supersteps unless it receives a message. If reactivated by a message, the vertex must be explicitly deactivated again. The algorithm as a whole terminates when all vertices are simultaneously deactivated and there are no more messages in transit.

[0024] The output of a Pregel program is the set of values that the vertices explicitly emit. The output is often a directed graph isomorphic to the input, but this is not a necessary property of the system, as vertices and edges can be added or removed during the computation. For example, a clustering algorithm might generate a small set of disconnected vertices selected from a larger graph. A graph mining algorithm might simply output aggregate statistics mined from a graph.

[0025] Vertices communicate directly with each other by sending messages, each of which contains a message value and the name of the vertex it is sent to. The type of the message value is specified by the user as a template parameter of the Vertex class.

[0026] A vertex can send any number of messages in a superstep. All messages sent to vertex V in superstep S are available, via the iterator, when V's Compute() method is called in superstep S+1. The order of messages in the iterator is not guaranteed, but messages are guaranteed to be delivered and not duplicated.

[0027] The Pregel aggregator is a mechanism for global communication, monitoring, and data. Each vertex can provide values to the aggregator in superstep S, the system combines those values using a reduction operator, and the resulting value is made available to all vertices in superstep S+1. The Pregel model includes a number of predefined aggregators, such as min, max, or sum operations on various integer or string types.

[0028] There are many possibilities for the file format of a graph, such as a text file, a set of vertices in a relational database, or rows in a table. To avoid forcing the choice of a specific file format, the Pregel model separates the task of interpreting an input file as a graph from the task of graph computation. Similarly, output can be produced in any format and saved in the format that best suits a given application. The Pregel library provides many common file formats for readers and writers. The Pregel library divides a graph into partitions, where each partition contains a set of vertices and all of those vertices' outgoing edges. The assignment of vertices to partitions depends only on the vertex ID, which means that it is possible to know which partition a given vertex belongs to even if the vertex is owned by another machine or even if the vertex does not exist yet.

[0029] In Figure 1, by adopting the DFS approach, there are five messages or five IDs sent from vertices 0 and 6.

[0030] In particular, ID {6} is transmitted via edges from vertex 6 to 4, 6 to 3, and 6 to 5.

[0031] ID {0} is sent via vertices 0 to 3 and edges 0 to 5.

[0032] So the first iteration contains 5 messages with 5 IDs.

[0033] The target vertices (0 and 6) send their own IDs ({0}, {6}) to the adjacent out-edges.

[0034] With respect to Figures 1-4, note that in the kth iteration, a candidate edge for the last edge of the cycle is identified solely by redirecting the received ID. In the kth iteration, the identified edge is notified to the target vertex.

[0035] FIG. 2 is the exemplary directed graph of FIG. 1 where a second iteration is performed to find the ID, according to one embodiment of the present invention.

[0036] By adopting the DFS approach, there are five messages with eight IDs sent from vertices 0 and 6.

[0037] In particular, ID {6} is transmitted via edges from vertex 3 to 1, 3 to 4, 4 to 1, 4 to 2, and 5 to 7.

[0038] ID {0} is sent via edges from vertex 3 to 1, 3 to 4, and 5 to 7.

[0039] Thus, the second iteration contains 5 messages with 8 IDs.

[0040] The receiving vertices (3, 4, and 5) transmit the received IDs to their adjacent out-edges.

[0041] FIG. 3 is the exemplary directed graph of FIG. 2 where a third iteration is performed to find the ID, according to one embodiment of the present invention.

[0042] By adopting the DFS approach, there are six messages with 11 IDs sent from vertices 0 and 6.

[0043] In particular, ID {6} is transmitted via edges from vertices 1 to 0, 1 to 2, 2 to 0, 4 to 1, 4 to 2, and 7 to 8.

[0044] ID {0} is sent via edges from vertex 1 to 0, 1 to 2, 4 to 1, 4 to 2, and 7 to 8.

[0045] Thus, the third iteration contains 6 messages with 11 IDs.

[0046] The receiving vertices (0, 1, 2, 4, and 8) send the received IDs to their adjacent target-out edges except for vertex 0. Vertex 0 ignores the received {0} because it is not included twice in a cycle. Also, vertex 0 ignores {6} because vertex 0 and vertex 6 are target vertices. To avoid duplication of the detected cycle, target vertices do not redirect higher IDs.

[0047] FIG. 4 is the exemplary directed graph of FIG. 3 where a fourth iteration is performed to find the ID, according to one embodiment of the present invention.

[0048] By adopting the DFS approach, there are six messages with six IDs sent from vertices 0 and 6.

[0049] In particular, ID {6} is transmitted via edges from vertex 1 to 0, 1 to 2, 2 to 0, and 8 to 6.

[0050] ID {0} is sent via edges from vertex 1 to 0, 1 to 2, 2 to 0, and 8 to 6.

[0051] Thus, the fourth iteration contains 8 messages with 8 IDs.

[0052] Note that the receiving target vertices (0 and 6) have identified candidate last edges for the cycle. For example, vertex 0 knows that the edges from 1 to 0 (0←1) and from 2 to 0 (0←2) could be the last edges for one or more cycles, and vertex 6 knows that the edge from 8 to 6 (6←8) could be the last edge for one or more cycles. To identify the next edge for the cycle in the next k iterations (5 to 8), vertices 0 and 6 send these identified edges to their adjacent out-edges.

[0053] FIG. 5 is the exemplary directed graph of FIG. 4 where a fifth iteration is performed to find the ID, according to one embodiment of the present invention.

[0054] By adopting the DFS approach, there are four messages with 12 IDs sent from vertices 0 and 6.

[0055] In particular, the edge {6←8} is sent via the edges from vertex 6 to 3, 6 to 4, and 6 to 5.

[0056] The two edges {0←1, 0←2} are sent via the edges from vertices 0 to 3 and 0 to 5.

[0057] Thus, the fifth iteration contains four messages with 12 IDs.

[0058] FIG. 6 is the example directed graph of FIG. 5 where a sixth iteration is performed to find the ID, according to one embodiment of the present invention.

[0059] By adopting the DFS approach, there are five messages with 22 IDs sent from vertices 0 and 6.

[0060] In particular, the edge {6←8} is sent via edges from vertices 3 to 1, 3 to 4, 4 to 1, 4 to 2, and 5 to 7.

[0061] The two edges {0←1, 0←2} are sent via edges from vertices 3 to 1, 3 to 4, and 5 to 7.

[0062] Thus, the sixth iteration contains 5 messages with 22 IDs.

[0063] FIG. 7 is the exemplary directed graph of FIG. 6 with the seventh iteration performed to find the ID, according to one embodiment of the present invention.

[0064] By adopting the DFS approach, there are six messages with 32 IDs sent from vertices 0 and 6.

[0065] In particular, the edge {6←8} is sent via edges from vertices 1 to 0, 1 to 2, 2 to 0, 4 to 1, 4 to 2, and 7 to 8.

[0066] The two edges {0←1, 0←2} are sent via edges from vertices 1 to 0, 1 to 2, 4 to 1, 4 to 2, and 7 to 8.

[0067] Thus, the seventh iteration contains 6 messages or 32 IDs.

[0068] After the seventh iteration, if the receiving vertex is the source of the received edge, it can identify the next edge in the cycle. Vertex 1 received {0←1} from vertex 4, so it identifies the path 4→1→0 (0←1←4). Vertex 2 received {0←2) from vertex 1 and vertex 4, so it identifies two paths: 1→2→0 (0←2←1) and 4→2→0 (0←2←4). Vertex 8 received {6←8} from vertex 7, so it can identify the path 7→8→6 (6←8←7).

[0069] When a new edge is detected in a cycle, it is signaled by sending a new path to the target vertex.

[0070] FIG. 8 is the example directed graph of FIG. 7 with the eighth iteration performed to find the ID, according to one embodiment of the present invention.

[0071] By adopting the DFS approach, there are four messages with 15 IDs.

[0072] In particular, the path {0←1←4} is sent via edges from vertex 1 to 0 and from 1 to 2.

[0073] Two paths {0←2←1, 0←2←4} are sent via the edge from vertex 2 to 0.

[0074] The path {6←8←7} is sent via the edge from vertex 8 to 6.

[0075] Therefore, the eighth iteration also contains four messages or 15 IDs.

[0076] Note that the first ID in the path is not vertex 2, so vertex 2 ignores the received path {0←1←4}. On the other hand, vertex 0 and vertex 6 do not ignore the received path because their first vertices are vertex 0 and vertex 6, respectively.

[0077] We also note that target vertices 0 and 6 identify two edge candidates in this cycle and redirect the received paths ({0←1←4, 0←2←1, 0←2←4}, {6←8←7}, respectively) to all adjacent vertices in order to identify a third edge candidate in the next iteration.

[0078] FIG. 9 is the exemplary directed graph of FIG. 8 where the ninth iteration is performed to find the ID, according to one embodiment of the present invention.

[0079] By adopting the DFS approach, there are 5 messages or 24 IDs sent from vertices 0 and 6.

[0080] Specifically, the path {6←8←7} is sent via edges from vertex 6 to 3, 6 to 4, and 6 to 5.

[0081] The path {0←1←4, 0←2←1, 0←2←4} is sent via edges from vertices 0 to 3 and 0 to 5.

[0082] Thus, the 9th iteration contains 5 messages or 27 IDs.

[0083] FIG. 10 is the exemplary directed graph of FIG. 9 where the tenth iteration is performed to find the ID, according to one embodiment of the present invention.

[0084] By adopting the DFS approach, there are 5 messages or 42 IDs.

[0085] Specifically, the path {6←8←7} is sent via edges from vertices 3 to 1, 3 to 4, 4 to 1, 4 to 2, and 5 to 7.

[0086] The path {0←1←4, 0←2←1, 0←2←4} is sent via edges from vertex 3 to 1, 3 to 4, and 5 to 7.

[0087] Thus, the 10th iteration contains 5 messages or 42 IDs.

[0088] After the 10th iteration, the receiving vertex can identify the next edge in the cycle if it is the last edge ID it received. Vertex 1 receives {0←2←1}, so it identifies the edge from 3 to 1; vertex 4 receives {0←1←4, 0←2←4}, so it identifies the edge from 3 to 4; and vertex 7 receives {6←8←7}, so it identifies the edge from 5 to 7.

[0089] 11 illustrates the example directed graph of FIG. 10 after the tenth iteration to detect IDs, according to one embodiment of the present invention. Because vertex 1 knew the edge from vertex 3 to 1, it follows the path 0←2←1, identifying the path 0←2←1←3 in the cycle. Now that a cycle of length 4 has been detected, vertex 1 knows that there is an edge from 0 to 3, and 0←2←1←3 is a cycle. Similarly, because vertex 4 knew the edge from vertex 3 to vertex 4, it follows the paths 0←1←4 and 0←2←4, identifying two cycles: 0←1←4←3, 0←2←4←3. Because vertex 5 knew the edge from vertex 6 to vertex 5, it follows the path 6←8←7, identifying the cycle 6←8←7←5.

[0090] Therefore, with reference to Figures 1-11, the Pregel model is a distributed programming framework focused on providing users with a natural API for programming graph algorithms while managing distribution details, including messaging and fault tolerance, invisibly. The Pregel model is similar in concept to MapReduce, but supports a natural graph API and more efficient iterative computations on graphs. This focus on graphs distinguishes it from other frameworks that hide the details of distribution. Pregel also differs in that it implements a stateful model in which long-lived processes compute, communicate, and modify local state, rather than a dataflow model in which each process computes only on input data and outputs data input from other processes. Pregel was inspired by the Bulk Synchronous Parallel model, which provides a synchronous superstep model of computation and communication. However, a BFS approach is adopted in the Pregel model. An exemplary embodiment of the present invention instead adopts a DFS approach to the Pregel model. In the exemplary embodiment, over k iterations, candidate edges in a cycle are identified solely by redirecting received IDs. In the k-1 iterations, the candidate next edge of the identified edge in the cycle is identified only by the redirection of the received ID, and in the i-th iteration, the identified edge is notified to the target vertex.

[0091] FIG. 12 is a block / flow diagram of an exemplary method for applying depth-first search (DFS) based cycle detection in the Pregel model, according to one embodiment of the present invention.

[0092] In block 1110, the ID of the first vertex is set as the path (information) and the first vertex is set as the target vertex.

[0093] At block 1120, the following steps are repeated n-1 times:

[0094] At block 1130, a path is sent on an out-edge starting from the first vertex, and the path is forwarded n-1 times by subsequent received vertices (via the out-edges).

[0095] At block 1140, one vertex is found before returning to the target vertex.

[0096] At block 1150, the ID of the discovered vertex is added to the path.

[0097] At block 1160, set the discovered vertex as the target vertex and n=n-1.

[0098] FIG. 13 is a block / flow diagram of an exemplary cloud computing environment, according to one embodiment of the present invention.

[0099] Although the present invention includes detailed descriptions relating to cloud computing, implementation of the teachings described herein is not limited to cloud computing environments. Rather, embodiments of the present invention can be practiced in conjunction with any other type of computing environment now known or developed in the future.

[0100] Cloud computing is a service delivery model for enabling convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) that can be rapidly provisioned and released with minimal management effort or interaction with the service provider. This cloud model may include at least five characteristics, at least three service models, and at least four implementation models.

[0101] The characteristics are as follows:

[0102] On-Demand Self-Service: Cloud consumers can unilaterally provision computing capacity, such as server time or network storage, automatically as needed, without the need for human interaction with the service provider.

[0103] Broad network access: Computing power is available over the network and can be accessed through standard mechanisms, facilitating use by heterogeneous thin or thick client platforms (e.g., cell phones, laptops, PDAs).

[0104] Resource Pooling: Computing resources from a provider are pooled and offered to multiple consumers using a multi-tenant model. Various physical and virtual resources are dynamically allocated and reallocated based on demand. Consumers generally have no control or knowledge of the exact location of the resources they are provided with, resulting in a sense of location independence. However, consumers may be able to determine location at a higher level of abstraction (e.g., country, state, data center).

[0105] Rapid Elasticity: Computing capacity can be provisioned quickly and elastically, sometimes automatically, to instantly scale out and quickly release to instantly scale in. To the consumer, the computing power available for provisioning often appears unlimited, and can be purchased at any time and in any quantity.

[0106] Metered Services: Cloud systems leverage measurement capabilities at some level of abstraction appropriate to the type of service (e.g., storage, processing, bandwidth, active user count) to automatically control and optimize resource usage. Resource usage can be monitored, controlled, and reported to provide transparency to both providers and consumers of utilized services.

[0107] The service model is as follows:

[0108] Software as a Service (SaaS): The functionality offered to the consumer is the availability of a provider's applications running on a cloud infrastructure that can be accessed from a variety of client devices through a thin client interface such as a web browser (e.g., webmail). The consumer does not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, storage, or even individual application functionality, except for limited user-specific application configuration settings.

[0109] Platform as a Service (PaaS): The capability offered to consumers is to deploy applications they create or acquire using programming languages and tools supported by the provider onto a cloud infrastructure. The consumer does not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, or storage, but does have control over the deployed applications and, in some cases, the configuration of their hosting environment.

[0110] Infrastructure as a Service (IaaS): The functionality offered to consumers is the provisioning of processors, storage, networking, and other basic computing resources on which they can deploy and run any software, which may include operating systems and applications. The consumer does not manage or control the underlying cloud infrastructure, but has control over the operating system, storage, and deployed applications, and in some cases partial control over some network components (e.g., host firewalls).

[0111] The deployment model is as follows:

[0112] Private Cloud: This cloud infrastructure is dedicated to a specific organization and can be managed by that organization or a third party, and can exist on-premise or off-premise.

[0113] Community Cloud: This cloud infrastructure is shared by multiple organizations to support a specific community with common concerns (e.g., mission, security requirements, policies, and compliance). This cloud infrastructure can be managed by those organizations or a third party and can exist on-premises or off-premises.

[0114] Public cloud: This cloud infrastructure is available to the general public or large industry organizations and is owned by an organization that sells cloud services.

[0115] Hybrid cloud: This cloud infrastructure combines two or more cloud models (private, community, or public), each of which retains its inherent nuances but is bound by standards or specific technologies that enable data and application portability (e.g., cloud bursting for load balancing between clouds).

[0116] A cloud computing environment is a service-oriented environment that emphasizes statelessness, low coupling, modularity, and semantic interoperability. At the core of cloud computing is an infrastructure that includes a network of interconnected nodes.

[0117] FIG. 13 illustrates an exemplary cloud computing environment 1250 for enabling use cases of the present invention. The cloud computing environment 1250 includes one or more cloud computing nodes 1210, to which local computing devices used by cloud consumers (e.g., PDAs or cell phones 1254A, desktop computers 1254B, laptop computers 1254C, or automobile computer systems 1254N, or combinations thereof) can communicate. The nodes 1210 can communicate with each other. The nodes 1210 can be physically or virtually grouped (not shown) in one or more networks, such as, for example, a private, community, public, or hybrid cloud, or combinations thereof, as described above. This enables the cloud computing environment 1250 to provide infrastructure, platform, or software as a service, or combinations thereof, for which cloud consumers do not need to maintain resources on their local computing devices. It should be understood that the types of computing devices 1254A-N shown in FIG. 13 are merely exemplary, and that the computing node 1210 and cloud computing environment 1250 can communicate with any type of electronic device via any type of network or network-addressable connection (e.g., using a web browser), or both.

[0118] Figure 14 is a schematic diagram of exemplary abstraction model layers according to one embodiment of the present invention. It should be understood in advance that the components, layers, and functions shown in Figure 14 are merely exemplary, and embodiments of the present invention are not limited thereto. As shown, the following layers and corresponding functions are provided:

[0119] Hardware and software layer 1360 includes hardware and software components. Examples of hardware components include mainframe 1361, reduced instruction set computer (RISC) architecture-based server 1362, server 1363, blade server 1364, storage device 1365, and network and network components 1366. In some embodiments, software components include network application server software 1367 and database software 1368.

[0120] Virtualization layer 1370 provides an abstraction layer from which the following virtual entities can be provided, for example: virtual servers 1371, virtual storage 1372, virtual networks including virtual private networks 1373, virtual applications and operating systems 1374, and virtual clients 1375.

[0121] As an example, management layer 1380 may provide the following functionality: Resource provisioning 1381 enables dynamic procurement of computing and other resources utilized to execute tasks within the cloud computing environment. Metering and pricing 1382 enables cost tracking as resources are utilized within the cloud computing environment and billing or invoicing for the consumption of these resources. As an example, these resources may include application software licenses. Security enables identification and verification of cloud consumers and tasks, as well as protection for data and other resources. User portal 1383 provides consumers and system administrators with access to the cloud computing environment. Service level management 1384 enables allocation and management of cloud computing resources so that requested service levels are met. Service level agreement (SLA) planning and fulfillment 1385 enables advance arrangement and procurement of anticipated future cloud computing resources required according to SLAs.

[0122] The workload layer 1390 provides examples of functionality available to a cloud computing environment. Examples of workloads and functionality that can be provided from this layer include mapping and navigation 1391, software development and lifecycle management 1392, virtual classroom instruction delivery 1393, data analytics processing 1394, transaction processing 1395, and DFS-based cycle detection in cloud servers 1396.

[0123] FIG. 15 is a block / flow diagram of a practical application for applying depth-first search (DFS) based cycle detection in the Pregel model, according to one embodiment of the present invention.

[0124] Financial crime (fraud, theft, money laundering, etc.) is a large and growing problem that affects nearly all financial institutions in some way, as well as many individuals and, in some cases, society as a whole. Financial institutions are on the front lines of the fight against financial crime and, as such, must devote significant human and technical resources to this effort. Current financial fraud detection processes (including the technologies they use) have limitations in their ability to effectively distinguish between malicious activity and normal financial activity. These limitations result in a tendency for suspicious activity (usually manifested as "alerts") to be over-reported, requiring time-consuming and costly manual review.

[0125] However, the DFS-based approach for cycle detection of the present invention can assist in better detecting, for example, financial crimes. Accordingly, at least one practical application of the present invention relates to fraud detection, particularly as it relates to banking systems.

[0126] Referring back to FIG. 15 , a bank 1420 processes financial transactions 1410. One or more servers 1425 may be used to process such financial transactions 1410 by accessing various databases 1430 containing customer information / data. An exemplary embodiment may be employed to generate a graph 1435 including a plurality of nodes and a plurality of edges connecting the nodes. Accordingly, graph-based feature generation 1440 may be achieved by a DFS approach 1442, as described above. Graph-based feature generation 1440 results in risk assessment and alert filtering, as shown at 1450. Accordingly, accurate alerts 1460 may be generated based on the use of the DFS approach 1442. Such alerts 1460 may be analyzed by investigators 1470.

[0127] Financial crime, therefore, is a widespread and growing type of criminal activity that involves the misuse, misappropriation, or misrepresentation of entities of monetary value. Common subclasses of financial crime include theft, fraud, and money laundering (i.e., obscuring the true origin of monetary entities for the purposes of regulatory evasion or tax avoidance). While the monetary value of such crimes can range from tens of dollars to tens of billions of dollars, the overall negative impact of such crimes goes far beyond monetary value. Rather, the impact can be felt across the societal spectrum.

[0128] Financial institutions have been exploring the use of machine learning techniques to enhance their existing transaction monitoring capabilities. Machine learning techniques offer promising capabilities for identifying suspicious activity from incoming transaction streams and filtering false positives from alerts generated by current technologies, thereby making existing processes more efficient and ultimately more effective. These machine learning techniques rely on a set of features generated from knowledge of the transacting parties, individual and aggregate transaction metrics, and a topology of the relationships between the parties derived from static knowledge and transaction history. Topological features can be calculated according to the DFS-based approach to cycle detection advanced by exemplary embodiments of the present invention. For example, exemplary embodiments of the present invention generate a graph from transfers (e.g., accounts = nodes, transfers = edges). If a (temporal) cycle is present, accounts in the cycle will receive a higher score. Other scores, such as the number of transfers and large balances, can be used by machine learning to alert operators or investigators.

[0129] As used herein, the terms “data,” “content,” “information,” and similar terms may be used interchangeably to refer to data that may be captured, transmitted, received, displayed, or stored, or combinations thereof, in accordance with various exemplary embodiments. Accordingly, the use of any such terms should not be deemed to limit the scope of the present disclosure. Additionally, when a computing device is described herein as receiving data from another computing device, the data may be received directly from the other computing device or indirectly through one or more intermediary computing devices, such as, for example, one or more servers, relays, routers, network access points, base stations, or the like, or a combination thereof.

[0130] To provide for user interaction, embodiments of the subject matter described herein can be implemented on a computer having a display device, such as a CRT (cathode ray tube) or LCD (liquid crystal display) monitor, for displaying information to the user, as well as a keyboard and pointing device, such as a mouse or trackball, by which the user can provide input to the computer. Other types of devices can also be used to provide for user interaction. For example, feedback provided to the user can be any form of sensory feedback, such as visual feedback, auditory feedback, or tactile feedback, and input from the user can be received in any form, such as acoustic, speech, or tactile input.

[0131] The present invention may be a system, a method, or a computer program product, or a combination thereof. The computer program product may include a computer-readable storage medium having stored thereon computer-readable program instructions for causing a processor to carry out aspects of the present invention.

[0132] A computer-readable storage medium may be a tangible device capable of retaining and storing instructions for use by an instruction execution device. The computer-readable storage medium may be, by way of example, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or a suitable combination thereof. More specific examples of computer-readable storage media include portable computer diskettes, hard disks, RAM, ROM, EPROM (or flash memory), SRAM, CD-ROMs, DVDs, memory sticks, floppy disks, mechanically encoded devices having instructions recorded on punch cards or ridge-in-groove structures, or the like, and suitable combinations thereof. Computer-readable storage devices, as used herein, should not be construed as ephemeral signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses passing through a fiber optic cable), or electrical signals transmitted over wires.

[0133] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device or to an external computer or external storage device via a network (e.g., the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof). The network may be comprised of copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium within the respective computing / processing device.

[0134] The computer-readable program instructions for carrying out the operations of the present invention may be either source code or object code written in any combination of one or more programming languages, including assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, or object code written in any combination of one or more programming languages, including object-oriented programming languages such as Smalltalk, C++, etc., and procedural programming languages such as the "C" programming language and similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, as a standalone software package, or partially on the user's computer. Alternatively, the computer may be executed partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) can execute computer-readable program instructions by utilizing state information of the computer-readable program instructions to personalize the computer-readable program instructions in order to carry out aspects of the present invention.

[0135] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0136] These computer-readable program instructions can be provided to at least one processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to generate a machine, such that the instructions, executed by the processor of the computer or other programmable data processing apparatus, generate means for implementing the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams. These computer-readable program instructions can also be stored in a computer-readable storage medium connectable to a computer, a programmable data processing apparatus, or other device, or a combination thereof, that functions in a particular way, such that the computer-readable program instructions stored therein comprise one of a product comprising instructions that implement aspects of the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0137] Computer-readable program instructions, such as instructions to perform the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams on a computer, other programmable apparatus, or other device, can also be loaded into a computer, other programmable data processing apparatus, or other device to perform a series of operational blocks / steps on the computer, other programmable apparatus, or other device to generate a computer-implemented process.

[0138] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of executable implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of instructions, which constitute one or more executable instructions for implementing the specified logical function(s). In some alternative embodiments, the functions shown in the blocks may occur out of the order shown in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may be executed in the reverse order, depending on the functionality involved. It should also be noted that each block of the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by a special-purpose hardware-based system that performs the specified functions or operations or executes a combination of special-purpose hardware and computer instructions.

[0139] References herein to "one embodiment," "an embodiment," and other variations of the present principles mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of the present principles. Thus, appearances of the phrases "in one embodiment" or "in an embodiment," as well as any other variations, appearing in various places throughout this specification are not necessarily all referring to the same embodiment.

[0140] It will be understood that the use of any of the following: " / ", "and / or", "at least one of", e.g., "A / B", "A and / or B", "at least one of A and B" is intended to encompass the selection of only the first listed alternative (A), or the selection of only the second listed alternative (B), or the selection of both alternatives (A and B). As a further example, "A, B, and / or C" and "at least one of A, B, and C" are intended to encompass the selection of only the first listed alternative (A), or the selection of only the second listed alternative (B), or the selection of only the third listed alternative (C), or the selection of only the first and second listed alternatives (A and B), or the selection of only the first and third listed alternatives (A and C), or the selection of only the second and third listed alternatives (B and C), or the selection of all three alternatives (A, B, and C). This can be expanded upon for many of the items listed, as will be readily understood by those of ordinary skill in this and related arts.

[0141] Having described preferred embodiments of a system and method for cycle detection based on depth-first search (DFS) in the Pregel model, which are intended to be illustrative and not limiting, it is noted that modifications and variations can be made by those skilled in the art in light of the above teachings. It will therefore be understood that changes can be made in the particular embodiments described which are within the scope of the invention as outlined by the appended claims. Thus, while aspects of the invention have been described with the detail and particularity required by the patent laws, what is claimed and desired to be protected by Letters Patent is set forth in the appended claims.

[0142] In a preferred embodiment of the present invention, a computer-implemented method for reducing memory consumption in a depth-first search (DFS)-based cycle detection process for detecting n-length cycles in the Pregel model is provided, the computer-implemented method including: generating a graph including a plurality of vertices and edges connecting the plurality of vertices; starting a cycle from a first vertex among the plurality of vertices; setting the identification (ID) of the first vertex as a path and the first vertex as a target vertex; and repeating the following n-1 times: sending the path to an out-edge starting from the first vertex; forwarding the path n-1 times through the out-edges with subsequent received vertices; discovering a vertex before returning to the target vertex; adding the ID of the discovered vertex to the path; and setting the discovered vertex as a target vertex such that n=n-1, where n is the number of iterations. Preferably, in k iterations, a candidate for the last edge in the cycle is identified by only redirecting the received ID. Preferably, in the k iterations, the identified edge is notified to the target vertex. Preferably, the output of the Pregel model is a set of values output by multiple vertices.

Claims

1. 1. A computer-implemented method for reducing memory consumption in a cycle detection process, the computer-implemented method comprising: generating a graph including a plurality of vertices and edges connecting the plurality of vertices; starting a cycle at a first vertex of the plurality of vertices; setting an identification (ID) of the first vertex as a path and the first vertex as a target vertex; repeating a depth-first search (DFS) process n-1 times, where n is the number of iterations; We adopt a DFS approach to detect n-long cycles in the Pregel model by A computer-implemented method comprising:

2. 2. The computer-implemented method of claim 1, wherein the DFS process includes sending the path to an out-edge starting from the first vertex and forwarding the path n-1 times through the out-edge by subsequent received vertices.

3. The computer-implemented method of claim 2 , wherein the DFS process further comprises discovering a vertex before returning to the target vertex.

4. The computer-implemented method of claim 3 , wherein the DFS process further comprises adding IDs of discovered vertices to the path.

5. 5. The computer-implemented method of claim 4, wherein the DFS process further comprises setting the discovered vertex as the target vertex, such that n=n-1.

6. The computer-implemented method of claim 1 , wherein the Pregel model is a programming model that implements bulk synchronous parallel processing for graph analysis.

7. The computer-implemented method of claim 1 , wherein in k iterations, candidates for the last edge in a cycle are identified solely by redirecting received IDs.

8. The computer-implemented method of claim 7 , wherein at the kth iteration, the identified edge is signaled to a target vertex.

9. The computer-implemented method of claim 1 , wherein an output of the Pregel model is a set of values output by the plurality of vertices.

10. A computer program for reducing memory consumption in a cycle detection process, the computer program being executable by a computer and causing the computer to perform the method of any one of claims 1 to 9.

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