Multilayer ceramic capacitors

Abstract

To provide a multilayer ceramic capacitor.SOLUTION: A multilayer ceramic capacitor in one embodiment of the present invention includes a main body including a multilayer structure where a plurality of dielectric layers are stacked and a plurality of internal electrodes stacked with the dielectric layers held therebetween, and an external electrode formed outside the main body and connected to the internal electrode. At least one of the dielectric layers includes one or more grains. The ratio of grains with dislocation to the grains is 20% or more.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a multilayer ceramic capacitor. [Background technology]

[0002] A capacitor is an element that can store electricity, and generally, when two electrodes are placed opposite each other and a voltage is applied, electricity accumulates in each electrode. When a DC voltage is applied, current flows inside the capacitor as electricity is stored, but once storage is complete, the current stops flowing. On the other hand, when an AC voltage is applied, the polarity of the electrodes is reversed and an AC current begins to flow.

[0003] Capacitors are classified into various types depending on the type of electrodes and the type of insulator between the electrodes. For example, there are aluminum electrolytic capacitors, which have aluminum electrodes with a thin oxide film between them, tantalum capacitors, which use tantalum as the electrode material, ceramic capacitors, which use a high-dielectric-constant dielectric such as barium titanate between the electrodes, multi-layer ceramic capacitors (MLCCs), which use a multi-layer structure of high-dielectric-constant ceramic as the dielectric between the electrodes, and film capacitors, which use polystyrene film as the dielectric between the electrodes.

[0004] Among these, multilayer ceramic capacitors have excellent temperature and frequency characteristics, and are easily mounted in a compact package. This has led to their widespread application in a variety of fields, including high-frequency circuits. In recent years, efforts have been made to further miniaturize multilayer ceramic capacitors by thinning the dielectric layers and internal electrodes. However, the thinner the dielectric layer, the stronger the electric field applied to the dielectric layer at the same driving voltage. This increases the need to ensure sufficient DC bias capacitance, which is the effective capacitance of a multilayer ceramic capacitor when a DC electric field is applied. Furthermore, with the trend toward greater integration and miniaturization of electronic devices using multilayer ceramic capacitors, there is a demand for multilayer ceramic capacitor designs that minimize the reduction in effective capacitance at high temperatures due to heat generation.

[0005] Specifically, it is known that DC bias capacitance generally decreases as the grain size of a dielectric increases. Therefore, to ensure DC bias capacitance, it is necessary to reduce the grain size. Furthermore, to mitigate the phenomenon of a decrease in high-temperature effective capacitance, it is necessary to suppress the grain growth of the dielectric and maintain a high core ratio within the core / shell structure formed within the grain. However, suppressing the grain growth of the dielectric to reduce the grain size also reduces the dielectric constant, making it difficult to ensure a high level of capacitance. Therefore, there is a need in the art for a technology that can ensure DC bias capacitance and high-temperature effective capacitance without suppressing the grain growth of the dielectric. Summary of the Invention [Problem to be solved by the invention]

[0006] The present invention aims to provide a multilayer ceramic capacitor that adjusts the density of dislocation defects in a dielectric layer to improve DC bias capacitance while minimizing the decrease in high-temperature effective capacitance. [Means for solving the problem]

[0007] To solve the above-mentioned problems, the present invention proposes a new structure for a multilayer ceramic capacitor, specifically, a multilayer ceramic capacitor including a body including a laminated structure in which a plurality of dielectric layers are stacked, a plurality of internal electrodes stacked with the dielectric layers sandwiched therebetween, and external electrodes formed outside the body and connected to the internal electrodes, at least one of the plurality of dielectric layers including a plurality of grains, the proportion of grains having dislocations being 20% or more.

[0008] In one embodiment, the dislocation defects preferably do not contact grain boundaries between the grains.

[0009] In one embodiment, the dislocation defect may contact only one grain boundary among the grain boundaries between the plurality of grains.

[0010] In one embodiment, the dislocation defects are preferably formed inside the grains between a phase having a tetragonal crystal structure and a phase having a cubic crystal structure.

[0011] In one embodiment, some of the plurality of grains may have a plurality of dislocation defects.

[0012] In one embodiment, the proportion of grains having dislocation defects among the plurality of grains is an average value obtained by measuring values over at least four unit areas of the cut surface of the dielectric layer.

[0013] In one embodiment, the proportion of grains having dislocation defects among the plurality of grains is 40% or less. [Effects of the Invention]

[0014] In the case of a multilayer ceramic capacitor according to an embodiment of the present invention, it is possible to improve DC bias capacitance while minimizing the decrease in high temperature effective capacitance. [Brief explanation of the drawings]

[0015] [Figure 1] 1 is a perspective view schematically illustrating the appearance of a multilayer ceramic capacitor according to an embodiment of the present invention. [Figure 2] FIG. 2 is a cross-sectional view taken along line II' in the multilayer ceramic capacitor of FIG. [Figure 3] 2 is a cross-sectional view taken along line II-II' in the multilayer ceramic capacitor of FIG. [Figure 4] This is an enlarged view of region A in FIG. 2, which shows a schematic diagram of the grains in the dielectric layer. [Figure 5] This is an image of the microstructure of an MLCC photographed with an ADF-STEM. [Figure 6] This is an image of the microstructure of an MLCC photographed with an ADF-STEM. [Figure 7] 1 is an image showing the grain microstructure taken in a comparative example sample. [Figure 8] 1 is an image showing the grain microstructure taken in an example sample. [Figure 9] 10 shows the results of d33 analysis by PFM (Piezoelectric Force Microscopy) according to a comparative example. [Figure 10] 1 shows the results of d33 analysis by PFM (Piezoelectric Force Microscopy) according to an embodiment. [Figure 11] 1 is a graph showing the results of d33 analysis by PFM (Piezoelectric Force Microscopy) according to a comparative example and an example. [Figure 12] 1 is a graph showing the results of measuring the high temperature TCC (Temperature Coefficient of Capacitance) in a comparative example and an example. DETAILED DESCRIPTION OF THE INVENTION

[0016] Hereinafter, embodiments of the present invention will be described with reference to specific embodiments and the accompanying drawings. However, the embodiments of the present invention may be modified into several other forms, and the scope of the present invention is not limited to the embodiments described below. Furthermore, the embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Therefore, the shapes and sizes of elements in the drawings may be enlarged or reduced (or highlighted or simplified) for clearer explanation, and elements designated by the same reference numerals in the drawings are the same elements.

[0017] In the drawings, parts not relevant to the description are omitted in order to clearly explain the present invention, thicknesses are exaggerated to clearly depict multiple layers and regions, and components having the same function within the same concept are referred to by the same reference numerals. Furthermore, throughout the specification, when a part "comprises" a certain element, it does not mean that it excludes other elements, but that it may further include other elements, unless otherwise specified.

[0018] Fig. 1 is a perspective view schematically showing the appearance of a multilayer ceramic capacitor according to one embodiment of the present invention. Fig. 2 is a cross-sectional view taken along line II' in the multilayer capacitor of Fig. 1, and Fig. 3 is a cross-sectional view taken along line II-II' in the multilayer capacitor of Fig. 1. Fig. 4 is an enlarged view of region A in Fig. 2, showing a schematic diagram of the grains of the dielectric layer.

[0019] 1 to 4, a multilayer ceramic capacitor 100 according to an embodiment of the present invention includes a body 110 including a dielectric layer 111 and a plurality of internal electrodes 121 and 122 stacked on either side of the dielectric layer 111, and external electrodes 131 and 132. At least one of the plurality of dielectric layers 111 includes a plurality of grains G, some of which have dislocations D. Here, the proportion of the grains G including the dislocations D among the plurality of grains G is 20% or more. When this condition is satisfied, the DC bias capacitance of the multilayer ceramic capacitor 100 can be improved while minimizing a decrease in high-temperature effective capacitance.

[0020] The body 110 has a laminated structure in which a plurality of dielectric layers 111 are stacked in a first direction (X direction). For example, the body 110 is obtained by stacking a plurality of green sheets and then sintering them. The plurality of dielectric layers 111 may be integrated into one body through the sintering process. As shown in FIG. 1, the body 110 has a shape similar to a rectangular parallelepiped. The dielectric layers 111 included in the body 110 may include a ceramic material with a high dielectric constant, such as a BT-based, i.e., barium titanate (BaTiO3)-based ceramic. However, other materials known in the art may also be used as long as sufficient capacitance is obtained. The dielectric layers 111 may further include additives, organic solvents, plasticizers, binders, dispersants, and the like, as needed, in addition to the ceramic material as the main component. The additives may include metal components, which are preferably added in the form of metal oxides during the manufacturing process. Examples of the metal oxide additive may include at least one of MnO2, Dy2O3, BaO, MgO, Al2O3, SiO2, Cr2O3, and CaCO3.

[0021] The plurality of internal electrodes 121, 122 are obtained by printing a paste containing a conductive metal to a predetermined thickness on one surface of a ceramic green sheet and then sintering the printed paste. In this case, the plurality of internal electrodes 121, 122 may include first and second internal electrodes 121, 122 arranged in a third direction (Z direction) facing each other across the body 110, as shown in FIG. 2. Here, the third direction (Z direction) is a direction perpendicular to the first direction (X direction) and the second direction (Y direction). The first and second internal electrodes 121, 122 may have different polarities when connected to different external electrodes 131, 132 and are electrically isolated from each other by a dielectric layer 111 disposed therebetween. However, the number of external electrodes 131, 132 and the manner of connection to the internal electrodes 121, 122 may vary depending on the embodiment. Examples of main constituent materials of the internal electrodes 121, 122 include nickel (Ni), copper (Cu), palladium (Pd), and silver (Ag), and alloys of these may also be used.

[0022] The external electrodes 131 and 132 are formed outside the main body 110 and may include first and second external electrodes 131 and 132 connected to the first and second internal electrodes 121 and 122, respectively. The external electrodes 131 and 132 may be formed by preparing a paste containing a conductive metal and then applying the paste to the main body 110. Examples of conductive metals include nickel (Ni), copper (Cu), palladium (Pd), gold (Au), or alloys thereof. The external electrodes 131 and 132 may further include a plating layer containing Ni, Sn, etc.

[0023] As described above, in this embodiment, at least one of the dielectric layers 111 includes a plurality of grains G, and the proportion of the grains G containing dislocation defects D among the plurality of grains G is 20% or more. It is generally known that the fewer defects within the grains G, the better. However, according to the inventors' research, when the dislocation defects D present in the grains G are present at a certain proportion or more, characteristics such as DC bias are improved. As described above, the dielectric layer 111 may have a composition containing a barium titanate component and an additive component, and a ferroelectric phase having a tetragonal crystal structure and a relaxor phase having a cubic crystal structure coexist within the grains G. When these two phases are aligned in the c-axis direction, DC bias capacitance can be improved. In other words, DC bias capacitance essentially means the capacitance when domains are aligned in the c-axis direction when a DC electric field is applied, so if the internal domains of the dielectric are fabricated in a form aligned in the c-axis direction, it is possible to minimize the capacitance reduction due to domain wall pinning.

[0024] When the ferroelectric and relaxor phases are aligned in one direction, numerous dislocation defects may occur during the process of stabilizing and aligning the two phases. This is due to increased stress in the c-axis direction. As a result, increasing the density of dislocation defects D in the dielectric layer 111 increases the DC bias capacitance. Furthermore, increasing the density of dislocation defects D reduces the extrinsic capacitance contribution due to temperature-sensitive domain wall vibration, thereby suppressing the decrease in high-temperature effective capacitance. However, excessively high density of dislocation defects D can degrade the performance and reliability of the dielectric layer 111. Specifically, dislocation defects D, which are line defects, can serve as crack propagation paths during crack propagation, potentially creating weak areas of mechanical strength. Furthermore, dislocation defects D have a high charge concentration in defect chemistry, which can serve as a path for charge migration, potentially acting as a conduction path for leakage current. The upper limit of the density of dislocation defects D must be determined taking these side effects into consideration. The proportion of grains G containing dislocation defects D can be set to 40% or less.

[0025] Regarding the form of dislocation defects D, measurement methods, and methods for achieving a high dislocation defect density, first, as shown in Figure 4, dislocation defects D cannot contact the grain boundaries between multiple grains G. Also, some dislocation defects D may be formed in a range that contacts only one grain boundary but does not completely cross the grain G. In this case, as mentioned above, dislocation defects D may be formed within the grain G between a phase having a tetragonal crystal structure and a phase having a cubic crystal structure. Also, some of the multiple grains G may have multiple dislocation defects D.

[0026] For example, at least four points are set on the entire cross section of the dielectric layer 111, and the percentage of grains G having dislocation defects D per unit area is calculated based on these points. The presence or absence of dislocation defects D can be determined by observing the microstructure using an annular dark field scanning TEM (ADF-STEM). Figures 5 and 6 show images of the microstructure of an MLCC taken with an FEI Osiris model under dark field conditions, with an accelerating voltage of 200 kV, a camera length of 110 nm, a magnification of 40,000, and dark field imaging. As can be seen in Figure 5, dislocation defects are indicated by white lines that do not completely cross the grains. However, while the color of dislocation defects observed during ADF-STEM imaging can vary depending on the camera length (the distance between the sample and the image frame), setting the measurement conditions to a specific camera length (e.g., less than 150 nm) makes it possible to distinguish dislocation defects from contrast caused by other factors. That is, dislocation defects can be clearly distinguished in shape from other defects such as twin boundaries and domain boundaries, which appear in the microstructure of Figure 6. Furthermore, when photographing with ADF-STEM, it is desirable to use an accelerating voltage in the range of 80-300 kV.

[0027] The following describes a method for controlling the dislocation defect density and experimental examples. Research by the present inventors has revealed that a relatively highly reducing atmosphere (hereinafter referred to as a "strong reducing atmosphere") used for sintering a dielectric layer results in a high dislocation defect density. A "strong reducing atmosphere" refers to an atmosphere with a relatively high H2 partial pressure during sintering. In this embodiment, a H2 / N2 concentration ratio of 0.2-1.0% is used as the reference. In contrast, a "weak reducing atmosphere" refers to an H2 / N2 concentration ratio of less than 0.2% during sintering. In this invention, the reducing atmosphere is determined based on the H2 concentration rather than the oxygen partial pressure. This is based on research findings that the H2 concentration affects cation diffusion behavior. Regarding the H2 concentration ratio of 0.2-1.0%, 0.2% is set as the lower limit necessary for diffusion control, and 1.0% is set as the upper limit due to the secondary effect of oxygen vacancy formation (IR reduction). In a heavily reducing atmosphere set according to the above criteria, additive components (e.g., Mg) penetrate into the BT phase to form a segregation phase, which reduces the rate at which rare earth elements penetrate into the BT phase. This adjusts the rate at which the cubic phase is formed by the penetration of rare earth elements, and ultimately maintains a balance between the amounts of the tetragonal and cubic phases, allowing sufficient dislocation defects to be formed.

[0028] The inventors prepared samples in the comparative example and the example and analyzed dislocation defects present in the grains of the dielectric layer using the following measurement method. -The comparative example was fired in an atmosphere of 0.1% H2 to N2, and the example was fired in an atmosphere of 0.56% H2 to N2. - 4 points measured per sample -Measurement magnification: ×40,000 Measurement area: Approximately 3 μm × 3 μm (The shape and number of grains in the unit area should preferably be such that a total of 150 or more grains are included.) -Measurement of the number of grains containing dislocation defects and the total number of grains in each measurement area

[0029] Figures 7 and 8 are images showing the grain microstructures of the comparative example and example samples, respectively. In Figures 7 and 8, arrows indicate dislocation defects at four designated points on the cut surface of each sample. Table 1 below summarizes the percentage of grains with dislocation defects in the comparative example and example samples.

[0030] [Table 1]

[0031] According to the experimental results, the ratio of grains having dislocation defects among a plurality of grains was measured to be 0.11 (11%) in the comparative example and 0.21 (21%) in the example.

[0032] 9 to 11 show the d of PFM (Piezoelectric Force Microscopy) according to the comparative example and the embodiment, respectively. 33 This shows the results of the analysis, 33 This is an analytical method that can confirm the degree of domain alignment and the magnitude of polarization by analyzing the phase deviation and amplitude. In this experiment, PFM analysis was performed on Park System's NX10 model using a Budget Sensors Multi75E-G tip at a frequency of 1 Hz over a 1 μm x 1 μm area. Figures 9 and 10 show the d 33 The phase mapping results are shown in Fig. 11, where the color indicates the angle at which the domains are aligned perpendicular to the applied voltage. The smaller the color deviation, the higher the degree of alignment in one direction. As a result of the experiment, the example (Fig. 10) with a relatively high dislocation defect density had less color deviation than the comparative example (Fig. 9), which means that the degree of alignment in the c-axis direction of the dielectric internal domains was higher. Fig. 11 shows the d 33This is a graph showing the amplitude of the displacement as a function of the applied voltage, and it can be seen that the displacement increased in the example. This can be understood as being due to the fact that the degree of alignment of the domains in one direction was high, which increased the overall magnitude of polarization. The above results indicate that increasing the dislocation defect density in the dielectric layer can further increase the degree of alignment of the domains in the direction of the applied electric field.

[0033] Table 2 below shows the results of measuring the DC bias capacitance (C), capacitance reduction rate (ΔC), and Df (Dissipation Factor) in the comparative example and the example.

[0034] [Table 2]

[0035] As can be seen from the above results, when the DC bias capacitance of the two samples was measured according to the DC voltage, the Example with a high dislocation defect density had a lower DC bias capacitance reduction rate than the Comparative Example at all DC voltages. In the Example, even though the DC bias capacitance was not improved by suppressing grain growth, the nominal capacitance value remained almost the same, indicating that the DC bias capacitance can be improved without a decrease in capacitance.

[0036] 12 shows the results of measuring the temperature coefficient of capacitance (TCC) at high temperatures in the comparative example and the example. It can be seen that the example with a high dislocation defect density had an increased effective high-temperature capacity, and the capacity loss at high temperatures was improved by 36.7% at 85°C.

[0037] Thus, the experimental results described above indicate that the DC bias capacitance and high-temperature effective capacitance can be increased by increasing the dislocation defect density in the dielectric grains to control the degree of domain alignment and extrinsic capacitance contribution.

[0038] The present invention is not limited by the above-described embodiments and the accompanying drawings, but is limited by the scope of the accompanying claims. Therefore, it is obvious to those skilled in the art that various substitutions, modifications, and changes can be made without departing from the technical idea of the present invention as set forth in the claims, and these also belong to the technical idea as set forth in the claims. [Explanation of symbols]

[0039] 100: Multilayer ceramic capacitor 110:Main body 111: Dielectric layer 121, 122: Internal electrode 131, 132: External electrode

Claims

1. a main body including a laminated structure in which a plurality of dielectric layers are laminated, and a plurality of internal electrodes laminated with the plurality of dielectric layers sandwiched therebetween; an external electrode formed on the outside of the body and connected to the plurality of internal electrodes; At least one of the plurality of dielectric layers includes a plurality of grains containing barium titanate, and a ratio of grains having dislocation defects among the plurality of grains is 20% or more; A multilayer ceramic capacitor, wherein the proportion of grains having dislocation defects among the plurality of grains is 40% or less.

2. 2. The multilayer ceramic capacitor according to claim 1, wherein at least one of the dislocation defects does not contact any of the grain boundaries between the plurality of grains.

3. 3. The multilayer ceramic capacitor according to claim 1, wherein at least one of the dislocation defects is in contact with only one grain boundary among the grain boundaries between the plurality of grains.

4. 4. The multilayer ceramic capacitor according to claim 1, wherein the dislocation defects are formed inside the grains between a phase having a tetragonal crystal structure and a phase having a cubic crystal structure.

5. The multilayer ceramic capacitor according to claim 1 , wherein some of the plurality of grains have a plurality of dislocation defects.

6. 6. The multilayer ceramic capacitor according to claim 1, wherein the proportion of grains having dislocation defects among the plurality of grains is an average value obtained by measuring values over at least four unit areas of the cut surfaces of the plurality of dielectric layers.

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