Multilayer ceramic electronic components

Abstract

To provide a multilayer ceramic electronic component.SOLUTION: A multilayer ceramic electronic component according to an embodiment of the present invention includes: a ceramic body including a dielectric layer and first and second internal electrodes, the first and second internal electrodes being disposed to face each other across the dielectric layer; a first external electrode connected to the first internal electrode; and a second external electrode connected to the second internal electrode. The ceramic body includes: a capacitance formation portion which has first and second surfaces facing each other in a first direction, third and fourth surfaces facing each other in a second direction, and fifth and sixth surfaces facing each other in a third direction and which includes the first internal electrode and the second internal electrode stacked in the third direction to form capacitance; a first margin portion disposed on the third and fifth surfaces of the capacitance formation portion and a second margin portion disposed on the fourth and sixth surfaces of the capacitance formation portion.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a multilayer ceramic electronic component. [Background technology]

[0002] In general, electronic components using ceramic materials, such as capacitors, inductors, piezoelectric elements, varistors, or thermistors, include a ceramic body made of a ceramic material, internal electrodes formed inside the body, and external electrodes disposed on the surface of the ceramic body so as to be connected to the internal electrodes.

[0003] Recently, as electronic products have become smaller and more multifunctional, chip components have also tended to become smaller and more functional. This has led to a demand for small, high-capacity multilayer ceramic electronic components.

[0004] In the past, the area of the dielectric layer was made larger than the area of the internal electrode, and a margin area was formed around the remaining area of the internal electrode, excluding the portion connected to the external electrode. However, in this case, when tens to hundreds of dielectric layers are stacked, the dielectric layer stretches to fill the gap, causing the internal electrode to warp. When the internal electrode warps, the breakdown voltage (BDV) in that portion decreases, which is a problem.

[0005] To solve this problem, a method of attaching a separately prepared sheet-like margin has recently been used, but when a separately prepared sheet is attached to form the margin, there is a problem in that delamination occurs between the margin and the ceramic body. Summary of the Invention [Problem to be solved by the invention]

[0006] One of the various objects of the present invention is to provide a multilayer ceramic electronic component with improved moisture resistance reliability.

[0007] One of the various objects of the present invention is to provide a multilayer ceramic electronic component having improved mechanical strength. [Means for solving the problem]

[0008] A multilayer ceramic electronic component according to an embodiment of the present invention includes a ceramic body including a dielectric layer and first and second internal electrodes arranged to face each other with the dielectric layer interposed therebetween; a first external electrode connected to the first internal electrode; and a second external electrode connected to the second internal electrode, wherein the ceramic body includes first and second surfaces facing each other in a first direction, third and fourth surfaces facing each other in a second direction, and fifth and sixth surfaces facing each other in a third direction, and includes a capacitive portion including the first internal electrodes and the second internal electrodes stacked in the third direction to form a capacitance; a first margin portion arranged on the third and fifth surfaces of the capacitive portion; and a second margin portion arranged on the fourth and sixth surfaces of the capacitive portion and distinct from the first margin portion.

[0009] According to another embodiment of the present invention, there is provided a multilayer ceramic electronic component comprising: a ceramic body including a dielectric layer and first and second internal electrodes arranged to face each other with the dielectric layer therebetween; a first external electrode connected to the first internal electrode; and a second external electrode connected to the second internal electrode, wherein the ceramic body includes first and second surfaces facing each other in a first direction, third and fourth surfaces facing each other in a second direction, and fifth and sixth surfaces facing each other in a third direction; a capacitive portion including the first and second internal electrodes stacked in the third direction to form a capacitance; a first margin portion arranged on the third and fifth surfaces of the capacitive portion; and a second margin portion arranged on the fourth and sixth surfaces of the capacitive portion. [Effects of the Invention]

[0010] One of the effects of the present invention is that it can improve the moisture resistance reliability of multilayer ceramic electronic components.

[0011] One of the effects of the present invention is that it can improve the mechanical strength of a multilayer ceramic electronic component.

[0012] However, the various beneficial advantages and effects of the present invention are not limited to the above, and will be more easily understood in the course of describing specific embodiments of the present invention. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a perspective view schematically showing a multilayer ceramic electronic component according to one embodiment of the present invention. [Figure 2] FIG. 2 is a perspective view schematically illustrating the ceramic body of FIG. [Figure 3] FIG. 2 is a perspective view schematically showing a capacitance section of FIG. [Figure 4] FIG. 2 is a cross-sectional view taken along line II' in FIG. [Figure 5] FIG. 2 is a cross-sectional view taken along line II-II' in FIG. [Figure 6] FIG. 6 is an enlarged view of areas A and B in FIG. 5. [Figure 7] FIG. 4 is a perspective view schematically illustrating a ceramic body of a multilayer ceramic electronic component according to another embodiment of the present invention. [Figure 8] FIG. 8 is a cross-sectional view of FIG. [Figure 9] 9 is an enlarged view of areas C and D in FIG. 8. [Figure 10] FIG. 4 is a perspective view schematically illustrating a ceramic body of a multilayer ceramic electronic component according to another embodiment of the present invention. [Figure 11] FIG. 11 is a cross-sectional view of FIG. [Figure 12] 12 is an enlarged view of areas E and F in FIG. 11. FIG. [Figure 13] 2 is a perspective view schematically showing a part of the manufacturing process of the multilayer ceramic electronic component of FIG. 1. FIG. [Figure 14] 10 is a photograph of a cover portion where delamination has occurred in a conventional structure. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, embodiments of the present invention will be described with reference to specific embodiments and the accompanying drawings. This is not intended to limit the technology described in this specification to a specific embodiment, but should be understood to include various modifications, equivalents, and / or alternatives of the embodiments of the present invention. Furthermore, similar reference numerals may be used for similar components in connection with the description of the drawings.

[0015] In the drawings, in order to clearly explain the present invention, parts that are not relevant to the explanation are omitted, thicknesses are shown exaggerated to clearly represent multiple layers and regions, and components that have the same function within the same concept may be described using the same reference symbols.

[0016] In this specification, the terms "have," "can have," "include," or "can include" refer to the presence of a given feature (e.g., a value, function, operation, or component such as a part) and do not exclude the presence of additional features.

[0017] As used herein, expressions such as "A or B," "at least one of A and / or B," or "one or more of A and / or B" can include all possible combinations of the items listed together. For example, "A or B," "at least one of A and B," or "at least one of A or B" can refer to all cases where (1) at least one A is included, (2) at least one B is included, or (3) both at least one A and at least one B are included.

[0018] In the drawings, the X direction can be defined as the first direction, L direction or length direction, the Y direction can be defined as the second direction, W direction or width direction, and the Z direction can be defined as the third direction, T direction or thickness direction.

[0019] The present invention relates to a multilayer ceramic electronic component. FIGS. 1 to 6 are diagrams schematically illustrating a multilayer ceramic electronic component according to an embodiment of the present invention. Referring to FIGS. 1 to 6, a multilayer ceramic electronic component 100 according to an embodiment of the present invention includes a ceramic body 110 including a dielectric layer 111, a first internal electrode 121, and a second internal electrode 122 disposed to face each other with the dielectric layer 111 interposed therebetween, a first external electrode 131 connected to the first internal electrode 121, and a second external electrode 132 connected to the second internal electrode 122. The ceramic body 110 has a first surface (S1) and a second surface (S2) facing each other in a first direction (X direction). The capacitor 120 may include a third surface (S3) and a fourth surface (S4) facing each other in the second direction (Y direction), and a fifth surface (S5) and a sixth surface (S6) facing each other in the third direction (Z direction), and may include a capacitive section 120 in which capacitance is formed including a first internal electrode 121 and a second internal electrode 122 stacked in the third direction (Z direction), a first margin portion 113 arranged on the third surface (S3) and the fifth surface (S5) of the capacitive section 120, and a second margin portion 112 arranged on the fourth and sixth surfaces (S6) of the capacitive section 120.

[0020] In the ceramic body 110 of the above embodiment, the first margin portion 113 being arranged on the third and fifth surfaces (S5) of the capacitive portion 120 may mean that the first margin portion is arranged on two of both surfaces in the second direction and both surfaces in the third direction (Z direction) of the capacitive portion 120. Furthermore, in the ceramic body 110, the second margin portion 112 being arranged on the fourth and sixth surfaces of the capacitive portion 120 may mean that the second margin portion 112 is arranged on two of both surfaces in the second direction and both surfaces in the third direction (Z direction) of the capacitive portion 120. That is, the multilayer ceramic electronic component of the present embodiment may have a structure in which two margin portions, the first margin portion and the second margin portion 112, are arranged on both surfaces in the second direction and both surfaces in the third direction (Z direction).

[0021] FIG. 14 is a photograph of a YZ cross section of a conventional multilayer ceramic electronic component. Conventional multilayer ceramic electronic components have a structure in which cover portions are attached to the top and bottom of a capacitor portion, and then margin portions are attached to cover both sides of the capacitor portion and the cover portion. In this case, a problem of gaps occurring in the margin portions can arise during the manufacturing process. FIG. 14 shows a multilayer ceramic electronic component in which gaps occur in the margin portions. Referring to FIG. 14, when delamination occurs in the margin portions, the internal electrodes are immediately exposed to external moisture, etc.

[0022] In contrast, the present invention has a structure in which the cover portion and margin portion are not formed separately. Delamination between the cover portion and margin portion may occur due to differences in the polishing degree of the cover portion and margin portion during the polishing of the ceramic body, such as differences in density between the cover portion and margin portion, or due to differences in the shrinkage behavior of the cover portion and margin portion during the sintering process. In the multilayer ceramic electronic component 100 according to the present invention, the first margin portion 113 is disposed on the third surface (S3) and fifth surface (S5) of the capacitive portion 120, and the second margin portion 112 is disposed on the fourth surface (S4) and sixth surface (S6) of the capacitive portion 120, thereby reducing the number of joint points between the cover portion and margin portion and thereby reducing the possibility of delamination.

[0023] In one embodiment of the present invention, the ceramic body 110 may include a capacitive portion 120 , a first margin portion 113 and a second margin portion 112 .

[0024] The specific shape of the ceramic body 110 is not particularly limited, but as shown in the drawing, the ceramic body 110 may have a hexahedral shape or a shape similar thereto. Furthermore, the ceramic body 110 may have a substantially hexahedral shape, although not a hexahedral shape with perfectly straight lines, due to shrinkage of the ceramic powder contained in the ceramic body 110 during the firing process. The ceramic body 110 may be rounded to remove sharp corners, as necessary. The rounding may be performed by, for example, barrel polishing, but is not limited thereto.

[0025] The capacitive section 120 of the multilayer ceramic electronic component 100 according to the present invention may be formed by alternately stacking dielectric layers 111, first internal electrodes 121, and second internal electrodes 122. The dielectric layers 111, first internal electrodes 121, and second internal electrodes 122 may be stacked in a third direction (Z direction). The plurality of dielectric layers 111 forming the capacitive section 120 may be in a fired state, and the boundaries between adjacent dielectric layers 111 may be integrated to the extent that they are difficult to identify without using a scanning electron microscope (SEM).

[0026] According to an embodiment of the present invention, the material for forming the dielectric layer 111 is not particularly limited as long as it can provide sufficient capacitance. For example, a barium titanate-based material, a lead complex perovskite-based material, or a strontium titanate-based material may be used. 1-x Ca x )(Ti 1-y (Zr, Sn, Hf) y )O3 (where 0≦x≦1, 0≦y≦0.5), or the like, can be used. The material forming the dielectric layer 111 may be a powder of barium titanate (BaTiO3) or the like, to which various ceramic additives, organic solvents, plasticizers, binders, dispersants, etc. may be added depending on the purpose of the present invention.

[0027] The dielectric layer 111 may be formed by adding additives as needed to a slurry containing the above-mentioned materials, coating the slurry on a carrier film, and drying the coating to form a plurality of ceramic sheets. The ceramic sheets may be formed by forming the slurry into sheets having a thickness of several μm using a doctor blade method, but are not limited to this.

[0028] The first and second internal electrodes 121 and 122 may be laminated such that their cross sections are exposed at opposite ends of the ceramic body 110. Specifically, the first and second internal electrodes 121 and 122 may be exposed at both surfaces of the ceramic body 110 in a first direction (X direction), and the first internal electrode 121 may be exposed at a first surface (S1) of the ceramic body 110, and the second internal electrode 122 may be exposed at a second surface (S2) of the ceramic body 110.

[0029] The material for forming the first and second internal electrodes 121, 122 is not particularly limited, and may be formed using a conductive paste containing one or more of silver (Ag), palladium (Pd), gold (Au), platinum (Pt), nickel (Ni), copper (Cu), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof.

[0030] The ceramic body 110 may be formed by alternately stacking ceramic green sheets, each having a dielectric layer on which the first internal electrode 121 is printed, and ceramic green sheets, each having a dielectric layer on which the second internal electrode 122 is printed, in a third direction (Z direction). The first and second internal electrodes 121 and 122 may be printed by screen printing, gravure printing, or the like, but are not limited thereto.

[0031] The ceramic body 110 according to one embodiment of the present invention may include a capacitive portion 120, a first margin portion 113 disposed on a third surface (S3) and a fifth surface (S5) of the capacitive portion 120, and a second margin portion 112 disposed on a fourth surface (S4) and a sixth surface (S6) of the capacitive portion 120.

[0032] In one embodiment of the present invention, the first margin portion 113 of the multilayer ceramic electronic component 100 may be disposed in contact with the third surface (S3) and the fifth surface (S5) of the capacitive portion 120 simultaneously, and the second margin portion 112 may be disposed in contact with the fourth surface (S4) and the sixth surface (S6) of the capacitive portion 120 simultaneously. Referring to FIGS. 1 to 6 , the first margin portion 113 may be attached in contact with the third surface (S3) of the capacitive portion 120, and may extend to the fifth surface (S5) of the capacitive portion 120 and be attached in contact with the fifth surface (S5) of the capacitive portion 120. Furthermore, the second margin portion 112 may be attached in contact with the fourth surface (S4) of the capacitive portion 120, and may extend to the sixth surface (S6) of the capacitive portion 120 and be attached in contact with the sixth surface (S6) of the capacitive portion 120.

[0033] In this embodiment, the first margin portion 113 is disposed in contact with two sides of the capacitive portion 120 at the same time, and the second margin portion 112 is disposed in contact with the other two sides of the capacitive portion 120 at the same time, so that the exterior of the capacitive portion 120 can be completely covered with only two margin portions. Compared to the conventional method that uses four components, two cover portions and two margin portions, covering the exterior of the capacitive portion 120 with only two margin portions as in the above embodiment reduces the number of cases where delamination can occur and increases the mechanical strength of the electronic component.

[0034] The first margin portion 113 and the second margin portion 112 may each have a single structure. This means that the first margin portion 113 and the second margin portion 112 are each made up of a single component, rather than being made up of multiple components joined together. That is, the multilayer ceramic electronic component 100 according to this embodiment may have two components surrounding the exterior of the capacitive portion 120. By reducing the number of components attached to the exterior of the capacitive portion 120 as in this embodiment, it is possible to minimize the paths through which moisture and the like can penetrate from the outside.

[0035] In one example, the ceramic body 110 may include a first interface 113a and a second interface 112a where the first margin portion 113 and the second margin portion 112 are in contact with each other. In this specification, the term "interface" may refer to a surface where two adjacent layers are distinguishable from each other. Therefore, the second margin portion 112 of the multilayer ceramic electronic component 100 according to this example is distinguishable from the first margin portion 113. The distinguishable state may refer to the two layers being distinguished by physical, chemical, and / or simple optical differences. The interface may be visually confirmed using a scanning electron microscope (SEM) or the like, but is not limited thereto. If visual confirmation is difficult, the interface may be confirmed by analyzing the physical properties of the first margin portion 113 and the second margin portion 112.

[0036] Fig. 5 is a cross-sectional view taken along line II-II' in Fig. 1, and Fig. 6 is an enlarged view of areas A and B in Fig. 5. Referring to Fig. 5 and Fig. 6, the ceramic body 110 of the multilayer ceramic electronic component 100 according to the present invention may include two interfaces where the first margin portion 113 and the second margin portion 112 meet, and the interfaces may be divided into, for example, a first interface 113a and a second interface 112a.

[0037] In the above example, the first interface between the first margin portion 113 and the second margin portion 112 of the multilayer ceramic electronic component 100 of the present invention may be located on the same plane as the third surface (S3) of the capacitive portion 120, and the second interface may be located on the same plane as the fourth surface (S4) of the capacitive portion 120. Referring to FIGS. 5 and 6 , the first interface 113a of the multilayer ceramic electronic component 100 according to this example may be located on the same plane as the fourth surface (S4) of the capacitive portion 120, and the second interface 112a may be located on the same plane as the third surface (S3) of the capacitive portion 120. "The interface being located on the same plane as one surface of the capacitive portion 120" does not necessarily mean "the same plane" in the strict sense, but may also mean that the angle between the interface and one surface of the capacitive portion is within a certain range. The angle range may mean, for example, an angle of 10° or less, and the lower limit is not particularly limited, but may be, for example, 0° or more. The angle of any one surface of the interface and the capacitor may refer to the average angle of the surfaces in contact with any five points of the interface and the surface of the capacitor.

[0038] In one embodiment of the present invention, only the first margin portion 113 may be arranged at the corner where the third surface (S3) and the fifth surface (S5) of the capacitive portion 120 of the multilayer ceramic electronic component 100 of the present invention meet, and only the second margin portion 112 may be arranged at the corner where the fourth surface and the sixth surface of the capacitive portion 120 meet. In the multilayer ceramic electronic component 100 of the present invention, two margin portions, the first margin portion 113 and the second margin portion 112, may be arranged to surround four surfaces of the capacitive portion 120, so that the first margin portion 113 and the second margin portion 112 may each be arranged to cover two surfaces of the capacitive portion 120. Therefore, only the first margin portion 113 may be arranged at the corner where the third surface (S3) and the fifth surface (S5) of the capacitive portion 120 of the multilayer ceramic electronic component 100 of this preferred embodiment meet, and only the second margin portion 112 may be arranged at the corner where the fourth surface (S4) and the sixth surface (S6) of the capacitive portion 120 meet. That is, the same margin portion may be arranged on the third surface (S3) and the fifth surface (S5) of the capacitive portion 120, and the same margin portion may be arranged on the fourth surface (S4) and the sixth surface (S6) of the capacitive portion 120. This may mean that one margin portion covers two surfaces of the capacitive portion 120 at the same time.

[0039] In one embodiment of the present invention, the maximum widths of the first margin portion 113 and the second margin portion 112 of the multilayer ceramic electronic component 100 in the second direction (Y direction) may be greater than the maximum vertical distance between the third surface (S3) and the fourth surface (S4) of the capacitive portion 120. The maximum widths of the first margin portion 113 and the second margin portion 112 in the second direction (Y direction) may refer to the maximum distance from the interface between the first margin portion 113 and the second margin portion 112 to either one surface of the first margin portion 113 or the second margin portion 112 in the second direction. Furthermore, the vertical distance between the third surface (S3) and the fourth surface (S4) of the capacitive portion 120 may be a value measured based on a line perpendicular to the third surface (S3) of the capacitive portion 120 and a line perpendicular to the fourth surface (S4) of the capacitive portion 120, and the maximum value of the vertical distance between the third surface (S3) and the fourth surface (S4) of the capacitive portion 120 may mean the maximum value among the values measured based on the perpendicular lines.

[0040] In the above embodiment, the sum of the width in the second direction (Y direction) of the fifth surface (S5) of the capacitive portion 120 and the height in the third direction (Z direction) of the third surface (S3) may be smaller than the sum of the width in the second direction (Y direction) and the height in the third direction (Z direction) of the first margin portion 113. Furthermore, the sum of the width in the second direction (Y direction) of the sixth surface (S6) of the capacitive portion 120 and the height in the third direction (Z direction) of the fourth surface (S4) may be smaller than the sum of the width in the second direction (Y direction) and the height in the third direction (Z direction) of the second margin portion 112. This may mean that, in the present embodiment, both surfaces in the second direction (Y direction) and both surfaces in the third direction (Z direction) of the capacitive portion 120 of the multilayer ceramic electronic component 100 of the present invention can be entirely covered by only the first margin portion 113 and the second margin portion 112.

[0041] In one example, the XZ cross section of the first margin portion 113 and / or the second margin portion 112 of the multilayer ceramic electronic component 100 according to the present invention may be L-shaped. The XZ cross section of the first margin portion 113 and / or the second margin portion 112 may refer to a cross section of the ceramic body 110 of the multilayer ceramic electronic component 100 cut along a plane perpendicular to the first direction (X direction). The L-shape of the first margin portion 113 and / or the second margin portion 112 may be formed by a cut surface in the second direction (Y direction) and a cut surface in the third direction (Z direction) among the cut surfaces of the first margin portion 113 and the second margin portion 112.

[0042] The first margin portion 113 and the second margin portion 112 may include a ceramic material, for example, a barium titanate (BaTiO3)-based ceramic material.

[0043] The first margin portion 113 and the second margin portion 112 may be formed by laminating a single dielectric layer or two or more dielectric layers, respectively, and may basically serve to prevent damage to the internal electrodes due to physical or chemical stress.

[0044] In one embodiment of the present invention, the first margin portion 113 and the second margin portion 112 of the multilayer ceramic electronic component 100 according to the present invention may include, as a main component, a ceramic component having a composition similar to that of the dielectric layer 111 of the capacitive portion 120. In this specification, the term "main component" may refer to a component that occupies a relatively larger weight percentage than other components, and may refer to a component that accounts for 50 wt% or more based on the weight of the entire composition or all dielectric layers. Additionally, the term "minor component" may refer to a component that occupies a relatively smaller weight percentage than other components, and may refer to a component that accounts for less than 50 wt% based on the weight of the entire composition or all dielectric layers.

[0045] The main component is (Ba 1-x Ca x )(Ti 1-y (Zr, Sn, Hf) y )O3 (where 0≦x≦1, 0≦y≦0.5). The main component may be, for example, a chemical compound in which Ca, Zr, Sn, and / or Hf are partially dissolved in BaTiO3. In the composition formula, x may be in the range of 0 to 1, and y may be in the range of 0 to 0.5, but is not limited thereto. For example, when x is 0, y is 0, and z is 0 in the composition formula, the main component may be BaTiO3.

[0046] In one example, the first and second margin portions 113, 112 of the multilayer ceramic electronic component 100 according to the present invention may contain at least one selected from the group consisting of sodium (Na), lithium (Li), and boron (B) as a minor component. In another example, the first and second margin portions 113, 112 of the multilayer ceramic electronic component 100 according to the present invention may contain magnesium (Mg) as a minor component. By adjusting the contents of the minor components of the first and second margin portions 113, 112 as described above, the density of the first and second margin portions 113, 112 can be adjusted, thereby improving moisture resistance.

[0047] According to one example of the present invention, the average thickness of the first margin portion 113 and / or the second margin portion 112 of the multilayer ceramic electronic component 100 may be in the range of 10 μm or more and 25 μm or less. In this specification, "thickness" may refer to the thickness of a certain component measured in a direction perpendicular to the surface of the component, and "average thickness" may refer to the calculated average of thicknesses measured at points equally spaced along the first direction (X direction) in a region where the first margin portion 113 and / or the second margin portion 112 is disposed, with respect to a cut surface (XY plane) that passes through the center of the multilayer ceramic electronic component 100 and is cut in a direction perpendicular to the Z axis.

[0048] In one embodiment of the present invention, the thickness deviation (|ab| / a) of the average thickness (b) of the first margin portion 113 disposed on the fifth surface (S5) of the capacitive portion 120 with respect to the average thickness (a) of the first margin portion 113 disposed on the third surface (S3) of the capacitive portion 120 of the multilayer ceramic electronic component 100 may be 5% or less. The average thickness (a) of the first margin portion 113 disposed on the third surface (S3) of the capacitive portion 120 may be a value measured by the above-mentioned method for the first margin portion 113 in contact with the third surface (S3) of the capacitive portion 120. Furthermore, the average thickness (b) of the first margin portion 113 disposed on the fifth surface (S5) of the capacitive portion 120 may refer to the average thickness in the third direction (Z direction) of the first margin portion 113 in contact with the fifth surface (S5) of the capacitive portion 120, and may refer to the calculated average of distances in the third direction (Z direction) measured at 10 equally spaced points on the XZ cut surface passing through the center of the multilayer ceramic electronic component 100 relative to the first margin portion 113 in contact with the fifth surface (S5) of the capacitive portion 120. The thickness deviation (|ab| / a) of the average thickness (b) of the first margin portion 113 disposed on the fifth surface (S5) of the capacitive portion 120 from the average thickness (a) of the first margin portion 113 disposed on the third surface (S3) of the capacitive portion 120 may be 5% or less, 4% or less, or 3% or less, and the lower limit is not particularly limited and may be, for example, 0% or more.

[0049] Furthermore, the thickness deviation (|cd| / c) of the average thickness (d) of the second margin portion 112 arranged on the sixth surface (S6) of the capacitive portion 120 with respect to the average thickness (c) of the second margin portion 112 arranged on the fourth surface (S4) of the capacitive portion 120 of the multilayer ceramic electronic component 100 according to the present invention may be 5% or less. The average thickness (c) of the second margin portion 112 arranged on the fourth surface (S4) of the capacitive portion 120 may be a value measured by the above-mentioned method for the second margin portion 112 in contact with the fourth surface (S4) of the capacitive portion 120. Furthermore, the average thickness (d) of the second margin portion 112 disposed on the sixth surface (S6) of the capacitive portion 120 may refer to the average thickness in the third direction (Z direction) of the second margin portion 112 in contact with the sixth surface (S6) of the capacitive portion 120, and may refer to the calculated average of distances in the third direction (Z direction) measured at 10 equally spaced points on the XZ cut surface passing through the center of the multilayer ceramic electronic component 100 relative to the second margin layer 112 in contact with the sixth surface (S6) of the capacitive portion 120. The thickness deviation (|cd| / c) of the average thickness (d) of the second margin portion 112 disposed on the sixth surface (S6) of the capacitive portion 120 with respect to the average thickness (c) of the second margin portion 112 disposed on the fourth surface (S4) of the capacitive portion 120 may be 5% or less, 4% or less, or 3% or less, and the lower limit is not particularly limited and may be, for example, 0% or more.

[0050] In conventional structures, two cover portions are formed above and below the capacitance portion 120 and two margin portions are arranged on the left and right sides, resulting in thickness deviation between the cover portions and margin portions. However, in the multilayer ceramic electronic component 100 according to the present invention, the first margin portion 113 is arranged simultaneously on the third surface (S3) and fifth surface (S5) of the capacitance portion 120, thereby reducing size deviation after sintering.

[0051] In one example, the thickness deviation (|ad| / a) of the average thickness (d) of the second margin portion 112 disposed on the sixth surface (S6) of the capacitive portion 120 relative to the average thickness (a) of the first margin portion 113 disposed on the third surface (S3) of the capacitive portion 120 of the multilayer ceramic electronic component 100 of the present invention may be 5% or less. The thickness deviation (|ad| / a) may be 5% or less, 4% or less, or 3% or less, or may be 0% or more.

[0052] Furthermore, the thickness deviation (|cb| / c) of the average thickness (b) of the first margin portion 113 arranged on the fifth surface (S5) of the capacitive portion 120 relative to the average thickness (c) of the second margin portion 112 arranged on the fourth surface (S4) of the capacitive portion 120 may be 5% or less, 4% or less, or 3% or less, or may be 0% or more.

[0053] In the multilayer ceramic electronic component 100 according to this example, the first margin portion 113 and the second margin portion 112 can be formed from the same ceramic sheet, and the thickness deviation between the first margin portion 113 and the second margin portion 112 can be reduced.

[0054] In another embodiment of the present invention, the first margin portion 113 and the second margin portion 112 of the multilayer ceramic electronic component 100 according to the present invention may have different physical properties.

[0055] In one example, the first margin portion 113 and the second margin portion 112 of the multilayer ceramic electronic component 100 of the present invention may have different average densities. In this specification, the term "average density" refers to the average density of samples taken at 10 equally spaced locations in the first direction (X direction) on an X-Z cross section passing through the center of the multilayer ceramic electronic component 100. For example, the average density may be measured using a density meter such as a Density Meter Excellence D6 manufactured by METTLER TOLEDO. The multilayer ceramic electronic component 100 of this embodiment includes the first margin portion 113 and the second margin portion 112 having different average densities. This can prevent cracks due to firing mismatch that may occur during the sintering process and further improve moisture resistance reliability. Regarding the average densities of the margin portions, the average density of the first margin portion 113 may be higher than the average density of the second margin portion 112, but is not limited thereto.

[0056] According to an embodiment of the present invention, the first margin portion 113 and the second margin portion 112 of the multilayer ceramic electronic component 100 each include dielectric grains. The average grain size of the dielectric grains in the first margin portion 113 may be different from the average grain size of the dielectric grains in the second margin portion 112. In this specification, the “average grain size” of the grains may refer to the average length in the X-axis direction calculated using an image analysis program (Mediacybernetics’ ImagePro Plus version 4.5) after photographing 10 equally spaced locations in a first direction (X direction) of an X-Z cross section passing through the center of the multilayer ceramic electronic component 100 with a scanning electron microscope (SEM, Jeol’s JSM-7400F). The aforementioned average density, etc., can be achieved by adjusting the average grain sizes of the dielectric grains in the first and second margin portions 113 and 112 to be different. Regarding the average grain size of the dielectric grains, the average grain size of the dielectric grains in the first margin portion 113 may be larger than the average grain size of the dielectric grains in the second margin portion 112, but is not limited thereto.

[0057] When the average density and / or the average diameter of the dielectric grains of the first margin portion 113 and the second margin portion 112 are different as in the present embodiment, the contents of the minor components may be different between the first margin portion 113 and the second margin portion 112. Specifically, the first margin portion 113 and the second margin portion 112 may include one or more minor components selected from the group consisting of sodium (Na), lithium (Li), and boron (B), and the content of the minor component in the first margin portion 113 may be higher than the content of the minor component in the second margin portion 112.

[0058] In addition, the first margin portion 113 and the second margin portion 112 each contain magnesium (Mg), and the magnesium (Mg) content of the first margin portion 113 may be different from the magnesium (Mg) content of the second margin portion 112. By adjusting the contents of the minor components and magnesium (Mg), it is possible to adjust the density of the first margin portion 113 and the second margin portion 112. Regarding the magnesium (Mg) content, for example, the magnesium (Mg) content of the second margin portion 112 may be higher than the magnesium (Mg) content of the first margin portion 113, but is not limited thereto.

[0059] In yet another embodiment of the present invention, in the multilayer ceramic electronic component 100 according to the present invention, the dielectric layer 111 and the first margin portion 113 of the capacitive portion 120 may have different physical properties.

[0060] In the above embodiment, the average density of the outermost dielectric layers 111 in the third direction (Z direction) of the capacitive section 120 of the multilayer ceramic electronic component 100 of the present invention may be different from the average density of the first margin portions 113 arranged on the third surface (S3) of the capacitive section 120. Specifically, the average density of the outermost dielectric layers 111 in the third direction (Z direction) of the capacitive section 120 may be lower than the average density of the first margin portions 113 arranged on the third surface (S3) of the capacitive section 120.

[0061] In another embodiment, the dielectric layer 111 and the first margin portion 113 of the capacitive portion 120 of the multilayer ceramic electronic component 100 of the present invention each include dielectric grains, and the average grain size of the dielectric grains of the outermost dielectric layer 111 in the third direction (Z direction) of the capacitive portion 120 may be different from the average grain size of the dielectric grains of the first margin portion 113 disposed on the third surface (S3) of the capacitive portion 120. Specifically, the average grain size of the dielectric grains of the outermost dielectric layer 111 in the third direction (Z direction) of the capacitive portion 120 may be larger than the average grain size of the dielectric grains of the first margin portion 113 disposed on the third surface (S3) of the capacitive portion 120.

[0062] The description of the average density and the average particle size of the dielectric grains is omitted here since they are the same as those described above.

[0063] In another embodiment of the present invention, the first margin portion 213 of the multilayer ceramic electronic component 200 of the present invention may be disposed in contact with both one surface in the second direction (Y direction) and one surface in the third direction (Z direction) of the capacitive portion 220 and the second margin portion 212. FIGS. 7 to 9 are views showing the multilayer ceramic electronic component 200 according to this embodiment. Referring to FIGS. 7 to 9, the first margin portion 213 of the multilayer ceramic electronic component 200 of this embodiment may be disposed on the third surface (S3) of the capacitive portion 220 and also on one surface in the second direction (Y direction) of the second margin portion 212. The first margin portion 213 may also be disposed on the fifth surface (S5) of the capacitive portion 220 and one surface in the third direction (Z direction) of the second margin portion 212 simultaneously. That is, the first margin portion 213 may be larger in size than the second margin portion 212.

[0064] In the above embodiment, the first margin portion 213a and the second interface 212a where the first margin portion 213 and the second margin portion 212 contact each other may be formed on one surface in the second direction (Y direction) and one surface in the third direction (Z direction) of the first margin portion 213 and the second margin portion 212, respectively. In this case, the first margin portion 213 and the second margin portion 212 have asymmetric shapes, and by adjusting the average density, the average grain size of the dielectric grains, etc., as described above, it is possible to provide an electronic component with desired physical properties.

[0065] In one embodiment of the present invention, the first internal electrode 321 and / or the second internal electrode 322 of the multilayer ceramic electronic component 300 of the present invention may be exposed in the third direction (Z direction) of the capacitive unit 320. FIGS. 10 to 12 are diagrams schematically illustrating the multilayer ceramic electronic component 300 according to this embodiment. Referring to FIGS. 10 to 12, the fact that the first internal electrode 321 and / or the second internal electrode 322 are exposed in the third direction (Z direction) of the capacitive unit 320 may mean that the first internal electrode 321 and / or the second internal electrode 322 are disposed at the outermost periphery of the capacitive unit 320 in which the dielectric layer 311 and the first and second internal electrodes 321 and 322 are stacked in the third direction (Z direction). In this case, the first margin portion 313 and / or the second margin portion 312 may be disposed in direct contact with the first internal electrode 321 and / or the second internal electrode 322.

[0066] Even if the first internal electrode 321 and / or the second internal electrode 322 are arranged to be exposed in the third direction (Z direction) of the capacitive part 320 as in the present embodiment, the first margin part 313 and the second margin part 312 may prevent the first and second internal electrodes 321, 322 from being exposed to the outside of the ceramic body 310. Therefore, the dielectric layer 311 does not need to be arranged in the third direction (Z direction) of the outermost first internal electrode 321 and / or second internal electrode 322, and the internal electrodes are arranged up to the outermost periphery of the capacitive part 320, thereby maximizing the effective capacitance.

[0067] In the above embodiment, the ceramic body 310 of the multilayer ceramic electronic component 300 may include a first interface 313a and a second interface 312a where the first margin portion 313 and the second margin portion 312 contact each other.

[0068] The description of the capacitance portion, the internal electrodes, the margin portion, the interface, etc. is omitted since it has been described above.

[0069] The method for forming the margin portions of the multilayer ceramic electronic component 100 according to the present invention is not particularly limited, and may be, for example, by attaching a ceramic sheet for forming the first margin portion 113 and a ceramic sheet for forming the second margin portion 112. FIG. 10 is a schematic diagram illustrating a manufacturing method for the multilayer ceramic electronic component 100 according to an example of the present invention. Referring to FIG. 10, a method can be used in which the capacitive portion 120 is first formed and then two ceramic sheets for forming the first margin portion 113 and the second margin portion 112 are attached to the capacitive portion 120. The first and second margin portions 113 and 112 can be formed by fixing the capacitive portion 120 to a jig or the like and then transferring the ceramic sheets, but the method is not limited thereto.

[0070] In the multilayer ceramic electronic component 100 according to an example of the present invention, a first external electrode 131 and a second external electrode 132 may be disposed on an outer surface of the ceramic body 110. The first external electrode 131 may be connected to the first internal electrode 121, and the second external electrode 132 may be connected to the second internal electrode 122.

[0071] The first external electrode 131 and the second external electrode 132 may be fired electrodes containing a conductive metal and glass. The conductive metal may include, for example, at least one of nickel (Ni), copper (Cu), tin (Sn), palladium (Pd), platinum (Pt), iron (Fe), gold (Au), silver (Ag), tungsten (W), titanium (Ti), lead (Pb), and alloys thereof. The glass may be a mixture of oxides, and may be at least one selected from the group consisting of, but not limited to, silicon oxide, boron oxide, aluminum oxide, transition metal oxide, alkali metal oxide, and alkaline earth metal oxide. The transition metal may be selected from the group consisting of zinc (Zn), titanium (Ti), copper (Cu), vanadium (V), manganese (Mn), iron (Fe), and nickel (Ni), the alkali metal may be selected from the group consisting of lithium (Li), sodium (Na), and potassium (K), and the alkaline earth metal may be one or more selected from the group consisting of magnesium (Mg), calcium (Ca), strontium (Sr), and barium (Ba).

[0072] Examples of methods for forming the first external electrode 131 and the second external electrode 132 include dipping the ceramic body 110 in a conductive paste containing a conductive metal and then firing the electrode, or printing the conductive paste on the surface of the ceramic body 110 by screen printing, gravure printing, or the like, and then firing the electrode. Other examples include, but are not limited to, applying the conductive paste to the surface of the ceramic body 110, or transferring a dried film of the conductive paste onto the ceramic body 110 and then firing the film. For example, the first external electrode 131 and the second external electrode 132 may be formed by forming a conductive paste on the ceramic body 110 by various methods other than the above methods, and then firing the film.

[0073] In one example, the multilayer ceramic electronic component 100 according to the present invention may further include plating layers disposed on the first external electrode 131 and the second external electrode 132, respectively. The plating layers may include, but are not limited to, one or more selected from the group consisting of copper (Cu), nickel (Ni), tin (Sn), palladium (Pd), platinum (Pt), gold (Au), silver (Ag), tungsten (W), titanium (Ti), lead (Pb), and alloys thereof. The plating layers may be formed in a single layer or multiple layers and may be formed by, but are not limited to, sputtering or electroplating.

[0074] Although the embodiments of the present invention have been described in detail above, the present invention is not limited to the above-described embodiments and the accompanying drawings, but is limited by the appended claims. Therefore, various substitutions, modifications, and changes may be made by a person skilled in the art without departing from the technical spirit of the present invention as set forth in the claims, and these also fall within the scope of the present invention. [Explanation of symbols]

[0075] 100: Multilayer ceramic electronic components 111: Dielectric layer 113: First margin 112: Second margin 121: 1st internal electrode 122:Second internal electrode 131: 1st external electrode 132:Second external electrode

Claims

1. a ceramic body including a dielectric layer and a first internal electrode and a second internal electrode disposed opposite each other with the dielectric layer interposed therebetween; a first external electrode connected to the first internal electrode; a second external electrode connected to the second internal electrode, the ceramic body includes a first surface and a second surface facing each other in a first direction, a third surface and a fourth surface facing each other in a second direction, and a fifth surface and a sixth surface facing each other in a third direction; a capacitance portion including first internal electrodes and second internal electrodes stacked in the third direction to form a capacitance; a first margin portion disposed on the third surface and the fifth surface of the capacitance portion; and a second margin portion disposed on the fourth surface and the sixth surface of the capacitance portion and distinguished from the first margin portion; a maximum value of the width of the first margin portion and the second margin portion in the second direction is greater than a maximum value of the vertical distance between the third surface and the fourth surface of the capacitance portion; Multilayer ceramic electronic components.

2. the first margin portion is disposed in contact with the third surface and the fifth surface of the capacitance portion simultaneously; 2. The multilayer ceramic electronic component according to claim 1, wherein the second margin portion is disposed so as to be in contact with both a fourth surface and a sixth surface of the capacitance portion at the same time.

3. 3. The multilayer ceramic electronic component according to claim 1, wherein the first margin portion and the second margin portion each have a single structure.

4. The multilayer ceramic electronic component according to claim 1 , further comprising a first interface and a second interface disposed in a region where the first margin portion and the second margin portion are in contact with each other.

5. 5. The multilayer ceramic electronic component according to claim 4, wherein the first interface is disposed on the same plane as a third surface of the capacitive portion, and the second interface is disposed on the same plane as a fourth surface of the capacitive portion.

6. only a first margin portion is disposed at a corner where the third surface and the fifth surface of the capacitance portion meet, 6. The multilayer ceramic electronic component according to claim 1, wherein only the second margin portion is disposed at a corner where the fourth surface and the sixth surface of the capacitive portion meet.

7. 7. The multilayer ceramic electronic component according to claim 1, wherein a thickness deviation (|a-b| / a) of an average thickness (b) of the first margin portion disposed on the fifth surface of the capacitance section relative to an average thickness (a) of the first margin portion disposed on the third surface of the capacitance section is 5% or less.

8. 8. The multilayer ceramic electronic component according to claim 1, wherein a thickness deviation (|c-d| / c) of an average thickness (d) of the second margin portion disposed on the sixth surface of the capacitance section relative to an average thickness (c) of the second margin portion disposed on the fourth surface of the capacitance section is 5% or less.

9. The multilayer ceramic electronic component according to claim 1 , wherein the first margin portion and the second margin portion have different average densities.

10. the first margin portion and the second margin portion each include a dielectric grain; 10. The multilayer ceramic electronic component according to claim 1, wherein an average grain size of the dielectric grains in the first margin portion is different from an average grain size of the dielectric grains in the second margin portion.

11. the first margin portion and the second margin portion each contain magnesium (Mg); The multilayer ceramic electronic component according to claim 1 , wherein the first margin portion and the second margin portion have different magnesium (Mg) contents.

12. 12. The multilayer ceramic electronic component according to claim 1, wherein an average density of the dielectric layer at the outermost portion in the third direction of the capacitive section is different from an average density of a first margin portion disposed on the third surface of the capacitive section.

13. the dielectric layer of the capacitance section and the first margin section each include dielectric grains; 13. The multilayer ceramic electronic component according to claim 1, wherein an average grain size of dielectric grains in the outermost dielectric layer in the third direction of the capacitive section is different from an average grain size of dielectric grains in a first margin portion disposed on the third surface of the capacitive section.

14. The multilayer ceramic electronic component according to claim 1 , wherein the first margin portion is disposed in contact with both one surface in the second direction and one surface in the third direction of the capacitive portion and the second margin portion.

15. The multilayer ceramic electronic component according to claim 1 , wherein the XZ cross section of the first margin portion and / or the second margin portion is L-shaped.

16. 16. The multilayer ceramic electronic component according to claim 1, wherein the average thickness of the first margin portion and / or the second margin portion is in the range of 10 μm or more and 25 μm or less.

17. a ceramic body including a dielectric layer and a first internal electrode and a second internal electrode disposed opposite each other with the dielectric layer interposed therebetween; a first external electrode connected to the first internal electrode; a second external electrode connected to the second internal electrode, the ceramic body includes a first surface and a second surface facing each other in a first direction, a third surface and a fourth surface facing each other in a second direction, and a fifth surface and a sixth surface facing each other in a third direction; a capacitance portion including first internal electrodes and second internal electrodes stacked in the third direction to form a capacitance; a first margin portion disposed on the third surface and the fifth surface of the capacitance portion; and a second margin portion disposed on the fourth surface and the sixth surface of the capacitance portion; the first margin portion is disposed in contact with the first internal electrode or the second internal electrode disposed on the fifth surface of the capacitive portion; Multilayer ceramic electronic components.

18. the first margin portion is disposed in contact with the third surface and the fifth surface of the capacitance portion simultaneously; The multilayer ceramic electronic component according to claim 17 , wherein the second margin portion is disposed so as to be in contact with both the fourth surface and the sixth surface of the capacitance portion at the same time.

19. 19. The multilayer ceramic electronic component according to claim 2, wherein the first margin portion is arranged in contact with one surface of the second margin portion in the second direction, one surface of the second margin portion in the third direction, and the capacitance portion at the same time.

20. 20. The multilayer ceramic electronic component according to claim 2, wherein the first margin portion is arranged in contact with the first internal electrode or the second internal electrode arranged on the fifth surface of the capacitance portion.

21. 21. The multilayer ceramic electronic component according to claim 2, wherein the second margin portion is arranged in contact with the first internal electrode or the second internal electrode arranged on the sixth surface of the capacitance portion.

22. The multilayer ceramic electronic component according to claim 1 , wherein the first margin and the second margin are distinct from each other.

23. 23. The multilayer ceramic electronic component according to claim 2, wherein the XZ cross section of the first margin portion and / or the second margin portion is L-shaped.

Images