Filter Device

Abstract

A filter device (1) comprises: a dielectric substrate (DL1); a common terminal (Pcom), a first terminal (PH) and a second terminal (PL); a filter (1H); and a filter (1L). The filter (1H) comprises a capacitor (C1) and a capacitor (C2) connected in series. The capacitor (C1) includes a flat plate electrode (P3) and a flat plate electrode (P8) facing each other. The capacitor (C2) includes the flat plate electrode (P8) and a flat plate electrode (P10) facing each other. The flat plate electrode (P3) and the flat plate electrode (P10) are at least partially overlapped, when viewed on a plane from the normal direction of the dielectric substrate (DL1).

Description

[Technical Field]

[0001] The present disclosure relates to a filter device having a plurality of filters with different passbands, and more particularly to a technique for improving the characteristics of the filter device. [Background technology]

[0002] Japanese Patent Laid-Open Publication No. 2021-19304 (Patent Document 1) discloses a diplexer configuration including a high-pass circuit and a low-pass circuit. The diplexer disclosed in Japanese Patent Laid-Open Publication No. 2021-19304 (Patent Document 1) includes a common terminal, a first terminal, and a second terminal as input / output terminals for connecting to an external device.

[0003] The high-pass circuit is disposed between the common terminal and the first terminal, and the low-pass circuit is disposed between the common terminal and the second terminal. In addition, in the diplexer of JP 2021-19304 A (Patent Document 1), two capacitors are connected in series between the common terminal and the first terminal in the high-pass circuit. The two capacitors include one common plate electrode. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2021-19304 Summary of the Invention [Problem to be solved by the invention]

[0005] However, if the connection distance between the two capacitors connected in series between the common terminal and the first terminal becomes long, the parasitic inductance generated at the connection portion increases, which may lead to a deterioration in the characteristics of the diplexer.

[0006] The present disclosure has been made to solve such problems, and its purpose is to improve the characteristics of a filter device having multiple filters by reducing the parasitic inductance that occurs at the connection between two capacitors connected in series between a common terminal and a first terminal. [Means for solving the problem]

[0007] A filter device according to an aspect of the present disclosure includes a dielectric substrate, a common terminal, a first terminal, a second terminal, a first filter, and a second filter. The common terminal, the first terminal, and the second terminal are disposed on the dielectric substrate. The first filter is connected between the common terminal and the first terminal. The second filter is connected between the common terminal and the second terminal and has a lower passband than the first filter. The first filter includes a first capacitor and a second capacitor connected in series between the common terminal and the first terminal. The first capacitor includes a first plate electrode and a second plate electrode facing each other. The second capacitor includes a second plate electrode and a third plate electrode facing each other. When viewed in a plan view from the normal direction of the dielectric substrate, the first plate electrode and the third plate electrode at least partially overlap. [Effects of the Invention]

[0008] The first capacitor included in the filter device according to the present disclosure includes a first plate electrode and a second plate electrode, and the second capacitor includes a second plate electrode and a third plate electrode. That is, the first capacitor and the second capacitor share the second plate electrode, and when the dielectric substrate is viewed from above, the first plate electrode and the third plate electrode at least partially overlap. This configuration shortens the connection distance between the first capacitor and the second capacitor, thereby reducing parasitic inductance generated at the connection between the first capacitor and the second capacitor connected in series between the common terminal and the first terminal, thereby improving the characteristics of the filter device. [Brief explanation of the drawings]

[0009] [Figure 1]1 is an equivalent circuit diagram of a filter device according to an embodiment of the present invention. [Figure 2] 1 is a perspective view showing the inside of a filter device according to an embodiment of the present invention. [Figure 3] 1 is an exploded perspective view showing an example of a laminated structure of a filter device according to an embodiment of the present invention. [Figure 4] FIG. 10 is a plan view of part of the configuration included in the dielectric layers LY14 to LY19, viewed from the normal direction of the dielectric substrate. [Figure 5] FIG. 2 is a plan view of only some of the planar electrodes as viewed from the normal direction of the dielectric substrate. [Figure 6] FIG. 10 is a plan view of part of the configuration included in dielectric layers LY14 to LY19 as viewed from the normal direction of the dielectric substrate in the comparative example. [Figure 7] 10A and 10B are diagrams illustrating an example of insertion loss of the filter device according to the present embodiment and a filter device according to a comparative example. [Figure 8] FIG. 8 is a vertical enlarged view of the area shown in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are designated by the same reference numerals, and description thereof will not be repeated.

[0011] <Equivalent circuit of filter device 1> FIG. 1 is an equivalent circuit diagram of a filter device 1 according to this embodiment. The filter device 1 is a diplexer including a filter 1H and a filter 1L. The filter 1H passes a high-frequency signal in a high band HB. The filter 1L passes a high-frequency signal in a low band LB. The low band LB has a lower pass band than the high band HB. In other words, the filter 1L is a filter having a lower pass band than the filter 1H. The filter 1H corresponds to the "first filter" of the present disclosure, and the filter 1L corresponds to the "second filter" of the present disclosure.

[0012] The filter device 1 can be applied to, for example, a so-called dual-band communication device capable of communication in two frequency bands, a high band HB and a low band LB. The filter device 1 may be a multiplexer having three or more filters.

[0013] In addition to the filters 1H and 1L, the filter device 1 further includes a common terminal Pcom, a first terminal PH, a second terminal PL, and a ground terminal GND. The common terminal Pcom is connected to each of the filters 1H and 1L.

[0014] The filter 1H is connected between the common terminal Pcom and the first terminal PH, and includes a capacitor C1, a capacitor C2, a capacitor C3, an inductor L1, an inductor L2, and an inductor L3.

[0015] The capacitor C1, the capacitor C2, and the inductor L3 are connected in series, in this order, between the common terminal Pcom and the first terminal PH. That is, the capacitor C1 and the capacitor C2 are connected in series. The capacitor C1 corresponds to the "first capacitor" in this disclosure, and the capacitor C2 corresponds to the "second capacitor" in this disclosure.

[0016] One end of capacitor C1 is connected to common terminal Pcom, and the other end is connected to one end of capacitor C2. The other end of capacitor C2 is connected to one end of inductor L3. The other end of inductor L3 is connected to first terminal PH.

[0017] An inductor L1 is connected between a node N1 between the capacitors C1 and C2 and the ground terminal GND. An inductor L2 and a capacitor C3 are connected between a node N2 between the capacitors C2 and inductor L3 and the ground terminal GND. One end of the inductor L2 is connected to the node N2, and the other end is connected to one end of the capacitor C3. The other end of the capacitor C3 is connected to the ground terminal GND.

[0018] The filter 1L is connected between the common terminal Pcom and the second terminal PL, and includes a capacitor C4, a capacitor C5, a capacitor C6, an inductor L4, and an inductor L5.

[0019] Inductors L4 and L5 are connected in series between the common terminal Pcom and the second terminal PL. One end of inductor L4 is connected to the common terminal Pcom, and the other end is connected to one end of inductor L5. The other end of inductor L5 is connected to the second terminal PL.

[0020] A capacitor C4 is connected in parallel with the inductor L4. A capacitor C5 is connected in parallel with the inductor L5. A capacitor C6 is connected between a node N3 between the inductors L4 and L5 and the ground terminal GND.

[0021] <Structure of filter device 1> The structure of the filter device 1 will be described below with reference to Figs. 2 to 4. Fig. 2 is a perspective view showing the interior of the filter device 1. Fig. 3 is an exploded perspective view showing an example of the layered structure of the filter device 1. As shown in Figs. 2 and 3, the filter device 1 includes a dielectric substrate DL1. The dielectric substrate DL1 in this embodiment is formed by laminating a plurality of dielectric layers and has a rectangular parallelepiped shape.

[0022] 2 and 3, the stacking direction of the dielectric substrate DL1 is referred to as the "Z-axis direction." The direction perpendicular to the Z-axis direction and along the long side of the top surface Sf2 when the dielectric substrate DL1 is viewed in a plan view is referred to as the "X-axis direction." The direction perpendicular to the Z-axis direction and along the short side of the top surface Sf2 when the dielectric substrate DL1 is viewed in a plan view is referred to as the "Y-axis direction." In addition, the positive direction of the Z-axis in each figure may be referred to as the upper side, and the negative direction may be referred to as the lower side, and the Z-axis direction may be referred to as the "normal direction of the dielectric substrate DL1."

[0023] Each dielectric layer included in the dielectric substrate DL1 is made of ceramic such as low temperature co-fired ceramics (LTCC) or resin. In some aspects, the dielectric substrate DL1 may be made of a single dielectric layer instead of multiple dielectric layers.

[0024] The dielectric substrate DL1 has a bottom surface Sf1 and a top surface Sf2. The common terminal Pcom, the first terminal PH, the second terminal PL, and the ground terminal GND described in Fig. 1 have a flat plate shape. The common terminal Pcom, the first terminal PH, the second terminal PL, and the ground terminal GND are LGA (Land Grid Array) terminals arranged on the bottom surface Sf1.

[0025] 2 and 3 show an example in which a plurality of ground terminals GND (three in this embodiment) are arranged. The bottom surface Sf1 of the filter device 1 is connected to a circuit board (not shown) using connecting members such as solder bumps. A direction mark M for identifying the orientation of the filter device 1 is arranged on the top surface Sf2.

[0026] The dielectric substrate DL1 is provided with a plurality of electrodes and vias for forming the equivalent circuit shown in FIG. 1. The common terminal Pcom is connected to the plate electrode P3 through a via V1. In this specification, the term "via" refers to a conductor provided in a dielectric layer to connect electrodes provided on different dielectric layers. The vias are formed, for example, from conductive paste, plating, and / or metal pins.

[0027] 1, filter 1H includes capacitors C1, C2, C3, inductors L1, L2, and L3. As shown in Fig. 2, these components included in filter 1H are configured by electrodes and vias on the positive side of the X-axis on dielectric substrate DL1.

[0028] 1, filter 1L includes capacitor C4, inductor L4, capacitor C5, capacitor C6, and inductor L5. As shown in Fig. 2, these components included in filter 1L are configured by electrodes and vias on the negative side of the X-axis on dielectric substrate DL1.

[0029] As shown in Fig. 3, the dielectric substrate DL1 of this embodiment is formed by stacking a plurality of dielectric layers (dielectric layers LY1 to LY19) in the stacking direction. The connection relationship between the electrodes of each dielectric layer and the vias between each dielectric layer will be described below with reference to Fig. 3.

[0030] The electrodes arranged on each dielectric layer will be described below with reference to Fig. 3. In Fig. 3, all plate electrodes are drawn with solid lines to make the arrangement of each plate electrode easier to understand. A common terminal Pcom, a first terminal PH, a second terminal PL, and a ground terminal GND are arranged on the lower surface Sf1 (dielectric layer LY19) of the dielectric substrate DL1. Plate electrodes P1 to P5 are arranged on the dielectric layer LY18. A plate electrode P6 is arranged on the dielectric layer LY17. Plate electrodes P7 and P8 are arranged on the dielectric layer LY16. Plate electrodes P9 to P11 are arranged on the dielectric layer LY15.

[0031] A plate electrode P12 is disposed on the dielectric layer LY14. A plate electrode P13 is disposed on the dielectric layer LY13. A plate electrode P14 is disposed on the dielectric layer LY12. A plate electrode P15 is disposed on the dielectric layer LY11. A plate electrode P16 is disposed on the dielectric layer LY10.

[0032] Plate electrodes P17 and P18 are arranged on the dielectric layer LY9. Plate electrodes P19 and P20 are arranged on the dielectric layer LY8. Plate electrodes P21 to P23 are arranged on the dielectric layer LY7. Plate electrodes P24 to P26 are arranged on the dielectric layer LY6.

[0033] A plate electrode P27 is arranged on the dielectric layer LY5. A plate electrode P28 is arranged on the dielectric layer LY4. Plate electrodes P29 to P32 are arranged on the dielectric layer LY3. Plate electrodes P33 to P36 are arranged on the dielectric layer LY2.

[0034] Next, the connection relationship between each terminal and each plate electrode P1 to P36 will be described. The common terminal Pcom is connected to a plate electrode P3 provided on the dielectric layer LY18 by a via V1. The plate electrode P3 provided on the dielectric layer LY18 faces a plate electrode P8 provided on the dielectric layer LY16. The capacitor C1 in FIG. 1 is composed of the plate electrodes P3 and P8. The plate electrodes P3 and P8 correspond to the "first plate electrode" and "second plate electrode" of the present disclosure, respectively.

[0035] Plate electrode P8 is connected by via V2 to plate electrode P36 provided on dielectric layer LY2 and plate electrode P32 provided on dielectric layer LY3. Plate electrodes P36 and P32 are connected by via V3 to plate electrode P25 provided on dielectric layer LY6. In filter device 1 of the present embodiment, two plate electrodes P32 and P36 are disposed between via V2 and via V3 to reduce loss. In some aspects, filter device 1 may be provided with only one of the two plate electrodes P32 and P36.

[0036] Plate electrode P25 is connected by via V4 to plate electrode P22 provided on dielectric layer LY7 and plate electrode P20 provided on dielectric layer LY8. Plate electrode P20 is connected by via V5 to plate electrode P18 provided on dielectric layer LY9 and plate electrode P5 provided on dielectric layer LY18. Plate electrode P5 is connected by via V6 to ground terminal GND provided on dielectric layer LY19.

[0037] Inductor L1 in FIG. 1 is composed of plate electrodes P18, P20, P22, P25, P32, and P36. The plate electrodes P18, P20, P22, P25, P32, and P36 that make up inductor L1 are strip-shaped plate electrodes that are wound around the same winding axis extending in the Z-axis direction. The plate electrodes P18 and P20 have the same shape. The plate electrodes P22 and P25 have the same shape. The plate electrodes P32 and P36 have the same shape. In other words, the plate electrodes P18, P20, P22, P25, P32, and P36 form a helical coil.

[0038] Plate electrode P8 provided on dielectric layer LY16 faces plate electrode P10 provided on dielectric layer LY15. Capacitor C2 in Fig. 1 is composed of plate electrode P8 and plate electrode P10. Plate electrode P8 and plate electrode P10 correspond to the "second plate electrode" and "third plate electrode" of the present disclosure, respectively.

[0039] Plate electrode P10 is connected by via V7 to plate electrode P31 provided on dielectric layer LY3 and plate electrode P35 provided on dielectric layer LY2. Plate electrodes P31 and P35 are connected by via V8 to plate electrode P24 provided on dielectric layer LY6.

[0040] In filter device 1 of the present embodiment, two plate electrodes P31 and P35 are arranged between via V7 and via V8 to reduce loss. In some aspects, filter device 1 may be provided with only one of the two plate electrodes P31 and P35.

[0041] Plate electrode P24 is connected by via V9 to plate electrode P21 provided on dielectric layer LY7 and plate electrode P19 provided on dielectric layer LY8. Plate electrode P19 is connected by via V10 to plate electrode P17 provided on dielectric layer LY9 and plate electrode P16 provided on dielectric layer LY10. Plate electrode P16 is connected by via V11 to plate electrode P15 provided on dielectric layer LY11 and plate electrode P14 provided on dielectric layer LY12. Plate electrode P14 is connected by via V12 to plate electrode P13 provided on dielectric layer LY13 and plate electrode P11 provided on dielectric layer LY15.

[0042] A plate electrode P11 provided on the dielectric layer LY15 faces a plate electrode P5 provided on the dielectric layer LY18. The capacitor C3 in FIG. 1 is composed of the plate electrodes P11 and P5. The plate electrode P5 is connected to the ground terminal GND provided on the dielectric layer LY19 by a via V13. The via V13 is the same via as the via V6.

[0043] The inductor L2 in FIG. 1 is composed of plate electrodes P13 to P17, P19, P21, P24, P31, and P35. 2 The plate electrodes P13 to P17, P19, P21, P24, P31, and P35 that constitute the coil are strip-shaped plate electrodes that are wound around the same winding axis extending in the Z-axis direction. The plate electrodes P13 and P14 have the same shape. The plate electrodes P15 and P16 have the same shape. The plate electrodes P17 and P19 have the same shape. The plate electrodes P21 and P24 have the same shape. The plate electrodes P31 and P35 have the same shape. In other words, the plate electrodes P13 to P17, P19, P21, P24, P31, and P35 constitute a helical coil.

[0044] The plate electrode P10 is connected by a via V14 to a plate electrode P4 provided on the dielectric layer LY18, and the plate electrode P4 is connected by a via V15 to a first terminal PH provided on the dielectric layer LY19.

[0045] As shown in FIG. 1, the filter device 1 includes an inductor L3. The plate electrode P10 shown in FIGS. 2 and 3 extends to the position of the via V14 in order to be electrically connected to the via V14. As shown in FIG. 2, the portion of the plate electrode P10 that does not overlap with the plate electrode P8 is referred to as the lead-out portion Et1. The lead-out portion Et1 of the plate electrode P10 functions as the inductor L3. This adds a low-pass filter function to the filter 1H, and the low The passband on the frequency side is expanded.

[0046] The plate electrode P3 is connected by a via V16 to a plate electrode P30 provided on the dielectric layer LY3 and a plate electrode P34 provided on the dielectric layer LY2. The plate electrodes P30 and P34 are connected by a via V17 to a plate electrode P28 provided on the dielectric layer LY4. In the filter device 1 of the present embodiment, the two plate electrodes P30 and P34 are disposed between the via V16 and the via V17 to reduce loss. In some aspects, the filter device 1 may be provided with only one of the two plate electrodes P30 and P34.

[0047] Plate electrode P28 is connected by via V18 to plate electrode P27 provided on dielectric layer LY5 and plate electrode P26 provided on dielectric layer LY6. Plate electrode P26 is connected by via V19 to plate electrode P23 provided on dielectric layer LY6 and plate electrode P9 provided on dielectric layer LY15.

[0048] Inductor L4 in FIG. 1 is composed of plate electrodes P23, P26 to P28, P30, and P34. The plate electrodes P23, P26 to P28, P30, and P34 that make up inductor L4 are strip-shaped plate electrodes that are configured to be wound around the same winding axis extending in the Z-axis direction. Plate electrodes P23 and P26 have the same shape. Plate electrodes P27 and P28 have the same shape. Plate electrodes P30 and P34 have the same shape. In other words, plate electrodes P23, P26 to P28, P30, and P34 form a helical coil.

[0049] Plate electrode P9 is connected by via V20 to plate electrode P33 provided on dielectric layer LY2 and plate electrode P29 provided on dielectric layer LY3. Plate electrodes P33 and P29 are connected by via V21 to plate electrode P1 provided on dielectric layer LY18. Vias V20, via V21, and plate electrodes P28 and P33 form inductor L5 in FIG.

[0050] In filter device 1 of the present embodiment, two plate electrodes P29 and P33 are disposed between via V20 and via V21 to reduce loss. In some aspects, filter device 1 may be provided with only one of the two plate electrodes P29 and P33. Plate electrode P1 is connected to a second terminal PL provided on dielectric layer LY19 by via V22.

[0051] The plate electrode P3 is connected to a plate electrode P12 provided on the dielectric layer LY13 by a via V16. The plate electrode P12 provided on the dielectric layer LY13 faces a plate electrode P9 provided on the dielectric layer LY17. The capacitor C4 in FIG. 1 is formed by the plate electrodes P12 and P9.

[0052] The plate electrode P9 is connected to a plate electrode P6 provided on the dielectric layer LY17 by a via V20. The plate electrode P6 provided on the dielectric layer LY17 faces a plate electrode P1 provided on the dielectric layer LY18. The capacitor C5 in FIG. 1 is formed by the plate electrodes P6 and P1.

[0053] The plate electrode P6 faces a plate electrode P2 provided on the dielectric layer LY18. The capacitor C6 in Fig. 1 is composed of the plate electrodes P6 and P2. The plate electrode P2 is connected to a ground terminal GND provided on the dielectric layer LY19 by a via V23.

[0054] Fig. 4 is a plan view of part of the configuration included in the dielectric layers LY14 to LY19, viewed from the normal direction of the dielectric substrate DL1. Fig. 4 shows a plan view of the dielectric substrate DL1, viewed from the positive side of the Z axis.

[0055] FIG. 4 shows a common terminal Pcom, a first terminal PH, a second terminal PL, a ground terminal GND, plate electrodes P3 and P8 that constitute capacitor C1, and plate electrodes P8 and P10 that constitute capacitor C2.

[0056] 4, when viewed from above in the normal direction of the dielectric substrate DL1, the plate electrodes P3 and P10 at least partially overlap. Furthermore, the plate electrode P8 faces both the plate electrodes P3 and P10, and therefore the plate electrode P8 also at least partially overlaps the plate electrodes P3 and P10.

[0057] As described above, in the filter device 1 of this embodiment, the plate electrodes P3 and P10 overlap, and the plate electrode P8 also overlaps with the plate electrodes P3 and P10, thereby forming the capacitors C1 and C2. That is, in the filter device 1 of this embodiment, the plate electrode P8 does not need to extend in the XY plane in order to electrically connect the plate electrodes P3 and P10. That is, since the capacitors C1 and C2 are arranged close to each other, the plate electrode P 8 It is not necessary to have a portion for configuring the capacitors C1 and C2 and a portion for connecting the capacitors C1 and C2 separately.

[0058] In the filter device 1 of this embodiment, the connection distance between the capacitors C1 and C2 is short, resulting in small parasitic inductance. That is, in the filter device 1 of this embodiment, the parasitic inductance occurring at the connection between the capacitors C1 and C2, which are connected in series between the common terminal Pcom and the first terminal PH, can be reduced, thereby improving the characteristics of the filter device 1. Note that, although the plate electrodes P3, P8, and P10 are arranged in this order from the negative side of the Z axis, the order of the plate electrodes P3, P8, and P10 is not limited thereto. For example, the plate electrodes P3, P8, and P10 may be arranged in the order of the plate electrodes P10, P8, and P3 from the negative side of the Z axis.

[0059] 4, when viewed from above in the normal direction of the dielectric substrate DL1, the plate electrodes P3 and P8 constituting the capacitor C1 do not overlap with any of the ground terminals GND. Similarly, when viewed from above in the normal direction of the dielectric substrate DL1, the plate electrodes P8 and P10 constituting the capacitor C2 do not overlap with any of the ground terminals GND.

[0060] As a result, in the filter device 1 of this embodiment, the occurrence of parasitic capacitance between the capacitor C1 and the ground terminal GND and the capacitor C2 is suppressed, and loss due to the parasitic capacitance can be reduced.

[0061] Furthermore, when viewed from above in the normal direction of the dielectric substrate DL1, at least a portion of each of the plate electrodes P3, P8, and P10 overlaps with the common terminal Pcom and is disposed directly above the common terminal Pcom. Therefore, compared to a structure in which the plate electrodes P3 and P8 constituting capacitor C1 and the plate electrodes P8 and P10 constituting capacitor C2 do not overlap with the common terminal Pcom, the filter device 1 of this embodiment can shorten the path from the common terminal Pcom to the first terminal PH in FIG. 1. Therefore, the filter device 1 of this embodiment can reduce parasitic inductance in the path from the common terminal Pcom to the first terminal PH.

[0062] Furthermore, when viewed from above in the normal direction of the dielectric substrate DL1, the path electrically connecting the capacitor C2 and the first terminal PH does not overlap with the ground terminal GND. The lead-out portion Et1 of the plate electrode P10 is a path electrically connecting the capacitor C2 and the first terminal. As shown in FIG. 4, when viewed from above in the normal direction of the dielectric substrate DL1, the lead-out portion Et1 of the plate electrode P10 does not overlap with any of the ground terminals GND.

[0063] As a result, in the filter device 1 of the present embodiment, the occurrence of parasitic capacitance between the lead portion Et1 of the plate electrode P10 and the ground terminal GND is suppressed, and loss due to the parasitic capacitance can be reduced.

[0064] Next, the improvement in the characteristics of the filter device 1 from the viewpoint of the arrangement of the inductor L2 will be described. Fig. 5 is a plan view of only some of the planar electrodes as viewed from the normal direction of the dielectric substrate DL1. Fig. 5 shows the terminals removed from Fig. 4, and instead shows the plate electrodes P13 to P17, P19, P21, P24, P31, and P35 that form the inductor L2.

[0065] In this embodiment, inductor L2 is a helical coil with a winding axis Ax1 that is normal to dielectric substrate DL1. Inductor L2 includes plate electrodes P13 to P17, P19, P21, P24, P31, and P35. An opening Op1 of inductor L2 is shown in FIG. 5, which is a plan view taken from the normal to dielectric substrate DL1. In FIG. 5, a hatched region Ar1 of inductor L2 where plate electrodes P13 to P17, P19, P21, P24, P31, and P35 overlap is shown. In other words, the plate electrodes P13 to P17, P19, P21, P24, P31, and P35 shown in region Ar1 constitute inductor L2.

[0066] As shown in FIG. 5, the plate electrodes P13 to P17, P19, P21, P24, P31, and P35 represented by the region Ar1 do not overlap the regions of the plate electrodes P3, P8, and P10 that constitute the capacitors C1 and C2. Compared to a configuration in which the capacitors C1 and C2 do not overlap when viewed in a plan view from the normal direction of the filter device 1 and the dielectric substrate DL1 of the present embodiment, the area occupied by the capacitors C1 and C2 in the XY plane shown in FIG. 5 is smaller in the filter device 1 of the present embodiment. This allows the air-core diameter of the inductor L2 to be increased when the inductor L2 is arranged so as not to overlap with the capacitors C1 and C2, thereby improving the Q value of the filter device 1 of the present embodiment. The inductor L2 corresponds to the "first inductor" of the present disclosure.

[0067] Furthermore, since the capacitors C1, C2 and the inductor L2 do not overlap when viewed in a plane from the normal direction of the dielectric substrate DL1, in the filter device 1 of this embodiment, electromagnetic field coupling occurs between the capacitors C1, C2 and the inductor L2, reducing the impedance from the node N2 to the ground terminal GND, thereby suppressing deterioration in the characteristics of the filter device 1 due to loss.

[0068] <Comparative Example> A filter device 1Z, which is a comparative example of the filter device 1 of the present embodiment, will be described below with reference to Fig. 6. Fig. 6 is a plan view of part of the configuration included in the dielectric layers LY14 to LY19, viewed from the normal direction of the dielectric substrate in the comparative example. Fig. 6 shows a plan view of the dielectric substrate DL1 viewed from the positive side of the Z axis.

[0069] 6 shows a common terminal Pcom, a first terminal PH, a second terminal PL, a ground terminal GND, and plate electrodes P3, P8Z, and P10Z. The plate electrodes P3 and P8Z form a capacitor C1. The plate electrodes P8Z and P10Z form a capacitor C2. In the comparative example, both the plate electrodes P3 and P10Z are disposed on the negative side of the plate electrode P8Z along the Z axis.

[0070] As shown in FIG. 6, when viewed from above in the normal direction of the dielectric substrate DL1, the plate electrode P3 and the plate electrode P10Z do not overlap. Therefore, the connection distance between the capacitors C1 and C2 is longer than in the configuration of this embodiment. Furthermore, in the comparative example, when viewed from above in the normal direction of the dielectric substrate DL1, the capacitor C2 is arranged at a position overlapping the ground terminal GND. Furthermore, although not shown, when viewed from above in the normal direction of the dielectric substrate DL1, the capacitor C2 is arranged at a position overlapping the inductor L2.

[0071] <Characteristics of filter device 1> The characteristics of the filter device 1 according to this embodiment will be described below. First, the improvement in the characteristics of the filter device 1 from the viewpoint of the arrangement of the capacitors C1 and C2 will be described.

[0072] Fig. 7 is a diagram showing an example of insertion loss of the filter device 1 according to the present embodiment and the filter 1H of the filter device 1Z of the comparative example. Line Ln1 shown in Fig. 7 shows the waveform of the insertion loss of the filter device 1 according to the present embodiment. Line Ln2 shown in Fig. 7 shows the waveform of the insertion loss of the filter device 1Z of the comparative example.

[0073] Fig. 8 is a vertically enlarged view of region Ar2 shown in Fig. 7. Fig. 8 shows a waveform in which the vertical axis (insertion loss) direction of region Ar2 shown in Fig. 7 is enlarged. To make the difference between lines Ln1 and Ln2 easier to understand, the ratio in the horizontal axis (frequency) direction in Fig. 8 is the same as in Fig. 7, and only the ratio in the vertical axis (insertion loss) direction is enlarged.

[0074] 7 and 8, the insertion loss of filter 1H of filter device 1 according to the present embodiment is smaller than that of filter 1H of filter device 1Z of the comparative example. That is, in the frequency range from about 2.42 GHz to 3.0 GHz, the insertion loss of filter device 1 according to the present embodiment is smaller than that of filter device 1Z of the comparative example. In particular, at a frequency of 3.0 GHz, the insertion loss of filter 1H of filter device 1 according to the present embodiment is approximately 1.2 dB smaller than that of filter 1H of filter device 1Z of the comparative example.

[0075] As described above, in the filter device 1 of the present embodiment, when the dielectric substrate DL1 is viewed in a plan view from the normal direction, the plate electrodes P3 and P10 overlap each other. This shortens the connection distance between the capacitors C1 and C2, thereby reducing the parasitic inductance generated at the connection between the capacitors C1 and C2 connected in series between the common terminal Pcom and the first terminal PH, thereby improving the characteristics of the filter device 1.

[0076] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present invention is defined by the claims, not by the description of the above embodiments, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0077] 1,1Z filter device, 1H,1L filter, Ar1,Ar2 area, C1~C6 capacitor, DL1 dielectric substrate, GND ground terminal, HB high band, L1~L5 inductor, LY1~LY19 dielectric layer, Ln1,Ln2 line, M directional mark, N1~N7 node, Op1 opening, P1~P36,P8Z,P10Z flat plate electrode, PH first terminal, PL second terminal, Pcom common terminal, Sf1 bottom surface, Sf2 top surface, V1~V23 via, Et1 lead-out section.

Claims

1. a dielectric substrate; a common terminal, a first terminal, and a second terminal disposed on the dielectric substrate; a first filter connected between the common terminal and the first terminal; a second filter connected between the common terminal and the second terminal and having a lower passband than the first filter; a ground terminal; the first filter includes a first capacitor and a second capacitor connected in series between the common terminal and the first terminal; the first capacitor includes a first plate electrode and a second plate electrode facing each other; the second capacitor includes the second plate electrode and a third plate electrode facing each other, when viewed from above in a normal direction of the dielectric substrate, an area where the first plate electrode and the second plate electrode overlap does not overlap with the ground terminal, an overlapping region of the second plate electrode and the third plate electrode does not overlap with the ground terminal when viewed from above in a normal direction of the dielectric substrate; When viewed from above in a normal direction of the dielectric substrate, the first plate electrode and the third plate electrode do not at least partially overlap each other, A filter device in which, when viewed in a plane from the normal direction of the dielectric substrate, at least one of the regions where the first plate electrode and the second plate electrode overlap and the region where the second plate electrode and the third plate electrode overlap does not overlap with a ground electrode that is disposed on the dielectric substrate and connected to the ground terminal.

2. 2. The filter device according to claim 1, wherein, when viewed in a plane from a normal direction of the dielectric substrate, at least a portion of each of the first plate electrode, the second plate electrode, and the third plate electrode overlaps with the common terminal.

3. A filter device as described in claim 1 or claim 2, wherein when viewed in a plane from the normal direction of the dielectric substrate, each of the first flat plate electrode and the second flat plate electrode does not overlap with the ground terminal.

4. A filter device as described in claim 1 or claim 2, wherein when viewed in a plane from the normal direction of the dielectric substrate, each of the second flat plate electrode and the third flat plate electrode does not overlap with the ground terminal.

5. A filter device as described in claim 1 or claim 2, wherein when viewed in a plane from the normal direction of the dielectric substrate, the path electrically connecting the second capacitor and the first terminal does not overlap with the ground terminal.

6. the first filter further comprises a first inductor; The filter device according to claim 3 , wherein the first inductor does not overlap the first capacitor and the second capacitor when viewed in a plan view from a normal direction of the dielectric substrate.

7. The filter device according to claim 3 , wherein the first filter further comprises a second inductor connected between the second capacitor and the first terminal.

8. The filter device according to claim 7 , wherein the second inductor does not overlap the ground terminal when viewed in a plan view from a normal direction of the dielectric substrate.

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