Charge pump circuit and PLL circuit

Abstract

To provide a charge pump circuit and a PLL circuit that can be easily accelerated.SOLUTION: A comparator COMP compares a voltage between an output terminal OUT and a node and outputs the comparison result. A fifth switch SW5 is connected in series between the other end of a third constant current source 33, which flows the same current as a second constant current source 32, and the node A, and is controlled on / off by the output of the comparator COMP. A sixth switch SW6 is connected in series between the other end of a fourth constant current source 34, which flows the same current value as the first constant current source 31, and the node A, and is controlled on / off by the output of the comparator COMP. A capacitor C is connected between the node A and the second power supply VSS.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a charge pump circuit and a PLL circuit. [Background technology]

[0002] A known charge pump circuit that constitutes a PLL circuit is described in Patent Document 1. As shown in Fig. 7, the conventional charge pump circuit includes a transistor PT1 that supplies an up-current IUP, a transistor NT1 that supplies a down-current IDN, transistors PT2, PT3, NT2, and NT3, and an amplifier AMP.

[0003] When transistor NT3 is on and transistor NT2 is off, and transistor PT2 is on and transistor PT3 is off, an up current IUP can be output to the output terminal OUT. Also, when transistor NT3 is on and transistor NT2 is off, and transistor PT3 is on and transistor PT2 is off, the current flowing to the output terminal OUT becomes zero.

[0004] When transistor NT2 is on and transistor NT3 is off while transistor PT3 is on and transistor PT2 is off, a down current IDN can be drawn from the output terminal OUT. Also, when transistor PT3 is on and transistor PT2 is off, transistor NT3 is on and transistor NT2 is off, the current flowing to the output terminal OUT becomes zero.

[0005] 7 uses amplifier AMP, which forms a voltage follower, to keep the output terminal OUT and node A at the same voltage. This prevents current from flowing in or out of node A to the output terminal OUT when transistors PT2 and PT3 or transistors NT2 and NT3 are switched on and off. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent No. 4059077 Summary of the Invention [Problem to be solved by the invention]

[0007] However, the characteristics of the amplifier AMP that constitutes the voltage follower pose a bottleneck in conventional circuits, making their application to high-frequency charge pump circuits problematic. When the operating frequency of a charge pump circuit is high, the output of the amplifier AMP switches at high speed. Therefore, if the unity gain frequency, slew rate, or output resistance of the amplifier AMP is insufficient, the voltage error at node A can become large. For this reason, the characteristics of the voltage follower must be sufficiently higher than the operating frequency of the charge pump in order to achieve the intended effect of this circuit. In actual amplifier design, achieving both phase compensation and high speed is difficult. Furthermore, the output current capability of the amplifier AMP must be greater than the up-current and down-current, and the output resistance must also be sufficiently low, resulting in problems such as increased current consumption and circuit size.

[0008] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a charge pump circuit and a PLL circuit that can be easily made faster. [Means for solving the problem]

[0009] In order to achieve the above-mentioned object, the charge pump circuit and the PLL circuit according to the present invention are characterized by the following [1] and [2]. [1] A charge pump circuit constituting a PLL circuit, a first constant current source having one end connected to the first power supply; a second constant current source having one end connected to the second power supply; One end is connected to the first power supply a third constant current source connected to the second constant current source and having the same current value as the second constant current source; One end is connected to the second power supplya fourth constant current source connected to the first constant current source and having the same current value as the first constant current source; a first switch connected in series between the other end of the first constant current source and an output terminal, the first switch being controlled to be turned on and off by a first signal; a second switch connected in series between the other end of the first constant current source and a node, the second switch being controlled to be turned on and off by an inverted signal of the first signal; a third switch connected in series between the other end of the second constant current source and the node, the third switch being controlled to be turned on and off by a second signal; a fourth switch connected in series between the other end of the second constant current source and the output terminal, the fourth switch being controlled to be turned on and off by an inverted signal of the second signal; a comparator that compares the voltage of the output terminal with the voltage of the node and outputs the comparison result; a fifth switch connected in series between the other end of the third constant current source and the node, the fifth switch being turned on and off by the output of the comparator; a sixth switch connected in series between the other end of the fourth constant current source and the node, the sixth switch being controlled to be turned on and off inversely to the fifth switch by an output of the comparator; a capacitor connected between the node and the second power supply; It is a charge pump circuit. [2] a phase comparator that outputs a first signal and a second signal according to the phase difference between the input clock and the feedback clock; a charge pump circuit that outputs a current according to the first signal and the second signal; a loop filter that converts the current output from the charge pump circuit into a voltage and outputs a control voltage; a VCO that outputs an output clock having a frequency corresponding to the control voltage; a frequency divider that divides the output clock and inputs the divided clock as the feedback clock to the phase comparator, The charge pump circuit a first constant current source having one end connected to the first power supply; a second constant current source having one end connected to the second power supply; One end is connected to the first power supply a third constant current source connected to the second constant current source and having the same current value as the second constant current source; One end is connected to the second power supply a fourth constant current source connected to the first constant current source and having the same current value as the first constant current source; a first switch connected in series between the other end of the first constant current source and an output terminal, the first switch being controlled to be turned on and off by the first signal; a second switch connected in series between the other end of the first constant current source and a node, the second switch being controlled to be turned on and off by an inverted signal of the first signal; a third switch connected in series between the other end of the second constant current source and the node, the third switch being controlled to be turned on and off by the second signal; a fourth switch connected in series between the other end of the second constant current source and the output terminal, the fourth switch being controlled to be turned on and off by an inverted signal of the second signal; a comparator that compares the voltage of the output terminal with the voltage of the node and outputs the comparison result; a fifth switch connected in series between the other end of the third constant current source and the node, the fifth switch being turned on and off by the output of the comparator; a sixth switch connected in series between the other end of the fourth constant current source and the node, the sixth switch being controlled to be turned on and off inversely to the fifth switch by an output of the comparator; a capacitor connected between the node and the second power supply; It is a PLL circuit. [Effects of the Invention]

[0010] According to the present invention, it is possible to provide a charge pump circuit and a PLL circuit that can be easily made faster.

[0011] The present invention has been briefly described above. The details of the present invention will become clearer by reading the following detailed description of the invention (hereinafter referred to as "embodiments") with reference to the accompanying drawings. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a block diagram showing an embodiment of a PLL circuit incorporating a charge pump circuit of the present invention. [Figure 2] FIG. 2 is a circuit diagram illustrating an example of the charge pump circuit shown in FIG. [Figure 3] FIG. 3 is a circuit diagram for explaining the operation of the charge pump circuit shown in FIG. [Figure 4] FIG. 4 is a circuit diagram for explaining the operation of the charge pump circuit shown in FIG. [Figure 5] FIG. 5 is a circuit diagram for explaining the operation of the charge pump circuit shown in FIG. [Figure 6] FIG. 6 is a circuit diagram for explaining the operation of the charge pump circuit shown in FIG. [Figure 7] FIG. 7 is a circuit diagram showing an example of a conventional charge pump circuit. DETAILED DESCRIPTION OF THE INVENTION

[0013] Specific embodiments of the present invention will be described below with reference to the accompanying drawings.

[0014] Fig. 1 is a block diagram showing one embodiment of a PLL (Phase Locked Loop) circuit incorporating a charge pump circuit of the present invention. The PLL circuit 1 shown in Fig. 1 is a circuit that synchronizes an input clock Φin with an output clock Φout. As shown in the figure, the PLL circuit 1 includes a phase comparator 2, a charge pump circuit 3, a loop filter 4, a VCO 5, and a frequency divider 6.

[0015] The phase comparator 2 detects the phase difference between the input clock Φin and the feedback clock Φfb output from the frequency divider 6, and outputs an up signal UP (first signal) or a down signal DN (second signal) with a duty that corresponds to the detected phase difference. The up signal UP is a signal that remains H or L from the rising edge of one of the input clock Φin and the feedback clock Φfb to the rising edge of the other when the phase of the other of the input clock Φin and the feedback clock Φfb is ahead of the other. The down signal DN is a signal that remains H or L from the rising edge of the other of the input clock Φin to the rising edge of the other when the phase of the other of the feedback clock Φfb is ahead of the other.

[0016] The charge pump circuit 3 is a circuit that outputs a current corresponding to the phase difference detected by the phase comparator 2, i.e., the up signal UP and the down signal DN. When the up signal UP is output, the charge pump circuit 3 causes an up current IUP to flow from the charge pump circuit 3 to the output terminal OUT. When the down signal DN is output, the charge pump circuit 3 causes a down current IDN to flow from the output terminal OUT to the charge pump circuit 3. This charge pump circuit 3 will be described later.

[0017] The loop filter 4 converts the up current IUP and down current IDN output from the output terminal OUT of the charge pump circuit 3 into a voltage and outputs a control voltage. The loop filter 4 is composed of a resistor and a capacitor (not shown) connected in parallel between the output terminal OUT of the charge pump circuit 3 and the ground potential. In the loop filter 4, the capacitor is charged in accordance with the output of the up current IUP and discharged in accordance with the output of the down current IDN, generating a control voltage and outputting it to the VCO 5.

[0018] The VCO 5 oscillates at a frequency corresponding to the control voltage and outputs an output clock Φout having a frequency corresponding to the control voltage. The frequency divider 6 divides the output clock Φout and inputs it to the phase comparator 2 as a feedback clock Φfb.

[0019] The PLL circuit 1 configured as described above can output an output clock Φout whose phase and frequency match those of the input clock Φin and the feedback clock Φfb. That is, when the division ratio of the frequency divider 6 is N, it can output an output clock Φout that is N times the input clock Φin.

[0020] Next, details of the charge pump circuit 3 will be described with reference to FIG. 2. The charge pump circuit 3 includes first to fourth constant current sources 31 to 34, first to fourth switches SW1 to SW4, a comparator COMP, fifth and sixth switches SW5 and SW6, and a capacitor C. The first constant current source 31 has one end connected to a first power supply VDD, and flows an up current IUP from one end to the other end. The second constant current source 32 has one end connected to a second power supply VSS, and flows a down current IDN from the other end to the one end. In this embodiment, the up current IUP and the down current IDN are set to the same current value.

[0021] The third constant current source 33 has one end connected to the first power supply VDD and flows a replica down current IDNrep having a current value equal to the down current IDN from one end to the other end. The fourth constant current source 34 has one end connected to the second power supply VSS and flows a replica up current IUPrep having a current value equal to the up current IUP from the other end to one end.

[0022] In this embodiment, the first and third constant current sources 31 and 33 are configured with PMOS transistors. That is, the up current IUP and the replica down current IDNrep are drain currents of PMOS transistors. Also, in this embodiment, the second and fourth constant current sources 32 and 34 are configured with NMOS transistors. That is, the down current IDN and the replica up current IUPrep are drain currents of NMOS transistors.

[0023] The first switch SW1 is composed of a PMOS transistor. The source of the first switch SW1 is connected to the other end of the first constant current source 31, and the drain is connected to the output terminal OUT. An up signal UP is input to the gate of the first switch SW1. The second switch SW2 is composed of a PMOS transistor. The source of the second switch SW2 is connected to the other end of the first constant current source 31, and the drain is connected to node A. An inverted signal UPb of the up signal UP is input to the gate of the second switch SW2.

[0024] The third switch SW3 is composed of an NMOS transistor. The source of the third switch SW3 is connected to the other end of the second constant current source 32, and the drain is connected to node A and the drain of the second switch SW2. A down signal DN is input to the gate of the third switch SW3. The fourth switch SW4 is composed of an NMOS transistor. The source of the fourth switch SW4 is connected to the other end of the second constant current source 32, and the drain is connected to the output terminal OUT and the drain of the first switch SW1. An inverted signal DNb of the down signal DN is input to the gate of the fourth switch SW4.

[0025] The comparator COMP has an output terminal OUT connected to its inverting input terminal and a node A connected to its non-inverting input terminal, and compares the voltages at the output terminal OUT and node A to output the result.

[0026] The fifth switch SW5 is composed of a PMOS transistor. The fifth switch SW5 has a source connected to the other end of the third constant current source 33, a drain connected to node A, and a gate connected to the output of the comparator COMP. The sixth switch SW6 is composed of an NMOS transistor. The sixth switch SW6 has a source connected to the other end of the fourth constant current source 34, a drain connected to node A, and a gate connected to the output of the comparator COMP.

[0027] A capacitor C is connected between node A and a second power supply VSS.

[0028] Next, the operation of the charge pump circuit 3 configured as described above will be described with reference to Figures 3 to 6. For ease of explanation, the first to sixth switches SW1 to SW6 shown in Figures 3 to 6 are represented as on-off switches.

[0029] As shown in Figure 3, in this embodiment, when an L-level up signal UP is output, the first switch SW1 turns on and the second switch SW2, to which the inverted signal UPb is input, turns off. Furthermore, when the down signal DN is H, the third switch SW3 turns on and the fourth switch SW4, to which the inverted signal DNb is input, turns off. At this time, the voltage at the output terminal OUT becomes higher than the voltage at node A, and the comparator COMP outputs an L-level. When the comparator COMP outputs an L-level, the fifth switch SW5 turns on and the sixth switch SW6 turns off.

[0030] As a result, the up-current IUP from the first constant current source 31 flows toward the output terminal OUT via the first switch SW1, charging the capacitor of the loop filter 4. Furthermore, the second constant current source 32 and capacitor C, which are connected in parallel to each other, are connected in series downstream of the third constant current source 33. As described above, when the voltage of the output terminal OUT is higher than that of node A, the replica down-current IDNrep from the third constant current source 33 flows through the fifth switch SW5 to the second constant current source 32 and capacitor C. When the replica down-current IDNrep from the third constant current source 33 is supplied to capacitor C, the voltage of node A rises. As a result, when the voltage of node A becomes approximately equal to that of the output terminal OUT, the replica down-current IDNrep from the third constant current source 33 is not supplied to capacitor C, but flows entirely to the second constant current source 32 as the down-current IDN. Therefore, even while the up current IUP is flowing to the output terminal OUT, the second constant current source 32 can continue to flow the down current IDN, and the node A and the output terminal OUT can be maintained at the same voltage.

[0031] 4, when the up signal UP is output at a high level, the first switch SW1 is turned off and the second switch SW2, to which the inverted signal UPb is input, is turned on. When the down signal DN is at a high level, the third switch SW3 is turned on and the fourth switch SW4, to which the inverted signal DNb is input, is turned off.

[0032] As a result, the current flowing through the output terminal OUT becomes 0 A, and the up current IUP from the first constant current source 31 flows as a down current IDN to the second constant current source 32 via the second switch SW2 and the third switch SW3. At this time, if the voltage of the output terminal OUT is higher than the voltage of node A, the comparator COMP outputs an L level, as shown in FIG. 4. When the comparator COMP outputs an L level, the fifth switch SW5 turns on and the sixth switch SW6 turns off. Then, the capacitor C is charged by the constant current IDrep from the third constant current source 33, and the voltage at node A rises.

[0033] If the voltage at node A rises and the voltage at node A becomes higher than the voltage at the output terminal OUT, the comparator COMP outputs an H level, as shown in Figure 5. When the comparator COMP outputs an H level, the fifth switch SW5 turns off and the sixth switch SW6 turns on. Then, the replica up current IUPrep of the fourth constant current source 34 discharges the capacitor C, causing the voltage at node A to fall. As node A repeatedly rises and falls in this way, the output terminal OUT and node A maintain the same voltage.

[0034] 3 and the operations shown in FIG. 4 or 5 are repeated alternately in the charge pump circuit 3, alternately outputting the up current IUP and the current 0 to the loop filter 4. As a result, the control voltage output from the loop filter 4 increases, and the frequency from the VCO 5 becomes faster.

[0035] 6, in this embodiment, when a low-level down signal DN is output, the third switch SW3 is turned off and the fourth switch SW4, to which the inverted signal DNb is input, is turned on. When the up signal UP is high, the first switch SW1 is turned off and the second switch SW2, to which the inverted signal UPb is input, is turned on. At this time, the voltage at node A becomes higher than the voltage at the output terminal OUT, and the comparator COMP outputs a high level. When the comparator COMP outputs a high level, the sixth switch SW6 is turned on and the fifth switch SW5 is turned off.

[0036] As a result, a down current IDN flows from the output terminal OUT to the second constant current source 32, discharging the capacitor of the loop filter 4. Furthermore, downstream of the first constant current source 31, the fourth constant current source 34 and the capacitor C, which are connected in parallel with each other, are connected in series. As described above, when the voltage at node A is higher than the voltage at the output terminal OUT, the fourth constant current source 34 discharges the capacitor C, thereby lowering the voltage at node A. As a result, when the voltage at node A becomes approximately equal to the voltage at the output terminal OUT, the supply of the discharge current from the capacitor C to the fourth constant current source 34 is stopped, and only the up current IUP from the first constant current source 31 flows as the replica up current IUPrep. Therefore, even while the down current IDN is flowing to the output terminal OUT, the first constant current source 31 can continue to flow the up current IUP, and the node A and the output terminal OUT can be maintained at the same voltage.

[0037] 6 and the operations shown in FIG. 4 or 5 are repeated alternately in the charge pump circuit 3, alternately drawing in the down current IDN and outputting a current of 0 to the loop filter 4. This reduces the control voltage output from the loop filter 4, slowing down the frequency from the VCO 5.

[0038] According to the above-described embodiment, the comparator COMP is used to switch between the third constant current source 33 and the fourth constant current source 34, which makes it easier to achieve high speeds compared to the conventional voltage follower. In addition, the capacitor C removes high frequency components from the voltage at node A, improving the accuracy of the voltage at node A.

[0039] According to the above-described embodiment, the voltage accuracy of the node A can be improved by increasing the capacitance of the capacitor C or increasing the speed of the comparator COMP.

[0040] According to the above-described embodiment, the replica up current IUPrep and the replica down current IDNrep have the same current values as the up current IUP and the down current IDN, respectively. Therefore, unlike the voltage follower circuit of the conventional circuit, an excessive current is not required, and current consumption can be reduced.

[0041] In some cases, the up current IUP and the down current IDN are configured to be changeable. In this case, for example, if the first and third constant current sources 31 and 33 and the second and fourth constant current sources 32 and 34 are configured as current mirror circuits, the replica up current IPUrep and the replica down current IDNrep can be easily made the same as the up current IPU and the down current IDN.

[0042] The present invention is not limited to the above-described embodiments, and can be appropriately modified, improved, etc. Furthermore, the material, shape, size, number, location, etc. of each component in the above-described embodiments are arbitrary and not limited as long as they can achieve the present invention.

[0043] In the above-described embodiment, the up current IUP and the down current IDN are set to the same current value, but this is not limitative and the up current IUP and the down current IDN may have different current values.

[0044] In the above-described embodiment, an example has been described in which transistors are used as the first to fourth constant current sources 31 to 34, but the present invention is not limited to this. The first to fourth constant current sources 31 to 34 may be other well-known current sources capable of supplying current. [Explanation of symbols]

[0045] 1 PLL circuit 2 phase comparator 3 Charge pump circuit 4 Loop Filter 5 VCO 6 frequency divider 31 First constant current source 32 Second constant current source 33 Third constant current source 34 Fourth constant current source A-node C capacitor COMP Comparator OUT output terminal SW1 First switch SW2 Second switch SW3 Third switch SW4 4th switch SW5 Fifth switch SW6 6th switch DN Down signal (second signal) DNb Inverted signal (inverted signal of the second signal) UP Up signal (first signal) UPb Inverted signal (inverted signal of the first signal) VDD First power supply VSS Second power supply Φin Input clock Φfb Feedback clock

Claims

1. A charge pump circuit constituting a PLL circuit, a first constant current source having one end connected to the first power supply; a second constant current source having one end connected to the second power supply; a third constant current source having one end connected to the first power supply and having the same current value as the second constant current source; a fourth constant current source having one end connected to the second power supply and having the same current value as the first constant current source; a first switch connected in series between the other end of the first constant current source and an output terminal, the first switch being controlled to be turned on and off by a first signal; a second switch connected in series between the other end of the first constant current source and a node, the second switch being controlled to be turned on and off by an inverted signal of the first signal; a third switch connected in series between the other end of the second constant current source and the node, the third switch being controlled to be turned on and off by a second signal; a fourth switch connected in series between the other end of the second constant current source and the output terminal, the fourth switch being controlled to be turned on and off by an inverted signal of the second signal; a comparator that compares the voltage of the output terminal with the voltage of the node and outputs the comparison result; a fifth switch connected in series between the other end of the third constant current source and the node, the fifth switch being controlled to be turned on and off by the output of the comparator; a sixth switch connected in series between the other end of the fourth constant current source and the node, the sixth switch being controlled to be turned on and off inversely to the fifth switch by the output of the comparator; a capacitor connected between the node and the second power supply; Charge pump circuit.

2. a phase comparator that outputs a first signal and a second signal according to the phase difference between the input clock and the feedback clock; a charge pump circuit that outputs a current according to the first signal and the second signal; a loop filter that converts the current output from the charge pump circuit into a voltage and outputs a control voltage; a VCO that outputs an output clock having a frequency corresponding to the control voltage; a frequency divider that divides the output clock and inputs the divided clock as the feedback clock to the phase comparator, The charge pump circuit a first constant current source having one end connected to the first power supply; a second constant current source having one end connected to the second power supply; a third constant current source having one end connected to the first power supply and having the same current value as the second constant current source; a fourth constant current source having one end connected to the second power supply and having the same current value as the first constant current source; a first switch connected in series between the other end of the first constant current source and an output terminal, the first switch being controlled to be turned on and off by the first signal; a second switch connected in series between the other end of the first constant current source and a node, the second switch being controlled to be turned on and off by an inverted signal of the first signal; a third switch connected in series between the other end of the second constant current source and the node, the third switch being controlled to be turned on and off by the second signal; a fourth switch connected in series between the other end of the second constant current source and the output terminal, the fourth switch being controlled to be turned on and off by an inverted signal of the second signal; a comparator that compares the voltage of the output terminal with the voltage of the node and outputs the comparison result; a fifth switch connected in series between the other end of the third constant current source and the node, the fifth switch being controlled to be turned on and off by the output of the comparator; a sixth switch connected in series between the other end of the fourth constant current source and the node, the sixth switch being controlled to be turned on and off inversely to the fifth switch by the output of the comparator; a capacitor connected between the node and the second power supply; PLL circuit.

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