Capacitor manufacturing method

Abstract

This method for manufacturing a capacitor 1 includes: a groove forming step; a masking layer forming step; a porous section forming step; a dielectric layer forming step; and a conductor layer forming step. A silicon substrate 2 having a first surface 21, a second surface 22, a capacitance-generating region 31, and a non-capacitance-generating region 32 is prepared, and a groove 4 that sinks from the first surface 21 toward the second surface 22 is formed at the boundary between the capacitance-generating region 31 and the non-capacitance-generating region 32. A masking layer 5 that has a first masking section 51 and a second masking section 52 is formed on the first surface 21 of the silicon substrate 2. An anodic oxidation process is used to form, in the capacitance-generating region 31 of the silicon substrate 2, a porous section 6 that has pores 60. A dielectric layer 7 is formed on the inner surface of the pores 60. A conductor layer 8 having a first conductive section 81 and a second conductive section 82 is formed.

Description

[Technical Field]

[0001] TECHNICAL FIELD The present disclosure relates generally to a method for manufacturing a capacitor, and more particularly to a method for manufacturing a capacitor using a silicon substrate. [Background technology]

[0002] Patent Document 1 discloses a method for manufacturing a capacitor. According to this method, a capacitor is manufactured as follows.

[0003] First, a masking layer is provided on the non-capacitance generating region of a silicon substrate having a main surface including a capacitance generating region and a non-capacitance generating region. Next, pores are formed in the capacitance generating region not covered by the masking layer by anodizing, thereby forming a porous portion extending in the thickness direction of the silicon substrate in the capacitance generating region. Next, a dielectric layer is formed on the inner surface of the pore. Next, a conductor layer is formed, including a filling portion filling at least a portion of the pore and a surface portion covering at least a portion of the surface of the capacitance generating region.

[0004] In this manner, the capacitor is manufactured.

[0005] According to the capacitor manufacturing method of Patent Document 1, there is a risk that the corners of the porous portion may cut into the portion of the silicon substrate that overlaps with the capacitance producing region in the thickness direction, and then cut into the portion of the silicon substrate that overlaps with the non-capacitance producing region in the thickness direction (see FIG. 1B of Patent Document 1). When the corners of the porous portion cut into the porous portion in this way, it is expected that the thickness of the dielectric layer formed on the inner surface of the pores at the corners will become non-uniform. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] International Publication No. 2020 / 184517 Summary of the Invention

[0007] An object of the present disclosure is to provide a method for manufacturing a capacitor that can prevent a porous portion from being formed in a non-capacitance generating region.

[0008] A method for manufacturing a capacitor according to one embodiment of the present disclosure includes a groove forming step, a masking layer forming step, a porous portion forming step, a dielectric layer forming step, and a conductor layer forming step. The groove forming step involves preparing a silicon substrate having a first surface and a second surface opposite the first surface, and having a capacitance-producing region and a non-capacitance-producing region other than the capacitance-producing region when viewed along a line connecting the first and second surfaces. A groove recessed from the first surface toward the second surface is formed at the boundary between the capacitance-producing region and the non-capacitance-producing region. The masking layer forming step involves forming a masking layer on the first surface of the silicon substrate, the masking layer including a first masking portion covering the non-capacitance-producing region and a second masking portion not covering at least a portion of the capacitance-producing region. The porous portion forming step involves forming a porous portion having pores in the capacitance-producing region of the silicon substrate by anodizing. The dielectric layer forming step involves forming a dielectric layer on the inner surfaces of the pores. In the conductor layer forming process, a conductor layer is formed having a first conductive portion in contact with the dielectric layer and a second conductive portion electrically connected to the first conductive portion and present in the capacitance generating region of the first surface.

[0009] A method for manufacturing a capacitor according to one embodiment of the present disclosure includes an n-type semiconductor portion forming step, a masking layer forming step, a porous portion forming step, a dielectric layer forming step, and a conductor layer forming step. The n-type semiconductor portion forming step includes preparing a p-type silicon substrate having a first surface and a second surface opposite the first surface, and having a capacitance generating region and a non-capacitance generating region other than the capacitance generating region when viewed along a direction connecting the first surface and the second surface. An n-type semiconductor portion extending from the first surface toward the second surface is formed at the boundary between the capacitance generating region and the non-capacitance generating region. The masking layer forming step includes forming a masking layer on the first surface of the silicon substrate. The masking layer includes a first masking portion covering the non-capacitance generating region and a second masking portion not covering at least a portion of the capacitance generating region. The porous portion forming step includes forming a porous portion having pores in the capacitance generating region of the silicon substrate by anodizing. The dielectric layer forming step includes forming a dielectric layer on the inner surfaces of the pores. In the conductor layer forming process, a conductor layer is formed having a first conductive portion in contact with the dielectric layer and a second conductive portion electrically connected to the first conductive portion and present in the capacitance generating region of the first surface.

[0010] A method for manufacturing a capacitor according to one embodiment of the present disclosure includes a masking layer forming step, a porous portion forming step, a dielectric layer forming step, and a conductor layer forming step. The masking layer forming step includes preparing a silicon substrate having a first surface and a second surface opposite the first surface, and having a capacitance-producing region and a non-capacitance-producing region other than the capacitance-producing region when viewed along a line connecting the first and second surfaces. A masking layer is formed on the first surface of the silicon substrate, the masking layer having a first masking portion covering the non-capacitance-producing region and a second masking portion not covering at least a portion of the capacitance-producing region. The porous portion forming step includes forming a back surface electrode having the same shape as the capacitance-producing region when viewed along a line connecting the first and second surfaces, at the same position as the capacitance-producing region on the second surface of the silicon substrate, and performing an anodization process using the back surface electrode as an anode to form a porous portion having pores in the capacitance-producing region of the silicon substrate. The dielectric layer forming step includes forming a dielectric layer on the inner surfaces of the pores. In the conductor layer forming process, a conductor layer is formed having a first conductive portion in contact with the dielectric layer and a second conductive portion electrically connected to the first conductive portion and present in the capacitance generating region of the first surface.

[0011] A method for manufacturing a capacitor according to one embodiment of the present disclosure includes a masking layer forming step, a low-resistance portion forming step, a porous portion forming step, a dielectric layer forming step, and a conductor layer forming step. The masking layer forming step includes preparing a silicon substrate having a first surface and a second surface opposite the first surface, and having a capacitance-producing region and a non-capacitance region other than the capacitance-producing region when viewed along a line connecting the first surface and the second surface. A masking layer is formed on the first surface of the silicon substrate, the masking layer including a first masking portion covering the non-capacitance region and a second masking portion not covering at least a portion of the capacitance-producing region. The low-resistance portion forming step includes forming a low-resistance portion within the silicon substrate at the same position as the capacitance-producing region, the low-resistance portion having the same shape as the capacitance-producing region when viewed along a line connecting the first surface and the second surface and a lower resistivity than the silicon substrate, the low-resistance portion extending from the second surface toward the first surface. In the porous portion forming step, a porous portion having pores is formed in the capacitance generating region of the silicon substrate by anodizing. In the dielectric layer forming step, a dielectric layer is formed on the inner surface of the pores. In the conductor layer forming step, a conductor layer is formed having a first conductive portion in contact with the dielectric layer and a second conductive portion electrically connected to the first conductive portion and present in the capacitance generating region of the first surface. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a schematic perspective view showing a capacitor according to the first embodiment. [Figure 2] 2A to 2D are schematic perspective views showing an example of a method for manufacturing the capacitor. [Figure 3] 3A to 3C are schematic perspective views showing an example of a method for manufacturing the capacitor. [Figure 4] 4A to 4C are schematic perspective views showing an example of a method for manufacturing the capacitor. [Figure 5] 5A to 5D are schematic cross-sectional views showing modified examples of the groove portion. [Figure 6]6A to 6E are schematic cross-sectional views showing an example of a method for forming a groove. [Figure 7] 7A to 7C are schematic cross-sectional views showing an example of a method for forming a groove. [Figure 8] 8A to 8C are schematic cross-sectional views showing an example of a method for forming a groove. [Figure 9] Fig. 9A is a diagram illustrating the function of the grooves when anodizing treatment is performed in the first embodiment, and Fig. 9B is a diagram illustrating the function of the n-type semiconductor portion when anodizing treatment is performed in the second embodiment. [Figure 10] FIG. 10 is a schematic perspective view showing a capacitor according to the third embodiment. [Figure 11] 11A to 11C are schematic perspective views showing an example of a method for manufacturing the capacitor. [Figure 12] 12A to 12C are schematic perspective views showing an example of a method for manufacturing the capacitor. [Figure 13] 13A to 13C are schematic perspective views showing an example of a method for manufacturing the capacitor. [Figure 14] 14A to 14D are schematic cross-sectional views showing a modified example of the method for manufacturing the capacitor. [Figure 15] 15A to 15E are schematic cross-sectional views showing an example of a method for forming a groove. [Figure 16] 16A to 16C are schematic cross-sectional views showing an example of a method for forming a groove. [Figure 17] 17A to 17C are schematic cross-sectional views showing an example of a method for forming a groove. [Figure 18] Fig. 18A is a diagram illustrating the function of the back electrode when anodizing treatment is performed in the third embodiment, and Fig. 18B is a diagram illustrating the function of the low resistance portion when anodizing treatment is performed in the fourth embodiment. [Figure 19] FIG. 19 is a diagram illustrating a phenomenon that may occur when anodizing treatment is performed. DETAILED DESCRIPTION OF THE INVENTION

[0013] 1. First embodiment (overview) As described above, according to the capacitor manufacturing method of Patent Document 1, there is a risk that the corners of the porous portion may penetrate from the portion that overlaps the capacitance generating region of the silicon substrate in the thickness direction to the portion that overlaps the non-capacitance generating region of the silicon substrate in the thickness direction (see Figure 1B of Patent Document 1).

[0014] Fig. 19 illustrates a phenomenon that may occur during anodization. That is, anodization can be performed by immersing the silicon substrate 2 and a platinum electrode (not shown) in hydrofluoric acid and applying electricity to the back electrode 9 of the silicon substrate 2 as the anode and the platinum electrode as the cathode. Note that Fig. 19 does not illustrate the masking layer 5 that covers at least the non-capacitance generating region 32 of the first surface 21 of the silicon substrate 2.

[0015] 19, the direction of the electric field may be unique at the boundary between the capacitance generating region 31 and the non-capacitance generating region 32. Here, the direction of the electric field is indicated by the dotted arrow in FIG.

[0016] Specifically, in the capacitance generating region 31, the direction of the electric field is from the second surface 22 to the first surface 21. That is, in the capacitance generating region 31, the direction of the electric field can be substantially parallel to the thickness direction of the silicon substrate 2. On the other hand, in the non-capacitance generating region 32, the direction of the electric field can be inclined from the non-capacitance generating region 32 to the capacitance generating region 31 as it moves from the second surface 22 to the first surface 21.

[0017] Therefore, the porous portion 6 may be formed not only in the capacitance generating region 31 but also in the non-capacity generating region 32. That is, it is presumed that a part of the porous portion 6 protrudes from the capacitance generating region 31 toward the non-capacity generating region 32, forming an inclined pore 69. The inclined pore 69 is a pore that is inclined from the capacitance generating region 31 of the first surface 21 toward the non-capacity generating region 32 of the second surface 22.

[0018] In contrast, in this embodiment, as shown in FIG. 9A , a groove 4 is formed at the boundary between the capacitance generating region 31 and the non-capacitance generating region 32. The groove 4 is recessed from the first surface 21 toward the second surface 22 of the silicon substrate 2. The presence of such groove 4 can block the electric field that flows from the non-capacitance generating region 32 of the second surface 22 to the capacitance generating region 31 of the first surface 21 during anodization. As a result, the porous portion 6 is formed almost entirely in the capacitance generating region 31, and is prevented from being formed in the non-capacitance generating region 32. Note that in FIG. 9A , the first surface 21 of the silicon substrate 2 is covered with a masking layer 5. In the capacitance generating region 31, a plurality of through holes 520 are formed in the masking layer 5.

[0019] 2. First embodiment (details) (1) Capacitor The capacitor 1 according to this embodiment will be described below with reference to the drawings. For the convenience of explaining positional relationships, etc., arrows indicating the X-axis, Y-axis, and Z-axis that constitute a three-dimensional Cartesian coordinate system are shown in the drawings, but these arrows do not have any physical form. Hereinafter, the XY plan view refers to the view along the Z-axis direction. The directions of the X-axis, Y-axis, and Z-axis are merely examples and are not intended to limit the directions during the manufacture and use of the capacitor 1. Furthermore, the front surface (surface facing the positive X-axis direction) of an object (such as the capacitor 1) illustrated as a perspective view represents a cut surface.

[0020] 1 shows a capacitor 1 according to this embodiment. The capacitor 1 includes a silicon substrate 2, a dielectric layer 7, and a conductive layer 8. The capacitor 1 may further include an insulating layer 210 and a terminal 800.

[0021] <Silicon substrate> The silicon substrate 2 can constitute one electrode (first electrode) of the capacitor 1. In this embodiment, the silicon substrate 2 is a p-type semiconductor, but it may also be an n-type semiconductor. A p-type semiconductor is formed by adding a trace amount of a trivalent element (boron, aluminum, gallium, indium, etc.) to an intrinsic semiconductor of a tetravalent element (silicon). An n-type semiconductor is formed by adding a trace amount of a pentavalent element (phosphorus, arsenic, antimony, etc.) to an intrinsic semiconductor of a tetravalent element (silicon).

[0022] In this embodiment, the silicon substrate 2 has a plate shape extending in the X-axis direction and the Y-axis direction. The shape of the silicon substrate 2 in the XY plane view is rectangular, but is not particularly limited. The thickness of the silicon substrate 2 (length in the Z-axis direction) is not particularly limited, but is, for example, 300 μm or more and 1000 μm or less.

[0023] The silicon substrate 2 has a first surface 21 and a second surface 22. The first surface 21 is a surface facing in the positive direction of the Z axis. The second surface 22 is located on the opposite side of the first surface 21. In other words, the second surface 22 is a surface facing in the negative direction of the Z axis.

[0024] When viewed along the direction (Z-axis direction) connecting the first surface 21 and the second surface 22, the silicon substrate 2 has a capacitance generating region 31 and a non-capacitance generating region 32 (see FIG. 1). The capacitance generating region 31 is a region formed for the purpose of generating the capacitance of the capacitor 1. In this embodiment, the shape of the capacitance generating region 31 in the XY plane is rectangular, but is not particularly limited thereto. The non-capacitance generating region 32 is a region other than the capacitance generating region 31. In this embodiment, the non-capacitance generating region 32 surrounds the capacitance generating region 31 in the XY plane.

[0025] The silicon substrate 2 has a groove 4. The groove 4 exists at the boundary between the capacitance generating region 31 and the non-capacitance generating region 32. In this embodiment, the groove 4 surrounds the capacitance generating region 31 in the XY plane view. The groove 4 is recessed from the first surface 21 toward the second surface 22 of the silicon substrate 2. The depth of the groove 4 (the length in the Z-axis direction) is shorter than the thickness of the silicon substrate 2. The width of the groove 4 (the distance between opposing inner surfaces) is not particularly limited.

[0026] The silicon substrate 2 has a porous portion 6. The porous portion 6 exists in the capacitance generating region 31. In the XY plan view, the porous portion 6 is surrounded by the groove portion 4. The porous portion 6 exists from the first surface 21 of the silicon substrate 2 to between the first surface 21 and the second surface 22. The depth of the porous portion 6 is not particularly limited, but is, for example, 5 μm or more and 200 μm or less.

[0027] The porous portion 6 has a plurality of pores 60. In this embodiment, the plurality of pores 60 are arranged in a lattice pattern in an XY plan view (see FIG. 3A). That is, the plurality of pores 60 are arranged at a constant pitch in each of the X-axis direction and the Y-axis direction. The pores 60 are blind holes extending from the first surface 21 to the second surface of the silicon substrate 2. The pores 60 are open in the first surface 21 of the silicon substrate 2. The plurality of pores 60 are approximately parallel to the thickness direction (Z-axis direction) of the silicon substrate 2. The depth of the porous portion 6 is the average depth (length in the Z-axis direction) of the plurality of pores 60. The inner diameter of the pores 60 is not particularly limited, but is, for example, 0.5 μm or more and 5 μm or less.

[0028] <Insulating layer> The insulating layer 210 is a layer having electrical insulation properties. The insulating layer 210 is formed in the non-capacitance generating region 32 of the first surface 21 of the silicon substrate 2. The insulating layer 210 may be composed of a single layer, or may be composed of multiple layers. In this embodiment, the insulating layer 210 includes a first insulating layer 211 and a second insulating layer 212. The first insulating layer 211 may include silicon oxide (SiO2). The second insulating layer 212 may include silicon nitride (Si3N4).

[0029] The thickness of the insulating layer 210 is not particularly limited, but is, for example, not less than 0.1 μm and not more than 2.0 μm.

[0030] <Dielectric layer> The dielectric layer 7 is an electrically insulating layer interposed between the first electrode (mainly the silicon substrate 2) and the second electrode (mainly the conductor layer 8) of the capacitor 1. The dielectric layer 7 is formed on the inner surface of the pore 60 (see FIG. 1). The dielectric layer 7 is further formed in the capacitance generating region 31 of the first surface 21 of the silicon substrate 2. The thickness of the dielectric layer 7 is not particularly limited, but is, for example, 10 nm to 500 nm.

[0031] The material of the dielectric layer 7 is not particularly limited, but examples thereof include silicon oxide, titanium oxide, zirconium oxide, hafnium oxide, vanadium oxide, tungsten oxide, niobium oxide, tantalum oxide, and aluminum oxide. For example, the dielectric layer 7 containing silicon oxide can be formed by oxidizing the inner surface of the pores 60.

[0032] The dielectric layer 7 may be composed of a single film or multiple films. The multiple films are not particularly limited, but may include, for example, an ONO film (Oxide / Nitride / Oxide film). The ONO film includes a first silicon oxide film, a silicon nitride film, and a second silicon oxide film. The ONO film is formed by laminating the first silicon oxide film, the silicon nitride film, and the second silicon oxide film in this order.

[0033] <Conductive layer> The conductor layer 8 is a layer having conductivity and can constitute the other electrode (second electrode) of the capacitor 1. That is, the conductor layer 8 can constitute an electrode that forms a pair with the silicon substrate 2 in the capacitor 1. The material of the conductor layer 8 is not particularly limited, but examples thereof include polysilicon (polycrystalline silicon), platinum, and ruthenium.

[0034] The conductive layer 8 has a first conductive portion 81, a second conductive portion 82, and a third conductive portion 83 (see FIG. 1).

[0035] The first conductive portion 81 is in contact with the dielectric layer 7. In this embodiment, the first conductive portion 81 is filled inside the pore 60 via the dielectric layer 7. The first conductive portion 81 is not in contact with the silicon substrate 2.

[0036] The second conductive portion 82 is present in the capacitance generating region 31 of the first surface 21 of the silicon substrate 2. In this embodiment, the second conductive portion 82 is formed in the capacitance generating region 31 of the first surface 21 of the silicon substrate 2 via the dielectric layer 7. The second conductive portion 82 covers the porous portion 6 via the dielectric layer 7. The second conductive portion 82 is also not in contact with the silicon substrate 2. The second conductive portion 82 is electrically connected to the first conductive portion 81. The thickness (length in the Z-axis direction) of the second conductive portion 82 is not particularly limited, but is, for example, 1 μm or more and 20 μm or less.

[0037] The third conductive portion 83 is present in the non-capacitance generating region 32 of the first surface 21 of the silicon substrate 2. The third conductive portion 83 is formed in the non-capacitance generating region 32 of the first surface 21 of the silicon substrate 2 via the insulating layer 210. The third conductive portion 83 is also not in contact with the silicon substrate 2. The third conductive portion 83 is electrically connected to the second conductive portion 82. Therefore, the third conductive portion 83 is electrically connected to the first conductive portion 81 via the second conductive portion 82.

[0038] <Terminal> The terminal 800 is a conductive member. The terminal 800 includes a first terminal 810 and a second terminal 820.

[0039] The first terminal 810 is disposed on the surface (the surface facing the positive direction of the Z-axis) of the insulating layer 210 (particularly the second insulating layer 212). A portion of the first terminal 810 penetrates the insulating layer 210 in the Z-axis direction and is electrically connected to the silicon substrate 2. The first terminal 810 is in ohmic contact with the silicon substrate 2. The thickness (length in the Z-axis direction) of the first terminal 810 is not particularly limited, but is, for example, not less than 200 nm and not more than 500 nm. The thickness of the first terminal 810 is the thickness of the portion disposed on the surface of the insulating layer 210.

[0040] The second terminal 820 is disposed on the surface (surface facing the positive direction of the Z-axis) of the third conductive portion 83. The second terminal 820 is electrically connected to the third conductive portion 83. The second terminal 820 is in ohmic contact with the third conductive portion 83. The thickness (length in the Z-axis direction) of the second terminal 820 is not particularly limited, but is, for example, not less than 100 nm and not more than 2000 nm.

[0041] (2) Capacitor manufacturing method (2.1) First embodiment Next, a method for manufacturing the capacitor 1 according to the first embodiment will be described with reference to the drawings. The method for manufacturing the capacitor 1 includes a groove forming step, a masking layer forming step, a porous portion forming step, a dielectric layer forming step, and a conductor layer forming step. The method for manufacturing the capacitor 1 may further include a terminal forming step.

[0042] <Groove formation process> In the groove forming step, first, as shown in FIG. 2A, a silicon substrate 2 is prepared. Next, as shown in FIG. 2B, a groove 4 is formed at the boundary between the capacitance generating region 31 and the non-capacitance generating region 32 of the silicon substrate 2. That is, the groove 4 is formed so as to surround the capacitance generating region 31 in the XY plane view. In this embodiment, the groove 4 is formed in a rectangular shape in the XY plane view. The groove 4 is formed so as to be recessed from the first surface 21 toward the second surface 22 of the silicon substrate 2. That is, the groove 4 is formed so as to be recessed in the negative direction of the Z axis.

[0043] The method for forming the grooves 4 is not particularly limited, but examples thereof include dry etching and wet etching.

[0044] Dry etching can be exemplified by reactive ion etching (RIE). Among reactive ion etching methods, deep RIE is preferred because it allows etching with a high aspect ratio (narrow and deep). Among deep RIE methods, the Bosch process is particularly preferred because it allows etching with a high aspect ratio.

[0045] The Bosch process is a process that repeats two processes: an etching step and a protection step. The etching step mainly uses sulfur hexafluoride (SF6) for isotropic etching. The protection step uses Teflon (registered trademark)-based gas (C4F8) to protect the sidewalls and suppress lateral etching.

[0046] Examples of wet etching include anisotropic etching, etc. Examples of anisotropic etching solutions include, but are not limited to, a KOH aqueous solution and a TMAH (tetramethylammonium hydroxide) aqueous solution.

[0047] <Masking layer formation process> In the masking layer formation step, as shown in FIG. 2C , first, a first insulating layer 211 is formed on the first surface 21 of the silicon substrate 2, and a third insulating layer 213 is formed on the second surface 22 of the silicon substrate 2. The first insulating layer 211 and the third insulating layer 213 can be formed by, for example, thermal oxidation treatment. The thermal oxidation treatment can be performed by heating the silicon substrate 2 at a temperature of 1000° C. or higher and 1200° C. or lower in an oxygen atmosphere. As a result, the first insulating layer 211 and the third insulating layer 213 become layers containing silicon oxide.

[0048] Next, a masking layer 5 is formed on the first surface 21 of the silicon substrate 2. In this embodiment, as shown in FIG. 2C, the masking layer 5 is formed on the first surface 21 of the silicon substrate 2 via the first insulating layer 211. That is, the masking layer 5 is formed on the surface of the first insulating layer 211 (the surface facing the positive direction of the Z axis). The masking layer 5 can be formed by, for example, a chemical vapor deposition (CVD) method. Examples of chemical vapor deposition methods include, but are not limited to, thermal CVD and plasma CVD. Examples of materials for the masking layer 5 include, but are not limited to, silicon nitride. In this embodiment, the masking layer 5 is a layer containing silicon nitride.

[0049] Next, as shown in FIG. 2D, partial etching is performed on the masking layer 5. The partial etching is performed on the masking layer 5 present in the capacitance generating region 31, but not on the masking layer 5 present in the non-capacitance generating region 32. The partial etching is not particularly limited, but examples thereof include dry etching. Among dry etching methods, plasma etching is preferred.

[0050] The portion of the masking layer 5 that has not been partially etched becomes a first masking portion 51. The portion of the masking layer 5 that has been partially etched becomes a second masking portion 52. In this way, the masking layer 5 has the first masking portion 51 and the second masking portion 52 (see FIG. 2D).

[0051] The first masking portion 51, together with the first insulating layer 211, covers the non-capacitance generating region 32 of the first surface 21 of the silicon substrate 2. The first masking portion 51 will eventually become the second insulating layer 212.

[0052] The second masking portion 52 does not cover at least a portion of the capacitance generating region 31. In this embodiment, the second masking portion 52 has a plurality of through holes 520. The plurality of through holes 520 penetrate the masking layer 5 and the first insulating layer 211 in the thickness direction (Z-axis direction). In this manner, the portion of the capacitance generating region 31 on the first surface 21 of the silicon substrate 2 where the through holes 520 exist is not covered and is exposed to the outside.

[0053] The plurality of through holes 520 are arranged in a lattice pattern in the XY plane (see FIG. 2D). That is, the plurality of through holes 520 are arranged at a constant pitch in each of the X-axis direction and the Y-axis direction. The second masking portion 52 is finally removed.

[0054] 5A, a masking layer 5 may be formed on the inner surface of the groove 4. The groove 4 does not have to be filled with the masking layer 5. Note that the first insulating layer 211 is omitted in FIG. 5A.

[0055] <Porous part formation process> 3A, in the porous portion forming step, first, a back surface electrode 9 is formed on the second surface 22 of the silicon substrate 2. The back surface electrode 9 can be formed by, for example, a physical vapor deposition (PVD) method. The back surface electrode 9 is electrically connected to the silicon substrate 2. The back surface electrode 9 is in ohmic contact with the silicon substrate 2.

[0056] Next, an anodization process is performed on the silicon substrate 2. The anodization process can be performed by immersing the silicon substrate 2 and a platinum electrode (not shown) in an electrolyte and applying a current to the back electrode 9 of the silicon substrate 2 as the anode and the platinum electrode as the cathode. As a result, a porous portion 6 is formed in the capacitance generating region 31 of the silicon substrate 2.

[0057] The electrolytic solution is not particularly limited, but examples thereof include hydrofluoric acid. The hydrofluoric acid may further contain ethanol. This effectively removes hydrogen generated during anodization, resulting in the formation of a porous portion 6 with a more uniform structure.

[0058] In this embodiment, the second masking portion 52 has a plurality of through holes 520, so that the pores 60 tend to grow straight in the negative Z-axis direction starting from the through holes 520. The depth and inner diameter of the pores 60 can be adjusted by the conditions of the anodizing treatment. The conditions of the anodizing treatment are not particularly limited, but examples thereof include the resistivity (electrical resistivity) of the silicon substrate 2, the composition of the electrolyte, and the current density.

[0059] 3A, after the anodization treatment, the first insulating layer 211 and the second masking portion 52 in the capacitance generating region 31 are removed from the first surface 21 of the silicon substrate 2. This exposes the capacitance generating region 31 on the first surface 21 of the silicon substrate 2. That is, the openings of the multiple pores 60 are exposed. Furthermore, the back surface electrode 9 is removed from the second surface 22 of the silicon substrate 2.

[0060] <Dielectric layer forming process> 3B, in the dielectric layer forming step, the dielectric layer 7 is formed on the inner surface of the pore 60. Furthermore, in this embodiment, the dielectric layer 7 is formed in the capacitance generating region 31 of the first surface 21 of the silicon substrate 2.

[0061] The dielectric layer 7 can be formed by, for example, thermal oxidation. The thermal oxidation can be performed by heating the silicon substrate 2, on which the porous portion 6 is formed, at a temperature of 800°C or higher and 1200°C or lower in an oxygen atmosphere. As a result, the dielectric layer 7 becomes a layer containing silicon oxide. The dielectric layer 7 may also be formed by chemical vapor deposition.

[0062] <Conductor layer formation process> 3C, in the conductor layer forming step, a conductor layer 8 is formed to cover the first surface 21 of the silicon substrate 2. Specifically, in the capacitance generating region 31, the conductor layer 8 is formed on the first surface 21 of the silicon substrate 2 with a dielectric layer 7 interposed therebetween. In addition, in the non-capacitance generating region 32, the conductor layer 8 is formed on the first surface 21 of the silicon substrate 2 with an insulating layer 210 interposed therebetween.

[0063] The conductive layer 8 can be formed by, for example, chemical vapor deposition. The material of the conductive layer 8 is not particularly limited, but examples thereof include polysilicon, platinum, and ruthenium.

[0064] When chemical vapor deposition is performed, the material of the conductor layer 8 enters the pores 60 of the porous portion 6 and is deposited on the dielectric layer 7 formed on the inner surface of the pores 60, thereby forming the first conductive portion 81. In this way, the first conductive portion 81 comes into contact with the dielectric layer 7. Furthermore, in the capacitance generating region 31, the material of the conductor layer 8 is deposited on the surface of the dielectric layer 7 (the surface facing the positive direction of the Z axis), thereby forming the second conductive portion 82. In this way, the second conductive portion 82 is present in the capacitance generating region 31 on the first surface 21 of the silicon substrate 2. The second conductive portion 82 is electrically connected to the first conductive portion 81.

[0065] Next, a portion of the conductive layer 8 present in the non-capacitance generating region 32 on the first surface 21 of the silicon substrate 2 is removed. The conductive layer 8 can be removed using, for example, a semiconductor laser. As shown in FIG. 4A , the conductive layer 8 remaining in the non-capacitance generating region 32 becomes the third conductive portion 83. The third conductive portion 83 is connected to and electrically connected to the second conductive portion 82.

[0066] <Terminal formation process> 4B, in the terminal formation step, first, a hole 840 is formed in the non-capacitance generating region 32 of the silicon substrate 2, penetrating the insulating layer 210. The bottom surface of the hole 840 is the first surface 21 of the silicon substrate 2. The hole 840 can be formed by, for example, partial etching.

[0067] Next, as shown in FIG. 4C , a metal layer 830 is formed to cover the first surface 21 of the silicon substrate 2. Specifically, in the capacitance generating region 31, the metal layer 830 is formed on the first surface 21 of the silicon substrate 2 via the second conductive portion 82 and the dielectric layer 7. In addition, in part of the non-capacitance generating region 32, the metal layer 830 is formed on the inner surface of the hole 840. As a result, the metal layer 830 comes into contact with the first surface 21 of the silicon substrate 2. Furthermore, in the remaining part of the non-capacitance generating region 32, the metal layer 830 is formed on the first surface 21 of the silicon substrate 2 via the insulating layer 210. The metal layer 830 can be formed by, for example, chemical vapor deposition.

[0068] Thereafter, the metal layer 830 is removed, leaving only the portion in contact with the silicon substrate 2 through the hole 840 and the portion in contact with the third conductive portion 83. The metal layer 830 can be removed using, for example, a semiconductor laser. The portion in contact with the silicon substrate 2 through the hole 840 becomes the first terminal 810. The portion in contact with the third conductive portion 83 becomes the second terminal 820.

[0069] Through the above steps, the capacitor 1 shown in FIG. 1 is manufactured.

[0070] <Action and effect> In this embodiment, prior to the porous portion forming step (specifically, anodization), a groove portion 4 is formed at the boundary between the capacitance generating region 31 and the non-capacitance generating region 32, as shown in FIG. 9A. The groove portion 4 is recessed from the first surface 21 toward the second surface 22 of the silicon substrate 2. The presence of such groove portion 4 can block the electric field directed from the non-capacitance generating region 32 of the second surface 22 to the capacitance generating region 31 of the first surface 21 during anodization. As a result, the porous portion 6 is formed almost entirely in the capacitance generating region 31, and is prevented from being formed in the non-capacitance generating region 32. The dotted arrow in FIG. 9A indicates the direction of the electric field. The first insulating layer 211 is omitted from FIG. 9A.

[0071] Furthermore, in this embodiment, the second masking portion 52 of the masking layer 5 has a plurality of through holes 520 (see FIG. 2D ), and therefore the pores 60 tend to grow straight from the first surface 21 toward the second surface 22, starting from the through holes 520. That is, the plurality of pores 60 in the porous portion 6 tend to be formed elongated along the thickness direction of the silicon substrate 2. This makes it difficult to form inclined pores 69 as shown in FIG.

[0072] <Modification: Filling Process> Below, modified examples of the method for manufacturing the capacitor 1 according to the first embodiment will be described with reference to the drawings. In the following modified examples, components similar to those in the first embodiment will be given the same reference numerals as in the first embodiment, and detailed descriptions thereof may be omitted. The method for manufacturing the capacitor 1 according to the following modified examples further includes a filling step in addition to the steps included in the method for manufacturing the capacitor 1 according to the first embodiment.

[0073] <First Modification> In the filling step of the first modified example, as shown in FIG. 5B, an insulating material 41 is filled inside the groove 4. The insulating material 41 is not particularly limited, but examples thereof include silicon oxide. The insulating material 41 may be the material of the masking layer 5. That is, the masking layer 5 may be filled inside the groove 4.

[0074] The method for filling the insulating material 41 into the groove 4 is not particularly limited, but examples thereof include a method using thermal oxidation treatment, a chemical vapor deposition method, etc. These methods will be described below.

[0075] 7A to 7C show how insulating material 41 is filled into trench 4 using thermal oxidation. That is, as shown in FIG. 7A, a silicon substrate 2 is prepared. Next, as shown in FIG. 7B, trench 4 is formed in silicon substrate 2 by dry etching (e.g., reactive ion etching, etc.). Next, as shown in FIG. 7C, thermal oxidation is performed by heating silicon substrate 2 at a temperature of 1000°C or higher and 1200°C or lower in an oxygen atmosphere. As a result, silicon oxide, which is insulating material 41, is filled into trench 4. The method of using thermal oxidation is particularly effective when trench 4 has a shallow depth D1 and a narrow width W1.

[0076] 8A to 8C show how insulating material 41 is filled into trench 4 by chemical vapor deposition. That is, as shown in FIG. 8A, a silicon substrate 2 is prepared. Next, as shown in FIG. 8B, trench 4 is formed in silicon substrate 2 by dry etching (e.g., reactive ion etching, etc.). Next, as shown in FIG. 8C, chemical vapor deposition is performed on silicon substrate 2 under reduced pressure. As a result, insulating material 41 is filled into trench 4. Chemical vapor deposition is particularly effective when trench 4 has a deep depth D2 and a wide width W2.

[0077] As described above, according to the first modification, the insulating material 41 is filled inside the grooves 4, thereby improving the electric field blocking effect of the grooves 4. As a result, the formation of the porous portion 6 in the non-capacity generating region 32 can be further suppressed.

[0078] <<Second Modification>> In the filling step of the second modified example, as shown in FIG. 5C , an insulating layer 42 is formed on the inner surface of the groove 4, and a filling material 43 is filled into the groove 4 with the insulating layer 42 formed thereon. The material of the insulating layer 42 is not particularly limited, but examples thereof include silicon oxide. The insulating layer 42 may also be a masking layer 5. That is, a masking layer 5 may be formed on the inner surface of the groove 4. The filling material 43 may be a conductive material or an electrically insulating material. Thus, examples of the filling material 43 include, but are not particularly limited to, polysilicon. In the second modified example, for example, a method utilizing thermal oxidation and a chemical vapor deposition method are used in combination.

[0079] 6A to 6E show the filling process of the second modified example. First, a silicon substrate 2 is prepared as shown in FIG. 6A. Next, as shown in FIG. 6B, a groove 4 is formed in the silicon substrate 2 by dry etching (e.g., reactive ion etching, etc.). Next, as shown in FIG. 6C, a thermal oxidation process is performed by heating the silicon substrate 2 at a temperature of 1000°C to 1200°C in an oxygen atmosphere. This forms silicon oxide as an insulating layer 42 on the inner surface of the groove 4. Voids remain in the groove 4. Next, as shown in FIG. 6D, chemical vapor deposition is performed on the silicon substrate 2 under reduced pressure. This fills the voids in the groove 4 with a filling material 43. Because the filling material 43 fills the interior of the groove 4 through the insulating layer 42, the filling material 43 does not come into contact with the groove 4 (i.e., the silicon substrate 2). Therefore, the filling material 43 may be a conductive material. Thereafter, as shown in FIG. 6E, the filling material 43 that does not fill the groove 4 is removed.

[0080] According to the second modification, the electric field blocking effect of the grooves 4 can be improved by filling the grooves 4 with the filler material 43. As a result, it is possible to further prevent the porous portions 6 from being formed in the non-capacitance generating regions 32. Furthermore, even if the grooves 4 are formed deep, the grooves 4 can be easily filled with the filler material 43 by using the chemical vapor deposition method.

[0081] <Third Modification> In the third modification, the silicon substrate 2 is a p-type semiconductor. In the filling step, as shown in Fig. 5D, an n-type semiconductor layer 24 is formed on the inner surface of the groove 4, and a filling material 43 is filled into the groove 4 with the n-type semiconductor layer 24 formed therein. The filling material 43 is not particularly limited, but examples thereof include polysilicon.

[0082] First, a trench 4 is formed in the silicon substrate 2 by dry etching (e.g., reactive ion etching, etc.). Next, an n-type semiconductor layer 24 is formed on the inner surface of the trench 4. Specifically, a phosphate film (PO) is formed on the inner surface of the trench 4, phosphorus is diffused from the phosphate film into the trench 4, and the phosphate film is then removed by wet etching, etc., to form the n-type semiconductor layer 24 on the inner surface of the trench 4. Voids remain in the trench 4. Then, chemical vapor deposition is performed on the silicon substrate 2 under reduced pressure. As a result, a filler material 43 is filled into the voids in the trench 4. Because the filler material 43 fills the trench 4 through the n-type semiconductor layer 24, the filler material 43 does not come into contact with the trench 4 (i.e., the silicon substrate 2). Therefore, the filler material 43 may be a conductive material.

[0083] According to the third modification, the trenches 4 are filled with the filler material 43, thereby improving the electric field blocking effect of the trenches 4. As a result, it is possible to further prevent the porous portions 6 from being formed in the non-capacitance generating regions 32. Furthermore, even if the trenches 4 are formed deep, the chemical vapor deposition method makes it easy to fill the trenches 4 with the filler material 43.

[0084] (2.2) Second embodiment Next, a method for manufacturing the capacitor 1 according to the second embodiment will be described with reference to the drawings. In the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals as in the first embodiment, and detailed description thereof may be omitted.

[0085] The method for manufacturing the capacitor 1 according to this embodiment includes an n-type semiconductor portion forming step, a masking layer forming step, a porous portion forming step, a dielectric layer forming step, and a conductor layer forming step. The method for manufacturing the capacitor 1 may further include a terminal forming step.

[0086] The manufacturing method of the capacitor 1 according to this embodiment is different from the manufacturing method of the capacitor 1 according to the first embodiment in that it includes an n-type semiconductor portion forming step instead of a groove portion forming step. The masking layer forming step, the porous portion forming step, the dielectric layer forming step, the conductor layer forming step, and the terminal forming step are the same as those in the first embodiment, so the description thereof will be omitted.

[0087] <n-type semiconductor portion forming step> In the n-type semiconductor portion forming step, a silicon substrate 2 which is a p-type semiconductor is prepared. Next, an n-type semiconductor portion 25 is formed at the boundary between the capacitance generating region 31 and the non-capacitance generating region 32 of the silicon substrate 2 (see FIG. 9B). In this embodiment, the n-type semiconductor portion 25 surrounds the capacitance generating region 31 in a plan view in the XY plane.

[0088] The n-type semiconductor portion 25 is formed so as to extend from the first surface 21 to the second surface 22 of the silicon substrate 2. That is, the n-type semiconductor portion 25 is formed so as to extend in the negative Z-axis direction.

[0089] A part of the surface of the n-type semiconductor portion 25 is flush with the first surface 21 of the silicon substrate 2. The remaining surface of the n-type semiconductor portion 25 is in contact with the silicon substrate 2. The remaining surface of the n-type semiconductor portion 25 includes a surface facing the capacitance generating region 31 side, a surface facing the non-capacitance generating region 32 side, and a surface facing the second surface 22. A pn junction is formed at the contact surface between the silicon substrate 2 and the n-type semiconductor portion 25. That is, a pn junction is formed at the contact surface between the silicon substrate 2 and the remaining surface of the n-type semiconductor portion 25 described above.

[0090] The n-type semiconductor portion 25 can be formed, for example, by ion implantation. That is, the n-type semiconductor portion 25 can be formed by implanting high-energy phosphorus ions at the boundary between the capacitance generating region 31 and the non-capacitance generating region 32 of the silicon substrate 2.

[0091] <Operational effects> In this embodiment, prior to the porous portion forming step (specifically, anodization), an n-type semiconductor portion 25 is formed at the boundary between the capacitance generating region 31 and the non-capacitance generating region 32, as shown in FIG. 9B. The n-type semiconductor portion 25 extends from the first surface 21 toward the second surface 22 of the silicon substrate 2. Furthermore, the n-type semiconductor portion 25 forms a pn junction with the silicon substrate 2, except for a surface flush with the first surface 21. The presence of such an n-type semiconductor portion 25 can block the electric field from the non-capacitance generating region 32 of the second surface 22 toward the capacitance generating region 31 of the first surface 21 during anodization. As a result, the porous portion 6 is formed almost entirely in the capacitance generating region 31, and is prevented from being formed in the non-capacitance generating region 32. Note that the dotted arrow in FIG. 9B indicates the direction of the electric field. The first insulating layer 211 is omitted from FIG. 9B.

[0092] Furthermore, in this embodiment, the second masking portion 52 of the masking layer 5 also has a plurality of through holes 520 (see FIG. 2D ), and therefore the pores 60 tend to grow straight from the first surface 21 toward the second surface 22, starting from the through holes 520. That is, the plurality of pores 60 in the porous portion 6 tend to be formed elongated along the thickness direction of the silicon substrate 2. Therefore, it becomes difficult to form inclined pores 69 as shown in FIG.

[0093] 3. Third embodiment (overview) In this embodiment, as shown in FIG. 18A , a back surface electrode 9 having the same shape as the capacitance generating region 31 is formed at the same position as the capacitance generating region 31. By performing anodization treatment using such a back surface electrode 9 as an anode, it is possible to concentrate the electric field from the second surface 22 to the first surface 21 in the capacitance generating region 31 compared to the non-capacitance generating region 32. As a result, the porous portion 6 is formed almost entirely in the capacitance generating region 31, and it is possible to prevent the porous portion 6 from being formed in the non-capacitance generating region 32. Note that in FIG. 18A , the first surface 21 of the silicon substrate 2 is covered with a masking layer 5. In the capacitance generating region 31, a plurality of through holes 520 are formed in the masking layer 5.

[0094] 4. Third embodiment (details) (1) Capacitor The capacitor 1 according to this embodiment will be described below with reference to the drawings. Note that the same components as those in the first and second embodiments will be given the same reference numerals as in the first and second embodiments, and detailed description thereof may be omitted.

[0095] 10 shows a capacitor 1 according to this embodiment. The capacitor 1 includes a silicon substrate 2, a dielectric layer 7, and a conductive layer 8. The silicon substrate 2 of this embodiment differs from the silicon substrate 2 of the first embodiment shown in FIG. 1 in that it does not include a groove portion 4. The capacitor 1 may further include an insulating layer 210 and a terminal 800.

[0096] (2) Capacitor manufacturing method (2.1) Third embodiment Next, a method for manufacturing the capacitor 1 according to the third embodiment will be described with reference to the drawings. The method for manufacturing the capacitor 1 includes a masking layer forming step, a porous portion forming step, a dielectric layer forming step, and a conductor layer forming step. The method for manufacturing the capacitor 1 may further include a terminal forming step.

[0097] <Masking layer formation process> In the masking layer formation step, first, as shown in FIG. 11A, a silicon substrate 2 is prepared. Next, as shown in FIG. 11B, a first insulating layer 211 is formed on a first surface 21 of the silicon substrate 2, and a third insulating layer 213 is formed on a second surface 22 of the silicon substrate 2. The first insulating layer 211 and the third insulating layer 213 can be formed by, for example, thermal oxidation treatment. The thermal oxidation treatment can be performed by heating the silicon substrate 2 at a temperature of 1000°C or higher and 1200°C or lower in an oxygen atmosphere. As a result, the first insulating layer 211 and the third insulating layer 213 become layers containing silicon oxide.

[0098] Next, a masking layer 5 is formed on the first surface 21 of the silicon substrate 2. In this embodiment, as shown in FIG. 11B, the masking layer 5 is formed on the first surface 21 of the silicon substrate 2 via the first insulating layer 211. That is, the masking layer 5 is formed on the surface of the first insulating layer 211 (the surface facing the positive direction of the Z axis). The masking layer 5 can be formed by, for example, a chemical vapor deposition (CVD) method. Examples of chemical vapor deposition methods include, but are not limited to, thermal CVD and plasma CVD. Examples of materials for the masking layer 5 include, but are not limited to, silicon nitride. In this embodiment, the masking layer 5 is a layer containing silicon nitride.

[0099] 11C, partial etching is performed on the masking layer 5. The partial etching is performed on the masking layer 5 present in the capacitance generating region 31, but not on the masking layer 5 present in the non-capacitance generating region 32. The partial etching is not particularly limited, but examples thereof include dry etching. Among dry etching methods, plasma etching is preferred.

[0100] The portion of the masking layer 5 that has not been partially etched becomes a first masking portion 51. The portion of the masking layer 5 that has been partially etched becomes a second masking portion 52. In this way, the masking layer 5 has a first masking portion 51 and a second masking portion 52 (see FIG. 11C).

[0101] The first masking portion 51, together with the first insulating layer 211, covers the non-capacitance generating region 32 of the first surface 21 of the silicon substrate 2. The first masking portion 51 will eventually become the second insulating layer 212.

[0102] The second masking portion 52 does not cover at least a portion of the capacitance generating region 31. In this embodiment, the second masking portion 52 has a plurality of through holes 520. The plurality of through holes 520 penetrate the masking layer 5 and the first insulating layer 211 in the thickness direction (Z-axis direction). In this manner, the portion of the capacitance generating region 31 on the first surface 21 of the silicon substrate 2 where the through holes 520 exist is not covered and is exposed to the outside.

[0103] The plurality of through holes 520 are arranged in a lattice pattern in the XY plane (see FIG. 11C). That is, the plurality of through holes 520 are arranged at a constant pitch in each of the X-axis direction and the Y-axis direction. The second masking portion 52 is finally removed.

[0104] <Porous part formation process> 11C , in the porous portion forming step, first, a back surface electrode 9 is formed on the second surface 22 of the silicon substrate 2. The shape of the back surface electrode 9 is the same as the shape of the capacitance generating region 31 when viewed along the direction connecting the first surface 21 and the second surface 22 of the silicon substrate 2 (the Z-axis direction). In this embodiment, since the capacitance generating region 31 has a rectangular shape in the XY plane view, the back surface electrode 9 also has a rectangular shape. In the XY plane view, the size of the back surface electrode 9 and the size of the capacitance generating region 31 are equal.

[0105] Furthermore, the back surface electrode 9 is formed at the same position as the capacitance generating region 31 on the second surface 22 of the silicon substrate 2. That is, in the XY plane view, the outline of the back surface electrode 9 and the outline of the capacitance generating region 31 coincide with each other. In this embodiment, the second surface 22 of the silicon substrate 2 is exposed to the outside except for the portion where the back surface electrode 9 is formed.

[0106] The rear surface electrode 9 can be formed by, for example, physical vapor deposition (PVD). The rear surface electrode 9 is electrically connected to the silicon substrate 2. The rear surface electrode 9 is in ohmic contact with the silicon substrate 2.

[0107] Next, an anodization process is performed on the silicon substrate 2. The anodization process can be performed by immersing the silicon substrate 2 and a platinum electrode (not shown) in an electrolyte and applying a current to the back electrode 9 of the silicon substrate 2 as the anode and the platinum electrode as the cathode. As a result, a porous portion 6 is formed in the capacitance generating region 31 of the silicon substrate 2.

[0108] The electrolytic solution is not particularly limited, but examples thereof include hydrofluoric acid. The hydrofluoric acid may further contain ethanol. This effectively removes hydrogen generated during anodization, resulting in the formation of a porous portion 6 with a more uniform structure.

[0109] In this embodiment, the second masking portion 52 has a plurality of through holes 520, so that the pores 60 tend to grow straight in the negative Z-axis direction starting from the through holes 520. The depth and inner diameter of the pores 60 can be adjusted by the conditions of the anodizing treatment. The conditions of the anodizing treatment are not particularly limited, but examples thereof include the resistivity (electrical resistivity) of the silicon substrate 2, the composition of the electrolyte, and the current density.

[0110] 12A , after the anodization treatment, the first insulating layer 211 and the second masking portion 52 in the capacitance generating region 31 are removed from the first surface 21 of the silicon substrate 2. This exposes the capacitance generating region 31 on the first surface 21 of the silicon substrate 2. That is, the openings of the multiple pores 60 are exposed. Furthermore, the back surface electrode 9 is removed from the second surface 22 of the silicon substrate 2.

[0111] <Dielectric layer forming process> 12B, in the dielectric layer forming step, the dielectric layer 7 is formed on the inner surface of the pore 60. Furthermore, in this embodiment, the dielectric layer 7 is formed in the capacitance generating region 31 of the first surface 21 of the silicon substrate 2.

[0112] The dielectric layer 7 can be formed by, for example, thermal oxidation. The thermal oxidation can be performed by heating the silicon substrate 2, on which the porous portion 6 is formed, at a temperature of 800°C or higher and 1200°C or lower in an oxygen atmosphere. As a result, the dielectric layer 7 becomes a layer containing silicon oxide. The dielectric layer 7 may also be formed by chemical vapor deposition.

[0113] <Conductor layer formation process> 12C, in the conductor layer forming step, a conductor layer 8 is formed to cover the first surface 21 of the silicon substrate 2. Specifically, in the capacitance generating region 31, the conductor layer 8 is formed on the first surface 21 of the silicon substrate 2 with a dielectric layer 7 interposed therebetween. In addition, in the non-capacitance generating region 32, the conductor layer 8 is formed on the first surface 21 of the silicon substrate 2 with an insulating layer 210 interposed therebetween.

[0114] The conductive layer 8 can be formed by, for example, chemical vapor deposition. The material of the conductive layer 8 is not particularly limited, but examples thereof include polysilicon, platinum, and ruthenium.

[0115] When chemical vapor deposition is performed, the material of the conductor layer 8 enters the pores 60 of the porous portion 6 and is deposited on the dielectric layer 7 formed on the inner surface of the pores 60, thereby forming the first conductive portion 81. In this way, the first conductive portion 81 comes into contact with the dielectric layer 7. Furthermore, in the capacitance generating region 31, the material of the conductor layer 8 is deposited on the surface of the dielectric layer 7 (the surface facing the positive direction of the Z axis), thereby forming the second conductive portion 82. In this way, the second conductive portion 82 is present in the capacitance generating region 31 on the first surface 21 of the silicon substrate 2. The second conductive portion 82 is electrically connected to the first conductive portion 81.

[0116] Next, a portion of the conductive layer 8 present in the non-capacitance generating region 32 on the first surface 21 of the silicon substrate 2 is removed. The conductive layer 8 can be removed using, for example, a semiconductor laser. As shown in FIG. 13A , the conductive layer 8 remaining in the non-capacitance generating region 32 becomes the third conductive portion 83. The third conductive portion 83 is connected to and electrically connected to the second conductive portion 82.

[0117] <Terminal formation process> 13B, in the terminal formation step, first, a hole 840 is formed in the non-capacitance generating region 32 of the silicon substrate 2, penetrating the insulating layer 210. The bottom surface of the hole 840 is the first surface 21 of the silicon substrate 2. The hole 840 can be formed by, for example, partial etching.

[0118] 13C , a metal layer 830 is formed to cover the first surface 21 of the silicon substrate 2. Specifically, in the capacitance generating region 31, the metal layer 830 is formed on the first surface 21 of the silicon substrate 2 via the second conductive portion 82 and the dielectric layer 7. In addition, in part of the non-capacitance generating region 32, the metal layer 830 is formed on the inner surface of the hole 840. As a result, the metal layer 830 comes into contact with the first surface 21 of the silicon substrate 2. Furthermore, in the remaining part of the non-capacitance generating region 32, the metal layer 830 is formed on the first surface 21 of the silicon substrate 2 via the insulating layer 210. The metal layer 830 can be formed by, for example, chemical vapor deposition.

[0119] Thereafter, the metal layer 830 is removed, leaving only the portion in contact with the silicon substrate 2 through the hole 840 and the portion in contact with the third conductive portion 83. The metal layer 830 can be removed using, for example, a semiconductor laser. The portion in contact with the silicon substrate 2 through the hole 840 becomes the first terminal 810. The portion in contact with the third conductive portion 83 becomes the second terminal 820.

[0120] Through the above steps, the capacitor 1 shown in FIG. 10 is manufactured.

[0121] <Action and effect> In this embodiment, prior to the porous portion forming step (specifically, anodization), a back surface electrode 9 having the same shape as the capacitance generating region 31 is formed at the same position as the capacitance generating region 31, as shown in FIG. 18A. By performing anodization using such a back surface electrode 9 as an anode, the electric field directed from the second surface 22 to the first surface 21 can be concentrated in the capacitance generating region 31 compared to the non-capacitance generating region 32. As a result, the porous portion 6 is formed almost entirely in the capacitance generating region 31, and is prevented from being formed in the non-capacitance generating region 32. The dotted arrow in FIG. 18A indicates the direction of the electric field. The first insulating layer 211 is omitted from FIG. 18A.

[0122] Furthermore, in this embodiment, the second masking portion 52 of the masking layer 5 has a plurality of through holes 520 (see FIG. 11C ), and therefore the pores 60 tend to grow straight from the first surface 21 toward the second surface 22, starting from the through holes 520. That is, the plurality of pores 60 in the porous portion 6 tend to be formed elongated along the thickness direction of the silicon substrate 2. This makes it difficult to form inclined pores 69 as shown in FIG. 19 .

[0123] <Modification> Modifications of the method for manufacturing the capacitor 1 according to the third embodiment will be described below with reference to the drawings. In the following modifications, the same components as those in the third embodiment will be denoted by the same reference numerals as those in the third embodiment, and detailed descriptions thereof may be omitted.

[0124] <First Modification> In the first modification, the method for manufacturing the capacitor 1 further includes an insulating layer forming step, which is a step that precedes the anodizing treatment in the porous portion forming step.

[0125] 14A, in the insulating layer forming step, an insulating layer 90 is formed on the second surface 22 of the silicon substrate 2 except for the surface on the back surface electrode 9. The insulating layer 90 is a layer having electrical insulation properties.

[0126] As described above, the second surface 22 of the silicon substrate 2 is covered with the back surface electrode 9 and the insulating layer 90. Specifically, the capacitance generating region 31 of the second surface 22 of the silicon substrate 2 is covered with the back surface electrode 9. Furthermore, the non-capacitance generating region 32 of the second surface of the silicon substrate 2 is covered with the insulating layer 90. The insulating layer 90 can be formed by, for example, thermal oxidation or chemical vapor deposition.

[0127] According to the first modification, when performing the anodization treatment, the insulating layer 90 can prevent the power supply jig, which should be in contact with the back surface electrode 9, from directly contacting the second surface 22 of the silicon substrate 2. Furthermore, when performing the anodization treatment, an electric field is less likely to be generated in the non-capacitance generating region 32.

[0128] <<Second Modification>> In the second modified example, the method for manufacturing the capacitor 1 further includes a groove forming step. In the groove forming step, the groove 4 is formed around the back surface electrode 9 as shown in FIG. 14B. That is, the groove 4 is formed so as to surround the back surface electrode 9 in the XY plane view. In this embodiment, the groove 4 is formed in a rectangular shape in the XY plane view. The groove 4 is formed so as to be recessed from the second surface 22 toward the first surface 21 of the silicon substrate 2. That is, the groove 4 is formed so as to be recessed in the positive direction of the Z axis.

[0129] The method for forming the grooves 4 is not particularly limited, but examples thereof include dry etching and wet etching.

[0130] Dry etching can be exemplified by reactive ion etching (RIE). Among reactive ion etching methods, deep RIE is preferred because it allows etching with a high aspect ratio (narrow and deep). Among deep RIE methods, the Bosch process is particularly preferred because it allows etching with a high aspect ratio.

[0131] The Bosch process is a process that repeats two processes: an etching step and a protection step. The etching step mainly uses sulfur hexafluoride (SF6) for isotropic etching. The protection step uses Teflon (registered trademark)-based gas (C4F8) to protect the sidewalls and suppress lateral etching.

[0132] Examples of wet etching include anisotropic etching, etc. Examples of anisotropic etching solutions include, but are not limited to, a KOH aqueous solution and a TMAH (tetramethylammonium hydroxide) aqueous solution.

[0133] According to the second modification, the presence of the grooves 4 around the back surface electrode 9 allows the grooves 4 to block the electric field directed from the capacitance generating region 31 of the second surface 22 to the non-capacitance generating region 32 of the first surface 21. In other words, the grooves 4 can prevent the electric field from spreading from the capacitance generating region 31 to the non-capacitance generating region 32. This allows the electric field directed from the second surface 22 to the first surface 21 to be more concentrated in the capacitance generating region 31. As a result, the formation of the porous portion 6 in the non-capacitance generating region 32 can be further prevented.

[0134] <Third Modification> In the third modification, the method for manufacturing capacitor 1 further includes a filling step. In the filling step, insulating material 41 is filled into groove 4 as shown in Fig. 14C. The insulating material 41 is not particularly limited, but examples thereof include silicon oxide.

[0135] The method for filling the insulating material 41 into the groove 4 is not particularly limited, but examples thereof include a method using thermal oxidation treatment, a chemical vapor deposition method, etc. These methods will be described below.

[0136] 16A to 16C show how insulating material 41 is filled into trench 4 using thermal oxidation. That is, as shown in FIG. 16A, a silicon substrate 2 is prepared. Next, as shown in FIG. 16B, trench 4 is formed in silicon substrate 2 by dry etching (e.g., reactive ion etching, etc.). Next, as shown in FIG. 16C, thermal oxidation is performed by heating silicon substrate 2 at a temperature of 1000°C or higher and 1200°C or lower in an oxygen atmosphere. As a result, silicon oxide, which is insulating material 41, is filled into trench 4. The method of using thermal oxidation is particularly effective when trench 4 has a shallow depth D1 and a narrow width W1.

[0137] 17A to 17C show how insulating material 41 is filled into trench 4 by chemical vapor deposition. That is, as shown in FIG. 17A, a silicon substrate 2 is prepared. Next, as shown in FIG. 17B, trench 4 is formed in silicon substrate 2 by dry etching (e.g., reactive ion etching, etc.). Next, as shown in FIG. 17C, chemical vapor deposition is performed on silicon substrate 2 under reduced pressure. As a result, insulating material 41 is filled into trench 4. Chemical vapor deposition is particularly effective when trench 4 has a deep depth D2 and a wide width W2.

[0138] According to the third modification, the insulating material 41 is filled inside the grooves 4, thereby improving the effect of blocking the electric field by the grooves 4. As a result, the formation of the porous portion 6 in the non-capacity generating region 32 can be further suppressed.

[0139] <Fourth Variation> In the fourth modification, similar to the third modification, the method for manufacturing the capacitor 1 further includes a filling step. In the filling step, as shown in FIG. 15E, an insulating layer 42 is formed on the inner surface of the groove 4, and a filling material 43 is filled into the groove 4 with the insulating layer 42 formed therein. The material for the insulating layer 42 is not particularly limited, but examples thereof include silicon oxide. The filling material 43 may be either a conductive material or an electrically insulating material. Thus, examples of the filling material 43 are not particularly limited, but examples thereof include polysilicon. In the fourth modification, for example, a method using thermal oxidation treatment and a chemical vapor deposition method are used in combination.

[0140] 15A to 15E show the filling process of the fourth modified example. First, a silicon substrate 2 is prepared as shown in FIG. 15A. Next, as shown in FIG. 15B, a trench 4 is formed in the silicon substrate 2 by dry etching (e.g., reactive ion etching, etc.). Next, as shown in FIG. 15C, a thermal oxidation process is performed by heating the silicon substrate 2 at a temperature of 1000°C to 1200°C in an oxygen atmosphere. This forms silicon oxide as an insulating layer 42 on the inner surface of the trench 4. Voids remain in the trench 4. Next, as shown in FIG. 15D, chemical vapor deposition is performed on the silicon substrate 2 under reduced pressure. This fills the voids in the trench 4 with a filling material 43. Because the filling material 43 fills the interior of the trench 4 through the insulating layer 42, the filling material 43 does not come into contact with the trench 4. Therefore, the filling material 43 may be a conductive material. Thereafter, as shown in FIG. 15E, the filling material 43 that does not fill the trench 4 is removed.

[0141] According to the fourth modification, the electric field blocking effect of the grooves 4 can be improved by filling the grooves 4 with the filler material 43. As a result, it is possible to further prevent the porous portions 6 from being formed in the non-capacitance generating regions 32. Furthermore, even if the grooves 4 are formed deep, the grooves 4 can be easily filled with the filler material 43 by using the chemical vapor deposition method.

[0142] <<Fifth Variation>> In the fifth modification, the silicon substrate 2 further has a third surface 23. The third surface 23 is located on the opposite side to the first surface 21. That is, the third surface 23 is a surface facing in the negative direction of the Z axis.

[0143] In the XY plane view, the third surface 23 exists around the second surface 22. That is, in the XY plane view, the third surface 23 surrounds the second surface 22 on which the back surface electrode 9 is formed.

[0144] 14D, the distance L13 between the third surface 23 and the first surface 21 is shorter than the distance L12 between the second surface 22 on which the back surface electrode 9 is formed and the first surface 21. In other words, a step exists between the third surface 23 and the second surface 22 on which the back surface electrode 9 is formed.

[0145] According to the fifth modification, the presence of a step around the back surface electrode 9 can prevent the electric field from spreading from the capacitance generating region 31 to the non-capacitance generating region 32. Therefore, the electric field directed from the second surface 22 to the first surface 21 can be further concentrated in the capacitance generating region 31. As a result, the formation of the porous portion 6 in the non-capacitance generating region 32 can be further prevented. Furthermore, the presence of the step makes it difficult for the power supply jig that should be in contact with the back surface electrode 9 to directly contact the third surface 23 of the silicon substrate 2 during anodization.

[0146] (2.2) Fourth embodiment Next, a method for manufacturing the capacitor 1 according to the fourth embodiment will be described with reference to the drawings. In the fourth embodiment, the same components as those in the third embodiment are denoted by the same reference numerals as in the third embodiment, and detailed description thereof may be omitted.

[0147] The method for manufacturing the capacitor 1 according to this embodiment includes a masking layer forming step, a low-resistance portion forming step, a porous portion forming step, a dielectric layer forming step, and a conductor layer forming step. The method for manufacturing the capacitor 1 may further include a terminal forming step.

[0148] The method for manufacturing the capacitor 1 according to this embodiment differs from the method for manufacturing the capacitor 1 according to the third embodiment in that it includes a low-resistance portion forming step. The masking layer forming step, dielectric layer forming step, conductor layer forming step, and terminal forming step are the same as those in the third embodiment, and therefore descriptions thereof will be omitted.

[0149] <Low resistance part formation process> The low resistance portion forming step is a step that precedes the porous portion forming step (specifically, anodization treatment). In the low resistance portion forming step, a low resistance portion 26 is formed inside the silicon substrate 2, as shown in FIG.

[0150] The low resistance portion 26 is a portion having a lower specific resistance (electrical resistivity) than the silicon substrate 2. The low resistance portion 26 can be formed by, for example, ion implantation. The ions to be implanted are not particularly limited, but examples thereof include boron ions. Note that lattice defects caused by the ion implantation are removed by heat treatment.

[0151] The shape of the low resistance portion 26 is the same as that of the capacitance generating region 31 when viewed along the direction (Z-axis direction) connecting the first surface 21 and the second surface 22 of the silicon substrate 2. In this embodiment, since the capacitance generating region 31 has a rectangular shape when viewed in the XY plane, the low resistance portion 26 also has a rectangular shape. When viewed in the XY plane, the size of the back surface electrode 9 and the size of the capacitance generating region 31 are equal.

[0152] The low resistance portion 26 is formed to extend from the second surface 22 toward the first surface 21 of the silicon substrate 2. That is, the low resistance portion 26 is formed to extend in the positive direction of the Z axis. The thickness (length in the Z axis direction) of the low resistance portion 26 is thinner than the thickness of the silicon substrate 2.

[0153] The low resistance portion 26 is formed at the same position as the capacitance generating region 31 inside the silicon substrate 2. That is, the outline of the low resistance portion 26 and the outline of the capacitance generating region 31 coincide with each other in the XY plane view.

[0154] <Porous part formation process> The porous portion forming step of this embodiment is substantially the same as the porous portion forming step of the third embodiment. Like the back surface electrode 9 of the third embodiment, the back surface electrode 9 of this embodiment is preferably formed in the same shape and at the same position as the capacitance generating region 31. However, the back surface electrode 9 of this embodiment may be formed over the entire second surface 22 of the silicon substrate 2 (see FIG. 18B).

[0155] <Action and effect> In this embodiment, prior to the porous portion forming step (specifically, anodization), a low-resistance portion 26 having the same shape as the capacitance-producing region 31 is formed at the same position as the capacitance-producing region 31, as shown in FIG. 18B . The presence of such a low-resistance portion 26 creates a resistance difference in the silicon substrate 2 itself. That is, the electrical resistance between the first surface 21 and the second surface 22 in the capacitance-producing region 31 can be made lower than the electrical resistance between the first surface 21 and the second surface 22 in the non-capacitance-producing region 32. Therefore, the electric field from the second surface 22 to the first surface 21 can be concentrated in the capacitance-producing region 31 compared to the non-capacitance-producing region 32. As a result, the porous portion 6 is formed almost entirely in the capacitance-producing region 31, preventing it from being formed in the non-capacitance-producing region 32. Note that the dotted arrow in FIG. 18B indicates the direction of the electric field. The first insulating layer 211 is omitted from FIG. 18B .

[0156] In this embodiment, the back electrode 9 is formed over the entire second surface 22 of the silicon substrate 2, but like the low resistance portion 26, if the back electrode 9 is formed in the same shape and at the same position as the capacitance generating region 31, the electric field from the second surface 22 to the first surface 21 can be more concentrated.

[0157] Furthermore, in this embodiment, the second masking portion 52 of the masking layer 5 also has a plurality of through holes 520 (see FIG. 11C ), and therefore the pores 60 tend to grow straight from the first surface 21 toward the second surface 22, starting from the through holes 520. That is, the plurality of pores 60 in the porous portion 6 tend to be formed elongated along the thickness direction of the silicon substrate 2. Therefore, it becomes difficult to form the inclined pores 69 as shown in FIG. 19 .

[0158] 5. Variations In the first and second embodiments, the porous portion 6 is formed of a plurality of regularly arranged pores 60, but the arrangement of the plurality of pores 60 may be irregular. Each of the plurality of pores 60 may have a different shape and size.

[0159] In the first and second embodiments, the second masking portion 52 does not cover a part of the capacitance generating region 31, but it does not have to cover the entire capacitance generating region 31 (see, for example, FIG. 3A of Patent Document 1). In other words, the entire second masking portion 52 does not have to be present before the anodization process is performed.

[0160] In the third and fourth embodiments, the porous portion 6 is formed of a plurality of regularly arranged pores 60, but the arrangement of the plurality of pores 60 may be irregular. Each of the plurality of pores 60 may have a different shape and size.

[0161] In the third and fourth embodiments, the second masking portion 52 does not cover a part of the capacitance generating region 31, but it does not have to cover the entire capacitance generating region 31 (see, for example, FIG. 3A of Patent Document 1). In other words, the entire second masking portion 52 does not have to be present before the anodization process is performed.

[0162] In the third embodiment, the back electrode 9 and the capacitance generating region 31 have the same shape and size in the XY plane view, but the shape and size of the two do not need to be strictly the same as long as the effect of the third embodiment is not significantly impaired.

[0163] In the third embodiment, the rear surface electrode 9 and the capacitance generating region 31 are located at the same position in the XY plane, but the positions of the two may be shifted as long as the effect of the third embodiment is not significantly impaired.

[0164] In the fourth embodiment, the low resistance portion 26 and the capacitance generating region 31 have the same shape and size in the XY plane view, but the shape and size of the two do not have to be strictly the same as long as the effect of the fourth embodiment is not significantly impaired.

[0165] In the fourth embodiment, the low resistance portion 26 and the capacitance generating region 31 are located at the same position in the XY plane, but the positions of the two may be shifted as long as the effect of the fourth embodiment is not significantly impaired.

[0166] 6. Aspects As is clear from the above-described embodiments and modifications, the present disclosure includes the following aspects. In the following, reference numerals are given in parentheses only to clarify the correspondence with the embodiments.

[0167] A first aspect is a method for manufacturing a capacitor (1), including a groove forming step, a masking layer forming step, a porous portion forming step, a dielectric layer forming step, and a conductor layer forming step. In the groove forming step, a silicon substrate (2) is prepared, the silicon substrate (2) having a first surface (21) and a second surface (22) opposite to the first surface (21), and having a capacitance generating region (31) and a non-capacitance generating region (32) other than the capacitance generating region (31) when viewed along a direction connecting the first surface (21) and the second surface (22). A groove (4) recessed from the first surface (21) toward the second surface (22) is formed at the boundary between the capacitance generating region (31) and the non-capacitance generating region (32). In the masking layer forming step, a masking layer (5) having a first masking portion (51) covering the non-capacitance generating region (32) and a second masking portion (52) not covering at least a portion of the capacitance generating region (31) is formed on the first surface (21) of the silicon substrate (2). In the porous portion forming step, a porous portion (6) having pores (60) is formed in the capacitance generating region (31) of the silicon substrate (2) by anodizing. In the dielectric layer forming step, a dielectric layer (7) is formed on the inner surface of the pores (60). In the conductor layer forming step, a conductor layer (8) is formed having a first conductive portion (81) in contact with the dielectric layer (7) and a second conductive portion (82) electrically connected to the first conductive portion (81) and present in the capacitance generating region (31) of the first surface (21).

[0168] According to this embodiment, it is possible to prevent the porous portion (6) from being formed in the non-capacity generating region (32).

[0169] A second aspect is a method for manufacturing a capacitor (1) based on the first aspect. The second aspect further includes a filling step, in which an insulating material (41) is filled inside the groove portion (4).

[0170] According to this embodiment, the formation of the porous portion (6) in the non-capacity generating region (32) can be further suppressed.

[0171] A third aspect is a method for manufacturing a capacitor (1) based on the first aspect. The third aspect further includes a filling step, in which an insulating layer (42) is formed on the inner surface of the groove (4), and a filling material (43) is filled into the groove (4) with the insulating layer (42).

[0172] According to this embodiment, it is possible to further prevent the porous portion 6 from being formed in the non-capacity generating region 32. In addition, it is easy to form the groove portion 4 deep.

[0173] A fourth aspect is a method for manufacturing a capacitor (1) based on the first aspect. The fourth aspect further includes a filling step. In the filling step, the silicon substrate (2) is a p-type semiconductor, an n-type semiconductor layer (24) is formed on the inner surface of the groove (4), and a filling material (43) is filled into the groove (4) with the n-type semiconductor layer (24) formed therein.

[0174] According to this embodiment, it is possible to further prevent the porous portion 6 from being formed in the non-capacity generating region 32. In addition, it is easy to form the groove portion 4 deep.

[0175] A fifth aspect is a method for manufacturing a capacitor (1), including an n-type semiconductor portion forming step, a masking layer forming step, a porous portion forming step, a dielectric layer forming step, and a conductor layer forming step. In the n-type semiconductor portion forming step, a silicon substrate (2) is prepared, which is a p-type semiconductor, having a first surface (21) and a second surface (22) opposite to the first surface (21), and which has, when viewed along a direction connecting the first surface (21) and the second surface (22), a capacitance generating region (31) and a non-capacitance generating region (32) other than the capacitance generating region (31). An n-type semiconductor portion (25) extending from the first surface (21) toward the second surface (22) is formed at the boundary between the capacitance generating region (31) and the non-capacitance generating region (32). In the masking layer forming step, a masking layer (5) having a first masking portion (51) covering the non-capacitance generating region (32) and a second masking portion (52) not covering at least a portion of the capacitance generating region (31) is formed on the first surface (21) of the silicon substrate (2). In the porous portion forming step, a porous portion (6) having pores (60) is formed in the capacitance generating region (31) of the silicon substrate (2) by anodizing. In the dielectric layer forming step, a dielectric layer (7) is formed on the inner surface of the pores (60). In the conductor layer forming step, a conductor layer (8) is formed having a first conductive portion (81) in contact with the dielectric layer (7) and a second conductive portion (82) electrically connected to the first conductive portion (81) and present in the capacitance generating region (31) of the first surface (21).

[0176] According to this embodiment, it is possible to prevent the porous portion (6) from being formed in the non-capacity generating region (32).

[0177] A sixth aspect is a method for manufacturing a capacitor (1) based on any one of the first to fifth aspects. In the sixth aspect, the second masking portion (52) has a plurality of through holes (520) penetrating in the thickness direction.

[0178] According to this embodiment, the pores (60) of the porous portion (6) are easily formed to be elongated along the thickness direction of the silicon substrate (2).

[0179] A seventh aspect is a method for manufacturing a capacitor (1), including a masking layer forming step, a porous portion forming step, a dielectric layer forming step, and a conductor layer forming step. In the masking layer forming step, a silicon substrate (2) is prepared, the silicon substrate (2) having a first surface (21) and a second surface (22) opposite to the first surface (21), and having a capacitance generating region (31) and a non-capacitance generating region (32) other than the capacitance generating region (31) when viewed along a direction connecting the first surface (21) and the second surface (22). A masking layer (5) having a first masking portion (51) covering the non-capacitance generating region (32) and a second masking portion (52) not covering at least a portion of the capacitance generating region (31) is formed on the first surface (21) of the silicon substrate (2). In the porous portion forming step, a back surface electrode (9) having the same shape as the capacitance generating region (31) when viewed along a direction connecting the first surface (21) and the second surface (22) is formed on the second surface (22) of the silicon substrate (2) at the same position as the capacitance generating region (31), and anodization is performed using the back surface electrode (9) as an anode to form a porous portion (6) having pores (60) in the capacitance generating region (31) of the silicon substrate (2). In the dielectric layer forming step, a dielectric layer (7) is formed on the inner surface of the pores (60). In the conductor layer forming step, a conductor layer (8) is formed having a first conductive portion (81) in contact with the dielectric layer (7) and a second conductive portion (82) electrically connected to the first conductive portion (81) and present in the capacitance generating region (31) of the first surface (21).

[0180] According to this embodiment, it is possible to prevent the porous portion (6) from being formed in the non-capacity generating region (32).

[0181] An eighth aspect is a method for manufacturing a capacitor (1) based on the seventh aspect. The eighth aspect further includes an insulating layer forming step in which an insulating layer (90) is formed on the second surface (22) of the silicon substrate (2) other than the surface on which the back electrode (9) is formed.

[0182] According to this embodiment, when performing anodization, the insulating layer (90) can prevent the power supply jig, which should be in contact with the back electrode (9), from directly contacting the second surface (22) of the silicon substrate (2).

[0183] A ninth aspect is a method for manufacturing a capacitor (1) based on the seventh or eighth aspect. The ninth aspect further includes a groove forming step, in which a groove (4) recessed from the second surface (22) toward the first surface (21) is formed around the back electrode (9).

[0184] According to this embodiment, the formation of the porous portion (6) in the non-capacity generating region (32) can be further suppressed.

[0185] A tenth aspect is a method for manufacturing a capacitor (1) based on the ninth aspect, further comprising a filling step, in which an insulating material (41) is filled inside the grooves (4).

[0186] According to this embodiment, the formation of the porous portion (6) in the non-capacity generating region (32) can be further suppressed.

[0187] An eleventh aspect is a method for manufacturing a capacitor (1) based on any one of the seventh to tenth aspects. In the eleventh aspect, the silicon substrate (2) further has a third surface (23) located on the opposite side of the first surface (21). A distance (L13) between the third surface (23) and the first surface (21) is shorter than a distance (L12) between the second surface (22) on which the back electrode (9) is formed and the first surface (21).

[0188] According to this embodiment, it is possible to further prevent the porous portion 6 from being formed in the non-capacitance generating region 32. Furthermore, during anodization, the power supply jig that should be in contact with the back surface electrode 9 is less likely to come into direct contact with the third surface 23 of the silicon substrate 2.

[0189] A twelfth aspect is a method for manufacturing a capacitor (1), including a masking layer forming step, a low-resistance portion forming step, a porous portion forming step, a dielectric layer forming step, and a conductor layer forming step. In the masking layer forming step, a silicon substrate (2) is prepared, the silicon substrate (2) having a first surface (21) and a second surface (22) opposite to the first surface (21), and having a capacitance generating region (31) and a non-capacitance generating region (32) other than the capacitance generating region (31) when viewed along a direction connecting the first surface (21) and the second surface (22). A masking layer (5) having a first masking portion (51) covering the non-capacitance generating region (32) and a second masking portion (52) not covering at least a portion of the capacitance generating region (31) is formed on the first surface (21) of the silicon substrate (2). In the low-resistance portion forming step, a low-resistance portion (26) is formed in the silicon substrate (2) at the same position as the capacitance generating region (31), the low-resistance portion (26) having the same shape as the capacitance generating region (31) when viewed along a direction connecting the first surface (21) and the second surface (22), and having a lower resistivity than the silicon substrate (2), and extending from the second surface (22) toward the first surface (21). In the porous portion forming step, a porous portion (6) having pores (60) is formed in the capacitance generating region (31) of the silicon substrate (2) by anodizing. In the dielectric layer forming step, a dielectric layer (7) is formed on the inner surfaces of the pores (60). In the conductor layer forming process, a conductor layer (8) is formed having a first conductive portion (81) that contacts the dielectric layer (7) and a second conductive portion (82) that is electrically connected to the first conductive portion (81) and exists in the capacitance generating region (31) of the first surface (21).

[0190] According to this embodiment, it is possible to prevent the porous portion (6) from being formed in the non-capacity generating region (32).

[0191] A thirteenth aspect is a method for manufacturing a capacitor (1) based on any one of the seventh to twelfth aspects. In the thirteenth aspect, the second masking portion (52) has a plurality of through holes (520) penetrating in the thickness direction.

[0192] According to this embodiment, the pores (60) of the porous portion (6) are easily formed to be elongated along the thickness direction of the silicon substrate (2). [Explanation of symbols]

[0193] 1 capacitor 2. Silicon substrate 21 Page 1 22 Side 2 23 Page 3 24 n-type semiconductor layer 26 Low resistance part 31 Capacity Expression Region 32 Non-capacitating area 4 Groove 41 Insulating materials 42 Insulating layer 43 Filling material 5 Masking Layers 51 First Masking Section 52 Second Masking Section 520 Through hole 6 Porous part 60 pores 7 Dielectric Layer 8 Conductive Layer 81 First conductive part 82 Second conductive part 9 Back electrode 90 Insulating layer L12 distance L13 distance

Claims

1. a groove forming step of preparing a silicon substrate having a first surface and a second surface opposite to the first surface, the silicon substrate having a capacitance generating region and a non-capacitance generating region other than the capacitance generating region when viewed along a direction connecting the first surface and the second surface, and forming a groove recessed from the first surface toward the second surface at a boundary between the capacitance generating region and the non-capacitance generating region; a masking layer forming step of forming, on the first surface of the silicon substrate, a masking layer having a first masking portion that covers the non-capacitance generating region and a second masking portion that does not cover at least a part of the capacitance generating region; a porous portion forming step of forming a porous portion having pores in the capacitance generating region of the silicon substrate by performing an anodic oxidation treatment; a dielectric layer forming step of forming a dielectric layer on the inner surface of the pore; a conductor layer forming step of forming a conductor layer having a first conductive portion in contact with the dielectric layer and a second conductive portion electrically connected to the first conductive portion and present in the capacitance generating region of the first surface, A method for manufacturing a capacitor.

2. The method further includes a filling step of filling the inside of the groove with an insulating material. The method for manufacturing a capacitor according to claim 1 .

3. The method further includes a filling step of forming an insulating layer on the inner surface of the groove portion, and filling a filling material into the groove portion on which the insulating layer is formed. The method for manufacturing a capacitor according to claim 1 .

4. the silicon substrate is a p-type semiconductor, and the method further includes forming an n-type semiconductor layer on the inner surface of the groove, and filling a filling material into the groove in which the n-type semiconductor layer is formed. The method for manufacturing a capacitor according to claim 1 .

5. a silicon substrate that is a p-type semiconductor and has a first surface and a second surface opposite to the first surface, and when viewed along a direction connecting the first surface and the second surface, has a capacitance generating region and a non-capacitance generating region that is a region other than the capacitance generating region; and an n-type semiconductor portion forming step of forming an n-type semiconductor portion that extends from the first surface toward the second surface at a boundary between the capacitance generating region and the non-capacitance generating region; a masking layer forming step of forming, on the first surface of the silicon substrate, a masking layer having a first masking portion that covers the non-capacitance generating region and a second masking portion that does not cover at least a part of the capacitance generating region; a porous portion forming step of forming a porous portion having pores in the capacitance generating region of the silicon substrate by performing an anodic oxidation treatment; a dielectric layer forming step of forming a dielectric layer on the inner surface of the pore; a conductor layer forming step of forming a conductor layer having a first conductive portion in contact with the dielectric layer and a second conductive portion electrically connected to the first conductive portion and present in the capacitance generating region of the first surface, A method for manufacturing a capacitor.

6. The second masking portion has a plurality of through holes penetrating in a thickness direction. The method for manufacturing a capacitor according to any one of claims 1 to 5.

7. a masking layer forming step of preparing a silicon substrate having a first surface and a second surface opposite to the first surface, the silicon substrate having a capacitance generating region and a non-capacitance generating region other than the capacitance generating region when viewed along a direction connecting the first surface and the second surface, and forming, on the first surface of the silicon substrate, a masking layer having a first masking portion that covers the non-capacitance generating region and a second masking portion that does not cover at least a part of the capacitance generating region; a porous portion forming step of forming a back surface electrode having the same shape as the capacitance generating region when viewed along a direction connecting the first surface and the second surface at the same position as the capacitance generating region on the second surface of the silicon substrate, and performing an anodizing process using the back surface electrode as an anode to form a porous portion having pores in the capacitance generating region of the silicon substrate; a dielectric layer forming step of forming a dielectric layer on the inner surface of the pore; a conductor layer forming step of forming a conductor layer having a first conductive portion in contact with the dielectric layer and a second conductive portion electrically connected to the first conductive portion and present in the capacitance generating region of the first surface, A method for manufacturing a capacitor.

8. further comprising an insulating layer forming step of forming an insulating layer on the second surface of the silicon substrate other than the surface of the back surface electrode. The method for manufacturing a capacitor according to claim 7 .

9. a groove forming step of forming a groove recessed from the second surface toward the first surface around the back surface electrode, The method for manufacturing a capacitor according to claim 7 or 8.

10. The method further includes a filling step of filling the inside of the groove with an insulating material. The method for manufacturing a capacitor according to claim 9 .

11. the silicon substrate further has a third surface located on the opposite side of the first surface, and the distance between the third surface and the first surface is shorter than the distance between the second surface on which the back surface electrode is formed and the first surface; The method for manufacturing a capacitor according to any one of claims 7 to 10.

12. a masking layer forming step of preparing a silicon substrate having a first surface and a second surface opposite to the first surface, the silicon substrate having a capacitance generating region and a non-capacitance generating region other than the capacitance generating region when viewed along a direction connecting the first surface and the second surface, and forming, on the first surface of the silicon substrate, a masking layer having a first masking portion that covers the non-capacitance generating region and a second masking portion that does not cover at least a part of the capacitance generating region; a low resistance portion forming step of forming a low resistance portion, the low resistance portion having the same shape as the capacitance generating region when viewed along a direction connecting the first surface and the second surface, the low resistance portion having a lower resistivity than the silicon substrate, and extending from the second surface toward the first surface, at the same position as the capacitance generating region inside the silicon substrate; a porous portion forming step of forming a porous portion having pores in the capacitance generating region of the silicon substrate by performing an anodic oxidation treatment; a dielectric layer forming step of forming a dielectric layer on the inner surface of the pore; a conductor layer forming step of forming a conductor layer having a first conductive portion in contact with the dielectric layer and a second conductive portion electrically connected to the first conductive portion and present in the capacitance generating region of the first surface, A method for manufacturing a capacitor.

13. The second masking portion has a plurality of through holes penetrating in a thickness direction. The method for manufacturing a capacitor according to any one of claims 7 to 12.

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