Semiconductor Devices

Abstract

This semiconductor device includes a first electrode plate (10), a first semiconductor chip (20) arranged on the first electrode plate, a first plate-shaped electrode (30) arranged on the first semiconductor chip, a first tubular electrode (40) arranged on the first plate-shaped electrode, a first coil spring, a first stepped electrode (50) having a first lower step portion (51) arranged on the first tubular electrode and a first upper step portion (52) located on the first lower step portion, a first insulating frame (60) having a first side wall (61) and a first upper wall (62) contiguous with the upper end of the first side wall, and a second electrode plate (80) electrically connected to the first upper step portion. A first through hole (41) penetrating the first tubular electrode along the thickness direction of the first electrode plate is formed in the first tubular electrode. A first coil spring (42) is arranged in the first through hole and is compressed by the first plate-shaped electrode and the first lower step portion to generate a repulsive force that presses the first plate-shaped electrode against the first semiconductor chip.

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Japanese Patent Laid-Open Publication No. 2002-57263 (Patent Document 1) describes a pressure-welded type semiconductor device. The semiconductor device described in Patent Document 1 includes a semiconductor pellet, a frame metal plate, first and second frame support parts, first and second insulating plates, first and second main terminal plates, a frame flexible plate, an alignment mechanism, and a bolt.

[0003] The frame metal plate is rectangular in plan view. The first insulating plate is disposed on the frame metal plate. The first main terminal plate has a first base and a first external lead-out portion. The first base is disposed on the first insulating plate. A first external terminal is connected to the first external lead-out portion. The semiconductor pellet is disposed on the first base. This allows the semiconductor pellet to be electrically connected to the first external terminal. The second main terminal plate has a second base and a second external lead-out portion. The second base is disposed on the semiconductor pellet. The second external lead-out portion is connected to the second external terminal. This allows the semiconductor pellet to be electrically connected to the second external terminal. The second insulating plate is disposed on the second base.

[0004] The aligning mechanism is disposed on the second insulating plate. The frame metal plate has a first side surface and a second side surface. The second side surface is the surface opposite to the first side surface. The first frame support portion and the second frame support portion extend upward in the thickness direction of the frame metal plate from the first side surface and the second side surface, respectively. The first frame support portion and the second frame support portion are disposed opposite each other with the aligning mechanism sandwiched between them. The frame flexible plate is connected at one end to the upper end of the first frame support portion and at the other end to the upper end of the second frame support portion. A screw hole is formed in the frame flexible plate, penetrating the frame flexible plate in the thickness direction.

[0005] The bolt is threaded into the screw hole. By rotating the bolt, the tip of the bolt protrudes from the frame flexible plate and contacts the alignment mechanism. As a result, the alignment mechanism sandwiches the first insulating plate, the first base, the semiconductor pellet, the second base, and the second insulating plate between the frame metal plate. In this way, in the pressure-contact type semiconductor device described in Patent Document 1, pressure contact is achieved between the semiconductor pellet and the first main terminal plate and the second main terminal plate. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2002-57263 Summary of the Invention [Problem to be solved by the invention]

[0007] As described above, in the pressure-welded type semiconductor device described in Patent Document 1, an external pressure-welding mechanism consisting of a frame metal plate, an alignment mechanism, a first frame support part, a second frame support part, a frame flexible plate, and a bolt is required to press the semiconductor pellet and the first and second main terminal plates together.

[0008] The present disclosure has been made in view of the above-described problems of the conventional technology, and more specifically, the present disclosure provides a semiconductor device capable of maintaining a pressure on a semiconductor chip without using an external pressure welding mechanism. [Means for solving the problem]

[0009] The semiconductor device of the present disclosure includes a first electrode plate, a first semiconductor chip disposed on the first electrode plate, a first plate electrode disposed on the first semiconductor chip, a first cylindrical electrode disposed on the first plate electrode, a first coil spring, a first stepped electrode having a first lower step portion disposed on the first cylindrical electrode and a first upper step portion above the first lower step portion, a first insulating frame having a first side wall and a first upper wall connected to an upper end of the first side wall, and a second electrode plate electrically connected to the first upper step portion. The first cylindrical electrode has a first through hole formed therethrough along the thickness direction of the first electrode plate. The first coil spring is disposed within the first through hole and is compressed by the first plate electrode and the first lower step portion to generate a repulsive force that presses the first plate electrode against the first semiconductor chip. The first upper wall has a first through-hole formed therein, the first through-hole penetrating the first upper wall in the thickness direction of the first electrode plate and through which the first upper step portion passes so that the first upper step portion protrudes from the first upper wall. The lower end side of the first side wall is fixed to the first electrode plate with the first semiconductor chip, the first plate-like electrode, the first cylindrical electrode, and the first lower step portion sandwiched between the first upper wall and the first electrode plate. [Effects of the Invention]

[0010] According to the semiconductor device of the present disclosure, it is possible to maintain the pressure on the semiconductor chip without using an external pressure welding mechanism. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 2 is an exploded front view of the semiconductor device 100. [Figure 2] FIG. 1 is an exploded perspective view of a semiconductor device 100. [Figure 3] FIG. 1 is a cross-sectional view of a semiconductor device 100. [Figure 4] FIG. 10 is a cross-sectional view of a semiconductor device 100 according to a modified example. [Figure 5] FIG. 2 is a cross-sectional view of the semiconductor device 100A. [Figure 6] FIG. 2 is a plan view of the semiconductor device 100B. [Figure 7] FIG. 2 is a cross-sectional view of the semiconductor device 100B. [Figure 8] FIG. 10 is a cross-sectional view of a semiconductor device 100B according to a modified example. [Figure 9] FIG. 2 is a cross-sectional view of the semiconductor device 100C. [Figure 10] FIG. 10 is a cross-sectional view of a semiconductor device 100D. [Figure 11] FIG. 10 is a cross-sectional view of a semiconductor device 100E. [Figure 12] FIG. 1 is a plan view of a semiconductor device 100E. DETAILED DESCRIPTION OF THE INVENTION

[0012] The details of the embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and redundant explanations will not be repeated. The following embodiments may be applied in appropriate combinations.

[0013] Embodiment 1 A semiconductor device according to the first embodiment will be described. The semiconductor device according to the first embodiment is designated as a semiconductor device 100.

[0014] (Configuration of semiconductor device 100) The configuration of the semiconductor device 100 will be described below.

[0015] FIG. 1 is an exploded front view of a semiconductor device 100. FIG. 2 is an exploded perspective view of the semiconductor device 100. FIG. 3 is a cross-sectional view of the semiconductor device 100. As shown in FIGS. 1, 2, and 3, the semiconductor device 100 includes a first electrode plate 10, a plurality of semiconductor chips 20, a plurality of plate electrodes 30, a plurality of tubular electrodes 40, a plurality of stepped electrodes 50, a plurality of insulating frames 60, a module case 70, and a second electrode plate 80. The semiconductor device 100 is a pressure-welded semiconductor device. The number of the plate electrodes 30, the number of the tubular electrodes 40, the number of the stepped electrodes 50, and the number of the insulating frames 60 is equal to the number of the semiconductor chips 20.

[0016] The first electrode plate 10 is a plate-shaped member. The first electrode plate 10 is made of a conductive material. The first electrode plate 10 is made of, for example, a metal material. The first electrode plate 10 has a first surface 10a and a second surface 10b. The first surface 10a and the second surface 10b are end surfaces of the first electrode plate 10 in the thickness direction. The first surface 10a is formed with a plurality of pairs of screw holes 10c and screw holes 10d. The screw holes 10c and screw holes 10d are formed, for example, by tapping. Although not shown, an external electrode (first external electrode) such as a bus bar is connected to the first electrode plate 10. The first electrode plate 10 and the first external electrode are connected using a fastening member such as a screw.

[0017] The semiconductor chip 20 has a first surface 20a and a second surface 20b. The first surface 20a and the second surface 20b are end surfaces in the thickness direction of the semiconductor chip 20. The first surface 20a is, for example, the surface on which a guard ring is formed. Although not shown, the semiconductor chip 20 has electrodes on the first surface 20a and the second surface 20b. The semiconductor chip 20 is, for example, an IGBT (Insulated Gate Bipolar Transistor). However, the semiconductor chip 20 may also be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a GTO (Gate Turn-Off thyristor), a diode, or the like. In other words, the semiconductor chip 20 may have electrodes on the first surface 20a and the second surface 20b.

[0018] The semiconductor chip 20 is disposed on the first electrode plate 10. With the semiconductor chip 20 disposed on the first electrode plate 10, the second surface 20b is in contact with the first surface 10a. The semiconductor chip 20 is disposed between the screw holes 10c and 10d. A conductive material may be interposed between the second surface 20b and the first surface 10a to reduce contact resistance. The multiple semiconductor chips 20 are arranged, for example, in a grid pattern in a plan view.

[0019] The plate electrode 30 is a plate-shaped member. The plate electrode 30 is made of a conductive material. The plate electrode 30 is made of, for example, a metal material. The plate electrode 30 is disposed on the semiconductor chip 20 (on the first surface 20a). A conductive material may be interposed between the plate electrode 30 and the semiconductor chip 20 to reduce contact resistance. The dimensions of the plate electrode 30 in a plan view are appropriately selected, for example, taking into consideration the conductive area of ​​the semiconductor chip 20 (the area of ​​the electrode on the first surface 20a).

[0020] The cylindrical electrode 40 has a cylindrical shape extending along the thickness direction of the first electrode plate 10. The cylindrical electrode 40 is made of a conductive material. The cylindrical electrode 40 is made of, for example, a metal material. The cylindrical electrode 40 has an outer shape, for example, a rectangular shape, in a cross section perpendicular to the thickness direction of the first electrode plate 10. The cylindrical electrode 40 is disposed on the plate electrode 30. A through hole 41 is formed in the cylindrical electrode 40. The through hole 41 penetrates the cylindrical electrode 40 along the thickness direction of the first electrode plate 10. The through hole 41 has, for example, a circular shape, in a cross section perpendicular to the thickness direction of the first electrode plate 10. The cylindrical electrode 40 may be formed integrally with the plate electrode 30.

[0021] A coil spring 42 is disposed within the through-hole 41. The coil spring 42 extends spirally along the thickness direction of the first electrode plate 10. The coil spring 42 is compressed between the plate electrode 30 and a lower step portion 51 (second surface 51b) described below, thereby generating a repulsive force that presses the plate electrode 30 against the semiconductor chip 20. A buffer member 43 may be disposed between the coil spring 42 and the plate electrode 30, and a buffer member 44 may be disposed between the coil spring 42 and the lower step portion 51. To suppress wear of the plate electrode 30 and the stepped electrode 50 due to contact with the coil spring 42, the buffer members 43 and 44 are preferably formed from a highly wear-resistant material. Specific examples of materials used for the buffer members 43 and 44 include carbon steel, copper alloy, and stainless steel.

[0022] By using the coil springs 42 as springs for applying pressure to the semiconductor chip 20, it is possible to apply pressure to the semiconductor chip 20 more uniformly than with disc springs, etc. Furthermore, even if the conductive area of ​​the semiconductor chip 20 varies, uniform pressure can be applied to the semiconductor chip 20 by selecting the number and material of the coil springs 42 according to the area.

[0023] The stepped electrode 50 is made of a conductive material. The stepped electrode 50 is made of, for example, a metal material. The stepped electrode 50 has a lower step portion 51 and an upper step portion 52. The lower step portion 51 has a first surface 51a and a second surface 51b. The first surface 51a and the second surface 51b are end surfaces of the lower step portion 51 in the thickness direction. The lower step portion 51 is disposed on the cylindrical electrode 40. The second surface 51b is in contact with the cylindrical electrode 40. In a cross-sectional view perpendicular to the thickness direction of the first electrode plate 10, the lower step portion 51 has, for example, a rectangular shape.

[0024] The upper step portion 52 is located on the lower step portion 51. From another perspective, the upper step portion 52 protrudes from the first surface 51a. In a plan view, the outer shape of the upper step portion 52 is located more inward than the outer shape of the first surface 51a. In a cross-sectional view perpendicular to the thickness direction of the first electrode plate 10, the upper step portion 52 is, for example, circular. A screw hole 52a is formed in the top surface of the upper step portion 52. The screw hole 52a is formed, for example, by tapping.

[0025] The insulating frame 60 is made of an electrically insulating material. For example, the insulating frame 60 is made of an insulating resin material. Specific examples of insulating resin materials include epoxy resin and PPS (polyphenylene sulfide). The insulating frame 60 may also be made of insulating ceramic.

[0026] The insulating frame 60 has a side wall 61 and an upper wall 62. In a plan view, the side wall 61 surrounds the semiconductor chip 20, the plate electrode 30, the cylindrical electrode 40, and the stepped electrode 50. The side wall 61 is disposed on the first electrode plate 10 (first surface 10a). The side wall 61 extends along the thickness direction of the first electrode plate 10. The upper wall 62 is continuous with the upper end of the side wall 61. A through hole 62a is formed in the upper wall 62. The through hole 62a penetrates the upper wall 62 along the thickness direction of the first electrode plate 10. The upper step portion 52 passes through the through hole 62a. The first surface 51a is in contact with the inner wall surface of the upper wall 62 around the through hole 62a.

[0027] The lower end of the side wall 61 is fixed to the first electrode plate 10 (first surface 10a). More specifically, a through hole 61a and a through hole 61b are formed near the lower end of the side wall 61. A fastening member 63a and a fastening member 63b are passed through the through hole 61a and the through hole 61b, respectively. The fastening member 63a and the fastening member 63b are screws, bolts, etc. The fastening member 63a and the fastening member 63b are screwed into the screw hole 10c and the screw hole 10d, respectively. As a result, the semiconductor chip 20, the plate electrode 30, the tubular electrode 40, and the lower portion 51 are sandwiched between the upper wall 62 and the first electrode plate 10.

[0028] The module case 70 is made of an electrically insulating material. The module case 70 is made of, for example, an insulating resin material. A specific example of the insulating resin material is epoxy resin. The module case 70 may be made of insulating ceramic. The module case 70 is disposed on the outer peripheral edge of the first electrode plate 10 (first surface 10a). The module case 70 extends along the thickness direction of the first electrode plate 10.

[0029] The second electrode plate 80 is a plate-shaped member. The second electrode plate 80 is made of a conductive material. The second electrode plate 80 is made of, for example, a metal material. The second electrode plate 80 has a first surface 80a and a second surface 80b. The first surface 80a and the second surface 80b are end surfaces of the second electrode plate 80 in the thickness direction. The second electrode plate 80 is disposed on the module case 70 so that the second surface 80b faces the first surface 10a with a gap therebetween. From another perspective, the module case 70 is sandwiched between the first electrode plate 10 and the second electrode plate 80.

[0030] The second electrode plate 80 has a plurality of through holes 80c formed therein. The through holes 80c are positioned so as to overlap the screw holes 52a in a plan view. Fastening members 81 are passed through the through holes 80c. The fastening members 81 are screwed into the screw holes 52a. As a result, the second surface 80b around the through holes 80c comes into contact with the top surface of the upper step portion 52, electrically connecting the second electrode plate 80 to the stepped electrode 50. Although not shown, an external electrode (second external electrode) such as a bus bar is connected to the second electrode plate 80. The second electrode plate 80 and the second external electrode are connected using fastening members such as screws. The semiconductor device 100 is operated by passing current between the first external electrode and the second external electrode.

[0031] (Effects of the semiconductor device 100) The effects of the semiconductor device 100 will be described below.

[0032] In the semiconductor device 100, the first electrode plate 10 and the second electrode plate 80 can be electrically connected to the semiconductor chip 20 while maintaining a pressure on the semiconductor chip 20, without using an external pressure contact mechanism. Therefore, the semiconductor device 100 does not require an external pressure contact mechanism, and the device can be made smaller accordingly. Furthermore, in the semiconductor device 100, external connection electrodes such as bus bars can be easily connected to the first electrode plate 10 and the second electrode plate 80 using fastening members or the like.

[0033] When multiple semiconductor chips are pressed together using an external pressure welding mechanism, variations in the pressure force occur between the semiconductor chips arranged in the center and those arranged in the outer periphery. In the semiconductor device 100, pressure is applied to each semiconductor chip 20 using the coil spring 42, so the pressure applied to the semiconductor chips 20 is less likely to vary depending on their location.

[0034] (Variation) Fig. 4 is a cross-sectional view of a semiconductor device 100 according to a modified example. In the above, an example has been described in which the semiconductor device 100 includes multiple semiconductor chips 20. However, as shown in Fig. 4, the number of semiconductor chips 20 included in the semiconductor device 100 may be one.

[0035] Embodiment 2 A semiconductor device according to the second embodiment will be described. The semiconductor device according to the second embodiment is referred to as semiconductor device 100A. Here, differences from semiconductor device 100 will be mainly described, and overlapping descriptions will not be repeated.

[0036] (Configuration of semiconductor device 100A) The configuration of the semiconductor device 100A will be described below.

[0037] FIG. 5 is a cross-sectional view of the semiconductor device 100A. As shown in FIG. 5, the semiconductor device 100A includes a first electrode plate 10, a plurality of semiconductor chips 20, a plurality of plate-shaped electrodes 30, a plurality of cylindrical electrodes 40, a plurality of stepped electrodes 50, a module case 70, and a second electrode plate 80. In this respect, the configuration of the semiconductor device 100A is common to the configuration of the semiconductor device 100. In the semiconductor device 100A, a plurality of insulating frames 60 are integrated into a single insulating frame 64. In this respect, the configuration of the semiconductor device 100A differs from the configuration of the semiconductor device 100. Note that in the semiconductor device 100A, the plurality of insulating frames 60 may be divided into a plurality of groups, and each group may be integrated into an insulating frame 64.

[0038] (Effects of semiconductor device 100A) The effects of the semiconductor device 100A will be described below.

[0039] In the semiconductor device 100, multiple insulating frames 60 need to be individually assembled, which requires multiple steps for assembly. On the other hand, in the semiconductor device 100A, an insulating frame 64 is used that integrates multiple insulating frames 60, which makes it possible to reduce the number of steps required for assembly.

[0040] Embodiment 3 A semiconductor device according to the third embodiment will be described. The semiconductor device according to the third embodiment is referred to as semiconductor device 100B. Here, differences from semiconductor device 100 will be mainly described, and overlapping descriptions will not be repeated.

[0041] (Configuration of semiconductor device 100B) FIG. 6 is a plan view of the semiconductor device 100B. FIG. 7 is a cross-sectional view of the semiconductor device 100B. In FIG. 6, the second electrode plate 80 and fastening members 81 are omitted. As shown in FIGS. 6 and 7, the semiconductor device 100B has a first electrode plate 10, a plurality of semiconductor chips 20, a plurality of plate-shaped electrodes 30, a plurality of cylindrical electrodes 40, a plurality of stepped electrodes 50, a plurality of insulating frames 60, a module case 70, and a second electrode plate 80. In this respect, the configuration of the semiconductor device 100A is common to the configuration of the semiconductor device 100.

[0042] The semiconductor device 100B further includes a peripheral frame 90. In plan view, the peripheral frame 90 surrounds the outer periphery of the sidewall 61. That is, the peripheral frame 90 has a plurality of openings arranged in a grid pattern in plan view, and the sidewall 61 is disposed within the openings. The peripheral frame 90 is disposed inside the module case 70 in plan view. To avoid increasing the size of the semiconductor device 100B, the peripheral edge of the peripheral frame 90 preferably coincides with or is located inside the peripheral edge of the outermost insulating frame 60 in plan view. The upper and lower ends of the peripheral frame 90 are preferably spaced apart from the first electrode plate 10 and the second electrode plate 80, respectively. In these respects, the configuration of the semiconductor device 100B differs from the configuration of the semiconductor device 100.

[0043] (Effects of the semiconductor device 100B) The effects of the semiconductor device 100B will be described below.

[0044] In the semiconductor device 100B, the peripheral frame 90 can absorb the fracture energy of the semiconductor chip 20. When the upper and lower ends of the peripheral frame 90 are spaced apart from the first electrode plate 10 and the second electrode plate 80, respectively, there is no need to consider the creepage distance when ensuring insulation between the first electrode plate 10 and the second electrode plate 80, so insulation between the first electrode plate 10 and the second electrode plate 80 can be easily ensured.

[0045] (Variation) 8 is a cross-sectional view of a semiconductor device 100B according to a modified example. In the above example, the peripheral frame 90 is an integral member, but as shown in FIG. 8, the peripheral frame 90 may be divided into multiple peripheral frames 91. Each of the multiple peripheral frames 91 surrounds the outer periphery of the side wall 61.

[0046] Embodiment 4 A semiconductor device according to the fourth embodiment will be described. The semiconductor device according to the fourth embodiment is referred to as semiconductor device 100C. Here, differences from semiconductor device 100 will be mainly described, and overlapping descriptions will not be repeated.

[0047] (Configuration of semiconductor device 100C) The configuration of the semiconductor device 100C will be described below.

[0048] 9 is a cross-sectional view of the semiconductor device 100C. As shown in FIG. 9, the semiconductor device 100C has a first electrode plate 10, a plurality of semiconductor chips 20, a plurality of plate-shaped electrodes 30, a plurality of cylindrical electrodes 40, a plurality of stepped electrodes 50, a plurality of insulating frames 60, a module case 70, and a second electrode plate 80. In this respect, the configuration of the semiconductor device 100C is common to the configuration of the semiconductor device 100.

[0049] In the semiconductor device 100C, a through hole 62b is formed in the upper wall 62. It is preferable that there are a plurality of through holes 62b. The inside of the insulating frame 60 may be filled with a sealing resin 65. The sealing resin 65 is made of an insulating resin material. It is preferable that the sealing resin 65 is soft. In these respects, the configuration of the semiconductor device 100C differs from the configuration of the semiconductor device 100.

[0050] (Effects of semiconductor device 100C) The effects of the semiconductor device 100C will be described below.

[0051] In the semiconductor device 100C, the sealing resin 65 can be supplied from the through-holes 62b into the insulating frame 60, thereby further improving the insulation of the semiconductor chip 20. Furthermore, in the semiconductor device 100C, gas generated when the semiconductor chip 20 is broken down due to a short circuit can be discharged through the through-holes 62b.

[0052] Embodiment 5. A semiconductor device according to the fifth embodiment will be described. The semiconductor device according to the fifth embodiment is designated as semiconductor device 100D. Here, differences from semiconductor device 100 will be mainly described, and overlapping descriptions will not be repeated.

[0053] (Configuration of semiconductor device 100D) The configuration of the semiconductor device 100D will be described below.

[0054] 10 is a cross-sectional view of a semiconductor device 100D. As shown in FIG. 10, the semiconductor device 100D has a first electrode plate 10, a plurality of semiconductor chips 20, a plurality of plate-shaped electrodes 30, a plurality of cylindrical electrodes 40, a plurality of stepped electrodes 50, a plurality of insulating frames 60, a module case 70, and a second electrode plate 80. In this respect, the configuration of the semiconductor device 100D is common to the configuration of the semiconductor device 100.

[0055] In the semiconductor device 100D, projections and recesses are formed on the inner wall surface of the top wall 62. More specifically, in the semiconductor device 100D, a plurality of projections 62c are formed at intervals on the inner wall surface of the top wall 62, and a recess 62d is formed between two adjacent projections 62c. In this respect, the configuration of the semiconductor device 100D differs from the configuration of the semiconductor device 100.

[0056] (Effects of semiconductor device 100D) The effects of the semiconductor device 100D will be described below.

[0057] In the semiconductor device 100, the creepage distance between the stepped electrode 50 and the first electrode plate 10 is shorter on the inner wall surface side of the insulating frame 60 than on the outer wall surface side of the insulating frame 60. On the other hand, in the semiconductor device 100D, unevenness (protrusions 62c and recesses 62d) is formed on the upper wall 62, so the creepage distance between the stepped electrode 50 and the first electrode plate 10 on the outer wall surface side of the insulating frame 60 is larger. Therefore, with the semiconductor device 100D, it is possible to further ensure insulation between the stepped electrode 50 and the first electrode plate 10, and it can be applied to products that require even higher insulation.

[0058] Embodiment 6 A semiconductor device according to the sixth embodiment will be described. The semiconductor device according to the sixth embodiment is designated as semiconductor device 100E. Here, differences from semiconductor device 100C will be mainly described, and overlapping descriptions will not be repeated.

[0059] (Configuration of semiconductor device 100E) The configuration of the semiconductor device 100E will be described below.

[0060] FIG. 11 is a cross-sectional view of the semiconductor device 100E. FIG. 12 is a plan view of the semiconductor device 100E. In FIG. 12, the second electrode plate 80 and fastening members 81 are omitted. As shown in FIGS. 11 and 12, the semiconductor device 100E includes a first electrode plate 10, a plurality of semiconductor chips 20, a plurality of plate-shaped electrodes 30, a plurality of cylindrical electrodes 40, a plurality of stepped electrodes 50, a plurality of insulating frames 60, a module case 70, and a second electrode plate 80. In the semiconductor device 100E, a through-hole 62b is formed in the upper wall 62. In these respects, the configuration of the semiconductor device 100C is common to the configuration of the semiconductor device 100C.

[0061] In the semiconductor device 100E, a through hole 62e is formed in the upper wall 62. The through hole 62e penetrates the upper wall 62 along the thickness direction of the first electrode plate 10. The semiconductor device 100E further includes an insulating substrate 92 and a plurality of contact pins 93. The insulating substrate 92 includes a base material 92a and a conductive pattern 92b.

[0062] The base material 92a is made of an electrically insulating material. The base material 92a has a first surface 92aa and a second surface 92ab. The first surface 92aa and the second surface 92ab are end surfaces of the base material 92a in the thickness direction. The base material 92a is disposed on the upper wall 62. The second surface 92ab faces the upper wall 62. The conductive pattern 92b is disposed on the first surface 92aa. A plurality of through holes 92ac are formed in the base material 92a. The through holes 92ac penetrate the base material 92a along the thickness direction of the first electrode plate 10. The through holes 92ac overlap the through holes 62e in a plan view.

[0063] The contact pin 93 is passed through the through hole 62e and the through hole 92ac. The contact pin 93 is made of a conductive material. One end of the contact pin 93 is in contact with the conductive pattern 92b, and the other end of the contact pin 93 is in contact with the semiconductor chip 20 (first surface 20a). This electrically connects the insulating substrate 92 to the semiconductor chip 20. When the plate electrode 30 is in contact with the emitter electrode formed on the first surface 20a, the other end of the contact pin 93 is in contact with the gate electrode formed on the first surface 20a. The other end of the contact pin 93 is preferably a spring contact.

[0064] The insulating substrate 92 has a plurality of through holes 92c and a plurality of through holes 92d formed therein. The through holes 92c and 92d penetrate the insulating substrate 92 in the thickness direction of the first electrode plate 10. The through hole 92c overlaps with the through hole 62a in plan view. The upper stage portion 52 passes through the through hole 92c as well as the through hole 62a. The through hole 92d overlaps with the through hole 62b in plan view. The insulating substrate 92 has a lead-out portion 92e. The lead-out portion 92e passes through a through hole 70a formed in the module case 70 and is led out of the module case 70. An external electrode (third external electrode) is connected to the conductive pattern 92b in the lead-out portion 92e.

[0065] (Effects of the semiconductor device 100E) The effects of the semiconductor device 100E will be described below.

[0066] In the semiconductor device 100E, the semiconductor chip 20 and the insulating substrate 92 are electrically connected by contact pins 93. The insulating substrate 92 also has a lead-out portion 92e that is led out to the outside of the module case 70. Therefore, with the semiconductor device 100E, external signals can be easily input and output by connecting a third external electrode to the conductive pattern 92b on the lead-out portion 92e.

[0067] The embodiments disclosed herein are illustrative in all respects and should not be considered limiting. The basic scope of the present disclosure is defined by the claims, not the above-described embodiments, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0068] 10 First electrode plate, 10a First surface, 10b Second surface, 10c, 10d Screw hole, 20 Semiconductor chip, 20a First surface, 20b Second surface, 30 Plate electrode, 40 Cylindrical electrode, 41 Through hole, 42 Coil spring, 43, 44 Buffer member, 50 Stepped electrode, 51 Lower portion, 51a First surface, 51b Second surface, 52 Upper portion, 52a Screw hole, 60 Insulating frame, 61 Side wall, 61a, 61b Through hole, 62 Upper wall, 62a, 62b Through hole, 62c Convex portion, 62d Concave portion, 62e Through hole, 63a, 63b Fastening member, 64 Insulating frame, 65 Sealing resin, 70 Module case, 70a Through hole, 80 Second electrode plate, 80a First surface, 80b Second surface, 80c through hole, 81 fastening member, 90, 91 peripheral frame, 92 insulating substrate, 92a base material, 92aa first surface, 92ab second surface, 92ac through hole, 92b conductive pattern, 92c, 92d through hole, 92e lead-out portion, 93 contact pin, 100, 100A, 100B, 100C, 100D, 100E semiconductor device.

Claims

1. A first electrode plate; a first semiconductor chip disposed on the first electrode plate; a first plate electrode disposed on the first semiconductor chip; a first cylindrical electrode disposed on the first plate-like electrode; a first coil spring; a first stepped electrode having a first lower step portion disposed on the first cylindrical electrode and a first upper step portion disposed on the first lower step portion; a first insulating frame having a first side wall and a first upper wall connected to an upper end of the first side wall; a second electrode plate electrically connected to the first upper portion, a first through-hole penetrating the first cylindrical electrode along a thickness direction of the first electrode plate; the first coil spring is disposed in the first through hole, and is compressed by the first plate electrode and the first lower portion to generate a repulsive force that presses the first plate electrode against the first semiconductor chip; a first through-hole is formed in the first upper wall, the first through-hole penetrating the first upper wall along the thickness direction of the first electrode plate and through which the first upper step portion passes so that the first upper step portion protrudes from the first upper wall; a lower end side of the first side wall is fixed to the first electrode plate with the first semiconductor chip, the first plate-shaped electrode, the first cylindrical electrode, and the first lower portion sandwiched between the first upper wall and the first electrode plate.

2. a second semiconductor chip disposed on the first electrode plate; a second plate electrode disposed on the second semiconductor chip; a second cylindrical electrode disposed on the second plate-shaped electrode; A second coil spring; a second stepped electrode having a second lower step portion disposed on the second cylindrical electrode and a second upper step portion disposed on the second lower step portion; a second insulating frame having a second side wall and a second upper wall connected to an upper end of the second side wall; a second through-hole penetrating the second cylindrical electrode along a thickness direction of the first electrode plate is formed in the second cylindrical electrode; the second coil spring is disposed in the second through-hole, and is compressed by the second plate electrode and the second lower portion to generate a repulsive force that presses the second plate electrode against the second semiconductor chip; a second through-hole is formed in the second upper wall, the second through-hole penetrating the second upper wall along the thickness direction of the first electrode plate and through which the second upper step portion passes so that the second upper step portion protrudes from the second upper wall; a lower end side of the second side wall is fixed to the first electrode plate in a state in which the second semiconductor chip, the second plate-like electrode, the second cylindrical electrode, and the second lower portion are sandwiched between the second upper wall and the first electrode plate, The semiconductor device according to claim 1 , wherein the second upper portion is electrically connected to the second electrode plate.

3. The semiconductor device according to claim 2 , wherein said first insulating frame and said second insulating frame are integrally formed.

4. 4. The semiconductor device according to claim 2, further comprising a peripheral frame surrounding a periphery of said first side wall and a periphery of said second side wall.

5. 5. The semiconductor device according to claim 4, wherein a lower end and an upper end of said outer peripheral frame are spaced apart from said first electrode plate and said second electrode plate, respectively.

6. 6. The semiconductor device according to claim 4, wherein the outer periphery frame is divided into a first outer periphery frame surrounding the periphery of the first side wall and a second outer periphery frame surrounding the periphery of the second side wall.

7. The semiconductor device according to any one of claims 2 to 6, wherein a third through hole and a fourth through hole are formed in the first upper wall and the second upper wall, respectively, penetrating along the thickness direction of the first electrode plate.

8. 8. The semiconductor device according to claim 2, wherein an inner wall surface of said first upper wall and an inner wall surface of said second upper wall are formed with unevenness.

9. a first contact pin and a second contact pin; an insulating substrate having a wiring pattern; a fifth through hole and a sixth through hole penetrating the first upper wall along a thickness direction of the first electrode plate are formed in the first upper wall and the second upper wall, respectively; the first contact pin and the second contact pin are passed through the fifth through hole and the sixth through hole, one end and the other end of the first contact pin are electrically connected to the first semiconductor chip and the wiring pattern, respectively; 9. The semiconductor device according to claim 2, wherein one end and the other end of said second contact pin are electrically connected to said second semiconductor chip and said wiring pattern, respectively.

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