Analog-to-Digital Converter

Abstract

To provide a high-speed, small-sized analog-to-digital converter.SOLUTION: An analog-to-digital converter 1 that converts an input analog potential Ain into a digital conversion value CODE, comprises: a comparator 2 that compares the input analog potential Ain with a reference potential Vref; and a time measurement circuit 4 that measures a comparison operation time from the start to the end of a comparison operation by the comparator 2, and outputs the digital conversion value CODE depending on the measured comparison operation time and the comparison result Q by the comparator 2.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention is directed to an input analog signal (input analog potential A in ) to a digital value. [Background technology]

[0002] A flash AD converter is known as an analog-to-digital converter (hereinafter referred to as an AD converter) that converts an input analog signal into a digital value (see, for example, Patent Document 1). A flash AD converter has a resolution of n bits (2 n -1) comparison potentials, and (2 n The flash AD converter has an input analog potential A in All comparators simultaneously compare the potentials of 0 to (2 n The digital value is obtained by checking which of the digital values ​​(-1) it corresponds to.

[0003] The advantage of a flash AD converter is that the input analog potential A in The advantage of this is that it is possible to easily obtain a digital value for the input analog potential A, thereby realizing high-speed AD conversion. in Since sampling is not required, the means for sampling (capacitances, switches, and means for controlling them) is not required, and the time required for sampling is also not required.

[0004] As an AD converter, a successive approximation type AD converter is known (see, for example, Patent Document 2). A successive approximation type AD converter has a resolution of n bits (2 n ) capacitance elements, and the input analog potential A in The successive approximation type AD converter has a CDAC that functions as a sampling capacitor, one comparator, and a CDAC control circuit. The successive approximation type AD converter obtains a digital value by performing n comparison operations using a binary search method.

[0005] The advantage of a successive approximation type AD converter is that a digital value can be obtained by performing n comparison operations with one comparator, and that it has a good balance between the number of circuits, high speed, and power consumption.

[0006] As an AD converter, a Wilkinson type AD converter (also called a voltage-time conversion type AD converter) is known (see, for example, Patent Document 3).

[0007] The Wilkinson AD converter uses the input analog potential A in The Wilkinson AD converter has a capacitor that charges (samples) the input analog potential A in After the charged (sampled) capacitance is disconnected (held) from the input, the charge stored in the capacitance is discharged with a constant current, and the time until the charge becomes zero (0V) is measured by the TDC circuit to obtain a digital value.

[0008] The advantage of the Wilkinson type AD converter is that it is expected to be an AD converter with excellent differential linearity. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Application Publication No. 01-103320 [Patent Document 2] Japanese Patent Application Laid-Open No. 2002-374169 [Patent Document 3] Japanese Patent Application Laid-Open No. 62-109434 Summary of the Invention [Problem to be solved by the invention]

[0010] However, the flash AD converter has a n -1) means for obtaining comparison potentials and (2 n-1) The number of comparators required increases the size of the AD converter. For example, to obtain 12-bit resolution in a flash AD converter, 4095 comparison potentials and 4095 comparators are required.

[0011] In addition, the successive approximation type AD converter has a CDAC (2 n ) capacitance elements and analog switches are required. The capacitance elements and analog switches occupy a large layout area, which increases the size of the AD converter.

[0012] Furthermore, the Wilkinson AD converter uses the input analog potential A in A large capacitance element is required to sample the signal, which increases the size of the AD converter. The capacitance element of the Wilkinson AD converter is (2 n ) times larger, and the capacity increases exponentially as the resolution increases.

[0013] Digital logic circuits have benefited from the miniaturization of elements, becoming smaller and more highly integrated. However, analog circuits (especially elements such as capacitance and resistance) are difficult to miniaturize, and the proportion of analog circuit area in a chip is relatively large, which is a factor in pushing up prices.

[0014] Furthermore, as MOS elements become smaller, the leakage current of MOS switches increases, which is a problem. Successive approximation type AD converters and Wilkinson type AD converters contain a combination of capacitance elements and MOS switches in their circuits, so the leakage current causes an increase in error.

[0015] There are various types of AD converters, including slope type, tracking type (ramp input type), VF conversion type, and delta-sigma type. However, these AD converters are not large in size, but they take a long time to convert.

[0016] SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art and to provide a high-speed, small-sized AD converter. [Means for solving the problem]

[0017] The AD converter of the present invention is an analog-to-digital converter that converts an input analog potential into a digital converted value, The digital conversion circuit includes a plurality of comparators that compare the input analog potential with a plurality of different reference potentials, respectively, and a conversion circuit that outputs the digital conversion value according to a comparison operation time from when the comparator selected from the plurality of comparators starts to when the comparator finishes the comparison operation. The conversion circuit stores correlation characteristics between the potential difference between the input analog potential and the reference potential and the comparison operation time of the plurality of comparators, and calculates the digital conversion value from the comparison operation time based on the correlation characteristics of the selected comparator, and selects the comparator based on the comparison operation time. It is characterized by: The AD converter of the present invention is an analog-to-digital converter that converts an input analog potential into a digital conversion value, The digital signal processing device includes a plurality of comparators that respectively compare the input analog potential with a plurality of different reference potentials, a conversion circuit that stores a comparison operation time from start to finish of a comparison operation for each comparator and a correlation characteristic between the potential difference between the input analog potential and the reference potential, and outputs the digital conversion value from the comparison operation time based on the correlation characteristic of the selected comparator, and an intermediate potential comparator that compares the input analog potential with an intermediate potential between the plurality of reference potentials, the conversion circuit specifying the comparator based on a comparison result of the intermediate potential comparator, the plurality of comparators being configured with a combination of different types, and the conversion circuit specifying the comparator of the selected type based on the comparison result of the intermediate potential comparator. It is characterized by: [Effects of the Invention]

[0018] According to the present invention, AD conversion can be completed using a small number of comparators 2, with one comparison operation and calculation processing of the result, thereby providing an AD converter 1 that is fast and small in size. [Brief explanation of the drawings]

[0019] [Figure 1] 1 is a configuration diagram showing a configuration of a first embodiment of an AD converter according to the present invention. [Figure 2] 2 is a circuit diagram illustrating a configuration example of a comparator shown in FIG. 1. [Figure 3] 2 is a waveform diagram illustrating the operation of a comparator and an end detection circuit shown in FIG. 1. [Figure 4] 2 is a diagram illustrating an example of correlation characteristics of the comparator shown in FIG. [Figure 5] 2 is a diagram illustrating an example of calculating an input analog potential from a comparison operation time in the time measurement circuit shown in FIG. 1. FIG. [Figure 6] FIG. 10 is a configuration diagram showing the configuration of a second embodiment of an AD converter according to the present invention. [Figure 7] 7 is a diagram illustrating an example of correlation characteristics of the comparator shown in FIG. 6. [Figure 8] FIG. 10 is a configuration diagram showing the configuration of a third embodiment of an AD converter according to the present invention. [Figure 9]9 is a diagram illustrating an example of correlation characteristics of the comparator shown in FIG. 8. [Figure 10] FIG. 10 is a configuration diagram showing the configuration of a fourth embodiment of an AD converter according to the present invention. [Figure 11] 11 is a diagram illustrating an example of correlation characteristics of the comparator shown in FIG. 10. [Figure 12] FIG. 10 is a configuration diagram showing the configuration of a fifth embodiment of an AD converter according to the present invention. [Figure 13] 13 is a circuit diagram showing an example of the configuration of a different type of comparator shown in FIG. 12. FIG. [Figure 14] 13 is a diagram illustrating an example of correlation characteristics of the comparator shown in FIG. 12. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0020] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following embodiments, components having similar functions will be denoted by the same reference numerals, and the description thereof will be omitted as appropriate.

[0021] (First embodiment) Referring to FIG. 1, an analog-to-digital converter 1 (hereinafter referred to as AD converter 1) according to the first embodiment receives an input analog potential A in and the reference potential V ref a completion detection circuit 3 that detects the completion of the comparison operation by the comparator 2; and a time measurement circuit 4 (hereinafter referred to as TDC circuit 4) that measures the comparison operation time from when the comparator 2 starts to when it finishes the comparison operation, and outputs a digital conversion value CODE according to the measured comparison operation time and the comparison result Q by the comparator 2.

[0022] Comparator 2 is the lower limit reference potential V REFL ~Upper reference potential V REFH Input analog potential A in The first input terminal to which is input the lower limit reference potential V REFL ~Upper reference potential V REFH potential between the lower limit reference potential V REFL ~Upper reference potential V REFHThe reference potential V is set to the center potential of ref The second input terminal to which the analog input potential A is input. in and the reference potential V ref The output terminal that outputs the comparison result Q and the inverted output Q of the comparison result Q. - and an inverted output terminal that outputs the start signal START - and a start signal input terminal to which the start signal is input.

[0023] Comparator 2 detects the start signal START - is a comparison start instruction signal that instructs the comparator 2 to start comparison, and the start signal START - When the input analog potential A goes from high level Hi to low level Low, in and the reference potential V input to the second input terminal ref Then, the comparator 2 starts comparing the input analog potential A in >Reference potential V ref In this case, the comparison result Q is "1" (high level Hi) from the output terminal, and the input analog potential A in <Reference potential V ref In this case, the output terminal outputs "0" (low level) as the comparison result Q.

[0024] 2, the comparator 2 can be configured as a circuit in which a P-channel MOS transistor P0 that functions as a power switch 22 is added to a memory cell 21 of a general CMOS type SRAM. - This is the start signal input terminal of the comparator 2 to which the

[0025] The memory cell 21 includes P-channel MOS transistors P1 and P2 and N-channel MOS transistors N1, N2, N3, and N4.

[0026] The P-channel MOS transistor P1 and the N-channel MOS transistor N1 form a first CMOS inverter. The source of the P-channel MOS transistor P1 is connected to the power supply voltage Vcc via the power switch 22, and the drain of the P-channel MOS transistor P1 is connected to the drain of the N-channel MOS transistor N1. The source of the N-channel MOS transistor N1 is connected to the ground voltage Vss.

[0027] The P-channel MOS transistor P2 and the N-channel MOS transistor N2 form a second CMOS inverter. The source of the P-channel MOS transistor P2 is connected to the power supply voltage Vcc via the power switch 22, and the drain of the P-channel MOS transistor P2 is connected to the drain of the N-channel MOS transistor N2. The source of the N-channel MOS transistor N2 is connected to the ground voltage Vss.

[0028] The input of the first CMOS inverter, i.e., the gate of the P-channel MOS transistor P1 and the gate of the N-channel MOS transistor N1, is connected to the output of the second CMOS inverter, i.e., the connection point between the drain of the P-channel MOS transistor P1 and the drain of the N-channel MOS transistor N1, and an inverted output Q of the comparison result Q is output. - This is the inverting output terminal of comparator 2, which outputs

[0029] The input of the second CMOS inverter, i.e., the gate of the P-channel MOS transistor P2 and the gate of the N-channel MOS transistor N2, is connected to the output of the first CMOS inverter, i.e., the connection point between the drain of the P-channel MOS transistor P2 and the drain of the N-channel MOS transistor N2, and serves as the output terminal of the comparator 2 that outputs the comparison result Q.

[0030] The N-channel MOS transistor N3 is connected in parallel with the N-channel MOS transistor N1, and the gate of the N-channel MOS transistor N3 is connected to a reference potential V ref This is the second input terminal of the comparator 2 to which the

[0031] The N-channel MOS transistor N4 is connected in parallel with the N-channel MOS transistor N2, and the gate of the N-channel MOS transistor N4 is connected to the input analog potential A in This is the first input terminal of the comparator 2 to which the

[0032] Referring to Figure 3, the start signal START - is at high level Hi, the P-channel MOS transistor P0, which is the power switch 22, is turned off, and the comparison result Q and the inverted output Q - is the input analog potential A in , reference potential V ref In FIG. 3, (a) indicates the start signal START - 10(b) shows the output waveform of the comparator 2, and (c) shows the output waveform of the end detection circuit 3.

[0033] Start signalSTART - When the signal START goes low, the P-channel MOS transistor P0 serving as the power switch 22 is turned on, the power supply voltage Vcc is applied to the memory cell 21, and the comparison operation of the comparator 2 is started. - The time when the signal transitions from high level Hi to low level Low is the operation start time when the comparator 2 starts the comparison operation.

[0034] The memory cell 21 to which the power supply voltage Vcc is applied has a comparison result Q=inverted output Q - From the unstable state of - At this time, the input analog potential A in >Reference potential V ref In this case, the current flowing to the ground voltage Vss is larger in the N-channel MOS transistor N4 than in the N-channel MOS transistor N3, so the comparison result Q = inverted output Q - The unstable state of is broken, the comparison result Q becomes "1" (high level Hi), and the inverted output Q- becomes "0" (low level) and stabilizes.

[0035] The end detection circuit 3 detects the output of the comparator 2 (comparison result Q, inverted output Q - ) is a circuit that detects the operation end time of the comparator 2 based on the comparison result Q and the inverted output Q - If they are equal, the comparison result Q and the inverted output Q are set to "0" (low level). - In the example shown in FIG. 3, the output V of the end detection circuit 3 is time The time when the signal transitions from low level Low to high level Hi is the operation end time when the comparison operation of the comparator 2 ends.

[0036] The comparison operation time of the comparator 2 is the time from the operation start time when the comparator 2 starts the comparison operation to the operation end time when the comparison operation of the comparator 2 ends. As shown in FIG. 4, the comparison operation time of the comparator 2 is in and the reference potential V ref The comparison operation time is correlated with the potential difference between in and V ref The smaller the potential difference, the longer the in and V ref In other words, the comparison operation time is shorter as the potential difference between the input analog potential A in and the reference potential V ref A comparator 2 is used which correlates to the potential difference between

[0037] In the comparator, the comparison operation time and the input analog potential A in and the reference potential V ref The correlation between the comparison operation time and the potential difference between the input analog potential Ain and the reference potential Vref is a feature also seen in, for example, general operational amplifier type comparators. Therefore, the comparator 2 of this embodiment is not limited to the configuration shown in FIG. 2 as long as there is a correlation between the comparison operation time and the potential difference between the input analog potential Ain and the reference potential Vref, which are the objects of comparison.

[0038] The TDC circuit 4 has a function of measuring the comparison operation time of the comparator 2 and converts the input analog potential A into a reference potential A using the measured comparison operation time and comparison result Q. in and a function to calculate the digital conversion value CODE.

[0039] The TDC circuit 4 receives the start signal START - The output V of the end detection circuit 3 is time The time from when the signal transitions from low level Low to high level Hi until the operation of the comparator 2 ends is measured as the comparison operation time.

[0040] The TDC circuit 4 outputs the input analog potential A in and the reference potential V ref The correlation characteristics between the potential difference and the comparison operation time are stored, and this correlation characteristic is used to calculate the input analog potential A in The digital conversion value CODE is calculated.

[0041] When the comparison result Q is "1" (high level Hi), the TDC circuit 4 in is the reference potential V ref Using the correlation characteristics in the area larger than (area X shown in Figure 4), the input analog potential A corresponding to the measured comparison operation time is calculated. in and calculate the input analog potential A in The digital conversion value CODE is calculated and output.

[0042] When the comparison result Q is "0" (low level), the TDC circuit 4 in is the reference potential V ref Using the correlation characteristics in the area smaller than , the input analog potential A corresponding to the measured comparison operation time is calculated. in and calculate the input analog potential A in The digital conversion value CODE is calculated and output.

[0043] For example, if the comparison result Q is "0" and the measured comparison operation time is "Ta", the TDC circuit 4 uses the correlation characteristics in the region Y to calculate the input analog potential A corresponding to the measured comparison operation time "Ta". in = "Va" is calculated, and the input analog potential A is calculated. in Calculates and outputs the digital conversion value CODE of "Va".

[0044] In TDC circuit 4, the input analog potential A in The method for calculating the value is as follows: in This can be achieved by storing the correlation characteristics with the frequency band as a lookup table or a function. When storing the correlation characteristics as a function, it can be a linear approximation separated by several thresholds as shown in Figure 5(b), or a logarithmic approximation separated by several thresholds as shown in Figure 5(c).

[0045] When using the comparator 2 shown in Figure 2, if the circuit is designed to be too fast, the input analog voltage A in The comparison operation time varies less with respect to the input voltage, resulting in coarse resolution during AD conversion. Therefore, to achieve fine resolution, the comparison operation time of comparator 2 must be designed to be appropriately long. The comparison operation time of comparator 2 can be lengthened by reducing the drain current Ids of N-channel MOS transistors N3 and N4 (reducing W and increasing L in the shape ratio W / L). The comparison operation time of comparator 2 can also be lengthened by uniformly reducing the drain current Ids of P-channel MOS transistors P1 and P2 and N-channel MOS transistors N1, N2, N3, and N4, or by adding capacitance to the nodes of the output terminal and inverting output terminal.

[0046] In addition, when the comparator 2 shown in FIG. 2 is used, the input analog potential A in and the reference potential V ref The smaller the potential difference between the input analog potential A in The change in comparison operation time is large with respect to the input analog potential A in and the reference potential V refThe greater the potential difference between the input analog potential A in Therefore, the AD converter 1 has a small change in comparison operation time with respect to the input analog potential A in The change in comparison operation time is large with respect to the input analog potential A in is the reference potential V ref The second embodiment described below solves this problem.

[0047] (Second embodiment) Referring to FIG. 6, the AD converter 1A of the second embodiment has a lower limit reference potential V REFL ~Upper reference potential V REFH between different reference potentials V ref0 ~V ref3 and a voltage divider circuit 5A that generates an input analog potential A in and multiple reference potentials V ref0 ~V ref3 a plurality of comparators 20 to 23 for comparing the values ​​count0 to count3 of the plurality of comparators 20 to 23, a plurality of completion detection circuits 30 to 33 for detecting the completion of each of the comparison operations by the plurality of comparators 20 to 23, timers 60 to 63 for measuring the comparison operation times of the plurality of comparators 20 to 23, and a measurement value count selected from the measurement values ​​count0 to count3 of the timers 60 to 63. * (Hereinafter, * indicates one of the options) and the comparator 20 selected from the comparison results Q0 to Q3 of the multiple comparators 20 to 23. * Comparison results Q * The input analog potential A calculated based on in and a decoder circuit 7A that outputs the digital converted value CODE.

[0048] 7, the comparators 20 to 23 have a comparison operation time (measurement value) that is proportional to the input analog potential A in and the reference potential V ref0 ~V ref3 The input analog potential A in and the reference potential V ref0 ~V ref3 The smaller the potential difference between the input analog potential Ain The voltage dividing circuit 5A has a large change in the comparison operation time (measured value) for the input analog potential A in The reference potential V ref0 ~V ref3 Generate.

[0049] This allows the measurement range of the AD converter 1A (lower limit reference potential V REFL ~Upper reference potential V REFH ) is applied to the entire input analog potential A in The change in comparison operation time relative to the reference potential V ref The number of comparators 2 and end detection circuits 3 can be set appropriately depending on the measurement range, the required accuracy, and the like.

[0050] The voltage dividing circuit 5A may be configured with dividing resistors, but resistors are elements that vary widely and have a large layout size. Therefore, it is preferable to configure the voltage dividing circuit 5A with MOS elements and diode elements, as this will provide high accuracy and enable a small layout size.

[0051] The timers 60 to 63 are connected to the outputs V of the respective end detection circuits 30 to 33. time0 ~V time3 and the start signal START - and a clock signal CK are input. Then, the timers 60 to 63 receive a start signal START - The outputs V of the respective completion detection circuits 30 to 33 are changed from the high level Hi to the low level Low at the operation start time of the comparators 60 to 63. time0 ~V time03 The measurement values ​​count0 to count3 from the time when the comparator 20 to 23 transitions from low level Low to high level Hi until the operation end time are measured as the comparison operation times of the plurality of comparators 20 to 23 and output to the decoder circuit 7A.

[0052] As shown in FIG. 7, the decoder circuit 7A is a circuit for converting an input analog potential Ain into a reference potential Vref0 ~V ref3 The decoder circuit 7A stores the correlation characteristics between the potential difference between the comparators 20 and 23 and the comparison operation time (measurement value) in each of the comparators 20 to 23. The decoder circuit 7A stores the largest measurement value count0 to count3. * Select the comparator with the longest comparison operation time, comparator 2 * Then, the decoder circuit 7A determines the value of the specified comparator 2 * Using the correlation characteristics of the specified comparator 2 * Comparison results Q * and the selected measurement count * A digital conversion value CODE of the input analog potential Ain is calculated based on the above.

[0053] For example, the unknown input analog potential A in is Vb shown in FIG. 7, the output V of the end detection circuit 32 time2 transitions from low level Low to high level Hi the slowest, and the decoder circuit 7A selects the measurement value count2=Tb measured by the timer 62. The decoder circuit 7A also identifies the comparator 22 with the longest comparison operation time.

[0054] The decoder circuit 7A outputs the specified comparator 2 * Comparison results Q * If ="1" (high level Hi), the specified comparator 2 * Input analog potential A in is the reference potential V ref* The area larger than the area X shown in Figure 7 * ) using the correlation characteristics of the input analog potential A corresponding to the selected comparison operation time (measurement value). in and calculate the input analog potential A in The digital conversion value CODE is calculated and output.

[0055] The decoder circuit 7A outputs the specified comparator 2 * Comparison results Q * If ="0" (low level), the specified comparator 2 * The input analog potential Ain is the reference potential V ref*The area smaller than the area Y * ) using the correlation characteristics of the input analog potential A corresponding to the selected comparison operation time (measurement value). in and calculate the input analog potential A in The digital conversion value CODE is calculated and output.

[0056] For example, the specified comparator 2 * When the comparison result Q2 is "0" and the selected maximum comparison operation time (measurement value count2) is "Tb", the decoder circuit 7A uses the correlation characteristics in the region Y2 to select the input analog potential A corresponding to the measured comparison operation time = "Tb". in = "Vb" is calculated, and the input analog potential A is calculated. in Calculates and outputs the digital conversion value CODE of "Vb".

[0057] (Third embodiment) Referring to FIG. 8, the AD converter 1B of the third embodiment has a lower limit reference potential V REFL ~Upper reference potential V REFH between different reference potentials V ref0 ~V ref3 , V ref0 -V ref1 The intermediate potential V ref(0-1) , V ref1 -V ref2 The intermediate potential V ref(1-2) , V ref2 -V ref3 The intermediate potential V ref(2-3) and a voltage divider circuit 5B that generates an input analog potential A in and multiple reference potentials V ref0 ~V ref3 and a plurality of comparators 20 to 23 for comparing the input analog potential A in and the intermediate potential V ref(0-1) , V ref(1-2) , V ref(2-3) and multiple comparators 2 that compare A0 ~2 A2a plurality of completion detection circuits 30 to 33 for detecting the completion of each comparison operation by the plurality of comparators 20 to 23; a selection circuit 8B for selecting one of the plurality of comparators 20 to 23; and a comparator 2 selected by the selection circuit 8B. * A timer 6 for measuring the comparison operation time of the timer 6 and a comparator 2 specified from among the plurality of comparators 20 to 23. * Comparison results Q * The input analog potential A calculated based on in and a decoder circuit 7B that outputs the digital converted value CODE.

[0058] The selection circuit 8B is connected to the comparator 2 A0 ~2 A2 Comparison results Q A0 ~Q A2 Based on this, the selection circuit 8B selects one of the plurality of comparators 20 to 23. The selection circuit 8B includes AND circuits AND0 to AND3 and an OR circuit OR.

[0059] In addition, comparator 2 A0 ~2 A2 The comparators 20 to 24 may be of any type, but should operate faster than the comparators 20 to 24.

[0060] The AND circuit AND0 has comparator 2 A0 Comparison results Q A0 The output V of the end detection circuit 30 time0 is input as a selection signal to comparator 2 A0 Comparison results Q A0 When the value is "1", the output V of the end detection circuit 30 time0 is input to timer 6 via the OR circuit OR.

[0061] The AND circuit AND1 has comparator 2 A1 Comparison results Q A1 = "1" and comparator 2 A0 Comparison results Q A0 = "0" and the signal that becomes "1" (other combinations are "0") is the output V of the end detection circuit 31. time1 is input as a selection signal to comparator 2 A1Comparison results Q A1 = "1" and comparator 2 A0 Comparison results Q A0 ="0", the output V of the end detection circuit 31 time1 is input to timer 6 via the OR circuit OR.

[0062] The AND circuit AND2 has comparator 2 A2 Comparison results Q A2 = "1" and comparator 2 A1 Comparison results Q A1 = "0" and the signal that becomes "1" (other combinations are "0") is the output V of the end detection circuit 32. time2 is input as a selection signal to comparator 2 A2 Comparison results Q A2 = "1" and comparator 2 A1 Comparison results Q A1 ="0", the output V of the end detection circuit 32 time2 is input to timer 6 via the OR circuit OR.

[0063] The AND circuit AND2 has comparator 2 A2 Comparison results Q A2 The inverted signal is the output V of the end detection circuit 33. time3 is input as a selection signal to comparator 2 A0 Comparison results Q A0 When is "0", the output V of the end detection circuit 33 time3 is input to timer 6 via the OR circuit OR.

[0064] This causes the input analog potential A in is the intermediate potential V ref(0-1) If the input analog potential A exceeds the threshold, the selection circuit 8B selects the comparator 20, and the timer 6 measures the comparison operation time of the comparator 20. in is the intermediate potential V ref(0-1) ~V ref(1-2) In this case, the selection circuit 8B selects the comparator 21, and the comparison operation time of the comparator 21 is measured by the timer 6. in is the intermediate potential V ref(1-2) ~V ref(2-3)In this case, the selection circuit 8B selects the comparator 22, and the comparison operation time of the comparator 22 is measured by the timer 6. in is the intermediate potential V ref(2-3) If the voltage Vcc is lower than 0.001V, the selection circuit 8B selects the comparator 23, and the timer 6 measures the comparison operation time of the comparator 23.

[0065] As shown in FIG. 9, the decoder circuit 7B is a circuit for converting an input analog potential Ain into a reference potential V ref0 ~V ref3 The decoder circuit 7B stores the correlation characteristics between the potential difference between the comparators 20 and 23 and the comparison operation time (measured value) in the comparators 20 to 23. * Using the correlation characteristics of the specified comparator 2 * Comparison results Q * and the input analog potential A calculated based on the measurement value count of timer 6 in The digital conversion value CODE is output.

[0066] (Fourth embodiment) Referring to FIG. 10, the AD converter 1C of the fourth embodiment has a lower limit reference potential V REFL ~Upper reference potential V REFH between different reference potentials V ref0 ~V ref7 and a voltage divider circuit 5C that generates an input analog potential A in and multiple reference potentials V ref0 ~V ref7 a plurality of comparators 20 to 27 for comparing the signals, a plurality of completion detection circuits 30 to 37 for detecting the completion of the comparison operations by the plurality of comparators 20 to 23, a selection circuit 8C for selecting one of the plurality of comparators 20 to 27, and a comparator 2 selected by the selection circuit 8B. * A timer 6 for measuring the comparison operation time of the timer 6, a measured value "count" of the timer 6, and a comparator 2 specified from among a plurality of comparators 20 to 27. * Comparison results Q * The input analog potential A calculated based on in and a decoder circuit 7C that outputs the digital converted value CODE.

[0067] The selection circuit 8C selects one of the plurality of comparators 20 to 27 based on the comparison results Q0 to Q7 of the comparators 20 to 27. The selection circuit 8C includes AND circuits AND0 to AND7 and an OR circuit OR.

[0068] The AND circuit AND0 receives the comparison result Q0 of the comparator 20 and the output V of the end detection circuit 30. time0 When the comparison result Q0 of the comparator 20 is "1", the output V of the completion detection circuit 30 time0 is input to timer 6 via the OR circuit OR.

[0069] The AND circuit AND1 receives a signal that becomes "1" when the comparison result Q1 of the comparator 21 is "1" and the comparison result Q0 of the comparator 20 is "0" (other combinations are "0"), and outputs V time1 When the comparison result Q1 of the comparator 21 is "1" and the comparison result Q0 of the comparator 20 is "0", the output V of the completion detection circuit 31 is time1 is input to timer 6 via the OR circuit OR.

[0070] The AND circuit AND2 receives a signal that becomes "1" when the comparison result Q2 of the comparator 22 is "1" and the comparison result Q1 of the comparator 21 is "0" (other combinations are "0"), and outputs V time2 When the comparison result Q2 of the comparator 22 is "1" and the comparison result Q1 of the comparator 21 is "0", the output V of the completion detection circuit 32 is time2 is input to timer 6 via the OR circuit OR.

[0071] The AND circuit AND3 receives a signal that becomes "1" when the comparison result Q3 of the comparator 23 is "1" and the comparison result Q2 of the comparator 22 is "0" (other combinations are "0"), and outputs V time3 When the comparison result Q3 of the comparator 23 is "1" and the comparison result Q2 of the comparator 22 is "0", the output V of the completion detection circuit 33 is time3 is input to timer 6 via the OR circuit OR.

[0072] The AND circuit AND4 receives a selection signal that becomes "1" when the comparison result Q4 of the comparator 24 is "1" and the comparison result Q3 of the comparator 23 is "0" (other combinations are "0"), and the output V of the end detection circuit 34 time4 When the comparison result Q4 of the comparator 24 is "1" and the comparison result Q3 of the comparator 23 is "0", the output V of the completion detection circuit 34 is time4 is input to timer 6 via the OR circuit OR.

[0073] The AND circuit AND5 receives a signal that becomes "1" when the comparison result Q5 of the comparator 25 is "1" and the comparison result Q4 of the comparator 24 is "0" (other combinations are "0"), and outputs V time5 When the comparison result Q5 of the comparator 25 is "1" and the comparison result Q4 of the comparator 24 is "0", the output V of the completion detection circuit 35 is time5 is input to timer 6 via the OR circuit OR.

[0074] The AND circuit AND6 receives a selection signal that becomes "1" when the comparison result Q6 of the comparator 26 is "1" and the comparison result Q5 of the comparator 25 is "0" (other combinations are "0"), and the output V of the end detection circuit 36 time6 When the comparison result Q6 of the comparator 26 is "1" and the comparison result Q5 of the comparator 25 is "0", the output V of the completion detection circuit 36 ​​is time6 is input to timer 6 via the OR circuit OR.

[0075] The AND circuit AND7 receives an inverted signal of the comparison result Q6 of the comparator 26, and outputs V time7 When the comparison result Q6 of the comparator 27 is "0", the output V of the completion detection circuit 37 time7 is input to timer 6 via the OR circuit OR.

[0076] This causes the input analog potential A in is the reference potential V ref0If the input analog potential A exceeds the threshold, the selection circuit 8C selects the comparator 20, and the comparison operation time of the comparator 20 is measured by the timer 6. in is the reference potential V ref0 ~V ref1 In this case, the selection circuit 8C selects the comparator 21, and the comparison operation time of the comparator 21 is measured by the timer 6. in is the reference potential V ref1 ~V ref2 In this case, the selection circuit 8C selects the comparator 22, and the comparison operation time of the comparator 22 is measured by the timer 6. in is the reference potential V ref2 ~V ref3 In this case, the selection circuit 8C selects the comparator 23, and the comparison operation time of the comparator 23 is measured by the timer 6. in is the reference potential V ref3 ~V ref4 In this case, the selection circuit 8C selects the comparator 24, and the comparison operation time of the comparator 24 is measured by the timer 6. in is the reference potential V ref4 ~V ref5 In this case, the selection circuit 8C selects the comparator 25, and the comparison operation time of the comparator 25 is measured by the timer 6. in is the reference potential V ref5 ~V ref6 In this case, the selection circuit 8C selects the comparator 26, and the comparison operation time of the comparator 26 is measured by the timer 6. in is the reference potential V ref6 If the voltage Vcc is lower than 0.001V, the selection circuit 8C selects the comparator 27, and the timer 6 measures the comparison operation time of the comparator 27.

[0077] As shown in FIG. 11, the decoder circuit 7C is configured to convert the input analog potential Ain into a reference potential V ref0 ~V ref7 The decoder circuit 7C stores the correlation characteristics between the potential difference between the comparators 20 and 27 and the comparison operation time (measured value) in the comparators 20 to 27. *Using the correlation characteristics of the input analog potential A, calculated based on the measurement value count of timer 6 in The digital conversion value CODE is output.

[0078] As shown in FIG. 11, the decoder circuit 7C receives the input analog potential A in is the reference potential V ref* The area larger than the area X shown in Figure 7 * ) is used. In this case, comparator 2 * After identifying, the comparison result Q B* The digital conversion value CODE can be calculated based on the measured value count of the timer 6 without using the input analog potential A in is the reference potential V ref* The area smaller than the area Y * ) may be used alone.

[0079] (Fifth embodiment) Referring to FIG. 12, the AD converter 1D according to the fifth embodiment has a lower limit reference potential V REFL ~Upper reference potential V REFH between different reference potentials V ref0 ~V ref3 , V ref1 -V ref2 The intermediate potential V ref(1-2) and a voltage divider circuit 5D that generates an input analog potential A in and multiple reference potentials V ref0 ~V ref1 and a plurality of comparators 20 to 21 that respectively compare the input analog potential A in and the intermediate potential V ref1-2 Comparator 2 A and the input analog potential A in and multiple reference potentials V ref2 ~V ref3 and multiple comparators 2 that compare B0 ~2 B1 and a plurality of comparators 20 to 21, 2 B0 ~2 B1 A plurality of completion detection circuits 30 to 33 for detecting the completion of each comparison operation by the plurality of comparators 20 to 21, 2 B0 ~2B1 Timers 60 to 63 measure the comparison operation times of comparators 2 and 3, respectively. A and the count selected from count0 to count3 of each measurement value of timers 60 to 63 * and a plurality of comparators 20 to 21, 2 B2 ~2 B3 Comparison results Q0~Q1, Q2 B2 ~Q B3 Comparator 2 identified from * Comparison results Q * and a decoder circuit 7D that outputs a digital conversion value CODE based on the signal.

[0080] As in the AD converter 1A of the second embodiment, the comparators 20 to 23 are configured as CMOS SRAMs, and the power supplies (power supply voltage Vcc, ground voltage Vss) are used as the reference power supplies (upper reference potential V REFH , lower limit reference potential V REFL ) and the same single power supply, the input analog potential A in and the reference potential V ref3 If both of these are low, the P-channel MOS transistors P1 and P2 cannot be turned on sufficiently, and the circuit becomes unstable.

[0081] Therefore, the AD converter 1D receives the input analog potential A in In the low region, the comparator 2 having the structure of a PMOS type SRAM B0 ~2 B1 is used for AD conversion.

[0082] Comparator 2 B* As shown in FIG. 13, the circuit is configured by adding an N-channel MOS transistor NT0 that functions as a power switch 24 to a memory cell 23 of a general PMOS type SRAM. The gate of the N-channel MOS transistor NT0 is connected to a comparator 2 B* This is the start signal input terminal.

[0083] The memory cell 23 has N-channel MOS transistors NT1 and NT2 and P-channel MOS transistors PT1, PT2, PT3, and PT4.

[0084] The P-channel MOS transistor PT1 and the N-channel MOS transistor NT1 form a first CMOS inverter. The source of the N-channel MOS transistor NT1 is connected to the ground voltage Vss via the power switch 24, and the drain of the N-channel MOS transistor NT1 is connected to the drain of the P-channel MOS transistor PT1. The source of the P-channel MOS transistor PT1 is connected to the power supply voltage Vcc.

[0085] The P-channel MOS transistor PT2 and the N-channel MOS transistor NT2 form a second CMOS inverter. The source of the N-channel MOS transistor NT2 is connected to the ground voltage Vss via the power switch 24, and the drain of the N-channel MOS transistor NT2 is connected to the drain of the P-channel MOS transistor PT2. The source of the P-channel MOS transistor PT2 is connected to the power supply voltage Vcc.

[0086] The input of the first CMOS inverter, i.e., the gate of the P-channel MOS transistor PT1 and the gate of the N-channel MOS transistor NT1, is connected to the output of the second CMOS inverter, i.e., the connection point between the drain of the P-channel MOS transistor PT1 and the drain of the N-channel MOS transistor NT1, and the comparison result Q B* Inverted output Q B* - Comparator 2 outputs B* This is the inverting output terminal.

[0087] The input of the second CMOS inverter, i.e., the gate of the P-channel MOS transistor PT2 and the gate of the N-channel MOS transistor NT2, is connected to the output of the first CMOS inverter, i.e., the connection point between the drain of the P-channel MOS transistor PT2 and the drain of the N-channel MOS transistor NT2, and the comparison result QB* Comparator 2 outputs B* This is the output terminal of

[0088] The P-channel MOS transistor PT3 is connected in parallel with the P-channel MOS transistor PT1, and the gate of the P-channel MOS transistor PT3 is connected to a reference potential V ref* Comparator 2 to which B* This is the second input terminal of the

[0089] The P-channel MOS transistor PT4 is connected in parallel with the P-channel MOS transistor PT2, and the gate of the P-channel MOS transistor PT4 is connected to the input analog potential A in Comparator 2 to which B* This is the first input terminal of the

[0090] Referring to FIG. 14, comparators 20-21, 2 B0 ~2 B1 is the comparison operation time of the input analog potential A in and the reference potential V ref0 ~V ref3 The input analog potential A in and the reference potential V ref0 ~V ref3 The smaller the potential difference between the input analog potential A in The voltage dividing circuit 5D has a large change in comparison operation time with respect to the input analog potential A in The reference potential V ref0 ~V ref3 Generate.

[0091] In addition, all 2 B* When configured as in and the reference potential V ref0 If both of these are high, the N-channel MOS transistors NT1 and NT2 cannot be turned on sufficiently, and the circuit becomes unstable.

[0092] As shown in FIG. 14, comparators 20 to 21 and 2B0 ~2 B1 The correlation characteristics between the comparison operation time and the potential difference are different from those of the decoder circuit 7D. in and the intermediate potential V ref1-2 Comparator 2 to compare A The comparison result Q is output from A Based on this, comparators 20-21 and 2 B0 ~2 B1 Select either one of the following.

[0093] Comparator 2 A Comparison results Q A ="1" (high level Hi), the decoder circuit 7D detects the largest measured value count0 to count3 of the comparison operation times of the comparators 20 to 21. * Select the comparator with the longest comparison operation time, comparator 2 * Then, the decoder circuit 7D determines the value of the specified comparator 2 * Using the correlation characteristics of the specified comparator 2 * Comparison results Q * and the selected measurement count * A digital conversion value CODE of the input analog potential Ain is calculated based on the above.

[0094] The decoder circuit 7D detects the detected comparator 2 * Comparison results Q * If ="1" (high level Hi), the specified comparator 2 * Input analog potential A in is the reference potential V ref* (area X shown in Figure 14) * ) using the correlation characteristics of the input analog potential A corresponding to the selected comparison operation time (measurement value). in and calculate the input analog potential A in The digital conversion value CODE is calculated and output.

[0095] The decoder circuit 7 outputs the specified comparator 2 * Comparison results Q * If ="0" (low level), the specified comparator 2 *The input analog potential Ain is the reference potential V ref* The area smaller than the area Y * ) using the correlation characteristics of the input analog potential A corresponding to the selected comparison operation time (measurement value). in and calculate the input analog potential A in The digital conversion value CODE is calculated and output.

[0096] Comparator 2 A Comparison results Q A ="0" (low level), the decoder circuit 7D B0 ~2 B1 The largest measurement value among the comparison operation time measurement values ​​count2 to count3 is count * Select the comparator with the longest comparison operation time, comparator 2 B* Then, the decoder circuit 7D determines the value of the specified comparator 2 B* Using the correlation characteristics of the specified comparator 2 B* Comparison results Q B* and the selected measurement count * A digital conversion value CODE of the input analog potential Ain is calculated based on the above.

[0097] The decoder circuit 7D detects the detected comparator 2 B* Comparison results Q B* If ="1" (high level Hi), the specified comparator 2 B* Input analog potential A in is the reference potential V ref* (area X shown in Figure 14) B* ) using the correlation characteristics of the input analog potential A corresponding to the selected comparison operation time (measurement value). in and calculate the input analog potential A in The digital conversion value CODE is calculated and output.

[0098] The decoder circuit 7 outputs the specified comparator 2 B* Comparison results Q B* If ="0" (low level), the specified comparator 2 B* The input analog potential Ain is the reference potential Vref* The area smaller than the area Y B* ) using the correlation characteristics of the input analog potential A corresponding to the selected comparison operation time (measurement value). in and calculate the input analog potential A in The digital conversion value CODE is calculated and output.

[0099] In addition, comparator 2 A can be in any form, but comparator 2 A Comparators 20-21 and 22 are connected to each other so that the operation time of the B0 ~2 B1 Something that runs faster than

[0100] In addition, the AD converter 1D has comparators 20 to 21 and 2 B0 ~2 B1 In this way, when a plurality of comparators 2 of different types are used, it is necessary to select which type of comparator 2 to use for AD conversion. In this case, as in the AD converter 1B, the input analog potential A in Alternatively, the selection may be made based on a combination of the comparison result Q of each comparator 2 and the comparison operation time.

[0101] In the embodiment described above, one comparator 2 * is identified, and the identified comparator 2 * However, the digital conversion value CODE is calculated based on the comparison operation time of the multiple comparators 2. * is identified, and multiple comparators 2 * It is also possible to calculate the digital conversion value CODE based on the comparison operation time.

[0102] As described above, according to this embodiment, the input analog potential A in an analog-to-digital converter 1 that converts an input analog potential A into a digital conversion value CODE; in and the reference potential V refand a conversion circuit (TDC circuit 4) that measures the comparison operation time from when the comparator 2 starts the comparison operation until it ends, and outputs a digital conversion value CODE according to the measured comparison operation time and the comparison result Q by the comparator 2. This configuration allows AD conversion to be completed with one comparison operation and calculation processing of the result using one comparator 2, making it possible to provide a high-speed, small-sized AD converter 1. The AD converter 1 has a resolution of n bits (2 n -1) comparators and (2 n -1) Instead of requiring multiple reference potentials, only comparator 2 and a reference potential are required, allowing for a significant reduction in circuit area. Also, AD converter 1 does not need to have a sample-and-hold function or a large capacitance element for CDAC, as in a successive approximation type AD converter, allowing for a significant reduction in circuit area and eliminating the problem of current leakage in MOS transistors. Furthermore, AD converter 1 can be configured primarily with MOS transistors and diode elements, allowing for the benefits of process miniaturization.

[0103] Furthermore, according to this embodiment, the conversion circuit converts the input analog potential A in and the reference potential V ref Based on the correlation characteristics between the potential difference between the input and output terminals and the comparison operation time of the comparator 2, the digital conversion value CODE is calculated from the comparison operation time. With this configuration, by using a comparator 2 of a type in which the comparison operation time correlates with the potential difference between the input analog potential Vin and the reference potential Vref, AD conversion can be performed with high accuracy.

[0104] Furthermore, according to this embodiment, the input analog potential A in An analog-to-digital converter 1A converts an input analog potential A into a digital converted value. in and multiple different reference potentials V ref0 ~V ref3 and a comparator 20 selected from the plurality of comparators 20 to 23. *The decoder circuit 7A includes a conversion circuit that outputs a digital conversion value CODE according to the comparison operation time from when the comparison operation starts to when the comparison operation ends. This configuration allows AD conversion to be completed using a small number of comparators 2, with one comparison operation and calculation processing of the result, making it possible to provide a high-speed, small-sized AD converter 1.

[0105] Furthermore, according to this embodiment, the conversion circuit converts the input analog potential A in and the reference potential V ref0 ~V ref3 The correlation characteristics between the potential difference and the comparison operation time of the plurality of comparators 20 to 23 are stored. * Based on the correlation characteristics, a digital conversion value CODE is calculated from the comparison operation time. This configuration allows the input analog potential A in Therefore, it is possible to use the correlation characteristics in the region where the change in comparison operation time is large, and to perform AD conversion with high accuracy.

[0106] Furthermore, according to this embodiment, the conversion circuit determines whether comparator 2 is in a low-power state based on the comparison operation time. * Identify. This configuration allows for a maximum count * Comparator 2 * By specifying the input analog potential A in Therefore, it is possible to use the correlation characteristics in the region where the change in comparison operation time is large, and to perform AD conversion with high accuracy.

[0107] Furthermore, according to this embodiment, the conversion circuit (decoder circuit 7C) outputs the signal from comparator 20 based on the comparison results of the plurality of comparators 20 to 27. * Identify. This configuration allows for quick and simple configuration of comparator 2. * can be identified.

[0108] Furthermore, according to this embodiment, A in and the reference potential V ref0 ~V ref3The intermediate potential V ref(0-1) , V ref(1-2) , V ref(2-3) Comparator 2 functions as an intermediate potential comparator that compares A0 ~2 A2 The conversion circuit (decoder circuit 7B) includes a comparator 2 A0 ~2 A2 The comparator is identified based on the comparison result. This configuration allows for quick and simple configuration of comparator 2. * can be identified.

[0109] Furthermore, according to this embodiment, the plurality of comparators 20 to 21, 2 B0 ~2 B1 The converter circuit (decoder circuit 7D) is configured with a comparator 2 that functions as an intermediate potential comparator. A The type selected based on the comparison result (comparator 20-21 or 2 B0 ~2 B1 ) comparator *もしくはB* Identify. This configuration allows the use of different types of comparators 2, making it possible to prevent the comparators 2 from being used in an unstable region (potential), and to perform AD conversion with high precision.

[0110] Although the present invention has been described above with reference to specific embodiments, it goes without saying that the above embodiments are merely examples and can be modified and implemented without departing from the spirit of the present invention. [Explanation of symbols]

[0111] 1, 1A, 1B, 1C, 1D Analog-to-Digital Converter (AD Converter) 2, 20-27, 2 A , 2 A0 ~2 A2 , 2 B0 ~2 B1 Comparator 3. 30~37 End detection circuit 4 Time measurement circuit (TDC circuit) 5A, 5B, 5C, 5D Voltage divider circuit 6, 60-63 timer 7A, 7B, 7C, 7D decoder circuit 8B, 8C selection circuit 21, 23 memory cells 22, 24 Power switch N1 to N4, NT0 to NT2 N-channel MOS transistors P1 to P4, PT1 to PT4 P-channel MOS transistors

Claims

1. An analog-to-digital converter that converts an input analog potential into a digital converted value, a plurality of comparators for comparing the input analog potential with a plurality of different reference potentials; a conversion circuit that outputs the digital conversion value according to a comparison operation time from when the comparator specified from among the plurality of comparators starts to when the comparator finishes the comparison operation, The conversion circuit storing correlation characteristics between the potential difference between the input analog potential and the reference potential and the comparison operation times of the plurality of comparators, and calculating the digital conversion value from the comparison operation times based on the correlation characteristics of a selected comparator; The analog-to-digital converter is characterized in that the comparator is specified based on the comparison operation time.

2. An analog-to-digital converter that converts an input analog potential into a digital converted value, a plurality of comparators for comparing the input analog potential with a plurality of different reference potentials; a conversion circuit that stores a correlation characteristic between a comparison operation time from the start to the end of a comparison operation for each of the comparators and a potential difference between the input analog potential and the reference potential, and outputs the digital conversion value from the comparison operation time based on the correlation characteristic of the selected comparator; an intermediate potential comparator that compares the input analog potential with an intermediate potential between the plurality of reference potentials; Equipped with the conversion circuit identifies the comparator based on a comparison result of the intermediate potential comparator; The plurality of comparators are configured by a combination of different types, The analog-to-digital converter according to claim 1, wherein the conversion circuit specifies the selected type of the comparator based on a comparison result of the intermediate potential comparator.

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