Image sensor

Abstract

To improve the image quality of an image sensor.SOLUTION: According to one embodiment of the present invention, an image sensor includes a substrate including a first surface and a second surface facing each other, color filters disposed on the first surface of the substrate, a fence pattern interposed between the color filters, and a protection film disposed between the substrate and the color filter and covering the fence pattern. The fence pattern includes a first fence pattern including a first lower surface and a first upper surface that face each other, and a second fence pattern provided on the first upper surface of the first fence pattern and including a material different from the first fence pattern. The width of the first lower surface of the first fence pattern may be smaller than the width of the second fence pattern. The protection film can cover a side wall of the first fence pattern.SELECTED DRAWING: Figure 3B

Description

[Technical Field]

[0001] The present invention relates to image sensors, and more particularly to fence patterns for image sensors. [Background technology]

[0002] An image sensor is a device that converts an optical image into an electrical signal. Image sensors can be classified into CCD (Charge Coupled Device) and CMOS (Complementary Metal Oxide Semiconductor) types. CMOS image sensors are abbreviated as CIS (CMOS image sensor). The CIS has a number of pixels arranged two-dimensionally. Each pixel includes a photodiode (PD). The photodiode converts incident light into an electrical signal. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent Publication No. 2020 / 0083268 [Patent Document 2] U.S. Patent No. 10,091,439 Summary of the Invention [Problem to be solved by the invention]

[0004] The problem to be solved by the present invention is to improve the image quality of an image sensor.

[0005] The problems to be solved by the present invention are not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0006] An image sensor is provided. According to an embodiment of the present invention, the image sensor includes a substrate having a first surface and a second surface facing each other, color filters disposed on the first surface of the substrate, fence patterns interposed between the color filters, and a protective film disposed between the substrate and the color filters and covering the fence patterns. The fence patterns may include a first fence pattern having a first lower surface and a first upper surface facing each other, and a second fence pattern provided on the first upper surface of the first fence pattern and including a different material from the first fence pattern. A width of the first lower surface of the first fence pattern may be smaller than a width of the second fence pattern. The protective film may cover sidewalls of the first fence pattern.

[0007] According to an embodiment of the present invention, an image sensor includes a substrate having a first surface and a second surface facing each other and including a photoelectric conversion region, an isolation pattern provided between the photoelectric conversion regions within the substrate, a color filter disposed on the first surface of the substrate, and a fence pattern provided on the isolation pattern and disposed between the color filters, wherein the fence pattern includes a first fence pattern having a bottom surface and a top surface facing each other, and a second fence pattern provided on the top surface of the first fence pattern, wherein the width of the bottom surface of the first fence pattern is smaller than the width of the top surface, and the maximum width of the second fence pattern is 100% to 102% of the minimum width of the second fence pattern.

[0008] According to an embodiment of the present invention, an image sensor includes a substrate having first and second surfaces facing each other and including photoelectric conversion regions therein; separation patterns provided between the photoelectric conversion regions in the substrate; color filters disposed on the first surface of the substrate; fence patterns provided on the separation patterns and disposed between the color filters; a protection film interposed between the insulating layer and the color filters and covering sidewalls of the first fence pattern and sidewalls and a top surface of the second fence pattern; a microlens layer disposed on the color filters and the fence pattern; and a protection film between the color filters and the substrate. and a wiring layer disposed on the second surface of the substrate, the wiring layer including a lower insulating layer and a wiring structure, the lower insulating layer covering the gate pattern and the wiring structure being disposed in the lower insulating layer. The fence pattern may include a first fence pattern having a first lower surface and a first upper surface facing each other, and a second fence pattern provided on the first upper surface of the first fence pattern and including a different material from the first fence pattern, wherein a width of the first lower surface of the first fence pattern is smaller than a width of the first upper surface. [Effects of the Invention]

[0009] According to the present invention, the fence pattern may include a first fence pattern and a second fence pattern. A width of a lower surface of the first fence pattern may be smaller than a width of an upper surface of the first fence pattern. Therefore, more light may be incident on a photoelectric conversion region of the substrate. Image quality of the image sensor may be improved. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 2 is a circuit diagram of a pixel of the image sensor according to the embodiment. [Figure 2A] FIG. 1 is a plan view showing an image sensor according to an embodiment. [Figure 2B]This is a cross section taken along line II' in FIG. 2A. [Figure 3A] 2B is a plan view showing a pixel array region of the image sensor according to the embodiment, and is an enlarged view of region A of FIG. 2A. [Figure 3B] 3B is a cross-sectional view taken along line II-II' of FIG. 3A and an enlarged view of region B of FIG. 2B. [Figure 3C] This is an enlarged view of region C in FIG. 3B. [Figure 4A] 3B is a cross-sectional view showing a pixel array region of an image sensor according to an embodiment, which corresponds to a cross-section showing an enlarged view of region C in FIG. 3B. [Figure 4B] 3B is a cross-sectional view showing a pixel array region of an image sensor according to an embodiment, which corresponds to a cross-section showing an enlarged view of region C in FIG. 3B. [Figure 4C] 3B is a cross-sectional view showing a pixel array region of an image sensor according to an embodiment, which corresponds to a cross-section showing an enlarged view of region C in FIG. 3B. [Figure 4D] 3B is a cross-sectional view showing a pixel array region of an image sensor according to an embodiment, which corresponds to a cross-section showing an enlarged view of region C in FIG. 3B. [Figure 4E] 3B is a cross-sectional view showing a pixel array region of an image sensor according to an embodiment, which corresponds to a cross-section showing an enlarged view of region C in FIG. 3B. [Figure 5] 2 is a view illustrating a pixel array region of an image sensor according to an embodiment, and corresponds to a cross section taken along line II-II' of FIG. 3A. [Figure 6] 2B is a view illustrating an image sensor according to an embodiment, and corresponds to a cross section taken along line II' of FIG. 2A. DETAILED DESCRIPTION OF THE INVENTION

[0011] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An image sensor according to an embodiment of the present invention will now be described.

[0012] FIG. 1 is a circuit diagram of a pixel of an image sensor according to an embodiment.

[0013] 1, each pixel of the image sensor may include a photoelectric conversion region PD, a transfer transistor Tx, a source follower transistor Sx, a reset transistor Rx, and a selection transistor Ax, which may each include a transfer gate TG, a source follower gate SG, a reset gate RG, and a selection gate AG.

[0014] The photoelectric conversion region PD is a photodiode including an n-type impurity region and a p-type impurity region. The floating diffusion region FD can function as the drain of the transfer transistor Tx. The floating diffusion region FD can function as the source of the reset transistor RX. The floating diffusion region FD can be electrically connected to a source follower gate SG of the source follower transistor SX. The source follower transistor Sx is connected to a selection transistor AX.

[0015] The operation of the image sensor can be explained with reference to FIG. 1 as follows. First, with light blocked, a power supply voltage VDD is applied to the drain of the reset transistor RX and the drain of the source follower transistor SX, turning on the reset transistor RX to discharge the charge remaining in the floating diffusion region FD. Then, when the reset transistor Rx is turned off and external light is incident on the photoelectric conversion region PD, electron-hole pairs are generated in the photoelectric conversion region PD. The holes move to the p-type impurity region of the photoelectric conversion region PD, and the electrons move to the n-type impurity region and are stored there. When the transfer transistor Tx is turned on, the charge, such as the electrons and holes, is transferred to and stored in the floating diffusion region FD. The gate bias of the source follower transistor SX changes in proportion to the amount of stored charge, causing a change in the source potential of the source follower transistor SX. When the select transistor Ax is turned on, a signal corresponding to the charge is read out to the column line.

[0016] A wiring line may be electrically connected to at least one of the transfer gate TG, the source follower gate SG, the reset gate RG, and the select gate AG. The wiring line may be configured to apply a power supply voltage VDD to the drain of the reset transistor RX or the drain of the source follower transistor SX. The wiring line may include a column line connected to the select transistor AX. The wiring line is a first conductive structure 830, which will be described later with reference to FIGS. 2B and 3B.

[0017] 1 illustrates a pixel having one photoelectric conversion region PD and four transistors TX, RX, AX, and SX, but the present invention is not limited thereto. For example, a plurality of pixels may be provided, and the reset transistor RX, the source follower transistor SX, or the selection transistor AX may be shared by adjacent pixels. This may improve the integration density of the image sensor.

[0018] 2A is a plan view illustrating an image sensor according to an embodiment, and FIG 2B is a cross-sectional view taken along line II' in FIG 2A.

[0019] 2A and 2B, the image sensor may include a sensor chip 10. The sensor chip 10 may include a first substrate 100, a first wiring layer 800, an insulating layer 400, a protective film 470, a color filter CF, a fence pattern 300, and a microlens layer 500.

[0020] The first substrate 100 may include a pixel array region APS, an optical black region OB, and a pad region PAD in a plan view. The pixel array region APS may be disposed in a central portion of the first substrate 100 in a plan view. The pixel array region APS may include a plurality of pixel regions PX. The pixels described with reference to FIG. 1 may be formed in the pixel regions PX of the substrate 100. For example, pixel components may be provided in the pixel regions PX. The pixel regions PX may output photoelectric signals from incident light. The pixel regions PX may be arranged two-dimensionally in rows and columns. The rows may be parallel to a first direction D1, and the columns may be parallel to a second direction D2. In this specification, the first direction D1 may be parallel to a first surface 100a of the first substrate 100. The second direction D2 may be parallel to the first surface 100a of the first substrate 100 and may be different from the first direction D1. For example, the second direction D2 may be substantially perpendicular to the first direction D1. The third direction D3 may intersect the first direction D1 and the second direction D2. For example, the third direction D3 may be substantially perpendicular to the first surface 100a of the first substrate 100.

[0021] The pad area PAD may be provided at an edge portion of the first substrate 100 and may surround the pixel array area APS. A pad terminal 900 may be provided on the pad area PAD. The pad terminal 900 may output an electrical signal generated in the pixel area PX to the outside, or an external electrical signal or voltage may be transmitted to the pixel area PX through the pad terminal 900. Because the pad area PAD is provided at the edge portion of the first substrate 100, the second pad terminal 900 may be easily connected to the outside. For simplicity, the following description will be limited to a single pad terminal 900. The optical black area OB will be described later. The pixel array area APS of the sensor chip 10 of the image sensor will be described in more detail below.

[0022] 3A is a plan view showing a pixel array region of an image sensor according to an embodiment, and is an enlarged view of region A in FIG. 2A. FIG. 3B is a cross-sectional view taken along line II-II' in FIG. 3A and is an enlarged view of region B in FIG. 2B. FIG. 3C is an enlarged view of region C in FIG. 3B. Below, content that overlaps with what has been previously described will be omitted.

[0023] 3A, 3B, and 3C, the image sensor may include a first substrate 100, a first wiring layer 800, an isolation pattern 200, an insulating layer 400, a color filter CF, a fence pattern 300, and a microlens layer 500.

[0024] The first substrate 100 may have a first surface 100a and a second surface 100b facing each other. The first surface 100a of the first substrate 100 is a rear surface, and the second surface 100b is a front surface. Light may be incident on the second surface 100a of the first substrate 100. The substrate 100 may be a semiconductor substrate or an SOI (Silicon on Insulator) substrate. The semiconductor substrate may include, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The first substrate 100 may further include a Group 3 element. The Group 3 element is a first conductivity type impurity. The first substrate 100 may include a first conductivity type impurity to have the first conductivity type. For example, the first conductivity type impurity may include a P-type impurity such as aluminum (Al), boron (B), indium (In), and / or gallium (Ga). The first substrate 100 may have a plurality of pixel regions PX. As shown in FIG. 3B, the pixel region PX may include a first pixel region PX1 and a second pixel region PX2 adjacent to each other.

[0025] The first substrate 100 may include a photoelectric conversion region PD. The photoelectric conversion region PD may be interposed between the first surface 100a and the second surface 100b of the substrate 100. The photoelectric conversion region PD may be provided in each pixel region PX within the substrate 100. Each photoelectric conversion region PD may perform the same function and role as the photoelectric conversion region PD of FIG. 1. The photoelectric conversion region PD may further include a Group 5 element. The Group 5 element is a second conductive type impurity. The photoelectric conversion region PD is a region within the first substrate 100 doped with second conductive type impurities. The second conductive type impurities may have an opposite conductivity type to the first conductive type impurities. The second conductive type impurities may include n-type impurities such as phosphorus, arsenic, bismuth, and / or antimony. Each photoelectric conversion region PD may be disposed deep within the first surface 100a of the substrate 100.

[0026] The isolation pattern 200 may be provided in the first substrate 100 to define pixel regions PX. For example, the isolation pattern 200 may be provided between the pixel regions PX of the first substrate 100. The isolation pattern 200 is a pixel isolation pattern. The isolation pattern 200 may be provided in a first trench 201, which may be recessed from the second surface 100b of the first substrate 100. The isolation pattern 200 is a deep trench isolation film. The isolation pattern 200 may penetrate the first surface 100a of the first substrate 100. As shown in FIG. 3B, the width W11 of the upper surface of the isolation pattern 200 may be smaller than the width W12 of the lower surface of the isolation pattern 200. In this case, the upper surface of the isolation pattern 200 may be coplanar with the first surface 100a of the first substrate 100. The lower surface of the isolation pattern 200 may face the upper surface. The isolation pattern 200 may include a first isolation pattern 210 and a second isolation pattern 220. The first isolation pattern 210 may be provided along a sidewall of the first trench 201. The first isolation pattern 210 may include, for example, a silicon-based insulating material (e.g., silicon nitride, silicon oxide, and / or silicon oxynitride) and / or a high-k material (e.g., hafnium oxide and / or aluminum oxide). As another example, the first isolation pattern 210 may include multiple layers, each of which may include different materials. The first isolation pattern 210 may have a lower refractive index than the first substrate 100. Therefore, crosstalk between the pixel regions PX of the first substrate 100 may be prevented / reduced.

[0027] The second isolated pattern 220 may be provided within the first isolated pattern 210. The first isolated pattern 210 may be interposed between the second isolated pattern 220 and the first substrate 100. The second isolated pattern 220 may be separated from the first substrate 100 by the first isolated pattern 210. Therefore, the second isolated pattern 220 may be electrically isolated from the first substrate 100 during operation of the image sensor. The second isolated pattern 220 may include a crystalline semiconductor material, such as polysilicon. For example, the second isolated pattern 220 may further include a dopant, and the dopant may include impurities of a first conductivity type or impurities of a second conductivity type. For example, the second isolated pattern 220 may include doped polysilicon.

[0028] The color filters CF may be disposed on the pixel regions PX on the first surface 100a of the first substrate 100. For example, the color filters CF may be provided at positions corresponding to the photoelectric conversion regions PD. Each of the color filters CF may include one of a red filter, a blue filter, and a green filter. The color filters CF may form a color filter array. For example, the color filters CF may be arranged along a first direction D1 and a second direction D2 in a plan view.

[0029] A fence pattern 300 may be disposed on the separation pattern 200. For example, the fence pattern 300 may overlap the separation pattern 200 in a plan view. The fence pattern 300 may be interposed between two adjacent color filters CF to separate the color filters CF. For example, the fence pattern 300 may physically and optically separate a plurality of color filters CF from one another.

[0030] The fence pattern 300 may overlap the separation pattern 200 in a plan view. The fence pattern 300 may have a planar shape corresponding to the separation pattern 200. For example, the fence pattern 300 may have a grid shape as shown in FIG. 3A . In a plan view, the fence pattern 300 may surround each pixel region PX. For example, the fence pattern 300 may surround each color filter CF. The fence pattern 300 may include a first portion and a second portion. The first portion may extend parallel to a first direction D1 and be spaced apart from each other in a second direction D2. The second portions may extend parallel to the second direction D2. The second portions may be spaced apart from each other in the first direction D1. The second portions may be connected to the first portion.

[0031] 3B, the fence pattern 300 may include a first fence pattern 310 and a second fence pattern 320. The first fence pattern 310 may be disposed between the separation pattern 200 and the second fence pattern 320. The first fence pattern 310 may include a conductive material such as a metal and / or a metal nitride. For example, the first fence pattern 310 may include titanium and / or titanium nitride.

[0032] The second fence pattern 320 may be disposed on the first fence pattern 310. The second fence pattern 320 may include a different material from the first fence pattern 310. The second fence pattern 320 may include an organic material. The second fence pattern 320 may include a low refractive index material and have insulating properties. The second fence pattern 320 may have, for example, a rectangular cross section. The width of the bottom surface of the fence pattern 300 may be smaller than the width of the top surface of the fence pattern 300. Therefore, the amount of light incident on the first substrate 100 may be increased. The fence pattern 300 will be described in more detail in the description of FIG. 3C.

[0033] The insulating layer 400 may be interposed between the first substrate 100 and the color filter CF and between the separation pattern 200 and the fence pattern 300. The insulating layer 400 may cover the first surface 100a of the first substrate 100 and the upper surface of the separation pattern 200. The insulating layer 400 is a rear insulating layer. The insulating layer 400 may include a bottom antireflective coating (BARC) layer. The insulating layer 400 may include multiple layers, and the layers of the insulating layer 400 may have different functions.

[0034] The insulating layer 400, the color filter CF, the protective film 470, and the microlens layer 500 according to the embodiment will be described in more detail below.

[0035] 3B and 3C, the color filters CF are provided on the first surface 100a of the first substrate 100 and may be arranged side by side. The color filters CF may include a first color filter CF1 and a second color filter CF2 adjacent to each other. The first color filter CF1 and the second color filter CF2 may correspond to the first pixel region PX1 and the second pixel region PX2, respectively. For example, the first color filter CF1 and the second color filter CF2 may correspond to the first pixel region PX1 and the second pixel region PX2, respectively. The second color filter CF2 is a different type of color filter from the first color filter CF1. The second color filter CF2 is a color filter of a different color from the first color filter CF1. For example, the second color filter CF2 is one of a red filter, a blue filter, and a green filter, and the first color filter CF1 is the other of a red filter, a blue filter, and a green filter. Alternatively, the second color filter CF2 may be the same type of color filter as the first color filter CF1.

[0036] The fence pattern 300 may be interposed between the color filters CF on the insulating layer 400. The fence pattern 300 may vertically overlap the separation pattern 200. In this specification, "vertical" may mean aligned with the third direction D3 or the opposite direction to the third direction D3. External light may be incident on the first surface 100a of the first substrate 100 through the microlens layer 500 and the color filters CF. At this time, the light may be incident in a direction oblique to the first surface 100a of the first substrate 100. The fence pattern 300 may prevent light incident on the first color filter CF1 from being transmitted to the photoelectric conversion region PD of the second pixel region PX2. Similarly, the fence pattern 300 may prevent light incident on the second color filter CF2 from being transmitted to the photoelectric conversion region PD of the first pixel region PX1. Therefore, crosstalk between the pixel regions PX of the image sensor may be reduced.

[0037] The fence pattern 300 may include a first fence pattern 310 and a second fence pattern 320. The first fence pattern 310 may have a first bottom surface 310b, a first sidewall 310c, and a first top surface 310a. The first bottom surface 310b of the first fence pattern 310 may correspond to the bottom surface of the fence pattern 300. The first top surface 310a of the first fence pattern 310 may face the first bottom surface 310b. The first sidewall 310c may connect an edge of the first top surface 310a to an edge of the first bottom surface 310b. The first sidewall 310c may be inclined with respect to the first bottom surface 310b. The first fence pattern 310 may function as a barrier layer. According to the embodiment, charges may be trapped at the interface between the first substrate 100 and the insulating layer 400. A first lower surface 310b of the first fence pattern 310 contacts the insulating layer 400, allowing the first fence pattern 310 to remove the trapped charge. The first fence pattern 310 functions as an adhesive layer, allowing the second fence pattern 320 to be well attached to the insulating layer 400 through the first fence pattern 310.

[0038] If the width of the fence pattern 300 is excessively large, externally incident light may be absorbed or reflected by the fence pattern 300 and not be transmitted to the first substrate 100. As the area of ​​the lower surface of the fence pattern 300 increases, the amount of light incident on the first substrate 100 may decrease. According to the embodiment, the first lower surface 310b of the first fence pattern 310 may have a relatively small width W1. The width W1 of the first lower surface 310b of the first fence pattern 310 may be smaller than the width W3 of the first upper surface 310a. The width W1 of the first lower surface 310b of the first fence pattern 310 is approximately 45 nm to 55 nm. When the first lower surface 310b of the first fence pattern 310 has a width W1 of 55 nm or less, the amount of light incident on each pixel region PX of the first substrate 100 may be increased. For example, the amount of light incident on each photoelectric conversion region PD of the first substrate 100 may be increased. Since the width W1 of the first lower surface 310b of the first fence pattern 310 is 45 nm or more, the first fence pattern 310 can prevent crosstalk between the pixel regions PX. The width W1 of the first lower surface 310b of the first fence pattern 310 may be smaller than the width W11 of the upper surface of the isolation pattern 200.

[0039] As another example, the width W3 of the first upper surface 310a of the first fence pattern 310 may be substantially the same as the width W11 of the upper surface of the separation pattern 211.

[0040] As another example, the width W1 of the first lower surface 310b of the first fence pattern 310 may be substantially the same as the width W3 of the first upper surface 310a of the first fence pattern 310.

[0041] The first fence pattern 310 may have, for example, an hourglass shape. For example, the first fence pattern 310 may include a lower portion, a middle portion, and an upper portion. The lower portion of the first fence pattern 310 may include a first lower surface 310b. The upper portion of the first fence pattern 310 may include a first upper surface 310a. The middle portion of the first fence pattern 310 may be provided between the lower portion and the upper portion. The width of the middle portion of the first fence pattern 310 may be smaller than the width W1 of the first lower surface 310b and the width W3 of the first upper surface 310a of the first fence pattern 310. For example, the minimum width of the second fence pattern 320 is measured at a position higher than the first lower surface 310b and lower than the first upper surface 310a.

[0042] The second fence pattern 320 may be disposed on the first upper surface 310a of the first fence pattern 310. The second fence pattern 320 may have a second lower surface and a second upper surface 320a facing each other. The second lower surface of the second fence pattern 320 may be in physical contact with the first upper surface 310a of the first fence pattern 310. The edge portion of the first upper surface 310a of the first fence pattern 310 may not be covered by the second fence pattern 320.

[0043] The width W2 of the second fence pattern 320 may be smaller than the width W3 of the first upper surface 310a of the first fence pattern 310 and larger than the width W1 of the first lower surface 310b. For example, the width W2 of the second fence pattern 320 may be 72 nm to 88 nm. Unless otherwise specified herein, the width W2 of the second fence pattern 320 may refer to the width of the second lower surface 320b of the second fence pattern 320. Because the width W2 of the second fence pattern 320 is 72 nm or more, the second fence pattern 320 can sufficiently prevent crosstalk between the color filters CF and between the pixel regions PX of the first substrate 100. Because the width W2 of the second fence pattern 320 is 88 nm or less, the amount of light incident on each pixel region PX of the first substrate 100 can be increased. The width W3 of the second fence pattern 320 may be substantially the same as or similar to the width W11 of the upper surface of the separation pattern 200.

[0044] The second upper surface 320a of the second fence pattern 320 may correspond to the upper surface of the fence pattern 300. The width of the second upper surface 320a of the second fence pattern 320 may be substantially the same as the width of the second lower surface 320b of the second fence pattern 320. For example, the width of the second upper surface 320a of the second fence pattern 320 is 72 nm to 88 nm.

[0045] If the width of the second fence pattern 320 is non-uniform, the structural stability of the second fence pattern 320 may be reduced, or incident light may be reflected externally by the second fence pattern 320. According to an embodiment, the width W2 of the second fence pattern 320 may be uniform along the vertical level. For example, the width of the second upper surface 320a of the second fence pattern 320 may be substantially the same as the width of the second lower surface 320b of the second fence pattern 320. The maximum and minimum widths of the second fence pattern 320 may each satisfy the condition of 72 nm to 88 nm. The maximum width of the second fence pattern 320 is 100% to 102% of the minimum width. Therefore, the structural stability of the second fence pattern 320 is improved, and the amount of light incident on the pixel region PX of the first substrate 100 may be increased.

[0046] The height H2 of the second fence pattern 320 may be greater than the height H1 of the first fence pattern 310.

[0047] The second fence pattern 320 may include a low refractive index material. The refractive index of the second fence pattern 320 may be lower than that of the first substrate 100. For example, the refractive index of the second fence pattern 320 is approximately 1.3 or less. As shown in FIG. 3C, the second fence pattern 320 may include polymer structures 321 and nanoparticles 323 within the polymer structures 321. The nanoparticles 323 may be dispersed within the polymer structures 321. For example, the nanoparticles 323 may be spaced apart. The nanoparticles 323 may include silica. Light may be reflected by the interface between the polymer structures 321 and the nanoparticles 323. Therefore, the second fence pattern 320 may have a low refractive index. The second fence pattern 320 may effectively prevent crosstalk between the color filters CF and optical interference between the pixel regions PX of the first substrate 100. Hereinafter, for simplicity's sake, the polymer structures 321 and the nanoparticles 323 are not separately illustrated in the drawings except for FIG. 3C.

[0048] The insulating layer 400 may be interposed between the separation pattern 200 and the fence pattern 300 and between the first substrate 100 and the color filter CF. The insulating layer 400 may include a first insulating layer 410, a second insulating layer 420, a third insulating layer 430, a fourth insulating layer 440, and a fifth insulating layer 450 stacked on the first surface 100a of the substrate 100. The first insulating layer 410 may contact the first surface 100a of the first substrate 100 and the upper surface of the separation pattern 200 and overlap the pixel region PX of the first substrate 100. The second insulating layer 420 may be disposed on the upper surface of the first insulating layer 410. The first insulating layer 410 and the second insulating layer 420 are fixed charge layers. Each of the fixed charge layers may be made of a metal oxide layer or a metal fluoride layer. The metal oxide layer contains a less-than-stoichiometric amount of oxygen, and the metal fluoride layer contains a less-than-stoichiometric amount of fluorine. For example, the first insulating layer 410 may be made of a metal oxide or metal fluoride containing at least one metal selected from the group consisting of hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium, and lanthanides. The second insulating layer 420 may include a metal oxide or metal fluoride as described above for the first insulating layer 410. However, the second insulating layer 420 may include a different material from the first insulating layer 410. For example, the first insulating layer 410 may include aluminum oxide, and the second insulating layer 420 may include hafnium oxide. Each of the first insulating layer 410 and the second insulating layer 420 has a negative fixed charge, which may cause hole accumulation. The first insulating layer 410 and the second insulating layer 420 can effectively reduce dark current and white spots in the first substrate 100. The thickness of the second insulating layer 420 can be greater than the thickness of the first insulating layer 410.

[0049] The third insulating layer 430 may be disposed on the second insulating layer 420. The third insulating layer 430 may include a first silicon-containing material. The first silicon-containing material may include tetraethylorthosilicate (TEOS) or silicon oxide. The third insulating layer 430 may have good filling properties. For example, the third insulating layer 430 may be formed by plasma enhanced CVD, but is not limited thereto. The thickness of the third insulating layer 430 may be greater than the thickness of the first insulating layer 410 and greater than the thickness of the second insulating layer 420.

[0050] A fourth insulating layer 440 may be disposed on the third insulating layer 430. The fourth insulating layer 440 may include a different material from the third insulating layer 430. The fourth insulating layer 440 may include a second silicon-containing material, which may be different from the first silicon-containing material. For example, the fourth insulating layer 440 may include silicon nitride. The thickness of the fourth insulating layer 440 may be greater than the thickness of the third insulating layer 430.

[0051] The fifth insulating layer 450 may be disposed between the fourth insulating layer 440 and the first fence pattern 310 and between the fourth insulating layer 440 and the color filter CF. The fifth insulating layer 450 may be in physical contact with the first lower surface 310b of the first fence pattern 310. The fifth insulating layer 450 may be an adhesive film or a capping film. The fifth insulating layer 450 may include a high-dielectric material or a metal oxide. The fifth insulating layer 450 may include the same material as the second insulating layer 420. For example, the fourth insulating layer 440 may include hafnium oxide. The thickness of the fifth insulating layer 450 may be greater than the thicknesses of the first insulating layer 410 and the second insulating layer 420, but less than the thicknesses of the third insulating layer 430 and the fourth insulating layer 440. The thickness of the insulating layer 400 may refer to the sum of the thicknesses of the first to fifth insulating layers 410, 420, 430, 440, and 450.

[0052] The number of layers of the insulating layer 400 may be variously modified. For example, at least one of the first to fifth insulating layers 410, 420, 430, 440, and 450 may be omitted.

[0053] The protective film 470 may cover the upper surface of the insulating layer 400, the sidewalls of the fence pattern 300, and the upper surface of the fence pattern 300. For example, the protective film 470 may conformally cover the first sidewall 310c of the first fence pattern 310, the second sidewall 320 of the second fence pattern 320, and the second upper surface 320a of the second fence pattern 320. For example, the thickness of the protective film 470 on the first sidewall 310c of the first fence pattern 310 may be substantially the same as the thickness of the protective film 470 on the second upper surface 320a of the second fence pattern 320. The protective film 470 may be in physical contact with a portion of the first upper surface 310a of the first fence pattern 310. For example, the protective film 470 may cover an edge portion of the first upper surface 310a of the first fence pattern 310. The thickness of the protective film 470 may be less than the thickness of the insulating layer 400. The protective film 470 may include a high-dielectric material and have insulating properties. For example, the protective layer 470 may include aluminum oxide or hafnium oxide. Specifically, the protective layer 470 may include, but is not limited to, aluminum oxide. The protective layer 470 may protect the photoelectric conversion region PD of the first substrate 100 from external environmental factors such as moisture.

[0054] The color filters CF may be laterally spaced apart from each other on the protective film 470. The sidewalls of the fence pattern 300 may include a first sidewall and a second sidewall facing each other. The first color filter CF1 and the second color filter CF2 may be disposed on the first sidewall and the second sidewall of the fence pattern 300, respectively. The color filters CF may not extend onto the second upper surface 320a of the second fence pattern 320.

[0055] 3B and 3C, the top surface CFa of each color filter CF may be convex upward. For example, as shown in FIG. 3B, the top surface CFa of each color filter CF may have a center portion and an edge portion. The level of the center portion of the top surface CFa of each color filter CF is higher than the level of the edge portion. However, the shape of the color filter CF is not limited thereto. In this specification, "level" may refer to a vertical level. The level difference between the two surfaces may be measured in a third direction D3.

[0056] The microlens layer 500 may be disposed on the first surface 100a of the first substrate 100. For example, the microlens layer 500 may be disposed on the color filter CF and the fence pattern 300. A protective film 470 may be interposed between the second upper surface 320a of the second fence pattern 320 and the microlens layer 500.

[0057] The microlens layer 500 may include a planarized portion 520 and a lens portion 510. The lens portion 510 may be provided at a position corresponding to the photoelectric conversion region PD of the first substrate 100. For example, the lens portion 510 may be provided on the color filter CF and correspond to the color filter CF. The lens portions 510 may form an array arranged along a first direction D1 and a second direction D2 in a plan view. Each of the lens portions 510 may protrude away from the first surface 100a of the first substrate 100. Each of the lens portions 510 may have a hemispherical cross section. The lens portions 510 may condense incident light.

[0058] The planarizing portion 520 of the microlens layer 500 may be interposed between the color filter CF and the lens portion 510 and between the fence pattern 300 and the lens portion 510. The planarizing portion 520 may be integrally formed with the lens portion 510 and connected without an interface. The planarizing portion 520 may include the same material as the lens portion 510. As another example, the planarizing portion 520 may be omitted, and the lens portions 510 of the microlens layer 500 may not be connected to each other.

[0059] The microlens layer 500 is transparent, allowing light to pass through. The microlens layer 500 may include an organic material such as a polymer. For example, the microlens layer 500 may include a photoresist material or a thermosetting resin.

[0060] The image sensor may further include a lens coating layer 530. The lens coating layer 530 may be transparent. The lens coating layer 530 may conformally cover the upper surface of the microlens layer 500. The lens coating layer 530 may protect the microlens layer 500.

[0061] As shown in FIG. 3B, the first substrate 100 may include impurity regions 111. The impurity regions 111 may be disposed in the pixel regions PX within the first substrate 100. The impurity regions 111 may be disposed adjacent to the second surface 100b of the first substrate 100. The bottom surface of the impurity regions 111 may be separated from the photoelectric conversion region PD. The impurity regions 111 are regions doped with impurities of a second conductivity type (e.g., N-type impurities). The impurity regions 111 are active regions. In this case, the active region may refer to a region for operating a transistor and may include the floating diffusion region FD and source / drain regions of the transistor, as described with reference to FIG. 1. The transistor may include the transfer transistor Tx, source follower transistor Sx, reset transistor Rx, or selection transistor Ax, as described with reference to FIG. 1.

[0062] An isolation pattern 240 may be provided in the first substrate 100. The isolation pattern 240 may define an active region. Specifically, in each pixel region PX, the isolation pattern 240 may define an impurity region 111, and the impurity regions 111 may be isolated from each other by the isolation pattern 240. For example, the isolation pattern 240 may be disposed on one side of the impurity region 111 in the first substrate 100. The isolation pattern 240 may be provided in a second trench, and the second trench may be recessed from the second surface 100b of the first substrate 100. The isolation pattern 240 may be a shallow isolation STI layer. For example, the height of the isolation pattern 240 may be smaller than the height of the isolation pattern 200. A portion of the isolation pattern 240 may be connected to a sidewall of the first isolation pattern 210. The isolation pattern 240 may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0063] A gate pattern 700 may be disposed on the second surface 100b of the first substrate 100. The gate pattern 700 may function as a gate electrode of the transfer transistor Tx, source follower transistor Sx, reset transistor Rx, or selection transistor Ax described above in FIG. 1. For example, the gate pattern 700 may include a transfer gate TG, a source follower gate SG, a reset gate RG, or a selection gate AG. For simplicity, FIG. 3B illustrates a single gate pattern 700 disposed on each pixel region PX, but multiple gate patterns 700 may be disposed on each pixel region PX. For simplicity, the following description will be limited to a single gate pattern 700.

[0064] The gate pattern 700 may have a recessed gate structure. For example, the gate pattern 700 may include a first portion 710 and a second portion 720. The first portion 710 of the gate pattern 700 may be disposed on the second surface 100b of the first substrate 100. The second portion 720 of the gate pattern 700 may protrude into the first substrate 100. The second portion 720 of the gate pattern 700 may be connected to the first portion 710. Unlike what is shown, the gate pattern 700 may have a planar gate structure. In this case, the gate pattern 700 may not include the second portion 720. The gate pattern 700 may include a metal material, a metal silicide material, polysilicon, or a combination thereof. In this case, the polysilicon may include doped polysilicon.

[0065] A gate insulating pattern 740 may be interposed between the gate pattern 700 and the first substrate 100. The gate insulating pattern 740 may include, for example, a silicon-based insulating material (e.g., silicon oxide, silicon nitride, and / or silicon oxynitride) and / or a high-k material (e.g., hafnium oxide and / or aluminum oxide).

[0066] A first wiring layer 800 may be disposed on the second surface 100b of the first substrate 100. The first wiring layer 800 may include a first lower insulating layer 810, a second lower insulating layer 820, and a first conductive structure 830. The first lower insulating layer 810 may cover the second surface 100b of the first substrate 100 and the gate pattern 700. The second lower insulating layer 820 may be stacked on the first lower insulating layer 810. The first and second lower insulating layers 810 and 820 may include a silicon-based insulating material such as, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0067] A first conductive structure 830 may be provided in the lower insulating layers 810 and 820. The first conductive structure 830 may include a contact plug portion, a wiring portion, and a via portion. The contact plug portion may be provided in the first lower insulating layer 810 and electrically connected to one of the impurity region 111 and the gate pattern 700. The wiring portion of the first conductive structure 830 may be interposed between two adjacent lower insulating layers 810 and 820. The wiring portion may be connected to the contact plug portion. The via portion of the first conductive structure 830 may penetrate at least one of the second lower insulating layers 820 and be connected to the wiring portion. The first conductive structure 830 may transmit a photoelectric signal output from the photoelectric conversion region PD.

[0068] The fence pattern according to the embodiment will be described below.

[0069] 4A to 4E are cross-sectional views illustrating a pixel array region of an image sensor according to an embodiment, each of which corresponds to an enlarged cross-section of region C in FIG. 3B. Hereinafter, a description will be given with reference to both FIGS. 3A and 3B.

[0070] 4A to 4E, the image sensor may include a first substrate 100, a separation pattern 200, an insulating layer 400, a fence pattern 300, a protective film 470, a color filter CF, and a microlens layer 500. The fence pattern 300 may include a first fence pattern 310 and a second fence pattern 320. The first fence pattern 310 and the second fence pattern 320 may be substantially the same as those described with reference to FIGS. 3A to 3C. For example, the width W1 of the first lower surface 310b of the first fence pattern 310 and the width W2 of the second fence pattern 320 may satisfy the conditions described with reference to FIGS. 3A to 3C. However, the shape of the fence pattern 300 may be variously modified.

[0071] 4A, the first fence pattern 310 may have an inverted trapezoidal cross section. A width W1 of a first lower surface 310b of the first fence pattern 310 is the minimum width of the first fence pattern 310, and a width W3 of a first upper surface 310a of the first fence pattern 310 is the maximum width of the first fence pattern 310. The width of the first fence pattern 310 may decrease from the first upper surface 310a to the first lower surface 310b.

[0072] As shown in FIG. 4B, the first fence pattern 310 may include a lower portion and an upper portion. The lower portion of the first fence pattern 310 may have a rectangular cross section. The first lower surface 310b of the first fence pattern 310 is the lower surface of the lower portion. The width of the lower portion of the first fence pattern 310 may be substantially uniform. The upper portion of the first fence pattern 310 may have an inverted trapezoidal shape. The width of the upper portion of the first fence pattern 310 may gradually increase toward the first upper surface 310a of the first fence pattern 310. The first upper surface 310a of the first fence pattern 310 may correspond to the upper surface of the upper portion. The upper portion of the first fence pattern 310 may include the same material as the lower portion and may be connected without a boundary surface.

[0073] 4C, the width W3' of the first top surface 310a of the first fence pattern 310 may be substantially the same as the width W2 of the second fence pattern 320. For example, the width W3' of the first top surface 310a of the first fence pattern 310 may be 72 nm to 88 nm. Contrary to what is shown in the figure, the width W3' of the first top surface 310a of the first fence pattern 310 may be smaller than the width W2 of the second fence pattern 320.

[0074] Referring to FIG. 4D, the width W1 of the first lower surface 310b of the first fence pattern 310 may be substantially the same as the width W11 of the upper surface of the separation pattern 200.

[0075] 4E, the width W1 of the first lower surface 310b of the first fence pattern 310 may be greater than the width W11 of the upper surface of the separation pattern 200. Therefore, a portion of the first lower surface 310b of the first fence pattern 310 may vertically overlap the first surface 100a of the first substrate 100.

[0076] 4A to 4E, the first substrate 100, isolation pattern 200, insulating layer 400, fence pattern 300, protective film 470, color filter CF, and microlens layer 500 may be substantially the same as those described in the examples of Figures 3A to 3C. Although not shown, the first substrate 100 may further include an isolation pattern 240 and an impurity region 111 as described in the examples of Figures 3A to 3C, and the image sensor may further include a first wiring layer 800, a gate pattern 700, and a gate insulating pattern 740.

[0077] FIG. 5 is a view illustrating a pixel array region of an image sensor according to an embodiment, and corresponds to a cross section taken along line II-II' of FIG. 3A and an enlarged view of region B of FIG. 2B.

[0078] Referring to FIG. 5, the image sensor may include a first substrate 100, an isolation pattern 200', an insulating layer 400, a fence pattern 300, a protective film 470, a color filter CF, and a microlens layer 500.

[0079] The separation pattern 200' may be provided in the first substrate 100. The separation pattern 200' may be provided in a first trench 201', and the first trench 201' may penetrate the first surface 100a of the first substrate 100. The bottom surface of the first trench 201' may be provided in the first substrate 100. The bottom surface of the separation pattern 200' may be spaced apart from the second surface 100b of the first substrate 100. The top surface of the separation pattern 200' may be disposed at substantially the same level as the first surface 100a of the first substrate 100. The width W11 of the top surface of the separation pattern 200' may be greater than the width W12 of the bottom surface of the separation pattern 200'. The width of the separation pattern 200' may gradually decrease toward the second surface 100b of the substrate 100. The separation pattern 200' may include a first separation pattern 210, but may not include the second separation pattern 220 described in FIGS. 3A and 3B.

[0080] An isolation region 120 may be provided in the first substrate 100. The isolation region 120 may be provided between the lower surface of the isolation pattern 200' and the second surface 100b of the first substrate 100. The isolation region 120 may include a Group III element. For example, the isolation region 120 is a region doped with impurities of a first conductivity type (e.g., p-type). The isolation region 120 may define a pixel region PX together with the isolation pattern 200'. Unlike what is shown, the isolation pattern 200' may further penetrate the second surface 100b of the first substrate 100.

[0081] According to an embodiment, the examples of Figures 3A to 3C, 4A, 4B, 4C, 4D, 4E, and 5 may be combined with each other. For example, first fence pattern 310 may have an hourglass shape as described in the example of Figure 3C, and width W1 of first lower surface 310b of first fence pattern 310 may be greater than width W11 of the upper surface of separation pattern 200 as described in the example of Figure 4E.

[0082] The circuit chip 20 of the image sensor and the optical black area OB and pad area PAD of the first substrate 100 will now be described.

[0083] 2A and 2B, the optical black area OB of the first substrate 100 may be interposed between the pixel array area APS and the pad area PAD. The optical black area OB may include a first reference pixel area RPX1 and a second reference pixel area RPX2. The first reference pixel area RPX1 may be disposed between the second reference pixel area RPX2 and the pixel array area APS. In the optical black area OB, a photoelectric conversion area PD may be provided in the first reference pixel area RPX1. The photoelectric conversion area PD of the first reference pixel area RPX1 may have the same plane area and volume as the photoelectric conversion area PD of the pixel area PX. The photoelectric conversion area PD may not be provided in the second reference pixel area RPX2.

[0084] The impurity regions 111, the gate patterns 700, and the device isolation patterns 240 may be disposed in each of the first and second reference pixel regions RPX1 and RPX2, respectively. The impurity regions 111, the gate patterns 700, and the device isolation patterns 240 are the same as those described with reference to FIG. 3B.

[0085] The insulating layer 400 may extend over the optical black area OB and the pad area PAD of the first substrate 100 and cover the first surface 100 a of the first substrate 100 .

[0086] The light-shielding film 950 may be provided on the first surface 100a of the optical black area OB of the first substrate 100. The light-shielding film 950 may be disposed on the upper surface of the insulating layer 400. The light-shielding film 950 prevents light from being incident on the photoelectric conversion area PD of the optical black area OB. The pixels of the first and second reference pixel areas RPX1 and RPX2 in the optical black area OB do not output photoelectric signals but may output noise signals. The noise signals may be generated by electrons generated by heat generation, dark current, or the like. Since the light-shielding film 950 does not cover the pixel array area APS, light may be incident on the photoelectric conversion area PD in the pixel array area APS. The noise signals may be removed from the photoelectric signals output from the pixel area PX. The light-shielding film 950 may include a metal such as tungsten, copper, aluminum, or an alloy thereof.

[0087] In the optical black area OB of the first substrate 100, a first conductive pattern 911 may be disposed between the insulating layer 400 and the light-shielding film 950. The first conductive pattern 911 may serve as a barrier layer or an adhesive layer. The first conductive pattern 911 may include metal and / or metal nitride. For example, the first conductive pattern 911 may include titanium and / or titanium nitride. The first conductive pattern 911 may not extend onto the pixel array area APS of the first substrate 100.

[0088] In the optical black area OB of the first substrate 100, a contact plug 960 may be provided on the first surface 100a of the first substrate 100. The contact plug 960 may be disposed in the insulating layer 400 and on an upper surface of an outermost portion of the isolation pattern 200. The outermost portion of the isolation pattern 200 may be adjacent to the pad area PAD. A contact trench may be formed on the first surface 100a of the first substrate 100, and the contact plug 960 may be provided in the contact trench. The contact plug 960 may include a different material from the light-shielding layer 950. For example, the contact plug 960 may include a metal material such as aluminum. The first conductive pattern 911 may extend between the contact plug 960 and the insulating layer 400 and between the contact plug 960 and the isolation pattern 200. The contact plug 960 may be electrically connected to the second isolation pattern 220 through the first conductive pattern 911. Therefore, a negative bias voltage may be applied to the second isolation pattern 220.

[0089] In the optical black region OB of the first substrate 100, a protective insulating layer 471 may be disposed on the upper surface of the light-blocking layer 950 and the upper surface of the contact plug 960. The protective insulating layer 471 may include the same material as the protective layer 470 and may be connected to the protective layer 470. The protective insulating layer 471 may be formed integrally with the protective layer 470. As another example, the protective insulating layer 471 may be formed in a separate process from the protective layer 470 and may be separated from the protective layer 470. The protective insulating layer 471 may include a high-dielectric material (e.g., aluminum oxide and / or hafnium oxide).

[0090] A filtering film 550 may be further disposed on the first surface 100a of the optical black region OB. The filtering film 550 may cover the upper surface of the protective insulating film 471. The filtering film 550 may block light of a different wavelength than the color filter CF. For example, the filtering film 550 may block infrared light. The filtering film 550 may include, but is not limited to, a blue color filter.

[0091] The organic film 501 may be disposed on the upper surface of the filtering film 550 in the optical black area OB. The organic film 501 may be transparent. The upper surface of the organic film 501 faces the first substrate 100 and may be substantially flat. The organic film 501 may include, for example, a polymer. The organic film 501 may have insulating properties. Unlike what is shown in the figure, the organic film 501 may be connected to the microlens layer 500. The organic film 501 may include the same material as the microlens layer 500.

[0092] A coating layer 531 may be provided on the organic film 501. The coating layer 531 may conformally cover the upper surface of the organic film 501. The coating layer 531 may include an insulating material and may be transparent. The coating layer 531 may include the same material as the lens coating layer 530.

[0093] The first wiring layer 800 covers the second surface 100b of the first substrate 100 and may be provided on the pixel array region APS, the optical black region OB, and the pad region PAD of the first substrate 100.

[0094] The image sensor may further include a circuit chip 20. The circuit chip 20 may be stacked on the sensor chip 10. The circuit chip 20 may include a second wiring layer 1800 and a second substrate 1000. The second wiring layer 1800 may be interposed between the first wiring layer 800 and the second substrate 1000. An integrated circuit 1700 may be disposed on the upper surface of the second substrate 1000 or within the second substrate 1000. The integrated circuit 1700 may include a logic circuit, a memory circuit, or a combination thereof. The integrated circuit 1700 may include, for example, a transistor. The second wiring layer 1800 may include a third lower insulating layer 1820 and a second conductive structure 1830. The second conductive structure 1830 may be provided between the third lower insulating layer 1820 or within the third lower insulating layer 1820. The second conductive structure 1830 may be electrically connected to the integrated circuit 1700. The second wiring layer 1800 may further include a via pattern, which may connect to a second conductive structure 1830 within the third lower insulating layer 1820. Hereinafter, for simplicity, a single second conductive structure 1830 will be described.

[0095] The configuration on the pad area PAD of the first substrate 100 will now be described.

[0096] The pad terminals 900 may be disposed on the pad region PAD of the first substrate 100. The pad terminals 900 may be disposed on the first surface 100a of the first substrate 100. The pad terminals 900 may be embedded in the first substrate 100. For example, a pad trench 990 may be formed on the first surface 100a of the pad region PAD of the first substrate 100, and the pad terminals 900 may be provided in the pad trench 990. The pad terminals 900 may include metals such as aluminum, copper, tungsten, titanium, tantalum, or alloys thereof. During the mounting process of the image sensor, bonding wires may be formed on the pad terminals 900 to connect to the pad terminals 900. The pad terminals 900 may be electrically connected to an external device through the bonding wires.

[0097] The first through hole 901 may be disposed on a first side of the pad terminal 900. The first through hole 901 may be provided between the pad terminal 900 and the contact plug 960. The first through hole 901 may penetrate the insulating layer 400, the first substrate 100, and the first wiring layer 800. The first through hole 901 may further penetrate at least a portion of the second wiring layer 1800. The first through hole 901 may have a first bottom surface and a second bottom surface. The first bottom surface of the first through hole 901 may expose the first conductive structure 830. The second bottom surface of the first through hole 901 may be disposed at a lower level than the first bottom surface. The second bottom surface of the first through hole 901 may expose the second conductive structure 1830.

[0098] The first conductive pattern 911 may extend onto the pad region PAD of the first substrate 100. In the pad region PAD of the first substrate 100, the first conductive pattern 911 may be disposed on the first surface 100a of the first substrate 100 and cover the inner wall of the first through-hole 901. As shown in FIG. 2A , a plurality of pad terminals 900 may be provided. The plurality of pad terminals 900 may include a first pad terminal and a second pad terminal. Although not shown, the first conductive pattern 911 may be provided on the bottom surface and sidewall of one of the plurality of pad terminals 900 (e.g., the first pad terminal) and may be electrically connected to the one of the pad terminals 900 (e.g., the first pad terminal).

[0099] The first conductive pattern 911 may cover the sidewall and the first bottom surface of the first through hole 901. The first conductive pattern 911 may be in contact with the top surface of the first conductive structure 830. Therefore, the first conductive structure 830 may be electrically connected to one of the pad terminals 900 (e.g., the first pad terminal) through the first conductive pattern 911. When the image sensor operates, a voltage may be applied to the first conductive structure 830 through the one of the pad terminals 900 and the first conductive pattern 911. The voltage may be applied to the second isolated pattern 220 through the first conductive pattern 911 and the contact plug 960. The voltage may be a negative bias voltage.

[0100] The first conductive pattern 911 may cover the second bottom surface of the first through hole 901 and be connected to the top surface of the second conductive structure 1830. The integrated circuit 1700 in the circuit chip 20 may be electrically connected to one of the pad terminals 900 (e.g., the first pad terminal) through the second conductive structure 1830 and the first conductive pattern 911. Although not shown, a plurality of first conductive patterns 911 and first through holes 901 may be provided. In this case, another one of the first conductive patterns 911 may not be connected to the contact plug 960 but may be connected to the first conductive structure 830 or the second conductive structure 1830. The first conductive pattern 911 may function as an electrical path between the integrated circuit 1700 of the circuit chip 20 and the transistors of the sensor chip 10. The first conductive pattern 911 may include a metal such as copper, tungsten, aluminum, titanium, tantalum, or an alloy thereof.

[0101] A first filled pattern 921 may be provided in the first through hole 901 to fill the first through hole 901. The first filled pattern 921 may not extend onto the first surface 100a of the first substrate 100. The first filled pattern 921 may include a low refractive index material and have insulating properties. The first filled pattern 921 may include the same material as the first fence pattern 310. The first filled pattern 921 may include the polymer structures 321 and nanoparticles 323 as described in the example of the first fence pattern 310 of FIG. 3C. The top surface of the first filled pattern 921 may have a recess. For example, the center portion of the top surface of the first filled pattern 921 may be positioned at a lower level than the edge portions.

[0102] A first capping pattern 931 may be disposed on the top surface of the first buried pattern 921 to fill the recessed portion. The top surface of the first capping pattern 931 may be substantially flat. The first capping pattern 931 may include an insulating polymer, such as a photoresist material.

[0103] The second through-hole 902 may be disposed on a second side of the pad terminal 900. The second side of the pad terminal 900 may be different from the first side. The second through-hole 902 may penetrate the insulating layer 400, the first substrate 100, and the first wiring layer 800. The second through-hole 902 may penetrate a portion of the second wiring layer 1800 to expose the second conductive structure 1830.

[0104] A second conductive pattern 912 may be provided on the first surface 100a of the first substrate 100 in the pad region PAD of the first substrate 100. The second conductive pattern 912 may be interposed between another one of the pad terminals 900 (e.g., a second pad terminal) and the first substrate 100 as shown in FIG. 2B and be electrically connected to the other one of the pad terminals 900 (e.g., the second pad terminal). The second conductive pattern 912 may extend into the second through-hole 902 and conformally cover the sidewalls and bottom surface of the second through-hole 902. The second conductive pattern 912 may be electrically connected to the second conductive structure 1830. When the image sensor operates, the integrated circuit 1700 of the circuit chip 20 may transmit and receive electrical signals through the second conductive structure 1830, the second conductive pattern 912, and the other one of the pad terminals 900 (e.g., the second pad terminal).

[0105] A second buried pattern 922 may be provided in the second through hole 902 to fill the second through hole 902. The second buried pattern 922 may not extend onto the first surface 100a of the first substrate 100. The second buried pattern 922 may include a low refractive index material and have insulating properties. For example, the second buried pattern 922 may include the same material as the first fence pattern 310. The top surface of the second buried pattern 922 may have a recess.

[0106] A second capping pattern 932 may be disposed on the top surface of the second buried pattern 922 to fill the recess. The top surface of the second capping pattern 932 may be substantially flat. The second capping pattern 932 may include an insulating polymer, such as a photoresist material.

[0107] The protective insulating film 471 may be provided to extend over the pad region PAD of the first substrate 100. The protective insulating film 471 may be provided on the upper surface of the insulating layer 400 and may extend into the first through-hole 901 and the second through-hole 902. The protective insulating film 471 may be interposed between the first conductive pattern 911 and the first filled pattern 921 in the first through-hole 901. The protective insulating film 471 may be interposed between the second conductive pattern 912 and the second filled pattern 922 in the second through-hole 902. The protective insulating film 471 may expose the pad terminal 900.

[0108] The organic film 501 and the coating layer 531 may be further provided on the pad region PAD of the first substrate 100. The organic film 501 may cover a portion of the first capping pattern 931 and the protective insulating film 471 on the first surface 100a of the first substrate 100. The organic film 501 may expose the top surface of the pad terminal 900.

[0109] 6 is a view illustrating an image sensor according to an embodiment, and corresponds to a cross section taken along line II' in FIG. 2A. In the following description, reference will be made to FIG. 2A, and any overlapping content will be omitted.

[0110] 6, the image sensor may include a sensor chip 10 and a circuit chip 20. The sensor chip 10 and the circuit chip 20 may be substantially the same as those described above with reference to FIGS. 2A and 2B. For example, the sensor chip 10 may include a first substrate 100, a first wiring layer 800, an isolation pattern 200, an insulating layer 400, a fence pattern 300, a color filter CF, a protective film 470, a microlens layer 500, a pad terminal 900, a first conductive pattern 911, and a second conductive pattern 912. The circuit chip 20 may include a second substrate 1000 and a second wiring layer 1800.

[0111] However, the sensor chip 10 may further include a first connection pad 850. The first connection pad 850 may be exposed on the lower surface of the sensor chip 10. For example, the first connection pad 850 may be disposed in the second lower insulating layer 820 of the first wiring layer 800. The first connection pad 850 may be electrically connected to the first conductive structure 830. The first connection pad 850 may include a conductive material such as a metal. For example, the first connection pad 850 may include copper. As another example, the first connection pad 850 may include aluminum, tungsten, titanium, and / or an alloy thereof.

[0112] The circuit chip 20 may include second connection pads 1850. The second connection pads 1850 may be exposed on the upper surface of the circuit chip 20. The second connection pads 1850 may be disposed within the third lower insulating layer 1820. The second connection pads 1850 may be electrically connected to the integrated circuit 1700. The second connection pads 1850 may include a conductive material such as a metal. For example, the second connection pads 1850 may include copper. As another example, the second connection pads 1850 may include aluminum, tungsten, titanium, and / or alloys thereof.

[0113] The circuit chip 20 may be connected to the sensor chip 10 by direct bonding. For example, the first connection pad 850 and the second connection pad 1850 may be vertically aligned and in contact with each other. Therefore, the second connection pad 1850 may be directly bonded to the first connection pad 850. An electrical signal from the integrated circuit 1700 of the circuit chip 20 may be transmitted to the transistor or pad terminal 900 of the sensor chip 10 through the second conductive structure 1830, the second connection pad 1850, the first connection pad 850, and the first conductive structure 830. The second lower insulating layer 820 may be directly bonded to the third lower insulating layer 1820. In this case, a chemical bond may be formed between the second lower insulating layer 820 and the third lower insulating layer 1820.

[0114] The first through hole 901 may include a first through hole portion 91, a second through hole portion 92, and a third through hole portion 93. The first through hole portion 91 may penetrate the insulating layer 400, the first substrate 100, and the first wiring layer 800 and may have a first bottom surface. The second through hole portion 92 may penetrate the insulating layer 400, the first substrate 100, and the first wiring layer 800 and may extend into the upper part of the second wiring layer 1800. The second through hole portion 92 may have a second bottom surface, and the second bottom surface may expose the upper surface of the second conductive structure 1830. A sidewall of the second through hole portion 92 may be spaced apart from a sidewall of the first through hole portion 91. The third through hole portion 93 may be provided between the upper part of the first through hole portion 91 and the upper part of the second through hole portion 92 and may be connected to the upper part of the first through hole portion 91 and the upper part of the second through hole portion 92. A first conductive pattern 911, a protective insulating film 471, and a first filled pattern 921 may be provided in the first through hole 901. The first conductive pattern 911 may cover the inner walls of the first through hole portion 91, the second through hole portion 92, and the third through hole portion 93.

[0115] The above detailed description of the invention is not intended to limit the invention to the disclosed embodiments, but rather the invention can be used in various other combinations, modifications, and environments without departing from the spirit and scope of the invention. The appended claims should be interpreted to include other embodiments. [Explanation of symbols]

[0116] 100 First substrate 200 Separation Patterns 300 fence patterns 400 insulating layer 470 Protective film 500 microlens layers 700 gate pattern 800 1st wiring layer 900 pad terminal APS pad area CF color filter PAD Pad area PD photoelectric conversion region PX pixel area OB Optical Black Area

Claims

1. a substrate having a first surface and a second surface facing each other; a color filter disposed on the second surface of the substrate; a fence pattern interposed between the color filters; a protective film disposed between the substrate and the color filter and covering the fence pattern, The fence pattern is a first fence pattern having a first lower surface and a first upper surface opposed to each other; a second fence pattern provided on the first upper surface of the first fence pattern and comprising a different material than the first fence pattern; a width of the first lower surface of the first fence pattern is smaller than a width of the second fence pattern; the protective film covers a sidewall of the first fence pattern; The width of the first lower surface of the first fence pattern is smaller than the width of the first upper surface of the first fence pattern.

2. further comprising an insulating layer interposed between the substrate and the color filter; The image sensor of claim 1 , wherein the first fence pattern is disposed on an upper surface of the insulating layer.

3. 2. The image sensor of claim 1, wherein the maximum width of the second fence pattern is 100% to 102% of the minimum width of the second fence pattern.

4. The image sensor of claim 1 , wherein a width of the first upper surface of the first fence pattern is greater than the width of the second fence pattern.

5. the first fence pattern includes a lower portion, an upper portion, and an intermediate portion between the lower portion and the upper portion; The image sensor of claim 1 , wherein a width of the middle portion of the first fence pattern is smaller than a width of the first lower surface of the first fence pattern.

6. The image sensor of claim 1 , wherein the protection film covers an edge portion of a first upper surface of the first fence pattern.

7. further comprising a microlens layer disposed on the color filter and the fence pattern; the second fence pattern has a second lower surface and a second upper surface facing each other, The image sensor of claim 1 , wherein the protective film is interposed between the second top surface of the second fence pattern and the microlens layer.

8. a substrate having a first surface and a second surface facing each other and including a photoelectric conversion region; an isolation pattern provided between the photoelectric conversion regions in the substrate; a color filter disposed on the second surface of the substrate; a fence pattern provided on the separation pattern and disposed between the color filters; The fence pattern is a first fence pattern having opposing lower and upper surfaces; a second fence pattern provided on the top surface of the first fence pattern; a width of the lower surface of the first fence pattern is smaller than a width of the upper surface of the first fence pattern; The maximum width of the second fence pattern is 100% to 102% of the minimum width of the second fence pattern.

9. a substrate having a first surface and a second surface facing each other and including a photoelectric conversion region therein; an isolation pattern provided between the photoelectric conversion regions in the substrate; a color filter disposed on the second surface of the substrate; a fence pattern provided on the separation pattern and disposed between the color filters, the fence pattern comprising: a first fence pattern having a first lower surface and a first upper surface opposed to each other; a second fence pattern provided on a first upper surface of the first fence pattern and including a material different from that of the first fence pattern, wherein a width of the first lower surface of the first fence pattern is smaller than a width of the first upper surface; an insulating layer interposed between the color filter and the substrate and between the fence pattern and the separation pattern; a protective film interposed between the insulating layer and the color filter and covering a sidewall of the first fence pattern and a sidewall and an upper surface of the second fence pattern; a microlens layer disposed on the color filter and the fence pattern; a gate pattern disposed on the second surface of the substrate; a wiring layer disposed on the second surface of the substrate, the wiring layer including a lower insulating layer and a wiring structure; The image sensor includes a lower insulating layer covering the gate pattern, and the wiring structure disposed within the lower insulating layer.

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