Symmetric read-out resistive random access memory cell with bipolar junction selectors

Abstract

The memory device and method for making the memory device include a resistive random access memory element electrically connected to an extrinsic base region of a bipolar junction transistor, the extrinsic base region of the bipolar junction transistor being comprised of epitaxially grown material that forms a bottom electrode of the resistive random access memory element. Furthermore, a method for writing to the memory device includes applying a first voltage to a word line of the memory device to form a filament in the resistive random access memory element. A second voltage having an opposite polarity to the first voltage can be applied to the word line to remove a portion of the filament in the resistive random access memory element.

Description

[Technical Field]

[0001] The present invention relates generally to the field of memory devices, and more particularly to fabricating a symmetric read-operated resistive random access memory bit cell with a bipolar junction selector. [Background technology]

[0002] Next-generation memory applications, such as resistive random-access memory (RRAM), require bidirectional selection for efficient operation. Transistor selectors enable bidirectional operation but introduce some read asymmetry because, depending on the voltage polarity of operation, the field-effect (or bipolar) transistor terminal connected to the memory element can be either a functional drain (or emitter) or a functional source (or collector). This issue can be addressed by using additional transistors within the bit cell. However, using additional transistors results in an increase in the bit cell area. Summary of the Invention

[0003] Alternative designs and techniques are needed to form memory bit cells that can prevent asymmetry problems while reducing bit cell area. Accordingly, embodiments of the present invention provide a memory device that includes a bipolar junction transistor (BJT) with an RRAM element integrated on the extrinsic base region of the BJT. The proposed structure and integration method can provide symmetric read operation and enable a small device footprint, among other benefits.

[0004] According to one embodiment, a memory device includes a resistive random access memory element electrically connected to an extrinsic base region of a bipolar junction transistor, the extrinsic base region of the bipolar junction transistor being comprised of an epitaxially grown material that forms a bottom electrode of the resistive random access memory element, the epitaxially grown material including a high dopant concentration and a triangular-shaped top region.

[0005] According to another embodiment, a method for writing to a memory device includes applying a first voltage to a word line of the memory device, the memory device including a resistive random access memory element electrically connected to an extrinsic base region of a bipolar junction transistor, wherein applying the first voltage forms a filament in the resistive random access memory element. A second voltage having an opposite polarity to the first voltage can be applied to the word line to remove a portion of the filament in the resistive random access memory element. A third voltage can be applied between the word line and at least one of a bit line and a select line to initiate a read operation in the resistive random access memory element.

[0006] According to yet another embodiment, a method of forming a memory structure includes forming a resistive random access memory element electrically connected to an extrinsic base region of a bipolar junction transistor, the extrinsic base region of the bipolar junction transistor comprising epitaxially grown material that forms a bottom electrode of the resistive random access memory element.

[0007] The following detailed description, given by way of example and not intended to limit the invention thereto, will be best understood in conjunction with the accompanying drawings, in which: [Brief explanation of the drawings]

[0008] [Figure 1]FIG. 2 illustrates an exemplary one-transistor-one-resistor RRAM structure with a BJT selector configured in accordance with an embodiment of the present disclosure. [Figure 2] 1 is a cross-sectional view of a memory device at an early step in the manufacturing process according to one embodiment of the present disclosure. [Figure 3] FIG. 1 is a cross-sectional view of a memory device after forming an extrinsic base layer according to one embodiment of the present disclosure. [Figure 4] FIG. 2 is a cross-sectional view of a memory device after forming a hard mask layer, followed by patterning an extrinsic base layer and forming sidewall spacers according to one embodiment of the present disclosure. [Figure 5] 1 is a cross-sectional view of a memory device after recessing a semiconductor layer according to one embodiment of the present disclosure. [Figure 6] 1A-1C are cross-sectional views of a memory device illustrating an ion implantation process according to one embodiment of the present disclosure. [Figure 7] FIG. 10 is a cross-sectional view of a memory device after forming emitter and collector regions according to another embodiment of the present disclosure. [Figure 8] FIG. 2 is a cross-sectional view of a memory device after forming a first dielectric layer according to one embodiment of the present disclosure. [Figure 9] FIG. 10 is a cross-sectional view of a memory device after removing the hard mask layer according to another embodiment of the present disclosure. [Figure 10] FIG. 10 is a cross-sectional view of a memory device after forming a faceted epitaxy layer according to another embodiment of the present disclosure. [Figure 11] FIG. 10 is a cross-sectional view of a memory device after forming an RRAM stack according to another embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0009] The drawings are not necessarily to scale. The drawings are merely schematic representations and are not intended to portray specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention. In the drawings, like numbering indicates like elements.

[0010] Detailed embodiments of the claimed structures and methods are disclosed herein; however, it will be understood that the disclosed embodiments may be embodied in a variety of forms and are merely illustrative of the claimed structures and methods. The present invention may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0011] For purposes of the following description, terms such as "upper," "lower," "right," "left," "vertical," "horizontal," "top," "bottom," and derivatives thereof, refer to the disclosed structures and methods while facing the drawing figures. Terms such as "above," "overlying," "atop," "on top," "positioned on," or "positioned atop" mean that a first element, such as a first structure, is on a second element, such as a second structure, and that intervening elements, such as interface structures, may be present between the first and second elements. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without an intermediate conductive, insulating, or semiconducting layer at the interface of the two elements.

[0012] Terms such as first, second, etc. may be used herein to describe various elements, but it will be understood that these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element discussed below could be referred to as a second element without departing from the scope of the present concepts.

[0013] In order to avoid obscuring the presentation of embodiments of the present invention, in the following detailed description, some process steps or operations known in the art may be combined together for presentation and illustration purposes, and in some cases may not be described in detail. In other cases, some process steps or operations known in the art may not be described at all. It should be understood that the following description will instead focus on the distinctive features or elements of various embodiments of the present invention.

[0014] Resistive random access memory (RRAM) is one of the next-generation nonvolatile memory technologies due to its simple structure, high density, low operating power read / write operation, and fast read and write speeds. A selector device connected in series with an RRAM device can be used to improve the sneak path current of the RRAM device and create high-density, large-size crossbar memory arrays. RRAM is a memory that stores information using resistive switches under an electric field, with high and low resistance states corresponding to logic 0 and 1, respectively.

[0015] In a traditional memory cell (BJT / RRAM and / or FET / RRAM), the voltage drop across the RRAM cell causes the gate-source voltage V GS (or base-emitter voltage V BE) is smaller, and therefore the transistor drive current is smaller when the transistor terminal connected to the RRAM is a functional source (or functional collector) compared to when it is a functional drain (or functional emitter). This leads to the well-known asymmetric read operation problem.

[0016] To address this issue, embodiments of the present invention provide a memory cell structure including an RRAM element integrated on the extrinsic base region of a BJT, enabling symmetric circuit operation. Figure 1 illustrates an exemplary one-transistor-one-resistor (1T1R) RRAM structure with a BJT selector configured in accordance with embodiments of the present invention. In particular, in the illustrated circuit, the RRAM element is connected to the base terminal of the BJT. Thus, during a write operation, a filament can be formed in the RRAM element by applying a positive (or negative) voltage on the word line (WL) relative to the bit line (BL) or select line (SL) for an npn (or pnp) BJT, thereby forward biasing the pn junction. Meanwhile, during an erase operation, filament removal can be performed by applying a negative (or positive) voltage on the WL relative to the BL or SL for an npn (pnp) BJT, thereby punching through or avalanching the pn junction. Voltage polarities opposite to those described above can also be used for filament formation and removal, but are typically less efficient.

[0017] Continuing to refer to FIG. 1, the read operation is the same as that of a traditional memory cell; however, in contrast to the traditional memory cell, the read current I READ The amplitude of I READThe polarity of the voltage applied between BL and SL determines the direction of the current flow. This is because the RRAM element is connected to the base terminal of the BJT, not its collector or emitter. The read voltage V applied between the WL line and the BL or SL line of a memory cell with an np-n BJT selector is READ In case of:I B =(V READ -V BE ) / R RRAM where V for silicon BE ≒0.7V, and I C = βI B and I E =I C +I B ≒I C where I B is the base current, and V BE is the base-emitter voltage, and R RRAM is the resistance of the resistive memory element, and I C is the collector current, and I E is the emitter current, β is the BJT gain, and I READ =I C or I E In the case of a memory cell with a pn-pBJT, V BE is V EB (emitter-base voltage). As can be seen from the above equation, I READ The amplitude of θ is independent of its direction, thus eliminating the asymmetric read operation problem.

[0018] Accordingly, embodiments of the present disclosure provide a memory device and method for making the same, including a bipolar junction transistor (BJT) having an RRAM element integrated on the extrinsic base region of the BJT, enabling symmetric read operations. The proposed structure and integration method may also enable a small device footprint and therefore a high density of memory cells. Embodiments by which a memory device having an RRAM element integrated on the extrinsic base region of the BJT may be formed are described in detail below with reference to the accompanying drawings, Figures 1-11.

[0019] Referring now to FIG. 2, a cross-sectional view of memory device 100 at an early step in the manufacturing process is shown, according to one embodiment of the present disclosure.

[0020] At this step in the fabrication process, memory device 100 may include a semiconductor-on-insulator (SOI) substrate in which a buried dielectric layer 108 (i.e., a buried oxide or BOX (buried oxide) layer) separates a (base) semiconductor substrate 102 from an upper semiconductor layer 110. Components of memory device 100 may then be formed from upper semiconductor layer 110. In other embodiments, a bulk semiconductor substrate may be used in the fabrication process.

[0021] In this embodiment, the semiconductor-on-insulator substrate formed by the semiconductor substrate 102, the buried dielectric layer 108, and the top semiconductor layer 110 comprises a silicon-germanium-on-insulator substrate. Thus, the buried dielectric layer 108 insulates the top semiconductor layer 110 from the semiconductor substrate 102. The semiconductor substrate 102 can be made of any of several known semiconductor materials, such as silicon, germanium, silicon-germanium alloys, and compound (e.g., III-V and II-VI) semiconductor materials. Non-limiting examples of compound semiconductor materials include gallium arsenide, indium arsenide, and indium phosphide. In this embodiment, the semiconductor substrate 102 is made of single-crystal silicon (Si). Typically, the semiconductor substrate 102 can be about several hundred microns thick. For example, the semiconductor substrate 102 can include thicknesses ranging from about 600 micrometers to about 1,000 micrometers, and ranges therebetween.

[0022] The buried dielectric layer 108 (i.e., the BOX layer) may be formed from any of several known dielectric materials. Non-limiting examples include oxides, nitrides, and oxynitrides of silicon. Oxides, nitrides, and oxynitrides of other elements are also contemplated. Furthermore, the buried dielectric layer 108 may comprise crystalline or amorphous dielectric materials. Furthermore, the buried dielectric layer 108 may be formed using any of several known methods. Non-limiting examples include ion implantation, thermal or plasma oxidation or nitridation, chemical vapor deposition, and physical vapor deposition. According to one embodiment, the buried dielectric layer 108 may have a thickness ranging from about 20 nm to about 200 nm, and ranges therebetween.

[0023] In some embodiments, depending on design requirements, the semiconductor substrate 102 and the top semiconductor layer 110 can comprise the same or different semiconductor materials with respect to chemical composition, dopant concentration, and crystalline orientation. In this embodiment, the top semiconductor layer 110 is made of silicon-germanium (SiGe). In particular, the top semiconductor layer 110 comprises a monocrystalline SiGe layer with a 20% germanium concentration. Methods for forming the top semiconductor layer 110 are well known in the art. Non-limiting examples include wafer bonding or thermal mixing. The top semiconductor layer 110 can comprise a thickness ranging from about 6 nm to about 100 nm, and ranges therebetween.

[0024] 3, there is shown a cross-sectional view of memory device 100 illustrating the formation of extrinsic base layer 204, according to one embodiment of the present disclosure. Extrinsic base layer 204 is formed just above top semiconductor layer 110. In this embodiment, extrinsic base layer 204 comprises an epitaxially grown single crystal silicon (Si) layer.

[0025] The terms "epitaxial growth and / or deposition" and "epitaxially formed and / or grown" refer to the growth of a semiconductor material (crystalline material) on the deposition surface of another semiconductor material (crystalline material), where the grown semiconductor material (crystalline overlayer) has substantially the same crystalline characteristics as the semiconductor material of the deposition surface (seed material). In an epitaxial deposition process, chemical reactants provided by source gases are controlled and system parameters are set so that the deposition atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move about the surface, thereby orienting themselves in the crystalline arrangement of the atoms of the deposition surface. Thus, the epitaxially grown semiconductor material has substantially the same crystalline characteristics as the deposition surface on which it is formed. For example, epitaxially grown semiconductor material deposited on a {100}-oriented crystalline surface will exhibit a {100} orientation. In some embodiments, the epitaxial growth and / or deposition process is selective to forming on semiconductor surfaces and generally does not deposit material on exposed surfaces such as silicon dioxide or silicon nitride surfaces.

[0026] In some embodiments, the gas source for deposition of epitaxial semiconductor materials includes a silicon-containing gas source, a germanium-containing gas source, or a combination thereof. For example, an epitaxial silicon (Si) layer can be deposited from a silicon gas source selected from the group consisting of silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorodisilane, dichlorosilane, trichlorosilane, and combinations thereof. An epitaxial germanium layer can be deposited from a germanium gas source selected from the group consisting of germane, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane, and combinations thereof. An epitaxial silicon-germanium layer can be formed using a combination of the above gas sources. Carrier gases such as hydrogen, nitrogen, helium, and argon can be used.

[0027] According to the proposed embodiment, the extrinsic base layer 204 can function as an extrinsic base region for a subsequently formed bipolar junction transistor, while the top semiconductor layer 110 can function as an intrinsic base region for the same bipolar junction transistor, as will be described in detail below.

[0028] Referring now to FIG. 4, a cross-sectional view of memory device 100 is shown after forming a hard mask layer 310, followed by patterning extrinsic base layer 204 and forming sidewall spacers 312, according to one embodiment of the present disclosure.

[0029] The hard mask layer 310 may comprise a dielectric material such as silicon dioxide, silicon nitride, silicon carbide, etc., and may be deposited by any suitable deposition method known in the art. The process of patterning the extrinsic base layer 204 consists of steps well known in the art and generally includes forming a pattern on a photoresist layer (not shown) that is transferred to the hard mask layer 310 and used to pattern the underlying extrinsic base layer 204 by any suitable etching technique.

[0030] After the patterning process, a spacer material may be deposited on the memory device 100 and then etched to form sidewall spacers 312, as configured in Figure 4. The final thickness of the hard mask layer 310 may range between about 50 nm and about 150 nm, although other thicknesses above or below this range may be used as desired for a particular application.

[0031] The spacer material forming the sidewall spacers 312 may include an insulating material such as an oxide, a nitride, an oxynitride, a silicon carbon oxynitride, a silicon boron oxynitride, a low-k dielectric, or a combination thereof. Standard deposition and etching techniques may be used to form the sidewall spacers 312. For example, the spacer material may be etched using an anisotropic etch to form the sidewall spacers 312. As known by those skilled in the art, the spacer material forming the sidewall spacers 312 is removed from all horizontal surfaces of the memory device 100 during the etching process.

[0032] As can be seen in the figure, sidewall spacers 312 are located on the sidewalls of the extrinsic base layer 204 and the hard mask layer 310. According to one embodiment, the width of the sidewall spacers 312 may range between about 6 nm and about 12 nm, although other thicknesses above or below this range may be used as desired for a particular application.

[0033] 5, a cross-sectional view of memory device 100 after recessing top semiconductor layer 110 is shown, according to one embodiment of the present disclosure. Known etching techniques may be applied to recess top semiconductor layer 110. In one exemplary embodiment, a reactive ion etching (RIE) process may be used to recess top semiconductor layer 110.

[0034] As shown, after etching, the final width of the top semiconductor layer 110 is equal to the width of the extrinsic base layer 204 plus the width of the sidewall spacers 312. In other words, the top semiconductor layer 110 is recessed until the outer surface of the top semiconductor layer 110 perpendicular to the semiconductor substrate 102 is coplanar with the outer surfaces of the sidewall spacers 312.

[0035] The embodiments described below illustrate the formation of a bipolar junction transistor (BJT) in memory device 100, for which recessed top semiconductor layer 110 constitutes a base region. In particular, the processing steps illustrated in Figures 6-7 describe the formation of emitter and collector regions on opposite sides of recessed top semiconductor layer 110 (i.e., the base region).

[0036] 6, a cross-sectional view of memory device 100 illustrating an ion implantation process is shown, according to one embodiment of the present disclosure, prior to forming the emitter and collector regions of the BJT.

[0037] As known by those skilled in the art, a BJT is a three-terminal electronic device that includes three semiconductor regions: an emitter, a base, and a collector. Generally, a BJT includes a pair of p-n junctions: a collector-base junction and an emitter-base junction. A voltage applied across the emitter-base junction of a BJT controls the movement of charge carriers, which creates a flow of charge between the collector and emitter regions of the BJT.

[0038] An npn bipolar junction transistor includes a region of p-type semiconductor material located between two regions of n-type semiconductor material that make up the emitter-collector and base regions of an np-n BJT device. A pnp bipolar junction transistor has a region of n-type semiconductor material located between two regions of p-type semiconductor material that make up the emitter-collector and base regions of a pn-p BJT device.

[0039] For purposes of illustration only and not limitation, the bipolar transistors formed in memory device 100 include npn bipolar transistors. Thus, in this embodiment, top semiconductor layer 110 (i.e., the base region of the BJT) includes a p-type semiconductor material, such as silicon-germanium (SiGe). As known by those skilled in the art, the process of forming a pnp bipolar transistor includes similar steps.

[0040] Therefore, to form the emitter / collector regions of the BJT, angled ion implantation is performed on opposing sides of the recessed top semiconductor layer 110, as shown by arrows 510. The ion implantation process provides the appropriate polarity for the subsequently formed emitter and collector regions (shown in FIG. 7). As noted above, embodiments of the present disclosure are illustrated using an npn bipolar junction transistor that includes two regions of n-type semiconductor material and a region of p-type semiconductor material located between the two regions of n-type semiconductor material.

[0041] Thus, first ions corresponding to a first polarity are implanted onto the first lateral surface 602 and the second lateral surface 604 of the semiconductor layer 110. As can be appreciated, the first polarity of the implanted ions (i.e., p-type or n-type) is selected according to the type of bipolar transistor being formed. In this embodiment, because an exemplary npn bipolar junction transistor is being formed, p-type dopants are used in the ion implantation process.

[0042] As illustrated in FIG. 7, emitter region 620 will be formed from first lateral surface 602 and collector region 640 will be formed from second lateral surface 604 .

[0043] The process of forming the emitter / collector regions for a pnp bipolar junction transistor is similar and involves selecting a second ion corresponding to a second polarity, i.e., a p-type dopant, for the implantation process.

[0044] In a preferred embodiment, high temperature angled ion implantation may be performed on memory device 100. In some embodiments, low temperature ion implantation may be performed to provide the appropriate polarity to first lateral surface 602 and second lateral surface 604 of semiconductor layer 110.

[0045] In embodiments in which p-type emitter / collector regions are formed, p-type dopants, such as boron (B), may be implanted by performing a high-temperature BF angled ion implant into memory device 100. In embodiments in which n-type emitter / collector regions are formed, n-type dopants, such as phosphorus (P) or arsenic (As), may be implanted by performing a high-temperature As or P angled ion implant into memory device 100. The dopant concentration of the p-type dopant (i.e., boron) may be approximately 1×10 18 ions / cm 3 From about 9 x 10 20 ions / cm 3 while the dopant concentration of the n-type dopant (i.e., arsenic or phosphorus) ranges from about 1×10 18 ions / cm 3 From about 9 x 10 20 ions / cm 3 The range may be up to.

[0046] Referring now to FIG. 7, a cross-sectional view of memory device 100 is shown after forming emitter region 620 and collector region 640 of a bipolar junction transistor according to one embodiment of the present disclosure.

[0047] The emitter region 620 and the collector region 640 may be formed, for example, by epitaxial growth of in-situ doped single-crystalline Si or SiGe layers from the first lateral surface 602 and the second lateral surface 604, respectively, of the semiconductor layer 110. In some embodiments, the emitter region 620 and the collector region 640 may comprise a material similar to the material forming the base region (i.e., the recessed upper semiconductor layer 110), but with a slightly higher bandgap. The epitaxial materials forming the emitter region 620 and the collector region 640 can be grown from gaseous or liquid precursors using low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), vapor-phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid-phase epitaxy (LPE), or other suitable processes. The epitaxial silicon, silicon-germanium, germanium, or carbon-doped silicon (Si:C), or combinations thereof, can be doped during deposition (in situ doped) by adding dopants, n-type dopants (e.g., phosphorus or arsenic), or p-type dopants (e.g., boron or gallium), depending on the type of transistor.

[0048] According to an exemplary embodiment, emitter region 620 (e.g., n + Si emitter), (base) upper semiconductor layer 110 (e.g., p-type SiGe), and collector region 640 (e.g., n + The Si collector) forms an npn bipolar transistor within the memory device 100.

[0049] Referring now to FIG. 8, a cross-sectional view of memory device 100 after forming a first dielectric layer 710 is shown according to one embodiment of the present disclosure.

[0050] After epitaxially growing the emitter region 620 and the collector region 640, a first dielectric layer 710 is formed on the memory device 100 as shown. The first dielectric layer 710 may be formed, for example, by chemical vapor deposition (CVD) of a dielectric material. Non-limiting examples of dielectric materials for forming the first dielectric layer 710 include silicon oxide, silicon nitride, hydrogenated silicon carbide oxide, silicon-based low-k dielectrics, flowable oxides, porous dielectrics, or organic dielectrics, including porous organic dielectrics.

[0051] In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), may be performed on memory device 100 after deposition of first dielectric layer 710.

[0052] 9, a cross-sectional view of memory device 100 is shown after removal of hard mask layer 310, according to one embodiment of the present disclosure. In this embodiment, hard mask layer 310 is selectively removed from memory device 100 using any suitable isotropic etch process, including, for example, an SC1 solution. Removal of hard mask layer 310 exposes the top surface of extrinsic base layer 204, as shown.

[0053] 10 , there is shown a cross-sectional view of memory device 100 after forming faceted epitaxy layer 902, according to one embodiment of the present disclosure. At this point in the fabrication process, faceted epitaxy layer 902 comprises epitaxially grown semiconductor material formed on the exposed upper surface of extrinsic base layer 204 following an epitaxial growth process similar to that described above with respect to emitter / collector regions 620, 640 of FIG.

[0054] As known by those skilled in the art, the triangular shapes observed in the upper portion of faceted epitaxial layer 902 can be the result of different growth rates during the epitaxial deposition process that are inherent to each crystal orientation plane of the material forming faceted epitaxial layer 902. In particular, the facets of triangular-shaped faceted epitaxial layer 902 are <111> 11 , the epitaxial layer 902 formed on the extrinsic base layer 204 has a triangular faceted surface, which is bounded by a plane. Thus, the sharp features or pointed tips 904 of the triangular faceted epitaxy layer 902 formed on the extrinsic base layer 204 enhance the electric field at the pointed tips 904, which can facilitate positional controllability for current-conducting filaments in subsequently formed RRAM devices, as described in detail below with reference to FIG. 11 . However, in some embodiments, the epitaxial material grown on the extrinsic base layer 204 may have a shape different from the triangular shape shown (e.g., a flat top shape).

[0055] In one embodiment, faceted epitaxy layer 902 may be made of a semiconductor material similar to the material forming extrinsic base layer 204 (i.e., single crystal Si). In other embodiments, faceted epitaxy layer 902 may be made of a semiconductor material different from the material forming extrinsic base layer 204. In a preferred embodiment, each of extrinsic base layer 204 and faceted epitaxy layer 902 is formed with a high dopant concentration, which may be the same or different.

[0056] For example, in one embodiment, the extrinsic base layer 204 has a maximum of 2×10 20 ions / cm 3 The faceted epitaxial layer 902 may include doped silicon having a first concentration of p-type dopant (i.e., boron) of up to 8×10 20 ions / cm 3 The SiGe layer may include SiGe having a second concentration of a p-type dopant (ie, boron).

[0057] Typically, a BJT structure includes an extrinsic base layer made of a polycrystalline material (e.g., poly-Si or poly-SiGe). As explained above, embodiments of the present disclosure provide a single-crystal extrinsic base region with a triangular-shaped top region with enhanced electrical properties that can act as both a bottom electrode for a subsequently formed RRAM device (FIG. 11) and an extrinsic base region for a BJT.

[0058] Thus, the extrinsic base layer 204 and the faceted epitaxy layer 902 form the extrinsic base region of the BJT, with the bottom portion of the extrinsic base region defined by the extrinsic base layer 204 and the top portion of the extrinsic base region defined by the faceted epitaxy layer 902. The proposed extrinsic base region configuration has a higher bandgap energy level (E G In the illustrated embodiment, the higher bandgap in the extrinsic base region is achieved, for example, by forming a heavily doped silicon extrinsic base region (i.e., extrinsic base layer 204 and faceted epitaxy layer 902) and an intrinsic base region (i.e., top semiconductor layer 110) with 20% SiGe.

[0059] In some embodiments, the extrinsic base layer 204 and the faceted epitaxy layer 902 may be formed with a stepped or graded doping profile. In such embodiments, the doping concentration increases as the material (e.g., Si) forming the extrinsic base layer 204 and the faceted epitaxy layer 902 is epitaxially grown. By doing this, the bottom portion of the extrinsic base region (i.e., the extrinsic base layer 204) can have a lower dopant concentration than the top portion of the extrinsic base region (i.e., the faceted epitaxy layer 902). For ease of illustration, the extrinsic base layer 204 and the faceted epitaxy layer 902 are shown as two distinct layers; however, it can be understood that the extrinsic base layer 204 and the faceted epitaxy layer 902 can comprise a single block of the same material.

[0060] Referring now to FIG. 11, a cross-sectional view of a memory device 100 after forming RRAM elements is shown, according to one embodiment of the present disclosure.

[0061] In this embodiment, a schematic RRAM stack is formed on a memory device 100. The RRAM stack includes a bottom electrode formed by a faceted epitaxy layer 902, a switching layer 1010, a top electrode layer 1012 formed above the switching layer 1010, and a metal fill 1014.

[0062] As shown, switching layer 1010 is conformally deposited just above faceted epitaxy layer 902 using known deposition techniques, such as, for example, atomic layer deposition (ALD). Switching layer 1010 substantially covers the topmost portion of the extrinsic base region of the BJT formed by faceted epitaxy layer 902.

[0063] The switching layer 1010 generally comprises a material having a switchable resistance. In this embodiment, the switching layer 1010 comprises a high-k oxide material. The switching layer 1010 serves as a dielectric layer for the RRAM structure, separating the faceted epitaxy layer 902 from the top electrode layer 1012. As known by those skilled in the art, the switching layer 1010 constitutes an insulation resistance switch (RS) layer, which is a key component of the RRAM structure when acting as a storage medium. Non-limiting examples of suitable materials for the switching layer 1010 include titanium oxide (TiOx), tantalum oxide (TaOx), and hafnium oxide (HfOx). The thickness of the switching layer 1010 can range from about 3 nm to about 10 nm, and can range therebetween. In a preferred embodiment, the switching layer 1010 can have a thickness of 5 nm.

[0064] The top electrode layer 1012 is conformally deposited above the switching layer 1010. The top electrode layer 1012 may be deposited using known deposition techniques, such as, for example, ALD. The top electrode layer 1012 may be comprised of a titanium-aluminum-containing alloy, such as, but not limited to, a titanium-nickel (TiN) alloy, a titanium-nickel-aluminum (TiN / Al) alloy, or a titanium-aluminum-carbon (TiAlC) alloy. The top electrode layer 1012 may have a thickness ranging from about 3 nm to about 10 nm, although other thicknesses above or below this range may be used as desired for a particular application.

[0065] Once the top electrode layer 1012 is deposited above the switching layer 1010, a metal fill 1014 is deposited above the top electrode layer 1012 using known deposition methods. After depositing the metal fill 1014, the memory device 100 is subjected to a CMP process to obtain the smooth and planar surface shown in the figure. The metal fill 1014 may be made of a suitable low resistivity metal, such as tungsten (W) or copper (Cu). The metal fill 1014 serves as an electrical conductor between the top electrode layer 1012 and subsequently formed metal contacts to the RRAM structure.

[0066] As shown, the bottom portion of the extrinsic region (i.e., extrinsic base layer 204) serves as the extrinsic base of the BJT, while the top portion (i.e., faceted epitaxy layer 902) serves as the bottom electrode of the RRAM structure.

[0067] Accordingly, embodiments of the present invention provide a memory device and method for making the same, which includes an RRAM structure integrated on the extrinsic base of a BJT structure that enables symmetric read operations. In particular, in the proposed embodiment, the extrinsic base of the BJT includes a heavily doped faceted epitaxy region having a triangular shape with a pointed tip on top that can simultaneously function as the bottom electrode of the RRAM element and as the extrinsic base of the BJT.

[0068] The description of various embodiments of the present invention has been presented for purposes of illustration and is not intended to be exhaustive or limited to the disclosed embodiments. Many changes and modifications will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been selected to best explain the principles of the embodiments, practical applications, or technical improvements over technology found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. 1. A memory device comprising: a resistive random access memory element electrically connected to an extrinsic base region of a bipolar junction transistor, the extrinsic base region of the bipolar junction transistor being a bottom electrode of the resistive random access memory element; The bipolar junction transistor is an intrinsic base region located between the emitter and collector regions of the bipolar junction transistor; the extrinsic base region above the intrinsic base region; Equipped with the extrinsic base region has a higher dopant concentration than the intrinsic base region; Memory devices.

2. The exogenous base region is an extrinsic base layer above the intrinsic base region; epitaxially grown material above the extrinsic base layer; and The memory device of claim 1 further comprising:

3. The memory device of claim 2 , wherein the epitaxially grown material is the bottom electrode of the resistive random access memory element.

4. The memory device of claim 2 , wherein the epitaxially grown material above the extrinsic base layer comprises a faceted epitaxial layer having a triangular shape with a pointed tip thereon.

5. 3. The memory device of claim 2, wherein the extrinsic base layer and the epitaxially grown material above the extrinsic base layer comprise epitaxially grown single crystal semiconductor material having a high doping profile.

6. The memory device of claim 5 , wherein the epitaxially grown material has a higher dopant concentration than the extrinsic base layer.

7. The memory device of claim 5 , wherein the high doping profile further comprises a step or gradual doping profile.

8. The resistive random access memory element comprises: the bottom electrode formed by the extrinsic base region of the bipolar junction transistor; a switching layer directly above the extrinsic base region; a top electrode layer above the switching layer; a metal fill above the top electrode layer; 8. A memory device according to claim 1, comprising:

9. 1. A method of operating a memory structure, comprising: the memory structure comprising a resistive random access memory element electrically connected to an extrinsic base region of a bipolar junction transistor; The bipolar junction transistor is an intrinsic base region located between the emitter and collector regions of the bipolar junction transistor; the extrinsic base region above the intrinsic base region; the extrinsic base region having a higher dopant concentration than the intrinsic base region; The method for writing to the memory structure comprises: applying a first voltage to a word line connected to the resistive random access memory element of the memory structure; the first voltage forms a filament in the resistive random access memory element. method.

10. further comprising applying a second voltage to the word line; 10. The method of claim 9, wherein the second voltage is of opposite polarity to the first voltage, and the second voltage removes a portion of the filament in the resistive random access memory element.

11. applying a third voltage between the word line and at least one of a bit line and a select line, the bit line being connected to one of the emitter region or the collector region and the select line being connected to the other; 11. The method of claim 9 or 10, wherein applying the third voltage initiates a read operation in the resistive random access memory element.

12. 12. The method of claim 9, wherein the extrinsic base region of the bipolar junction transistor comprises a triangular-shaped upper region that forms a bottom electrode of the resistive random access memory element.

13. 1. A method of forming a memory structure, comprising: forming a bipolar junction transistor comprising an intrinsic base region located between an emitter region and a collector region, and an extrinsic base region above the intrinsic base region, the extrinsic base region having a higher dopant concentration than the intrinsic base region; forming a resistive random access memory element on the extrinsic base region; Including, the extrinsic base region is a bottom electrode of the resistive random access memory element, and the resistive random access memory element is electrically connected to the extrinsic base region; method.

14. The exogenous base region is forming an extrinsic base layer on an intrinsic base region of the bipolar junction transistor; forming a faceted epitaxial layer on the extrinsic base layer; The method of claim 13 , wherein the compound is formed by

15. The method of claim 14 , wherein the faceted epitaxial layer is a triangular-shaped faceted epitaxial layer having a pointed tip thereon.

16. 16. The method of claim 14 or 15, comprising doping the extrinsic base layer and the epitaxy layer above the extrinsic base layer with a high doping profile.

17. 17. The method of claim 16, comprising doping the epitaxy layer with a higher dopant concentration than the extrinsic base layer.

18. The method of claim 17, wherein forming the resistive random access memory element comprises: on a bottom electrode formed by the extrinsic base region of the bipolar junction transistor; a switching layer directly above the extrinsic base region; a top electrode layer above the switching layer; a metal fill above the top electrode layer; 18. The method of any one of claims 13 to 17, comprising forming

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