Detection Device

Abstract

To provide a detector that can increase the accuracy of detection without causing data overflow.SOLUTION: A detector includes: a sensor unit in which a plurality of detection elements 3 having a photoelectric conversion element 30 are provided in a detection region; and a detection unit (a detection circuit 48) for detecting a difference of the potential between a voltage V<m,1> generated in a first detection element (a detection element 3<m,1>) and a voltage V<m,2> generated in a second detection element (a detection element 3<m,2>) adjacent to the first detection element (the detection element 3<m,1>) in the detection region.SELECTED DRAWING: Figure 11

Description

[Technical Field]

[0001] The present invention relates to a detection device. [Background technology]

[0002] In recent years, optical biosensors have become known as biosensors used for personal authentication and the like. Known biosensors include fingerprint sensors (see, for example, Patent Document 1) and vein sensors. The fingerprint sensor described in Patent Document 1 has a semiconductor photoelectric conversion element such as a photodiode. A plurality of photoelectric conversion elements are arranged on a conductive substrate. The signal output from each photoelectric conversion element changes depending on the amount of light incident on it. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2018 / 0012069 Summary of the Invention [Problem to be solved by the invention]

[0004] For example, when detecting unevenness on the surface of a fingerprint or other object to be detected, or veins inside a finger, if the amplification level of the analog stage is increased to detect slight differences in the signals output from each photoelectric conversion element, data overflow may occur in the subsequent digital processing process, making it impossible to perform proper detection.

[0005] An object of the present invention is to provide a detection device that can improve detection accuracy without causing data overflow. [Means for solving the problem]

[0006] A detection device according to one embodiment of the present disclosure includes a sensor unit having a plurality of detection elements each having a photoelectric conversion element, and a detection unit that detects the potential difference between a voltage generated in a first detection element and a voltage generated in a second detection element adjacent to the first detection element within the detection area. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a cross-sectional view showing a schematic cross-sectional configuration of a detection instrument with an illumination device having a detection device according to an embodiment. [Figure 2] FIG. 2 is a cross-sectional view showing a schematic cross-sectional configuration of a detection instrument with an illumination device according to a modified example. [Figure 3] FIG. 3 is a plan view showing the detection device according to the embodiment. [Figure 4] FIG. 4 is a block diagram illustrating an example of the configuration of a detection device according to an embodiment. [Figure 5] FIG. 5 is a circuit diagram showing a plurality of detection elements. [Figure 6] FIG. 6 is a timing waveform diagram showing an example of the operation of the detection element during the detection period. [Figure 7] FIG. 7 is a diagram showing an example of connection between a detection element and a detection circuit of a detection device according to a comparative example. [Figure 8] FIG. 8 is a diagram showing an example of a timing chart during the detection operation of the detection device according to the comparative example. [Figure 9] FIG. 9 is a diagram showing an example of digital data acquired during the detection operation of the detection device according to the comparative example. [Figure 10] FIG. 10 is a diagram showing an example of connection between the detection element and the detection circuit of the detection device according to the first embodiment. [Figure 11] FIG. 11 is a diagram showing an example of connection between the detection element and the detection circuit of the detection device according to the first embodiment. [Figure 12] FIG. 12 is a diagram showing an example of connection between the detection element and the detection circuit of the detection device according to the first embodiment. [Figure 13]FIG. 13 is a diagram showing an example of a timing chart during the detection operation of the detection device according to the first embodiment. [Figure 14] FIG. 14 is a diagram showing the correspondence relationship between digital data acquired at each sampling timing in the timing chart shown in FIG. [Figure 15] FIG. 15 is a diagram showing an example of digital data acquired during the detection operation of the detection device according to the first embodiment. [Figure 16] FIG. 16 is a diagram illustrating an example of the configuration of the signal line selection circuit and the detection circuit according to the first embodiment. [Figure 17] FIG. 17 is a diagram illustrating an example of a timing chart during the detection operation of the signal line selection circuit and the detection circuit according to the first embodiment. [Figure 18] FIG. 18 is a diagram showing the correspondence relationship between digital data acquired at each sampling timing in the timing chart shown in FIG. [Figure 19] FIG. 19 is a diagram illustrating an example of digital data acquired during the detection operation of the signal line selection circuit and the detection circuit according to the first embodiment. [Figure 20] FIG. 20 is a diagram showing an example of the configuration of a signal line selection circuit and a detection circuit according to a modification of the first embodiment. [Figure 21] FIG. 21 is a diagram illustrating an example of a timing chart during the detection operation of the signal line selection circuit and the detection circuit according to the modification of the first embodiment. [Figure 22] FIG. 22 is a diagram showing the correspondence relationship between digital data acquired at each sampling timing in the timing chart shown in FIG. [Figure 23] FIG. 23 is a diagram showing an example of digital data acquired during the detection operation of the signal line selection circuit and the detection circuit according to the modification of the first embodiment. [Figure 24] FIG. 24 is a diagram illustrating an example of the configuration of a signal line selection circuit and a detection circuit according to the second embodiment. [Figure 25]FIG. 25 is a diagram illustrating an example of a timing chart during the detection operation of the signal line selection circuit and the detection circuit according to the second embodiment. [Figure 26] FIG. 26 is a diagram showing the correspondence relationship between digital data acquired at each sampling timing in the timing chart shown in FIG. [Figure 27] FIG. 27 is a diagram illustrating an example of digital data acquired during the detection operation of the signal line selection circuit and the detection circuit according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Modes for carrying out the invention (embodiments) will be described in detail with reference to the drawings. The present invention is not limited to the contents described in the following embodiments. Furthermore, the components described below include those that can be easily imagined by a person skilled in the art and those that are substantially identical. Furthermore, the components described below can be combined as appropriate. Note that the disclosure is merely an example, and any appropriate modifications that a person skilled in the art can easily conceive while maintaining the gist of the invention are naturally included within the scope of the present invention. Furthermore, for clarity of explanation, the drawings may show the width, thickness, shape, etc. of each part schematically compared to the actual embodiment. However, these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each figure, elements similar to those previously described with reference to the preceding figures are designated by the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0009] Fig. 1 is a cross-sectional view showing a schematic cross-sectional configuration of a detection device with an illumination device having a detection device according to an embodiment. As shown in Fig. 1, a detection device with an illumination device 120 includes a detection device 1, an illumination device 121, and a cover glass 122. The illumination device 121, the detection device 1, and the cover glass 122 are stacked in this order in a direction perpendicular to the surface of the detection device 1. In the present disclosure, the detection device 1 is an optical sensor that detects a finger Fg according to the amount of light received.

[0010] The illumination device 121 has a light irradiation surface 121a that emits light, and emits light L1 from the light irradiation surface 121a toward the detection device 1. The illumination device 121 is a backlight. The illumination device 121 may be, for example, a so-called side-light type backlight that has a light guide plate provided at a position corresponding to the detection area AA and a plurality of light sources lined up at one end or both ends of the light guide plate. For example, a light-emitting diode (LED) that emits light of a predetermined color is used as the light source. The illumination device 121 may also be a so-called direct-type backlight that has a light source (for example, an LED) provided directly below the detection area AA. The illumination device 121 is not limited to a backlight, and may be provided to the side or above the detection device 1, and may emit light L1 from the side or above the finger Fg.

[0011] The detection device 1 is disposed opposite the light irradiation surface 121a of the illumination device 121. Light L1 emitted from the illumination device 121 passes through the detection device 1 and the cover glass 122. The detection device 1 is, for example, a light-reflection type biosensor, and can detect irregularities on the surface of the finger Fg (e.g., a fingerprint) by detecting light L2 reflected from the surface of the finger Fg. Alternatively, the detection device 1 may detect information about the living body by detecting light L2 reflected inside the finger Fg in addition to detecting a fingerprint. The information about the living body includes, for example, an image of blood vessels such as veins, a pulse rate, a pulse wave, etc. The color of the light L1 from the illumination device 121 may be varied depending on the detection target.

[0012] The cover glass 122 is a member for protecting the detection device 1 and the illumination device 121, and covers the detection device 1 and the illumination device 121. The cover glass 122 is, for example, a glass substrate. Note that the cover glass 122 is not limited to a glass substrate, and may be a resin substrate or the like. Also, the cover glass 122 may not be provided. In this case, a protective layer is provided on the surface of the detection device 1, and the finger Fg comes into contact with the protective layer of the detection device 1.

[0013] The detection device 120 with an illumination device may be provided with a display panel instead of the illumination device 121. The display panel may be, for example, an organic light-emitting diode (OLED) display panel or an inorganic light-emitting diode (micro LED, mini LED). Alternatively, the display panel may be a liquid crystal display panel (LCD: Liquid Crystal Display) using liquid crystal elements as display elements, or an electrophoretic display panel (EPD: Electrophoretic Display) using electrophoretic elements as display elements. Even in this case, display light emitted from the display panel passes through the detection device 1, and based on light L2 reflected by the finger Fg, information about the fingerprint and biometrics of the finger Fg can be detected.

[0014] Fig. 2 is a cross-sectional view showing a schematic cross-sectional configuration of a detection device with an illumination device according to a modified example. As shown in Fig. 2, detection device with an illumination device 120 has the detection device 1, an illumination device 121, and a cover glass 122 stacked in this order in a direction perpendicular to the surface of the detection device 1. In this modified example, a display panel such as an organic EL display panel can be used as the illumination device 121.

[0015] Light L1 emitted from the illumination device 121 passes through the cover glass 122 and is then reflected by the finger Fg. Light L2 reflected by the finger Fg passes through the cover glass 122 and then passes through the illumination device 121. The detection device 1 receives the light L2 that has passed through the illumination device 121, thereby enabling detection of information related to a living body, such as a fingerprint.

[0016] 3 is a plan view showing a detection device according to an embodiment. As shown in FIG. 3, the detection device 1 includes a substrate 21, a sensor unit 10, a first gate line driving circuit 15A, a second gate line driving circuit 15B, a signal line selection circuit 16, a detection circuit 48, a control circuit 102, and a power supply circuit 103.

[0017] A control board 101 is electrically connected to the substrate 21 via a wiring board 110. The wiring board 110 is, for example, a flexible printed circuit board or a rigid board. A detection circuit 48 is provided on the wiring board 110. A control circuit 102 and a power supply circuit 103 are provided on the control board 101. The control circuit 102 is, for example, an FPGA (Field Programmable Gate Array). The control circuit 102 supplies control signals to the sensor unit 10, the first gate line driving circuit 15A, the second gate line driving circuit 15B, and the signal line selection circuit 16 to control the detection operation of the sensor unit 10. The power supply circuit 103 supplies voltage signals such as a power supply voltage Vsf and a common voltage Vcom (see FIG. 5 ) to the sensor unit 10, the first gate line driving circuit 15A, the second gate line driving circuit 15B, and the signal line selection circuit 16.

[0018] The substrate 21 has a detection area AA and a peripheral area GA. The detection area AA is an area that overlaps with the multiple detection elements 3 of the sensor unit 10. The peripheral area GA is an area outside the detection area AA that does not overlap with the detection elements 3. In other words, the peripheral area GA is an area between the periphery of the detection area AA and the edge of the substrate 21. The first gate line driving circuit 15A, the second gate line driving circuit 15B, and the signal line selection circuit 16 are provided in the peripheral area GA.

[0019] Each of the multiple detection elements 3 of the sensor unit 10 is an optical sensor having a photoelectric conversion element 30. The photoelectric conversion element 30 is a photodiode that outputs an electrical signal corresponding to the light irradiated thereon. More specifically, the photoelectric conversion element 30 is a PIN (Positive Intrinsic Negative) photodiode. The detection elements 3 are arranged in a matrix in the detection area AA. The photoelectric conversion elements 30 of the multiple detection elements 3 perform detection in accordance with gate drive signals (e.g., a reset control signal RST and a read control signal RD) supplied from the first gate line drive circuit 15A and the second gate line drive circuit 15B. The multiple photoelectric conversion elements 30 output an electrical signal corresponding to the light irradiated thereon as a detection signal Vdet to the signal line selection circuit 16. The detection device 1 detects information related to a living body based on the detection signals Vdet from the multiple detection elements 3.

[0020] The first gate line driving circuit 15A, the second gate line driving circuit 15B, and the signal line selection circuit 16 are provided in the peripheral area GA. Specifically, the first gate line driving circuit 15A and the second gate line driving circuit 15B are provided in a region of the peripheral area GA extending along the second direction Dy. The signal line selection circuit 16 is provided in a region of the peripheral area GA extending along the first direction Dx, and is provided between the sensor unit 10 and the detection circuit 48. The first gate line driving circuit 15A and the second gate line driving circuit 15B are arranged on either side of the detection area AA in the first direction Dx. However, the first gate line driving circuit 15A and the second gate line driving circuit 15B may be formed as a single circuit and arranged along one side of the detection area AA.

[0021] The first direction Dx is a direction in a plane parallel to the substrate 21. The second direction Dy is a direction in a plane parallel to the substrate 21, and is a direction perpendicular to the first direction Dx. The second direction Dy may intersect with the first direction Dx without being perpendicular thereto. The third direction Dz is a direction perpendicular to the first direction Dx and the second direction Dy, and is a normal direction to the substrate 21.

[0022] The number of detection elements 3 lined up in the first direction Dx in the detection area AA is, for example, 1080. The number of detection elements 3 lined up in the second direction Dy in the detection area AA is, for example, 2340. In this case, in the detection area AA, 2340 element rows, each of which has 1080 detection elements 3 lined up in the first direction Dx, are lined up in the second direction Dy. In other words, in the detection area AA, 1080 element columns, each of which has 2340 detection elements 3 lined up in the second direction Dy, are lined up in the first direction Dx.

[0023] Fig. 4 is a block diagram showing an example of the configuration of a detection device according to an embodiment. As shown in Fig. 4, the detection device 1 further includes a detection control circuit 11 and a detection unit 40. Some or all of the functions of the detection control circuit 11 are included in a control circuit 102. In addition, some or all of the functions of the detection unit 40 other than the detection circuit 48 are included in the control circuit 102.

[0024] The detection control circuit 11 is a circuit that supplies control signals to the first gate line drive circuit 15A, the second gate line drive circuit 15B, the signal line selection circuit 16, and the detection unit 40, respectively, and controls their operations. The detection control circuit 11 supplies various control signals, such as a synchronization signal STV and a clock signal CK, to the first gate line drive circuit 15A and the second gate line drive circuit 15B. The detection control circuit 11 also supplies various control signals, such as a signal line selection signal ASW, to the signal line selection circuit 16 during a detection period in which detection processing is performed. In the present disclosure, the detection control circuit 11 also supplies various control signals, such as a differential input switching signal SSW, to the detection circuit 48 via a detection timing control circuit 47, which will be described later, during a detection period in which detection processing is performed.

[0025] The first gate line driving circuit 15A and the second gate line driving circuit 15B are circuits that drive multiple gate lines (read control scanning lines GLrd and reset control scanning lines GLrst (see FIG. 5)) based on various control signals. The first gate line driving circuit 15A and the second gate line driving circuit 15B sequentially or simultaneously select multiple gate lines and supply gate driving signals (e.g., reset control signal RST, read control signal RD) to the selected gate lines. In this way, the first gate line driving circuit 15A and the second gate line driving circuit 15B select multiple photoelectric conversion elements 30 connected to the gate lines.

[0026] The signal line selection circuit 16 is a switch circuit that sequentially or simultaneously selects a plurality of output signal lines SL (see FIG. 5). The signal line selection circuit 16 is, for example, a multiplexer. The signal line selection circuit 16 electrically connects the selected output signal line SL to the detection circuit 48 based on a signal line selection signal ASW supplied from the detection control circuit 11. As a result, the signal line selection circuit 16 outputs the detection signal Vdet from the detection element 3 to the detection unit 40. Note that the signal line selection circuit 16 may not be provided. In this case, the output signal line SL may be directly connected to the detection circuit 48.

[0027] The detection unit 40 includes a detection circuit 48 , a signal processing circuit 44 , a coordinate extraction circuit 45 , a storage circuit 46 , and a detection timing control circuit 47 .

[0028] In the present disclosure, the detection unit 40 is a circuit that detects biometric information such as the irregularities on the surface of the object to be detected, such as the fingerprint of the finger Fg, and the veins inside the finger, based on a control signal supplied from the detection control circuit 11 and a detection signal Vdet supplied from the detection element 3.

[0029] The detection timing control circuit 47 controls the detection circuit 48, the signal processing circuit 44, and the coordinate extraction circuit 45 based on a control signal supplied from the detection control circuit 11 so that they operate in synchronization with each other.

[0030] The detection circuit 48 is, for example, an analog front-end circuit (AFE). The detection circuit 48 is a signal processing circuit having at least the functions of a detection signal amplifier circuit 42 and an A / D conversion circuit 43. The detection signal amplifier circuit 42 amplifies the detection signal Vdet. The A / D conversion circuit 43 converts the analog signal output from the detection signal amplifier circuit 42 into a digital signal. In the present disclosure, the detection signal amplifier circuit 42 of the detection circuit 48 is an analog circuit including a differential amplifier circuit, which will be described later, and a circuit subsequent to the A / D conversion circuit 43 is a digital signal processing circuit that processes the digital data converted by the A / D conversion circuit 43.

[0031] The signal processing circuit 44 is a logic circuit that detects a predetermined physical quantity input to the sensor unit 10 based on the output signal of the detection circuit 48. The signal processing circuit 44 performs predetermined processing on the output signal of the detection circuit 48.

[0032] The memory circuit 46 temporarily stores the signals calculated by the signal processing circuit 44. The memory circuit 46 may be, for example, a RAM (Random Access Memory), a register circuit, or the like.

[0033] The coordinate extraction circuit 45 is a logic circuit that determines the detection coordinates of the unevenness of the surface of a detection object such as a finger Fg. Specifically, the coordinate extraction circuit 45 generates two-dimensional information (e.g., a picture image) that indicates the shape of the unevenness of the surface of a detection object such as a finger Fg. The coordinate extraction circuit 45 may also be configured to determine the detection coordinates of blood vessels in the finger Fg or palm, for example.

[0034] Next, an example of the circuit configuration and operation of the detection device 1 will be described. Fig. 5 is a circuit diagram showing a plurality of detection elements. As shown in Fig. 5, the detection element 3 has a photoelectric conversion element 30, a reset transistor Mrst, a readout transistor Mrd, and a source follower transistor Msf. Furthermore, the detection element 3 is provided with a reset control scanning line GLrst and a readout control scanning line GLrd as detection drive lines (gate lines), and an output signal line SL as wiring for signal readout.

[0035] The reset control scanning line GLrst, the readout control scanning line GLrd, and the output signal line SL are each connected to a plurality of detection elements 3. Specifically, the reset control scanning line GLrst and the readout control scanning line GLrd extend in a first direction Dx (see FIG. 3) and are connected to a plurality of detection elements 3 arranged in the first direction Dx. Furthermore, the output signal line SL extends in a second direction Dy and is connected to a plurality of detection elements 3 arranged in the second direction Dy. The output signal line SL is a wiring through which signals from a plurality of transistors (readout transistors Mrd and source follower transistors Msf) are output.

[0036] The reset transistor Mrst, the readout transistor Mrd, and the source follower transistor Msf are provided for one photoelectric conversion element 30. Each of the multiple transistors in the detection element 3 is configured as an n-type TFT (Thin Film Transistor). However, without being limited to this, each transistor may be configured as a p-type TFT.

[0037] A common voltage Vcom is applied to the anode of the photoelectric conversion element 30. The cathode of the photoelectric conversion element 30 is connected to a node N1. The node N1 is connected to one of the source or drain of the reset transistor Mrst and the gate of the source follower transistor Msf. When light is irradiated onto the photoelectric conversion element 30, a signal (charge) output from the photoelectric conversion element 30 is accumulated in a capacitance element formed at the node N1.

[0038] The gate of the reset transistor Mrst is connected to a reset control scanning line GLrst. A reset voltage Vrst is supplied to the other of the source or drain of the reset transistor Mrst. When the reset transistor Mrst is turned on (conductive) in response to a reset control signal RST supplied from the first gate line driving circuit 15A, the voltage of the node N1 is reset to the reset voltage Vrst. The common voltage Vcom has a voltage lower than the reset voltage Vrst, and the photoelectric conversion element 30 is reverse-bias driven.

[0039] The source follower transistor Msf is connected between a terminal to which a power supply voltage Vsf is supplied and the readout transistor Mrd (node ​​N2). The gate of the source follower transistor Msf is connected to the node N1. A signal (voltage) corresponding to the signal (charge) generated in the photoelectric conversion element 30 is supplied to the gate of the source follower transistor Msf. As a result, the source follower transistor Msf outputs a signal voltage corresponding to the signal (charge) generated in the photoelectric conversion element 30 to the readout transistor Mrd.

[0040] The readout transistor Mrd is connected between the source (node ​​N2) of the source follower transistor Msf and the output signal line SL. The gate of the readout transistor Mrd is connected to the readout control scanning line GLrd. When the readout transistor Mrd is turned on in response to a readout control signal RD supplied from the second gate line drive circuit 15B, the signal output from the source follower transistor Msf, i.e., a signal (voltage) corresponding to the signal (charge) generated in the photoelectric conversion element 30, is output to the output signal line SL as the detection signal Vdet.

[0041] 5, the reset transistor Mrst and the readout transistor Mrd each have a single-gate structure, but the reset transistor Mrst and the readout transistor Mrd may each have a so-called double-gate structure in which two transistors are connected in series, or may have a structure in which three or more transistors are connected in series. Furthermore, the circuit of one detection element 3 is not limited to a structure having three transistors: the reset transistor Mrst, the source-follower transistor Msf, and the readout transistor Mrd. The detection element 3 may have two transistors, or may have four or more transistors.

[0042] 6 is a timing waveform diagram showing an example of the operation of the detection element during the detection period. As shown in FIG. 6, the detection element 3 performs detection during the detection period in the order of the reset period Prst, the exposure period Pch, and the readout period Pdet. The power supply circuit 103 supplies a common voltage Vcom to the anode of the photoelectric conversion element 30 throughout the reset period Prst, the exposure period Pch, and the readout period Pdet.

[0043] At time t0, the detection control circuit 11 sets the reset control signal RST supplied to the reset control scanning line GLrst to high (high-level voltage), starting the reset period Prst. During the reset period Prst, the reset transistor Mrst is turned on (conductive), and the voltage at node N1 rises to the reset voltage Vrst. As a result, the photoelectric conversion element 30 is reverse-biased by the potential difference between the reset voltage Vrst and the common voltage Vcom. Furthermore, because the readout transistor Mrd is off (non-conductive), the source of the source follower transistor Msf is charged by the power supply voltage Vsf, and the voltage at node N2 rises.

[0044] At time t1, the detection control circuit 11 sets the read control signal RD supplied to the read control scanning line GLrd to high (high-level voltage). This turns on the read transistor Mrd (conducting state), and the voltage of the node N2 becomes (Vrst-Vthsf). Vthsf is the threshold voltage Vthsf of the source follower transistor Msf.

[0045] At time t2, the detection control circuit 11 sets the reset control signal RST to low (low-level voltage), ending the reset period Prst and starting the exposure period Pch. During the exposure period Pch, the reset transistor Mrst is turned off (non-conducting). A signal corresponding to the light irradiated on the photoelectric conversion element 30 is accumulated, and the voltage of the node N1 drops to (Vrst-Vphoto). Specifically, during the reset period Prst, for example, charges accumulated in the self-capacitance or a capacitance (not shown) within the photoelectric conversion element 30 are discharged by light irradiation, and a signal corresponding to the irradiated light is accumulated. Note that Vphoto is a signal (voltage fluctuation) corresponding to the light irradiated on the photoelectric conversion element 30.

[0046] At time t3, the voltage of the detection signal Vdet1 output from the output signal line SL becomes (Vrst-Vthsf-Vrdon), where Vrdon is the voltage drop caused by the on-resistance of the read transistor Mrd.

[0047] At time t3, the detection control circuit 11 sets the read control signal RD to low (low-level voltage). This turns the read transistor Mrd off (non-conductive state), and the voltage of the node N2 becomes constant at (Vrst-Vthsf). In addition, a load is applied so that the voltage of the detection signal Vdet output from the output signal line SL becomes low (low-level voltage).

[0048] At time t4, the detection control circuit 11 sets the read control signal RD to high (high-level voltage). As a result, after the exposure period Pch ends, the read transistor Mrd turns on (conducting state) and the read period Pdet begins. The voltage of the node N2 changes to (Vrst-Vthsf-Vphoto) in accordance with the signal Vphoto. The voltage of the detection signal Vdet2 output during the read period Pdet drops by the signal Vphoto from the voltage of the detection signal Vdet1 acquired at time t3, to (Vrst-Vthsf-Vrdon-Vphoto).

[0049] The detection unit 40 can detect light irradiated onto the photoelectric conversion element 30 based on the potential difference (Vphoto) between the detection signal Vdet1 detected during the reset period Prst and the detection signal Vdet2 detected during the readout period Pdet. While FIG. 6 shows an example of the operation of one detection element 3, the first gate line drive circuit 15A and the second gate line drive circuit 15B sequentially scan the reset control scanning line GLrst and the readout control scanning line GLrd in a time-division manner, thereby enabling detection by the detection elements 3 across the entire detection area AA. While FIG. 6 shows an example of detecting light irradiated onto the photoelectric conversion element 30 based on the potential difference between the detection signal Vdet1 detected during the reset period Prst and the detection signal Vdet2 detected during the readout period Pdet, the present invention is not limited to this. Alternatively, light irradiated onto the photoelectric conversion element 30 may be detected using the voltage of the detection signal Vdet2 detected during the readout period Pdet.

[0050] 7 is a diagram showing an example of connections between a detection element and a detection circuit of a detection device according to a comparative example. In the following description, a parameter corresponding to m columns and n rows (m is a natural number equal to or less than M, and n is a natural number equal to or less than N) is referred to as "X<m,n> Also, the parameter corresponding to the mth column is called "X <m>" Also, the parameter corresponding to the nth row is called "X <n>" is also called.

[0051] In Figure 7, m rows of detector elements 3<m,1> ,3<m,2> ,3<m,3> , and the m-th column output signal line SL of the detection circuit 48. <m>An example of connection via is shown.

[0052] As described above, the photoelectric conversion element 30 is reverse biased during the reset period Prst (see FIG. 6). At this time, the photoelectric conversion element 30 is applied with a reverse bias voltage Vpn, which is the potential difference between the reset voltage Vrst and the common voltage Vcom.

[0053] A constant current source for supplying a bias current Ib to the read transistor Mrd is connected to the detection circuit 48. This allows the detection voltage V <m>(The voltage of the detection signal Vdet1 detected in the reset period Prst and the voltage of the detection signal Vdet2 detected in the readout period Pdet) can be detected. This constant current source may be provided in the detection circuit 48 or in the substrate 21. In FIG. 7, the capacitance Cp may be a parasitic capacitance of the photoelectric conversion element 30 or an individual capacitance outside the photoelectric conversion element 30.

[0054] The detection circuit 48 detects the output signal line SL <m>The detection signal amplifier circuit 42 of the detection circuit 48 is connected to the output signal line SL <m>The voltage corresponding to the voltage of the input voltage is output to the A / D conversion circuit 43.

[0055] Specifically, the detection signal amplifier circuit 42 includes a differential amplifier circuit 421 and a first capacitance element C1 connected to the non-inverting input (+) of the differential amplifier circuit 421. <m>and a second capacitance element C2 connected to the inverting input (-) of the differential amplifier circuit 421. <m>In the comparative example, the differential amplifier circuit 421 has a non-inverting input (+) connected to an output signal line SL <m>The detection voltage V of the detection element 3 is <m>is applied, and the detection voltage V <m>The charge corresponding to the first capacitance element C1 <m>Furthermore, the differential amplifier circuit 421 has a reference voltage Vref applied to its inverting input (-), and a charge corresponding to the reference voltage Vref is stored in the second capacitance element C2 <m>will be charged.

[0056] FIG. 8 is a diagram showing an example of a timing chart during the detection operation of the detection device according to the comparative example.

[0057] During the reset period Prst, the first gate line driving circuit 15A drives the reset control scanning line GLrst based on the synchronization signal STV and the clock signal CK output from the detection control circuit 11. <1> ,GLrst <2> ,GLrst <3> ,... are sequentially set to "H" (high-level voltage). As a result, the reset transistor Mrst of each detection element 3 is sequentially turned on (conductive state), and the voltage at node N1 rises to the reset voltage Vrst. At this time, the photoelectric conversion element 30 is reverse-biased by the voltage difference between the reset voltage Vrst and the common voltage Vcom. Also, since the readout transistor Mrd is off (non-conductive state), the source of the source follower transistor Msf is charged by the power supply voltage Vsf, and the voltage at node N2 rises.

[0058] During the exposure period Pch after the reset period Prst, the voltage of the node N1 decreases in accordance with the light irradiated onto the photoelectric conversion element 30.

[0059] The second gate line driving circuit 15B drives the read control scanning line GLrd based on the clock signal CK output from the detection control circuit 11 during the read period Pdet after the exposure period Pch. <1> ,GLrd <2> ,GLrd <3> , . . . are sequentially set to "H" (high level voltage). As a result, the readout transistors Mrd of the detection elements 3 are sequentially turned on (conductive state), and the output signal line SL <m>The detection voltage V of the detection element 3 is <m>The charge corresponding to the first capacitance element C1 <m>will be charged.

[0060] The A / D conversion circuit 43 detects the read control scanning line GLrd <m>During the "H" period, the first capacitance element C1 <m>The detection voltage V <m>and the second capacitance element C2 <m>The potential difference between the reference voltage Vref charged to the capacitor 421 and the amplified value is converted into a digital signal.

[0061] Specifically, the A / D conversion circuit 43 outputs a read control scan line GLrd <1> During the "H" period, the first capacitance element C1 <m>The detection voltage V<m,1> and the second capacitance element C2 <m>The potential difference between this and the reference voltage Vref is converted into a digital signal.

[0062] The A / D conversion circuit 43 also outputs a read control scan line GLrd <2> During the "H" period, the first capacitance element C1 <m>The detection voltage V<m,2> and the second capacitance element C2 <m>The potential difference between this and the reference voltage Vref is converted into a digital signal.

[0063] The A / D conversion circuit 43 also outputs a read control scan line GLrd <3> During the "H" period, the first capacitance element C1 <m>The detection voltage V<m,3> and the second capacitance element C2 <m>The potential difference between this and the reference voltage Vref is converted into a digital signal.

[0064] Similarly, the A / D conversion circuit 43 outputs the read control scanning line GLrd <n>During each "H" period, the first capacitance element C1 <m>The detection voltage V<m,n> and the second capacitance element C2 <m>The potential difference between this and the reference voltage Vref is converted into a digital signal.

[0065] In this way, the read control scanning line GLrd <n>During the "H" period of each detector element 3<m,n> By providing sampling timing for acquiring digital data corresponding to the detection elements 3 in the entire detection area AA,<m,n> Digital data corresponding to the detected voltage at the input terminal can be obtained.

[0066] 9 is a diagram showing an example of digital data acquired during the detection operation of the detection device according to the comparative example.<m,n> The digital data corresponding to the detected voltage at<m,n> -Vref". Here, digital data when the amplification degree of the differential amplifier circuit 421 is "1" is shown as an example.

[0067] When the amplification degree of the differential amplifier circuit 421 is “k”, the detection element 3<m,n> The digital data corresponding to "k × (V<m,n> -Vref)" where, for example, when detecting a fingerprint or biological information of a finger Fg, each detection element 3<m,n> It is necessary to detect the difference between the detection elements 3 with high accuracy.<m,n> Since digital data corresponding to the detected voltage for each detection element is acquired, the data value of each digital data becomes large, and the data value of each detection element 3<m,n> If the amplification degree of the differential amplifier circuit 421 is increased in order to detect the difference in the detection voltage between the two with high accuracy, data overflow may occur in the downstream digital signal processing circuit (e.g., the signal processing circuit 44 or the coordinate extraction circuit 45), which may reduce the accuracy of fingerprint detection.

[0068] In the present disclosure, digital data corresponding to the potential difference of the detection voltage between adjacent detection elements 3 is acquired, and<m,n> The data value of each digital data is made smaller than that of the comparative example in which digital data corresponding to the detection voltage for each detection element 3 is acquired. This makes it possible to suppress data overflow in the subsequent digital signal processing circuit (for example, the signal processing circuit 44 or the coordinate extraction circuit 45), thereby improving the accuracy of fingerprint detection. Below, the configuration and operation for acquiring digital data corresponding to the potential difference in the detection voltage between adjacent detection elements 3 will be described.

[0069] (Embodiment 1) 10, 11, and 12 are diagrams showing examples of connections between the detection elements and the detection circuit of the detection device according to embodiment 1. Fig. 13 is a diagram showing an example of a timing chart during the detection operation of the detection device according to embodiment 1. Fig. 10 shows the readout control scanning line GLrd shown in Fig. 13. <1> 11 shows an example of connection during the "H" period of the read control scanning line GLrd shown in FIG. <2> 12 shows an example of connection during the "H" period of the read control scanning line GLrd shown in FIG. <3> 1 shows an example of connections during the "H" period of the above-mentioned comparative example. Note that components having the same functions as those in the comparative example described above are given the same reference numerals and their explanations will be omitted.

[0070] The detection signal amplifier circuit 42 according to the first embodiment includes a differential amplifier circuit 421 and a first capacitance element C1 connected to the non-inverting input (+) of the differential amplifier circuit 421. <m>and a second capacitance element C2 connected to the inverting input (-) of the differential amplifier circuit 421. <m>and the output signal line SL <m>The detection voltage V is input via <m>to either the non-inverting input (+) or the inverting input (−) of the differential amplifier circuit 421.

[0071] In the first embodiment, the differential amplifier circuit 421 has a non-inverting input (+) connected to the detection element 3 in the odd-numbered row via the switch circuit 422.<m,odd> Detection voltage V<m,odd> is applied, and the detection voltage V<m,odd> The charge corresponding to the first capacitance element C1 <m>The differential amplifier circuit 421 also has an inverting input (-) connected to the detection element 3 in the even-numbered row via a switch circuit 422.<m,even> Detection voltage V<m,even> is applied, and the detection voltage V<m,even> The charge corresponding to the second capacitance element C2 <m>will be charged.

[0072] The detection control circuit 11 outputs the read control scanning line GLrd <m>In synchronization with this, the control state of the switch circuit 422 is switched. <m>is electrically connected to either the non-inverting input (+) or the inverting input (−) of the differential amplifier circuit 421.

[0073] Specifically, the detection control circuit 11 controls the read control scanning lines GLrd of the odd-numbered rows, for example. <odd>During the "H" (high level voltage) period, the differential input switching signal SSW is set to "H" (high level voltage), and the non-inverting input (+) of the differential amplifier circuit 421 is connected to the detection element 3 in the odd-numbered row.<m,odd> Detection voltage V<m,odd> is applied.

[0074] The detection control circuit 11 also detects, for example, the read control scanning lines GLrd of the even-numbered rows. <even>During the "H" (high level voltage) period, the differential input switching signal SSW is set to "L" (low level voltage), and the inverting input (-) of the differential amplifier circuit 421 is connected to the detecting element 3 in the even-numbered row.<m,even> Detection voltage V<m,even> is applied.

[0075] The A / D conversion circuit 43 detects the read control scanning line GLrd <m>During the "H" period, the first capacitance element C1 <m>The detection voltage V<m,odd> and the second capacitance element C2 <m>The detection voltage V<m,even> The potential difference between these is amplified by a differential amplifier circuit 421 and converted into a digital signal.

[0076] Specifically, the read control scan line GLrd <1> During the "H" period, the differential input switching signal SSW is controlled to "H".<m,1> Detection voltage V<m,1> The charge corresponding to the first capacitance element C1 <m>will be charged.

[0077] Next read control scan line GLrd <2> During the "H" period, the differential input switching signal SSW is controlled to "L".<m,2> Detection voltage V<m,2> The charge corresponding to the second capacitance element C2 <m>At this time, the first capacitance element C1 <m>The charge stored in the electrode is retained.

[0078] This read control scan line GLrd <2> 13, the A / D conversion circuit 43 detects the first capacitance element C1 <m>The detection voltage V<m,1> and the second capacitance element C2 <m>The detection voltage V<m,2> The potential difference between these is converted into a digital signal.

[0079] Next read control scan line GLrd <3> During the "H" period, the differential input switching signal SSW is controlled to "H".<m,3> Detection voltage V<m,3> The charge corresponding to the first capacitance element C1 <m>At this time, the second capacitance element C2 <m>The charge stored in the electrode is retained.

[0080] This read control scan line GLrd <3> 13, the A / D conversion circuit 43 detects the first capacitance element C1 <m>The detection voltage V<m,3> and the second capacitance element C2 <m>The detection voltage V<m,2> The potential difference between these is converted into a digital signal.

[0081] It is desirable that the digital data acquired at sampling timing B undergoes sign inversion processing in a subsequent digital signal processing circuit (for example, signal processing circuit 44) after digital conversion.

[0082] Similarly, the A / D conversion circuit 43 outputs the read control scanning line GLrd <n>During each "H" period, the first capacitance element C1 <m>The detection voltage V<m,odd> and the second capacitance element C2 <m>The detection voltage V<m,even> The A / D conversion circuit 43 converts the potential difference between the first capacitance element C1 into a digital signal at a sampling timing C shown in FIG. <m>The detection voltage V<m,N> and the second capacitance element C2 <m>The detection voltage V<m,N-1> The potential difference between these is converted into a digital signal.

[0083] The above-mentioned operation is carried out for all output signal lines SL <m>By performing the measurement in accordance with the above, digital data corresponding to the potential difference of the detected voltage between two detecting elements 3 adjacent to each other in the second direction Dy can be obtained.

[0084] Fig. 14 is a diagram showing the correspondence relationship of digital data acquired at each sampling timing of the timing chart shown in Fig. 13. Fig. 15 is a diagram showing an example of digital data acquired during the detection operation of the detection device according to the first embodiment. Fig. 15 illustrates digital data when the amplification degree of the differential amplifier circuit 421 is "1". In Fig. 15, for example, the detection element 3<m,n> and detector element 3<m,n+1> The digital data corresponding to the potential difference between<m,n> -V<m,n+1> " is indicated.

[0085] When the amplification degree of the differential amplifier circuit 421 is “k”, the detection element 3<m,n> and detector element 3<m,n+1> The digital data corresponding to the potential difference between<m,n> -V<m,n+1> ". The digital data acquired by the configuration and operation of the first embodiment described above is digital data corresponding to the potential difference in the detection voltage between two adjacent detection elements 3 in the second direction Dy, and therefore has a value relatively smaller than that of the digital data acquired by the configuration and operation of the comparative example shown in FIGS. 7 and 8. Therefore, data overflow does not occur in the subsequent digital signal processing circuit (e.g., the signal processing circuit 44 or the coordinate extraction circuit 45), and the amplification degree of the differential amplifier circuit 421 can be set to a value larger than that of the comparative example. This makes it possible to achieve fingerprint detection with higher accuracy than that of the comparative example. In the configuration of the first embodiment, the number of data in the column direction (the second direction Dy, the vertical direction shown in FIG. 15) is N-1.

[0086] A more specific configuration example and operation of the detection device 1 according to embodiment 1 will be described below. Fig. 16 is a diagram showing an example of the configuration of a signal line selection circuit and a detection circuit according to embodiment 1. Fig. 17 is a diagram showing an example of a timing chart during detection operation of the signal line selection circuit and the detection circuit according to embodiment 1. Note that the reset period Prst and the exposure period Pch are omitted in Fig. 17.

[0087] In the examples shown in FIGS. 16 and 17, the signal line selection circuit 16 receives the signal line selection signal ASW supplied from the detection control circuit 11. <1> ,ASW <2> ,···,ASW (P is a natural number equal to or less than M / 2), the output signal line SL ,SL<P+p> ,···,SL<M-P+p> (p is a natural number equal to or less than P) are simultaneously selected, and the selected output signal lines SL are electrically connected to the detection circuit 48. In the examples shown in FIGS. 16 and 17, a plurality of output signal lines SL simultaneously selected by the signal line selection circuit 16 are electrically connected to the detection circuit 48. ,SL<P+p> ,···,SL<M-P+p> For each of the inputs, one differential amplifier circuit 421_1, 421_2, . . . , 421_M / P is provided.

[0088] The switch circuits 422_1, 422_2, . . . , 422_M / P of the detection circuit 48 select the detection voltage V input via the signal line selection circuit 16 based on the differential input switching signal SSW supplied from the detection control circuit 11 via the detection timing control circuit 47.<m,n> is applied to either the non-inverting input (+) or the inverting input (-) of the differential amplifier circuits 421_1, 421_2, . . . , 421_M / P.

[0089] The detection control circuit 11 detects the read period Pdet In the signal line selection signal ASW The second gate line driving circuit 15B sets each signal line selection signal ASW During the "H" period, the read control scanning line GLrd <1> ,GLrd <2> ,GLrd <3> ,···,GLrd <n>and supplies a read control signal RD to the selected read control scanning line GLrd.<m,n> Detection voltage V<m,n> is supplied.

[0090] Read period Pdet <1> In this case, the detection circuit 48 detects the output signal line SL <1> and obtains digital data corresponding to the potential difference between the detected voltage of the detection element 3<1, n> connected to the detector 3<1, n+1>.

[0091] Specifically, the read period Pdet <1> Readout control scan line GLrd <1> During the "H" period of the differential input switching signal SSW, the differential input switching signal SSW is controlled to "H". As a result, a charge according to the detection voltage V<1,1> of the detection element 3<1,1> is charged in the first capacitance element C1_1, and the detection element 3<P+1,1> Detection voltage V<P+1,1> The first capacitance element C1_2 is charged with a charge corresponding to the<M-P+1,1> Detection voltage V<M-P+1,1> The first capacitance element C1_M / P is charged with a charge according to the charge.

[0092] Next read control scan line GLrd <2> During the "H" period of the differential input switching signal SSW, the differential input switching signal SSW is controlled to "L". As a result, a charge according to the detection voltage V<1,2> ​​of the detection element 3<1,2> ​​is charged in the second capacitance element C2_1, and the detection element 3<P+1,2> Detection voltage V<P+1,2> The second capacitance element C2_2 is charged with a charge corresponding to the<M-P+1,2> Detection voltage V<M-P+1,2> The second capacitance element C2_M / P is charged with a charge according to the charge amount. At this time, the charges stored in the first capacitance elements C1_1, C1_2, . . . , C1_M / P are held.

[0093] This reading period Pdet <1> Readout control scan line GLrd <2> 17, the A / D conversion circuit 43 converts the potential difference between the detection voltage V<1,1> charged in the first capacitance element C1_1 and the detection voltage V<1,2> ​​charged in the second capacitance element C2_1 into a digital signal, and converts the potential difference between the detection voltage V<1,1> charged in the first capacitance element C1_2 into a digital signal.<P+1,1> Detection voltage V<P+1,1> and the detection element 3 charged in the second capacitance element C2_2<P+1,2> Detection voltage V<P+1,2> The potential difference between the first capacitance element C1_M / P and the second capacitance element C1_M / P is converted into a digital signal.<M-P+1,1> Detection voltage V<M-P+1,1> and the detection element 3 charged in the second capacitance element C2_M / P<M-P+1,2> Detection voltage V<M-P+1,2> The potential difference between these is converted into a digital signal.

[0094] Also, the following read control scan line GLrd <3> During the "H" period of the differential input switching signal SSW, the differential input switching signal SSW is controlled to "H". As a result, a charge according to the detection voltage V<1,3> of the detection element 3<1,3> is charged in the first capacitance element C1_1, and the detection element 3<P+1,3> Detection voltage V<P+1,3> The first capacitance element C1_2 is charged with a charge corresponding to the<M-P+1,3> Detection voltage V<M-P+1,3> The first capacitance element C1_M / P is charged with a charge according to the voltage Vcc. At this time, the charges stored in the second capacitance elements C2_1, C2_2, . . . , C2_M / P are held.

[0095] This reading period Pdet <1> Readout control scan line GLrd <3> 17, the A / D conversion circuit 43 converts the potential difference between the detection voltage V<1,3> charged in the first capacitance element C1_1 and the detection voltage V<1,2> ​​charged in the second capacitance element C2_1 into a digital signal, and converts the potential difference between the detection voltage V<1,3> charged in the first capacitance element C1_2 into a digital signal.<P+1,3> Detection voltage V<P+1,3> and the detection element 3 charged in the second capacitance element C2_2<P+1,2> Detection voltage V<P+1,2> The potential difference between the first capacitance element C1_M / P and the second capacitance element C1_M / P is converted into a digital signal.<M-P+1,3> Detection voltage V<M-P+1,3> and the detection element 3 charged in the second capacitance element C2_M / P<M-P+1,2> Detection voltage V<M-P+1,2> The potential difference between the input and output terminals is converted into a digital signal. A subsequent digital signal processing circuit (for example, the signal processing circuit 44) performs sign inversion processing on the digitally converted data.

[0096] Also, the read period Pdet <1> Readout control scan line GLrd <n>During the "H" period of the differential input switching signal SSW, the differential input switching signal SSW is controlled to "H". As a result, a charge according to the detection voltage V<1,N> of the detection element 3<1,N> is charged in the first capacitance element C1_1, and the detection element 3<P+1,N> Detection voltage V<P+1,N> The first capacitance element C1_2 is charged with a charge corresponding to the<M-P+1,N> Detection voltage V<M-P+1,N> The first capacitance element C1_M / P is charged with a charge according to the voltage Vcc. At this time, the charges stored in the second capacitance elements C2_1, C2_2, . . . , C2_M / P are held.

[0097] This reading period Pdet <1> Readout control scan line GLrd <n>17, the A / D conversion circuit 43 converts the potential difference between the detection voltage V<1,N> charged in the first capacitance element C1_1 and the detection voltage V<1,N-1> charged in the second capacitance element C2_1 into a digital signal, and converts the potential difference between the detection voltage V<1,N> charged in the first capacitance element C1_2 into a digital signal.<P+1,N> Detection voltage V<P+1,N> and the detection element 3 charged in the second capacitance element C2_2<P+1,N-1> Detection voltage V<P+1,N-1> The potential difference between the first capacitance element C1_M / P and the second capacitance element C1_M / P is converted into a digital signal.<M-P+1,N> Detection voltage V<M-P+1,N> and the detection element 3 charged in the second capacitance element C2_M / P<M-P+1,N-1> Detection voltage V<M-P+1,N-1> The potential difference between the input and output terminals is converted into a digital signal. A subsequent digital signal processing circuit (for example, the signal processing circuit 44) performs sign inversion processing on the digitally converted data.

[0098] Also, the read period Pdet <2> In this case, the detection circuit 48 detects the output signal line SL <2> and obtains digital data corresponding to the potential difference between the detection voltage of the detection element 3<2,n> connected to the detector 3<2,n+1>.

[0099] Specifically, the read period Pdet <2> Readout control scan line GLrd <1> During the "H" period of the differential input switching signal SSW, the differential input switching signal SSW is controlled to "H". As a result, a charge according to the detection voltage V<2,1> of the detection element 3<2,1> is charged in the first capacitance element C1_1, and the detection element 3<P+2,1> Detection voltage V<P+2,1> The first capacitance element C1_2 is charged with a charge corresponding to the<M-P+2,1> Detection voltage V<M-P+2,1> The first capacitance element C1_M / P is charged with a charge according to the charge.

[0100] Next read control scan line GLrd <2> During the "H" period of the differential input switching signal SSW, the differential input switching signal SSW is controlled to "L". As a result, a charge according to the detection voltage V<2,2> of the detection element 3<2,2> is charged in the second capacitance element C2_1, and the detection element 3<P+2,2> Detection voltage V<P+2,2> The second capacitance element C2_2 is charged with a charge corresponding to the<M-P+2,2> Detection voltage V<M-P+2,2> The second capacitance element C2_M / P is charged with a charge according to the charge amount. At this time, the charges stored in the first capacitance elements C1_1, C1_2, . . . , C1_M / P are held.

[0101] This reading period Pdet <2> Readout control scan line GLrd <2> 17, the A / D conversion circuit 43 converts the potential difference between the detection voltage V<2,1> charged in the first capacitance element C1_1 and the detection voltage V<2,2> charged in the second capacitance element C2_1 into a digital signal, and converts the potential difference between the detection voltage V<2,1> charged in the first capacitance element C1_2 into a digital signal.<P+2,1> Detection voltage V<P+2,1> and the detection element 3 charged in the second capacitance element C2_2<P+2,2> Detection voltage V<P+2,2> The potential difference between the first capacitance element C1_M / P and the second capacitance element C1_M / P is converted into a digital signal.<M-P+2,1> Detection voltage V<M-P+2,1> and the detection element 3 charged in the second capacitance element C2_M / P<M-P+2,2> Detection voltage V<M-P+2,2> The potential difference between these is converted into a digital signal.

[0102] Also, the following read control scan line GLrd <3> During the "H" period of the differential input switching signal SSW, the differential input switching signal SSW is controlled to "H". As a result, a charge according to the detection voltage V<2,3> of the detection element 3<2,3> is charged in the first capacitance element C1_1, and the detection element 3<P+2,3> Detection voltage V<P+2,3> The first capacitance element C1_2 is charged with a charge corresponding to the<M-P+2,3> Detection voltage V<M-P+2,3> The first capacitance element C1_M / P is charged with a charge according to the voltage Vcc. At this time, the charges stored in the second capacitance elements C2_1, C2_2, . . . , C2_M / P are held.

[0103] This reading period Pdet <2> Readout control scan line GLrd <3> 17, the A / D conversion circuit 43 converts the potential difference between the detection voltage V<2,3> charged in the first capacitance element C1_1 and the detection voltage V<2,2> charged in the second capacitance element C2_1 into a digital signal, and converts the potential difference between the detection voltage V<2,3> charged in the first capacitance element C1_2 into a digital signal.<P+2,3> Detection voltage V<P+2,3> and the detection element 3 charged in the second capacitance element C2_2<P+2,2> Detection voltage V<P+2,2> The potential difference between the first capacitance element C1_M / P and the second capacitance element C1_M / P is converted into a digital signal.<M-P+2,3> Detection voltage V<M-P+2,3> and the detection element 3 charged in the second capacitance element C2_M / P<M-P+2,2> Detection voltage V<M-P+2,2> The potential difference between the input and output terminals is converted into a digital signal. A subsequent digital signal processing circuit (for example, the signal processing circuit 44) performs sign inversion processing on the digitally converted data.

[0104] Also, the read period Pdet <2> Readout control scan line GLrd <n>During the "H" period of the differential input switching signal SSW, the differential input switching signal SSW is controlled to "H". As a result, a charge according to the detection voltage V<2,N> of the detection element 3<2,N> is charged in the first capacitance element C1_1, and the detection element 3<P+2,N> Detection voltage V<P+2,N> The first capacitance element C1_2 is charged with a charge corresponding to the<M-P+2,N> Detection voltage V<M-P+2,N> The first capacitance element C1_M / P is charged with a charge according to the voltage Vcc. At this time, the charges stored in the second capacitance elements C2_1, C2_2, . . . , C2_M / P are held.

[0105] This reading period Pdet <2> Readout control scan line GLrd <n>17, the A / D conversion circuit 43 converts the potential difference between the detection voltage V<2,N> charged in the first capacitance element C1_1 and the detection voltage V<2,N-1> charged in the second capacitance element C2_1 into a digital signal, and converts the potential difference between the detection voltage V<2,N> charged in the first capacitance element C1_2 into a digital signal.<P+2,N> Detection voltage V<P+2,N> and the detection element 3 charged in the second capacitance element C2_2<P+2,N-1> Detection voltage V<P+2,N-1> The potential difference between the first capacitance element C1_M / P and the second capacitance element C1_M / P is converted into a digital signal.<M-P+2,N> Detection voltage V<M-P+2,N> and the detection element 3 charged in the second capacitance element C2_M / P<M-P+2,N-1> Detection voltage V<M-P+2,N-1> The potential difference between the input and output terminals is converted into a digital signal. A subsequent digital signal processing circuit (for example, the signal processing circuit 44) performs sign inversion processing on the digitally converted data.

[0106] And the read period Pdet< / n> < / n> < / n> < / n> < / n> In this case, the detection circuit 48 detects the output signal line SL Detector element 3 connected to<P,n> Detection voltage and detection element 3<P,n+1> Digital data corresponding to the potential difference between the detected voltage and the

[0107] Specifically, the read period Pdet Readout control scan line GLrd <1> During the "H" period, the differential input switching signal SSW is controlled to "H".<P,1> Detection voltage V<P,1> The first capacitance element C1_1 is charged with a charge according to the detection voltage V<2P,1> of the detection element 3<2P,1>, and the first capacitance element C1_2 is charged with a charge according to the detection voltage V<2P,1> of the detection element 3<2P,1>.<M,1> Detection voltage V<M,1> The first capacitance element C1_M / P is charged with a charge according to the charge.

[0108] Next read control scan line GLrd <2> During the "H" period, the differential input switching signal SSW is controlled to "L".<P,2> Detection voltage V<P,2> The second capacitance element C2_1 is charged with a charge corresponding to the detection voltage V<2P,2> of the detection element 3<2P,2>, and the second capacitance element C2_2 is charged with a charge corresponding to the detection voltage V<2P,2> of the detection element 3<2P,2>.<M,2> Detection voltage V<M,2> The second capacitance element C2_M / P is charged with a charge according to the charge amount. At this time, the charges stored in the first capacitance elements C1_1, C1_2, . . . , C1_M / P are held.

[0109] This reading period Pdet Readout control scan line GLrd <2> 17, the A / D conversion circuit 43 detects the detected voltage V<P,1> and the detection voltage V charged in the second capacitance element C2_1<P,2> a potential difference between the detection voltage V<2P,1> of the detection element 3<2P,1> charged in the first capacitance element C1_2 and the detection voltage V<2P,2> of the detection element 3<2P,2> charged in the second capacitance element C2_2 is converted into a digital signal; a potential difference between the detection voltage V<2P,1> of the detection element 3<2P,1> charged in the first capacitance element C1_2 and the detection voltage V<2P,2> of the detection element 3<2P,2> charged in the second capacitance element C2_2 is converted into a digital signal;<M,1> Detection voltage V<M,1> and the detection element 3 charged in the second capacitance element C2_M / P<M,2> Detection voltage V<M,2> The potential difference between these is converted into a digital signal.

[0110] Also, the following read control scan line GLrd <3> During the "H" period, the differential input switching signal SSW is controlled to "H".<P,3> Detection voltage V<P,3> The first capacitance element C1_1 is charged with a charge according to the detection voltage V<2P,3> of the detection element 3<2P,3>, and the first capacitance element C1_2 is charged with a charge according to the detection voltage V<2P,3> of the detection element 3<2P,3>.<M,3> Detection voltage V<M,3> The first capacitance element C1_M / P is charged with a charge according to the voltage Vcc. At this time, the charges stored in the second capacitance elements C2_1, C2_2, . . . , C2_M / P are held.

[0111] This reading period Pdet Readout control scan line GLrd <3> 17, the A / D conversion circuit 43 detects the detected voltage V<P,3> and the detection voltage V charged in the second capacitance element C2_1<P,2> a potential difference between the detection voltage V<2P,3> of the detection element 3<2P,3> charged in the first capacitance element C1_2 and the detection voltage V<2P,2> of the detection element 3<2P,2> charged in the second capacitance element C2_2 is converted into a digital signal; a potential difference between the detection voltage V<2P,3> of the detection element 3<2P,3> charged in the first capacitance element C1_2 and the detection voltage V<2P,2> of the detection element 3<2P,2> charged in the second capacitance element C2_2 is converted into a digital signal;<M,3> Detection voltage V<M,3> and the detection element 3 charged in the second capacitance element C2_M / P<M,2> Detection voltage V<M,2> The potential difference between the input and output terminals is converted into a digital signal. A subsequent digital signal processing circuit (for example, the signal processing circuit 44) performs sign inversion processing on the digitally converted data.

[0112] Also, the read period Pdet Readout control scan line GLrd <n>During the "H" period, the differential input switching signal SSW is controlled to "H".<P,N> Detection voltage V<P,N> The first capacitance element C1_1 is charged with a charge according to the detection voltage V<2P,N> of the detection element 3<2P,N>, and the first capacitance element C1_2 is charged with a charge according to the detection voltage V<2P,N> of the detection element 3<2P,N>.<M,N> Detection voltage V<M,N> The first capacitance element C1_M / P is charged with a charge according to the voltage Vcc. At this time, the charges stored in the second capacitance elements C2_1, C2_2, . . . , C2_M / P are held.

[0113] This reading period Pdet< / n> Readout control scan line GLrd <n>17, the A / D conversion circuit 43 detects the detected voltage V<P,N> and the detection voltage V charged in the second capacitance element C2_1<P,N-1> a potential difference between the detection voltage V<2P,N> of the detection element 3<2P,N> charged in the first capacitance element C1_2 and the detection voltage V<2P,N-1> of the detection element 3<2P,N-1> charged in the second capacitance element C2_2 is converted into a digital signal; a potential difference between the detection voltage V<2P,N> of the detection element 3<2P,N> charged in the first capacitance element C1_2 and the detection voltage V<2P,N-1> of the detection element 3<2P,N-1> charged in the second capacitance element C2_2 is converted into a digital signal;<M,N> Detection voltage V<M,N> and the detection element 3 charged in the second capacitance element C2_M / P<M,N-1> Detection voltage V<M,N-1> The potential difference between the input and output terminals is converted into a digital signal. A subsequent digital signal processing circuit (for example, the signal processing circuit 44) performs sign inversion processing on the digitally converted data.

[0114] In this way, in the configuration shown in Figure 16, by repeating the combination of the reset period Prst, the exposure period Pch, and the readout period Pdet for P periods in the detection period FP, digital data corresponding to the potential difference in the detection voltage between two adjacent detection elements 3 in the second direction Dy can be obtained.

[0115] Fig. 18 is a diagram showing a correspondence relationship between digital data acquired at each sampling timing of the timing chart shown in Fig. 17. Fig. 19 is a diagram showing an example of digital data acquired during the detection operation of the signal line selection circuit and the detection circuit according to the first embodiment.

[0116] 19 illustrates an example of digital data when the amplification degree of the differential amplifier circuit 421 is "1." In FIG. 19, for example, the detection element 3<m,n> and detector element 3<m,n+1> The digital data corresponding to the potential difference between<m,n> -V<m,n+1> In this embodiment, the above-described configuration and operation are used to obtain digital data corresponding to the potential difference in the detection voltage between two adjacent detection elements 3 in the second direction Dy, so the number of data in the column direction (second direction Dy, vertical direction shown in FIG. 19) is N-1, which is one less than the number N of detection elements 3 lined up in the column direction (second direction Dy).

[0117] The signal processing circuit 44 sequentially converts the digital data acquired during the detection period FP into a first detection value ΔV<m,n> and stores it in the memory circuit 46 as

[0118] After the detection period FP ends, the signal processing circuit 44 converts the first detection value ΔV<m,n> A predetermined process is performed on the second detected value V<m,n> The data is stored in the memory circuitry 46 as a predetermined image. Here, the "predetermined processing" is, for example, processing for obtaining an image image corresponding to an image image drawn using digital data for each detection element acquired by the detection device according to the comparative example described above.

[0119] The coordinate extraction circuit 45 extracts the second detected value V stored in the memory circuit 46.<m,n> Based on the second detection value V, two-dimensional information (for example, an image) indicating the shape of the unevenness of the surface of the finger Fg or the like is generated.<m,n> The second detection value V may be read by the signal processing circuit 44 from the storage circuit 46 and output to the coordinate extraction circuit 45, or the coordinate extraction circuit 45 may read it directly from the storage circuit 46. Alternatively, the second detection value V calculated by the signal processing circuit 44 may be read by the coordinate extraction circuit 45 directly from the storage circuit 46.<m,n> may be output directly to the coordinate extraction circuit 45.

[0120] (Variation) Fig. 20 is a diagram showing an example of the configuration of a signal line selection circuit and a detection circuit according to a modification of embodiment 1. Fig. 21 is a diagram showing an example of a timing chart during detection operation of the signal line selection circuit and the detection circuit according to a modification of embodiment 1. Fig. 22 is a diagram showing the correspondence relationship of digital data acquired at each sampling timing of the timing chart shown in Fig. 21. Fig. 23 is a diagram showing an example of digital data acquired during detection operation of the signal line selection circuit and the detection circuit according to a modification of embodiment 1. Note that the reset period Prst and the exposure period Pch are omitted in Fig. 21.

[0121] The detection signal amplifier circuit 42a according to the modification of the first embodiment includes differential amplifier circuits 421_1a, 421_2a, . . . , 421_M / Pa, and a plurality of first capacitance elements C1 connected to the non-inverting inputs (+) of the differential amplifier circuits 421_1a, 421_2a, . . . , 421_M / Pa via switch circuits, respectively.< / n> _1,C1 _2,···,C1 _M / P, and a plurality of second capacitance elements C2 connected to the inverting inputs (-) of the differential amplifier circuits 421_1a, 421_2a, . . . , 421_M / Pa via switch circuits, _1,C2 _2,···,C2 _M / P and output signal line SL <m>The detection voltage V is input via <m> to either the non-inverting input (+) or the inverting input (-) of the differential amplifier circuits 421_1a, 421_2a, . . . , 421_M / Pa.< / m> < / m> _1,C1 _2,···,C1 _M / P are connected in parallel to the non-inverting inputs (+) of the differential amplifier circuits 421_1a, 421_2a, . . . , 421_M / Pa. _1,C2 _2,···,C2 _M / P is connected in parallel to the inverting inputs (-) of the differential amplifier circuits 421_1a, 421_2a, . . . , 421_M / Pa.

[0122] In the examples shown in FIGS. 20 and 21, the detection control circuit 11 outputs the read control scanning line GLrd during the read period Pdet. <n>The "H" (high level voltage) period is divided into P (P is an integer of 2 or more) and the read control scanning line GLrd <n> During the "H" (high level voltage) period, the signal line selection signal ASW <1> ,ASW <2> ,···,ASW< / n> < / n> is defined as "H" (high level voltage).

[0123] As a result, the signal line selection circuit 16 selects the read control scanning line GLrd <n> During the "H" (high level voltage) period (selection period), the signal line selection signal ASW supplied from the detection control circuit 11 <1> ,ASW <2> ,···ASW< / n> (P is a natural number equal to or smaller than M / 2), the output signal lines SL electrically connected to the differential amplifier circuits 421_1, 421_2, . . . , 421_M / P are sequentially selected along the first direction Dx, and the selected output signal lines SL are electrically connected to the detection circuit 48. _1,C1 _2,···,C1 _M / P is the read control scan line GLrd <n> The second capacitance elements C2 are provided corresponding to the plurality of output signal lines SL that are sequentially selected during the "H" (high level voltage) period (selection period) of the first capacitance element C1.< / n> _1,C2 _2,···,C2 _M / P is the read control scan line GLrd <n>The output signal lines SL are provided corresponding to the plurality of output signal lines SL that are sequentially selected during the "H" (high level voltage) period (selection period).

[0124] , 422_M / Pa of the detection circuit 48a are controlled based on the differential input switching signal SSW supplied from the detection control circuit 11 via the detection timing control circuit 47, and the read control scanning line GLrd set to "H" (high level voltage) based on the clock signal CK output from the detection control circuit 11. <1> ,GLrd <2> ,GLrd <3> ,···,GLrd <n>In synchronization with this, the detection voltage V<m,n> is applied to either the non-inverting input (+) or the inverting input (-) of the differential amplifier circuits 421_1, 421_2, . . . , 421_M / P.

[0125] The non-inverting inputs (+) of the differential amplifier circuits 421_1a, 421_2a, . . . , 421_M / Pa and the first capacitance elements C1< / n> < / n> _1,C1 _2,···,C1 Each switch circuit provided between the detection control circuit 11 and the detection timing control circuit 47 receives a capacitance switching signal CSW1. Based on this, the signal line selection signal ASW supplied from the detection control circuit 11 The ON control is synchronized with this.

[0126] In addition, the inverting inputs (-) of the differential amplifier circuits 421_1a, 421_2a, . . . , 421_M / Pa and the second capacitance elements C2 _1,C2 _2,···,C2 Each switch circuit provided between the detection control circuit 11 and the detection timing control circuit 47 receives a capacitance switching signal CSW2 During the "L" period of the differential input switching signal SSW supplied from the detection control circuit 11 via the detection timing control circuit 47, The ON control is synchronized with this.

[0127] The second gate line driving circuit 15B sequentially drives the read control scanning lines GLrd during the read period Pdet of the detection period FP. <1> ,GLrd <2> ,GLrd <3> ,···,GLrd <n>and supplies a read control signal RD to the selected read control scanning line GLrd. <1> ,GLrd <2> ,GLrd <3> ,···,GLrd <n> During the "H" period, the signal line selection signal ASW <1> ,ASW <2> ,···,ASW< / n> < / n> is defined as "H" (high level voltage).

[0128] Readout control scan line GLrd <1> During the "H" period of the differential input switching signal SSW synchronized with the "H" period of the <1> ,ASW <2> ,···,ASW When is set to "H" (high level voltage), the signal line selection signal ASW <1> ,ASW <2> ,···,ASW In synchronization with this, the capacitance switching signal CSW1 This causes the detection element 3<p,1> Detection voltage V<p,1> The charge corresponding to the first capacitance element C1 _1,C1 _2,···,C1 _Charged to M / P.

[0129] Next read control scan line GLrd <2> During the "L" period of the differential input switching signal SSW synchronized with the "H" period of the <1> ,ASW <2> ,···,ASW When is set to "H" (high level voltage), the signal line selection signal ASW <1> ,ASW <2> ,···,ASW In synchronization with this, the capacitance switching signal CSW2 This causes the detection element 3<p,2> Detection voltage V<p,2> The charge corresponding to the second capacitance element C2 _1,C2 _2,···,C2 At this time, the first capacitance element C1 _1,C1 _2,···,C1 The charge stored in the M / P is maintained.

[0130] This read control scan line GLrd <2> During the "H" period of the capacitance switching signal CSW2 In synchronization with this, the capacitance switching signal CSW1 is set to "H" (high level voltage). As a result, the detection circuit 48a detects the first capacitance element C1 _1,C1 _2,···,C1 _Detection element 3 charged to M / P<p,1> The detection voltage of the second capacitance element C2 _1,C2 _2,···,C2 _Detection element 3 charged to M / P<p,2> Digital data corresponding to the potential difference between the detected voltage and the

[0131] Specifically, the A / D conversion circuit 43 converts the first capacitance element C1 <1> The detection voltage V<1,1> charged to the capacitor C1 and the second capacitor C2 <1> The potential difference between the detected voltage V<1,2> ​​charged to _1 is converted into a digital signal.

[0132] Furthermore, the A / D conversion circuit 43 converts the first capacitance element C1 <2> The detection voltage V<2,1> charged to the second capacitance element C2 <2> The potential difference between the detected voltage V<2,2> charged to _1 is converted into a digital signal.

[0133] Furthermore, the A / D conversion circuit 43 converts the first capacitance element C1 <3> The detection voltage V<3,1> charged to the capacitor C1 and the second capacitor C2 <3> The potential difference between the detected voltage V<3,2> charged to _1 is converted into a digital signal.

[0134] Furthermore, the A / D conversion circuit 43 converts the first capacitance element C1 The detection voltage V charged to _1<P,1> and the second capacitance element C2 The detection voltage V charged to _1<P,2> The potential difference between these is converted into a digital signal.

[0135] Specifically, the A / D conversion circuit 43 converts the first capacitance element C1 <1> The detection voltage V<P+1,1> and the second capacitance element C2 <1> The detection voltage V<P+1,2> The potential difference between these is converted into a digital signal.

[0136] Furthermore, the A / D conversion circuit 43 converts the first capacitance element C1 <2> The detection voltage V<P+2,1> and the second capacitance element C2 <2> The detection voltage V<P+2,2> The potential difference between these is converted into a digital signal.

[0137] Furthermore, the A / D conversion circuit 43 converts the first capacitance element C1 <3> The detection voltage V<P+3,1> and the second capacitance element C2 <3> The detection voltage V<P+3,2> The potential difference between these is converted into a digital signal.

[0138] Furthermore, the A / D conversion circuit 43 converts the first capacitance element C1 The detection voltage V<P,1> and the second capacitance element C2 The detection voltage V<P,2> The potential difference between these is converted into a digital signal.

[0139] Specifically, the A / D conversion circuit 43 converts the first capacitance element C1 <1> _Detection voltage V charged to M / P<M-P+1,1> and the second capacitance element C2 <1> _Detection voltage V charged to M / P<M-P+1,2> The potential difference between these is converted into a digital signal.

[0140] Furthermore, the A / D conversion circuit 43 converts the first capacitance element C1 <2> _Detection voltage V charged to M / P<M-P+2,1> and the second capacitance element C2 <2> _Detection voltage V charged to M / P<M-P+2,2> The potential difference between these is converted into a digital signal.

[0141] Furthermore, the A / D conversion circuit 43 converts the first capacitance element C1 <3> _Detection voltage V charged to M / P<M-P+3,1> and the second capacitance element C2 <3> _Detection voltage V charged to M / P<M-P+3,2> The potential difference between these is converted into a digital signal.

[0142] Furthermore, the A / D conversion circuit 43 converts the first capacitance element C1 _Detection voltage V charged to M / P<M,1> and the second capacitance element C2 _Detection voltage V charged to M / P<M,2> The potential difference between these is converted into a digital signal.

[0143] Next read control scan line GLrd <3> During the "H" period of the differential input switching signal SSW synchronized with the "H" period of the <1> ,ASW <2> ,···,ASW When is set to "H" (high level voltage), the signal line selection signal ASW <1> ,ASW <2> ,···,ASW In synchronization with this, the capacitance switching signal CSW1 This causes the detection element 3<p,3> Detection voltage V<p,3> The charge corresponding to the first capacitance element C1 _1,C1 _2,···,C1 At this time, the second capacitance element C2 _1,C2 _2,···,C2 The charge stored in the M / P is maintained.

[0144] This read control scan line GLrd <3> During the "H" period, the detection circuit 48a detects the first capacitance element C1 _1,C1 _2,···,C1 _Detection element 3 charged to M / P<p,3> The detection voltage of the second capacitance element C2 _1,C2 _2,···,C2 Detector element 3 according to the charge held in M / P<p,2> Digital data corresponding to the potential difference between the detected voltage and the

[0145] Specifically, the A / D conversion circuit 43 converts the first capacitance element C1 <1> The detection voltage V<1,3> charged to the capacitor C1 and the second capacitor C2 <1> The potential difference between the detected voltage V<1,2> ​​charged to the capacitor _1 is converted into a digital signal. A subsequent digital signal processing circuit (for example, the signal processing circuit 44) performs sign inversion processing on the digitally converted data.

[0146] Furthermore, the A / D conversion circuit 43 converts the first capacitance element C1 <2> The detection voltage V<2,3> charged to the capacitor C1 and the second capacitor C2 <2> The potential difference between the detected voltage V<2,2> charged to the capacitor _1 is converted into a digital signal. A subsequent digital signal processing circuit (for example, the signal processing circuit 44) performs sign inversion processing on the digitally converted data.

[0147] Furthermore, the A / D conversion circuit 43 converts the first capacitance element C1 <3> The detection voltage V<3,3> charged to the capacitor C1 and the second capacitor C2 <3> The potential difference between the detected voltage V<3,2> charged to the capacitor _1 is converted into a digital signal. A subsequent digital signal processing circuit (for example, the signal processing circuit 44) performs sign inversion processing on the digitally converted data.

[0148] Furthermore, the A / D conversion circuit 43 converts the first capacitance element C1 The detection voltage V charged to _1<P,3> and the second capacitance element C2 The detection voltage V charged to _1<P,2> The potential difference between the input and output terminals is converted into a digital signal. A subsequent digital signal processing circuit (for example, the signal processing circuit 44) performs sign inversion processing on the digitally converted data.

[0149] Specifically, the A / D conversion circuit 43 converts the first capacitance element C1 <1> The detection voltage V<P+1,3> and the second capacitance element C2 <1> The detection voltage V<P+1,2> The potential difference between the input and output terminals is converted into a digital signal. A subsequent digital signal processing circuit (for example, the signal processing circuit 44) performs sign inversion processing on the digitally converted data.

[0150] Furthermore, the A / D conversion circuit 43 converts the first capacitance element C1 <2> The detection voltage V<P+2,3> and the second capacitance element C2 <2> The detection voltage V<P+2,2> The potential difference between the input and output terminals is converted into a digital signal. A subsequent digital signal processing circuit (for example, the signal processing circuit 44) performs sign inversion processing on the digitally converted data.

[0151] Furthermore, the A / D conversion circuit 43 converts the first capacitance element C1 <3> The detection voltage V<P+3,3> and the second capacitance element C2 <3> The detection voltage V<P+3,2> The potential difference between the input and output terminals is converted into a digital signal. A subsequent digital signal processing circuit (for example, the signal processing circuit 44) performs sign inversion processing on the digitally converted data.

[0152] Furthermore, the A / D conversion circuit 43 converts the first capacitance element C1 The detection voltage V<P,3> and the second capacitance element C2 The detection voltage V<P,2> The potential difference between the input and output terminals is converted into a digital signal. A subsequent digital signal processing circuit (for example, the signal processing circuit 44) performs sign inversion processing on the digitally converted data.

[0153] Specifically, the A / D conversion circuit 43 converts the first capacitance element C1 <1> _Detection voltage V charged to M / P<M-P+1,3> and the second capacitance element C2 <1> _Detection voltage V charged to M / P<M-P+1,2> The potential difference between the input and output terminals is converted into a digital signal. A subsequent digital signal processing circuit (for example, the signal processing circuit 44) performs sign inversion processing on the digitally converted data.

[0154] Furthermore, the A / D conversion circuit 43 converts the first capacitance element C1 <2> _Detection voltage V charged to M / P<M-P+2,3> and the second capacitance element C2 <2> _Detection voltage V charged to M / P<M-P+2,2> The potential difference between the input and output terminals is converted into a digital signal. A subsequent digital signal processing circuit (for example, the signal processing circuit 44) performs sign inversion processing on the digitally converted data.

[0155] Furthermore, the A / D conversion circuit 43 converts the first capacitance element C1 <3> _Detection voltage V charged to M / P<M-P+3,3> and the second capacitance element C2 <3> _Detection voltage V charged to M / P<M-P+3,2> The potential difference between the input and output terminals is converted into a digital signal. A subsequent digital signal processing circuit (for example, the signal processing circuit 44) performs sign inversion processing on the digitally converted data.

[0156] Furthermore, the A / D conversion circuit 43 converts the first capacitance element C1 _Detection voltage V charged to M / P<M,3> and the second capacitance element C2 _Detection voltage V charged to M / P<M,2> The potential difference between the input and output terminals is converted into a digital signal. A subsequent digital signal processing circuit (for example, the signal processing circuit 44) performs sign inversion processing on the digitally converted data.

[0157] Next read control scan line GLrd <4> During the "L" period of the differential input switching signal SSW synchronized with the "H" period of the <1> ,ASW <2> ,···,ASW When is set to "H" (high level voltage), the signal line selection signal ASW <1> ,ASW <2> ,···,ASW In synchronization with this, the capacitance switching signal CSW2 This causes the detection element 3<p,4> Detection voltage V<p,4> The charge corresponding to the second capacitance element C2 _1,C2 _2,···,C2 At this time, the first capacitance element C1 _1,C1 _2,···,C1 The charge stored in the M / P is maintained.

[0158] This read control scan line GLrd <4> During the "H" period of the capacitance switching signal CSW2 In synchronization with this, the capacitance switching signal CSW1 is set to "H" (high level voltage). As a result, the detection circuit 48a detects the first capacitance element C1 _1,C1 _2,···,C1 _Detection element 3 charged to M / P<p,3> The detection voltage of the second capacitance element C2 _1,C2 _2,···,C2 _Detection element 3 charged to M / P<p,4> Digital data corresponding to the potential difference between the detected voltage and the

[0159] Specifically, the A / D conversion circuit 43 converts the first capacitance element C1 <1> The detection voltage V<1,3> charged to the capacitor C1 and the second capacitor C2 <1> The potential difference between the detection voltage V<1,4> charged to _1 is converted into a digital signal.

[0160] Furthermore, the A / D conversion circuit 43 converts the first capacitance element C1 <2> The detection voltage V<2,3> charged to the capacitor C1 and the second capacitor C2 <2> The potential difference between the detected voltage V<2,4> charged to _1 is converted into a digital signal.

[0161] Furthermore, the A / D conversion circuit 43 converts the first capacitance element C1 <3> The detection voltage V<3,3> charged to the capacitor C1 and the second capacitor C2 <3> The potential difference between the detection voltage V<3,4> charged to _1 is converted into a digital signal.

[0162] Furthermore, the A / D conversion circuit 43 converts the first capacitance element C1 The detection voltage V charged to _1<P,3> and the second capacitance element C2 The detection voltage V charged to _1<P,4> The potential difference between these is converted into a digital signal.

[0163] Specifically, the A / D conversion circuit 43 converts the first capacitance element C1 <1> The detection voltage V<P+1,3> and the second capacitance element C2 <1> The detection voltage V<P+1,4> The potential difference between these is converted into a digital signal.

[0164] Furthermore, the A / D conversion circuit 43 converts the first capacitance element C1 <2> The detection voltage V<P+2,3> and the second capacitance element C2 <2> The detection voltage V<P+2,4> The potential difference between these is converted into a digital signal.

[0165] Furthermore, the A / D conversion circuit 43 converts the first capacitance element C1 <3> The detection voltage V<P+3,3> and the second capacitance element C2 <3> The detection voltage V<P+3,4> The potential difference between these is converted into a digital signal.

[0166] Furthermore, the A / D conversion circuit 43 converts the first capacitance element C1 The detection voltage V<P,3> and the second capacitance element C2 The detection voltage V<P,4> The potential difference between these is converted into a digital signal.

[0167] Specifically, the A / D conversion circuit 43 converts the first capacitance element C1 <1> _Detection voltage V charged to M / P<M-P+1,3> and the second capacitance element C2 <1> _Detection voltage V charged to M / P<M-P+1,4> The potential difference between these is converted into a digital signal.

[0168] Furthermore, the A / D conversion circuit 43 converts the first capacitance element C1 <2> _Detection voltage V charged to M / P<M-P+2,3> and the second capacitance element C2 <2> _Detection voltage V charged to M / P<M-P+2,4> The potential difference between these is converted into a digital signal.

[0169] Furthermore, the A / D conversion circuit 43 converts the first capacitance element C1 <3> _Detection voltage V charged to M / P<M-P+3,3> and the second capacitance element C2 <3> _Detection voltage V charged to M / P<M-P+3,4> The potential difference between these is converted into a digital signal.

[0170] Furthermore, the A / D conversion circuit 43 converts the first capacitance element C1 _Detection voltage V charged to M / P<M,3> and the second capacitance element C2 _Detection voltage V charged to M / P<M,4> The potential difference between these is converted into a digital signal.

[0171] And the read control scan line GLrd <n-1> During the "H" period of the differential input switching signal SSW synchronized with the "H" period of the <1> ,ASW <2> ,···,ASW When is set to "H" (high level voltage), the signal line selection signal ASW <1> ,ASW <2> ,···,ASW In synchronization with this, the capacitance switching signal CSW1 This causes the detection element 3<p,N-1> Detection voltage V<p,N-1> The charge corresponding to the first capacitance element C1 _1,C1 _2,···,C1 _Charged to M / P.

[0172] Next read control scan line GLrd <n> During the "L" period of the differential input switching signal SSW synchronized with the "H" period of the <1> ,ASW <2> ,···,ASW< / n> When is set to "H" (high level voltage), the signal line selection signal ASW <1> ,ASW <2> ,···,ASW In synchronization with this, the capacitance switching signal CSW2 This causes the detection element 3<p,N> Detection voltage V<p,N> The charge corresponding to the second capacitance element C2 _1,C2 _2,···,C2 At this time, the first capacitance element C1 _1,C1 _2,···,C1 The charge stored in the M / P is maintained.

[0173] This read control scan line GLrd <n> During the "H" period of the capacitance switching signal CSW2< / n> In synchronization with this, the capacitance switching signal CSW1 is set to "H" (high level voltage). As a result, the detection circuit 48a detects the first capacitance element C1 _1,C1 _2,···,C1 _Detection element 3 charged to M / P<p,N-1> The detection voltage of the second capacitance element C2 _1,C2 _2,···,C2 _Detection element 3 charged to M / P<p,N> Digital data corresponding to the potential difference between the detected voltage and the

[0174] Specifically, the A / D conversion circuit 43 converts the first capacitance element C1 <1> The detection voltage V<1,N-1> charged to the capacitor C1 and the second capacitor C2 <1> The potential difference between the detected voltage V<1,N> charged to _1 is converted into a digital signal.

[0175] Furthermore, the A / D conversion circuit 43 converts the first capacitance element C1 <2> The detection voltage V<2,N-1> charged to the second capacitance element C2 <2> The potential difference between the detected voltage V<2,N> charged to _1 is converted into a digital signal.

[0176] Furthermore, the A / D conversion circuit 43 converts the first capacitance element C1 <3> The detection voltage V<3,N-1> charged to the second capacitance element C2 <3> The potential difference between the detected voltage V<3,N> charged to _1 is converted into a digital signal.

[0177] Furthermore, the A / D conversion circuit 43 converts the first capacitance element C1 The detection voltage V charged to _1<P,N-1> and the second capacitance element C2 The detection voltage V charged to _1<P,N> The potential difference between these is converted into a digital signal.

[0178] Specifically, the A / D conversion circuit 43 converts the first capacitance element C1 <1> The detection voltage V<P+1,N-1> and the second capacitance element C2 <1> The detection voltage V<P+1,N> The potential difference between these is converted into a digital signal.

[0179] Furthermore, the A / D conversion circuit 43 converts the first capacitance element C1 <2> The detection voltage V<P+2,N-1> and the second capacitance element C2 <2> The detection voltage V<P+2,N> The potential difference between these is converted into a digital signal.

[0180] Furthermore, the A / D conversion circuit 43 converts the first capacitance element C1 <3> The detection voltage V<P+3,N-1> and the second capacitance element C2 <3> The detection voltage V<P+3,N> The potential difference between these is converted into a digital signal.

[0181] Furthermore, the A / D conversion circuit 43 converts the first capacitance element C1 The detection voltage V<P,N-1> and the second capacitance element C2 The detection voltage V<P,N> The potential difference between these is converted into a digital signal.

[0182] Specifically, the A / D conversion circuit 43 converts the first capacitance element C1 <1> _Detection voltage V charged to M / P<M-P+1,N-1> and the second capacitance element C2 <1> _Detection voltage V charged to M / P<M-P+1,N> The potential difference between these is converted into a digital signal.

[0183] Furthermore, the A / D conversion circuit 43 converts the first capacitance element C1 <2> _Detection voltage V charged to M / P<M-P+2,N-1> and the second capacitance element C2 <2> _Detection voltage V charged to M / P<M-P+2,N> The potential difference between these is converted into a digital signal.

[0184] Furthermore, the A / D conversion circuit 43 converts the first capacitance element C1 <3> _Detection voltage V charged to M / P<M-P+3,N-1> and the second capacitance element C2 <3> _Detection voltage V charged to M / P<M-P+3,N> The potential difference between these is converted into a digital signal.

[0185] Furthermore, the A / D conversion circuit 43 converts the first capacitance element C1 _Detection voltage V charged to M / P<M,N-1> and the second capacitance element C2 _Detection voltage V charged to M / P<M,N> The potential difference between these is converted into a digital signal.

[0186] 20, by performing one cycle of a combination of the reset period Prst, the exposure period Pch, and the readout period Pdet in the detection period FP, it is possible to obtain digital data corresponding to the potential difference in the detection voltage between two adjacent detection elements 3 in the second direction Dy. Therefore, it is possible to shorten the detection period FP compared to the configuration shown in FIG.

[0187] (Embodiment 2) In the first embodiment, an example was described in which digital data corresponding to the potential difference in the detection voltage between two adjacent detection elements 3 in the second direction Dy is acquired. In the present embodiment, an example will be described in which digital data corresponding to the potential difference in the detection voltage between two adjacent detection elements 3 in the first direction Dx is acquired.

[0188] Fig. 24 is a diagram showing an example of the configuration of a signal line selection circuit and a detection circuit according to embodiment 2. Fig. 25 is a diagram showing an example of a timing chart during detection operation of the signal line selection circuit and the detection circuit according to embodiment 2. Note that Fig. 25 omits the reset period Prst and the exposure period Pch.

[0189] In the examples shown in FIGS. 24 and 25, the signal line selection circuit 16a receives the signal line selection signal ASW supplied from the detection control circuit 11. <1> ,ASW <2> ,···,ASW ,ASW<P+1> (P is a natural number equal to or less than M / 2), multiple output signal lines SL electrically connected to the differential amplifier circuits 421_1, 421_2, ..., 421_M / P are sequentially selected along the first direction Dx, and the selected output signal lines SL are electrically connected to the detection circuit 48.

[0190] The second gate line driving circuit 15B sequentially drives the read control scanning lines GLrd during the read period Pdet of the detection period FP. <1> ,GLrd <2> ,GLrd <3> ,···,GLrd <n>and supplies a read control signal RD to the selected read control scanning line GLrd. <1> ,GLrd <2> ,GLrd <3> ,···,GLrd <n> During the "H" period, the signal line selection signal ASW <1> ,ASW <2> ,···,ASW< / n> < / n> ,ASW<P+1> is defined as "H" (high level voltage).

[0191] The configuration of the detection circuit 48 according to the second embodiment is the same as that of the first embodiment shown in Fig. 16. Specifically, in this embodiment, similarly to the first embodiment, the plurality of output signal lines SL simultaneously selected by the signal line selection circuit 16a are ,SL<P+p> ,···,SL<M-P+p> , 421_M / P are provided for the respective signal lines. <1> ,ASW <2> ,···,ASW ,ASW<P+1> In synchronization with this, the control states of the switch circuits 422_1, 422_2, . . . , 422_M / P of the detection circuit 48 are switched.

[0192] Specifically, the detection control circuit 11 detects, for example, the output signal lines SL <odd>During this selection period, the differential input switching signal SSW is set to “H” (high level voltage), and the non-inverting input (+) of the differential amplifier circuit 421 is connected to the detection element 3 of the odd-numbered column.<odd,n> Detection voltage V<odd,n> is applied.

[0193] Furthermore, the detection control circuit 11 detects, for example, the output signal lines SL <even>During this selection period, the differential input switching signal SSW is set to "L" (low level voltage), and the inverting input (-) of the differential amplifier circuit 421 is connected to the detecting element 3 in the even-numbered row.<even,n> Detection voltage V<even,n> is applied.

[0194] Readout control scan line GLrd <1> During the "H" period, the output signal line SL <1> When the differential input switching signal SSW is controlled to "H" during the selection period of the detection element 3<1,1>, a charge corresponding to the detection voltage V<1,1> of the detection element 3<1,1> is charged in the first capacitance element C1_1, and the detection element 3<P+1,1> Detection voltage V<P+1,1> The first capacitance element C1_2 is charged with a charge corresponding to the<M-P+1,1> Detection voltage V<M-P+1,1> The first capacitance element C1_M / P is charged with a charge according to the charge.

[0195] Next output signal line SL <2> When the differential input switching signal SSW is controlled to "L" during the selection period of the detection element 3<2,1>, a charge corresponding to the detection voltage V<2,1> of the detection element 3<2,1> is charged in the second capacitance element C2_2, and the detection element 3<2,1> is<P+2,1> Detection voltage V<P+2,1> The second capacitance element C2_2 is charged with a charge corresponding to the<M-P+2,1> Detection voltage V<M-P+2,1> The second capacitance element C2_M / P is charged with a charge according to the charge amount. At this time, the charges stored in the first capacitance elements C1_1, C1_2, . . . , C1_M / P are held.

[0196] This output signal line SL <2> During the selection period of the detection element 3<1,1>, more specifically, at sampling timing A shown in FIG. 25, the A / D conversion circuit 43 converts the potential difference between the detection voltage V<1,1> of the detection element 3<1,1> charged in the first capacitance element C1_1 and the detection voltage V<2,1> of the detection element 3<2,1> charged in the second capacitance element C2_1 into a digital signal, and outputs the detection voltage V<2,1> of the detection element 3<2,1> charged in the first capacitance element C1_2 as a digital signal.<P+1,1> Detection voltage V<P+1,1> and the detection element 3 charged in the second capacitance element C2_2<P+2,1> Detection voltage V<P+2,1> The potential difference between the first capacitance element C1_M / P and the second capacitance element C1_M / P is converted into a digital signal.<M-P+1,1> Detection voltage V<M-P+1,1> and the detection element 3 charged in the second capacitance element C2_M / P<M-P+2,1> Detection voltage V<M-P+2,1> The potential difference between these is converted into a digital signal.

[0197] Next output signal line SL <3> When the differential input switching signal SSW is controlled to "H" during the selection period of the detection element 3<3,1>, a charge corresponding to the detection voltage V<3,1> of the detection element 3<3,1> is charged in the first capacitance element C1_1, and the detection element 3<P+3,1> Detection voltage V<P+3,1> The first capacitance element C1_3 is charged with a charge corresponding to the<M-P+3,1> Detection voltage V<M-P+3,1> The first capacitance element C1_M / P is charged with a charge according to the voltage Vcc. At this time, the charges stored in the second capacitance elements C2_1, C2_2, . . . , C2_M / P are held.

[0198] This output signal line SL <3> During the selection period of the detection element 3<3,1>, more specifically, at sampling timing B shown in FIG. 25, the A / D conversion circuit 43 converts the potential difference between the detection voltage V<3,1> of the detection element 3<3,1> charged in the first capacitance element C1_1 and the detection voltage V<2,1> of the detection element 3<2,1> charged in the second capacitance element C2_1 into a digital signal, and outputs the detection voltage V<2,1> of the detection element 3<2,1> charged in the first capacitance element C1_2 as a digital signal.<P+3,1> Detection voltage V<P+3,1> and the detection element 3 charged in the second capacitance element C2_2<P+2,1> Detection voltage V<P+2,1> The potential difference between the first capacitance element C1_M / P and the second capacitance element C1_M / P is converted into a digital signal.<M-P+3,1> Detection voltage V<M-P+3,1> and the detection element 3 charged in the second capacitance element C2_M / P<M-P+2,1> Detection voltage V<M-P+2,1> The potential difference between the input and output terminals is converted into a digital signal. A subsequent digital signal processing circuit (for example, the signal processing circuit 44) performs sign inversion processing on the digitally converted data.

[0199] Output signal line SL< / even> < / odd> When the differential input switching signal SSW is controlled to "H" during the selection period of<P,1> Detection voltage V<P,1> The first capacitance element C1_1 is charged with a charge according to the detection voltage V<2P,1> of the detection element 3<2P,1>, and the first capacitance element C1_2 is charged with a charge according to the detection voltage V<2P,1> of the detection element 3<2P,1>.<M,1> Detection voltage V<M,1> The first capacitance element C1_M / P is charged with a charge according to the voltage Vcc. At this time, the charges stored in the second capacitance elements C2_1, C2_2, . . . , C2_M / P are held.

[0200] This output signal line SL During the selection period, more specifically, at the sampling timing C shown in FIG. 25, the A / D conversion circuit 43 detects the charge of the detection element 3<P,1> Detection voltage V<P,1> and the detection element 3 charged in the second capacitance element C2_1<P-1,1> Detection voltage V<P-1,1> a potential difference between the detection voltage V<2P,1> of the detection element 3<2P,1> charged in the first capacitance element C1_2 and the detection voltage V<2P-1,1> of the detection element 3<2P-1,1> charged in the second capacitance element C2_2 is converted into a digital signal; a potential difference between the detection voltage V<2P,1> of the detection element 3<2P,1> charged in the first capacitance element C1_2 and the detection voltage V<2P-1,1> of the detection element 3<2P-1,1> charged in the second capacitance element C2_2 is converted into a digital signal;<M,1> Detection voltage V<M,1> and the detection element 3 charged in the second capacitance element C2_M / P<M-1,1> Detection voltage V<M-1,1> The potential difference between the input and output terminals is converted into a digital signal. A subsequent digital signal processing circuit (for example, the signal processing circuit 44) performs sign inversion processing on the digitally converted data.

[0201] Next output signal line SL<P+1> When the differential input switching signal SSW is controlled to "L" during the selection period of<P+1,1> Detection voltage V<P+1,1> The second capacitance element C2_2 is charged with a charge according to the detected voltage V<2P+1,1> of the detection element 3<2P+1,1>, and the second capacitance element C2_2 is charged with a charge according to the detected voltage V<2P+1,1> of the detection element 3<2P+1,1>. At this time, the charges stored in the first capacitance elements C1_1, C1_2, . . . , C1_M / P are held.

[0202] This output signal line SL<P+1> During the selection period, more specifically, at sampling timing D shown in FIG. 25, the A / D conversion circuit 43 detects the charge of the detection element 3<P,1> Detection voltage V<P,1> and the detection element 3 charged in the second capacitance element C2_1<P+1,1> Detection voltage V<P+1,1> The potential difference between the detected voltage V<2P,1> of the detection element 3<2P,1> charged in the first capacitance element C1_2 and the detected voltage V<2P+1,1> of the detection element 3<2P+1,1> charged in the second capacitance element C2_2 is converted into a digital signal.

[0203] Readout control scan line GLrd <2> During the "H" period, the output signal line SL <1> When the differential input switching signal SSW is controlled to "H" during the selection period of the detection element 3<1,2>, a charge corresponding to the detection voltage V<1,2> ​​of the detection element 3<1,2> ​​is charged in the first capacitance element C1_1, and the detection element 3<1,2><P+1,2> Detection voltage V<P+1,2> The first capacitance element C1_2 is charged with a charge corresponding to the<M-P+1,2> Detection voltage V<M-P+1,2> The first capacitance element C1_M / P is charged with a charge according to the charge.

[0204] Next output signal line SL <2> When the differential input switching signal SSW is controlled to "L" during the selection period of the detection element 3<2,2>, a charge corresponding to the detection voltage V<2,2> of the detection element 3<2,2> is charged in the second capacitance element C2_2, and the detection element 3<P+2,2> Detection voltage V<P+2,2> The second capacitance element C2_2 is charged with a charge corresponding to the<M-P+2,2> Detection voltage V<M-P+2,2> The second capacitance element C2_M / P is charged with a charge according to the charge amount. At this time, the charges stored in the first capacitance elements C1_1, C1_2, . . . , C1_M / P are held.

[0205] This output signal line SL <2> During the selection period of the detection element 3<1,2>, more specifically, at sampling timing E shown in FIG. 25, the A / D conversion circuit 43 converts the potential difference between the detection voltage V<1,2> ​​of the detection element 3<1,2> ​​charged in the first capacitance element C1_1 and the detection voltage V<2,2> of the detection element 3<2,2> charged in the second capacitance element C2_1 into a digital signal, and outputs the detection voltage V<2,2> of the detection element 3<1,2> ​​charged in the first capacitance element C1_2 as a digital signal.<P+1,2> Detection voltage V<P+1,2> and the detection element 3 charged in the second capacitance element C2_2<P+2,2> Detection voltage V<P+2,2> The potential difference between the first capacitance element C1_M / P and the second capacitance element C1_M / P is converted into a digital signal.<M-P+1,2> Detection voltage V<M-P+1,2> and the detection element 3 charged in the second capacitance element C2_M / P<M-P+2,2> Detection voltage V<M-P+2,2> The potential difference between these is converted into a digital signal.

[0206] Next output signal line SL <3> When the differential input switching signal SSW is controlled to "H" during the selection period of the detection element 3<3,2>, a charge corresponding to the detection voltage V<3,2> of the detection element 3<3,2> is charged in the first capacitance element C1_1, and the detection element 3<P+3,2> Detection voltage V<P+3,2> The first capacitance element C1_3 is charged with a charge corresponding to the<M-P+3,2> Detection voltage V<M-P+3,2> The first capacitance element C1_M / P is charged with a charge according to the voltage Vcc. At this time, the charges stored in the second capacitance elements C2_1, C2_2, . . . , C2_M / P are held.

[0207] This output signal line SL <3> During the selection period of the detection element 3<3,2>, more specifically, at sampling timing F shown in FIG. 25, the A / D conversion circuit 43 converts the potential difference between the detection voltage V<3,2> of the detection element 3<3,2> charged in the first capacitance element C1_1 and the detection voltage V<2,2> of the detection element 3<2,2> charged in the second capacitance element C2_1 into a digital signal, and outputs the detection voltage V<2,2> of the detection element 3<3,2> charged in the first capacitance element C1_2 as a digital signal.<P+3,2> Detection voltage V<P+3,2> and the detection element 3 charged in the second capacitance element C2_2<P+2,2> Detection voltage V<P+2,2> The potential difference between the first capacitance element C1_M / P and the second capacitance element C1_M / P is converted into a digital signal.<M-P+3,2> Detection voltage V<M-P+3,2> and the detection element 3 charged in the second capacitance element C2_M / P<M-P+2,2> Detection voltage V<M-P+2,2> The potential difference between the input and output terminals is converted into a digital signal. A subsequent digital signal processing circuit (for example, the signal processing circuit 44) performs sign inversion processing on the digitally converted data.

[0208] Output signal line SL When the differential input switching signal SSW is controlled to "H" during the selection period of<P,2> Detection voltage V<P,2> The first capacitance element C1_1 is charged with a charge according to the detection voltage V<2P,2> of the detection element 3<2P,2>, and the first capacitance element C1_2 is charged with a charge according to the detection voltage V<2P,2> of the detection element 3<2P,2>.<M,2> Detection voltage V<M,2> The first capacitance element C1_M / P is charged with a charge according to the voltage Vcc. At this time, the charges stored in the second capacitance elements C2_1, C2_2, . . . , C2_M / P are held.

[0209] This output signal line SL During the selection period, more specifically, at the sampling timing G shown in FIG. 25, the A / D conversion circuit 43 detects the charge of the detection element 3<P,2> Detection voltage V<P,2> and the detection element 3 charged in the second capacitance element C2_1<P-1,2> Detection voltage V<P-1,2> a potential difference between the detection voltage V<2P,2> of the detection element 3<2P,2> charged in the first capacitance element C1_2 and the detection voltage V<2P-1,2> of the detection element 3<2P-1,2> charged in the second capacitance element C2_2 is converted into a digital signal; a potential difference between the detection voltage V<2P,2> of the detection element 3<2P,2> charged in the first capacitance element C1_2 and the detection voltage V<2P-1,2> of the detection element 3<2P-1,2> charged in the second capacitance element C2_2 is converted into a digital signal;<M,2> Detection voltage V<M,2> and the detection element 3 charged in the second capacitance element C2_M / P<M-1,2> Detection voltage V<M-1,2> The potential difference between the input and output terminals is converted into a digital signal. A subsequent digital signal processing circuit (for example, the signal processing circuit 44) performs sign inversion processing on the digitally converted data.

[0210] Next output signal line SL<P+1> When the differential input switching signal SSW is controlled to "L" during the selection period of<P+1,2> Detection voltage V<P+1,2> The second capacitance element C2_2 is charged with a charge according to the detected voltage V<2P+1,2> of the detection element 3<2P+1,2>, and the second capacitance element C2_2 is charged with a charge according to the detected voltage V<2P+1,2> of the detection element 3<2P+1,2>. At this time, the charges stored in the first capacitance elements C1_1, C1_2, . . . , C1_M / P are held.

[0211] This output signal line SL<P+1> During the selection period, more specifically, at the sampling timing H shown in FIG. 25, the A / D conversion circuit 43 detects the charge of the detection element 3<P,2> Detection voltage V<P,2> and the detection element 3 charged in the second capacitance element C2_1<P+1,2> Detection voltage V<P+1,2> The potential difference between the detected voltage V<2P,2> of the detection element 3<2P,2> charged in the first capacitance element C1_2 and the detected voltage V<2P+1,2> of the detection element 3<2P,2> charged in the second capacitance element C2_2 is converted into a digital signal.

[0212] Readout control scan line GLrd <n>During the "H" period, the output signal line SL <1> When the differential input switching signal SSW is controlled to "H" during the selection period of the detection element 3<1,N>, a charge corresponding to the detection voltage V<1,N> of the detection element 3<1,N> is charged in the first capacitance element C1_1, and the detection element 3<1,N><P+1,N> Detection voltage V<P+1,N> The first capacitance element C1_2 is charged with a charge corresponding to the<M-P+1,N> Detection voltage V<M-P+1,N> The first capacitance element C1_M / P is charged with a charge according to the charge.

[0213] Next output signal line SL <2> When the differential input switching signal SSW is controlled to "L" during the selection period of the detection element 3<2,N>, a charge corresponding to the detection voltage V<2,N> of the detection element 3<2,N> is charged in the second capacitance element C2_2, and the detection element 3<2,N><P+2,N> Detection voltage V<P+2,N> The second capacitance element C2_2 is charged with a charge corresponding to the<M-P+2,N> Detection voltage V<M-P+2,N> The second capacitance element C2_M / P is charged with a charge according to the charge amount. At this time, the charges stored in the first capacitance elements C1_1, C1_2, . . . , C1_M / P are held.

[0214] This output signal line SL <2> During the selection period of the detection element 3<1,N>, more specifically, at sampling timing I shown in FIG. 25, the A / D conversion circuit 43 converts the potential difference between the detection voltage V<1,N> of the detection element 3<1,N> charged in the first capacitance element C1_1 and the detection voltage V<2,N> of the detection element 3<2,N> charged in the second capacitance element C2_1 into a digital signal, and converts the potential difference between the detection voltage V<1,N> of the detection element 3<1,N> charged in the first capacitance element C1_2 into a digital signal.<P+1,N> Detection voltage V<P+1,N> and the detection element 3 charged in the second capacitance element C2_2<P+2,N> Detection voltage V<P+2,N> The potential difference between the first capacitance element C1_M / P and the second capacitance element C1_M / P is converted into a digital signal.<M-P+1,N> Detection voltage V<M-P+1,N> and the detection element 3 charged in the second capacitance element C2_M / P<M-P+2,N> Detection voltage V<M-P+2,N> The potential difference between these is converted into a digital signal.

[0215] Next output signal line SL <3> When the differential input switching signal SSW is controlled to "H" during the selection period of the detection element 3<3,N>, a charge corresponding to the detection voltage V<3,N> of the detection element 3<3,N> is charged in the first capacitance element C1_1, and the detection element 3<P+3,N> Detection voltage V<P+3,N> The first capacitance element C1_3 is charged with a charge corresponding to the<M-P+3,N> Detection voltage V<M-P+3,N> The first capacitance element C1_M / P is charged with a charge according to the voltage Vcc. At this time, the charges stored in the second capacitance elements C2_1, C2_2, . . . , C2_M / P are held.

[0216] This output signal line SL <3> 25, the A / D conversion circuit 43 converts the potential difference between the detection voltage V<3,N> of the detection element 3<3,N> charged in the first capacitance element C1_1 and the detection voltage V<2,N> of the detection element 3<2,N> charged in the second capacitance element C2_1 into a digital signal, and converts the potential difference between the detection voltage V<3,N> of the detection element 3<3,N> charged in the first capacitance element C1_2 into a digital signal.<P+3,N> Detection voltage V<P+3,N> and the detection element 3 charged in the second capacitance element C2_2<P+2,N> Detection voltage V<P+2,N> The potential difference between the first capacitance element C1_M / P and the second capacitance element C1_M / P is converted into a digital signal.<M-P+3,N> Detection voltage V<M-P+3,N> and the detection element 3 charged in the second capacitance element C2_M / P<M-P+2,N> Detection voltage V<M-P+2,N> The potential difference between the input and output terminals is converted into a digital signal. A subsequent digital signal processing circuit (for example, the signal processing circuit 44) performs sign inversion processing on the digitally converted data.

[0217] Output signal line SL< / n> When the differential input switching signal SSW is controlled to "H" during the selection period of<P,N> Detection voltage V<P,N> The first capacitance element C1_1 is charged with a charge according to the detection voltage V<2P,N> of the detection element 3<2P,N>, and the first capacitance element C1_2 is charged with a charge according to the detection voltage V<2P,N> of the detection element 3<2P,N>.<M,N> Detection voltage V<M,N> The first capacitance element C1_M / P is charged with a charge according to the voltage Vcc. At this time, the charges stored in the second capacitance elements C2_1, C2_2, . . . , C2_M / P are held.

[0218] This output signal line SL During the selection period, more specifically, at the sampling timing K shown in FIG. 25, the A / D conversion circuit 43 detects the charge of the detection element 3<P,N> Detection voltage V<P,N> and the detection element 3 charged in the second capacitance element C2_1<P-1,N> Detection voltage V<P-1,N> a potential difference between the detection voltage V<2P,N> of the detection element 3<2P,N> charged in the first capacitance element C1_2 and the detection voltage V<2P-1,N> of the detection element 3<2P-1,N> charged in the second capacitance element C2_2 is converted into a digital signal; a potential difference between the detection voltage V<2P,N> of the detection element 3<2P,N> charged in the first capacitance element C1_2 and the detection voltage V<2P-1,N> of the detection element 3<2P-1,N> charged in the second capacitance element C2_2 is converted into a digital signal;<M,N> Detection voltage V<M,N> and the detection element 3 charged in the second capacitance element C2_M / P<M-1,N> Detection voltage V<M-1,N> The potential difference between the input and output terminals is converted into a digital signal. A subsequent digital signal processing circuit (for example, the signal processing circuit 44) performs sign inversion processing on the digitally converted data.

[0219] Next output signal line SL<P+1> When the differential input switching signal SSW is controlled to "L" during the selection period of<P+1,N> Detection voltage V<P+1,N> The second capacitance element C2_2 is charged with a charge according to the detected voltage V<2P+1,N> of the detection element 3<2P+1,N>, and the second capacitance element C2_2 is charged with a charge according to the detected voltage V<2P+1,N> of the detection element 3<2P+1,N>. At this time, the charges stored in the first capacitance elements C1_1, C1_2, . . . , C1_M / P are held.

[0220] This output signal line SL<P+1> During the selection period, more specifically, at the sampling timing L shown in FIG. 25, the A / D conversion circuit 43 detects the charge of the detection element 3 charged in the first capacitance element C1_1.<P,N> Detection voltage V<P,N> and the detection element 3 charged in the second capacitance element C2_1<P+1,N> Detection voltage V<P+1,N> The potential difference between the detected voltage V<2P,N> of the detection element 3<2P,N> charged in the first capacitance element C1_2 and the detected voltage V<2P+1,N> of the detection element 3<2P,N> charged in the second capacitance element C2_2 is converted into a digital signal.

[0221] Fig. 26 is a diagram showing a correspondence relationship between digital data acquired at each sampling timing of the timing chart shown in Fig. 25. Fig. 27 is a diagram showing an example of digital data acquired during the detection operation of the signal line selection circuit and the detection circuit according to the second embodiment.

[0222] 27 illustrates an example of digital data when the amplification degree of the differential amplifier circuit 421 is "1." In FIG. 27, for example, the detection element 3<m,n> and detector element 3<m+1,n> The digital data corresponding to the potential difference between<m,n> -V<m+1,n> In this embodiment, the above-described configuration and operation are used to obtain digital data corresponding to the potential difference in the detection voltage between two adjacent detection elements 3 in the first direction Dx, so the number of data in the row direction (first direction Dx, vertical direction shown in FIG. 27) is M−1, which is one less than the number M of detection elements 3 lined up in the row direction (first direction Dx).

[0223] The signal processing circuit 44 sequentially converts the digital data acquired during the detection period FP into a first detection value ΔV<m,n> and stores it in the memory circuit 46 as

[0224] After the detection period FP ends, the signal processing circuit 44 converts the first detection value ΔV<m,n> A predetermined process is performed on the second detected value V<m,n> The data is stored in the memory circuitry 46 as a predetermined image. Here, the "predetermined processing" is, for example, processing for obtaining an image image corresponding to an image image drawn using digital data for each detection element acquired by the detection device according to the comparative example described above.

[0225] The coordinate extraction circuit 45 extracts the second detected value V stored in the memory circuit 46.<m,n> Based on the second detection value V, two-dimensional information (for example, an image) indicating the shape of the unevenness of the surface of the finger Fg or the like is generated.<m,n> The second detection value V may be read by the signal processing circuit 44 from the storage circuit 46 and output to the coordinate extraction circuit 45, or the coordinate extraction circuit 45 may read it directly from the storage circuit 46. Alternatively, the second detection value V calculated by the signal processing circuit 44 may be read by the coordinate extraction circuit 45 directly from the storage circuit 46.<m,n> may be output directly to the coordinate extraction circuit 45.

[0226] Although preferred embodiments of the present disclosure have been described above, the present disclosure is not limited to such embodiments. The contents disclosed in the embodiments are merely examples, and various modifications are possible within the scope of the present disclosure. Appropriate modifications made within the scope of the present disclosure also naturally fall within the technical scope of the present disclosure. [Explanation of symbols]

[0227] 1. Detection device 3. Detector element 10 Sensor section 11 Detection control circuit 15A First gate line driving circuit 15B Second gate line driving circuit 16, 16a Signal line selection circuit 21 PCB 30 Photoelectric conversion element 42, 42a Detection signal amplifier circuit 43 A / D conversion circuit 44 Signal Processing Circuit 45 Coordinate extraction circuit 46 Memory circuit 47 Detection timing control circuit 48,48a Detection circuit 101 Control board 102 control circuit 103 Power supply circuit 421 Differential Amplifier Circuit 422 Switch Circuit AA detection area C1 First capacitance element C2 Second capacitance element GA peripheral area GLrst Reset control scan line GLrd Readout control scan line Mrst Reset Transistor Mrd readout transistor Msf Source Follower Transistor RST Reset control signal RD Read control signal SL output signal line Vcom common voltage Vref Reference voltage Vrst Reset voltage Vsf power supply voltage < / m> < / m> < / m> < / m> < / m> < / n> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / even> < / odd> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / n> < / m> < / m> < / n> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / n> < / m>

Claims

1. a sensor unit in which a plurality of detection elements each having a photoelectric conversion element are provided in a detection area; a detection unit that detects a potential difference between a voltage generated in a first detection element and a voltage generated in a second detection element adjacent to the first detection element within the detection area; a read control scanning line for supplying a read control signal to the detection elements arranged in the first direction; a drive circuit that sequentially selects the readout control scanning lines along a second direction different from the first direction; an output signal line to which a voltage generated in the detection elements arranged in the second direction is supplied; Equipped with the detection elements are arranged in a matrix in the first direction and the second direction within the detection region, The detection unit a differential amplifier circuit that outputs a potential difference between voltages generated in the detection elements adjacent to each other in the second direction; a first capacitance element connected to the non-inverting input of the differential amplifier circuit; a second capacitance element connected to the inverting input of the differential amplifier circuit; a switch circuit that switches between the non-inverting input and the inverting input of the differential amplifier circuit in synchronization with the selection and switching of the read control scanning line, and electrically connects the non-inverting input and the inverting input to the output signal line; Including, an output of the first detection element is connected to one of the non-inverting input and the inverting input of the differential amplifier circuit, and after a voltage is charged to the first capacitance element, the one input is opened by the switch circuit; an output of the second detection element is connected to the other of the non-inverting input of the differential amplifier circuit and the inverting input of the differential amplifier circuit, and a voltage is charged in the second capacitance element; The differential amplifier circuit outputting a potential difference between the voltage charged in the first capacitance element and the voltage charged in the second capacitance element; Detection device.

2. A sensor section in which a plurality of detection elements each having a photoelectric conversion element are provided in a detection area; a detection unit that detects a potential difference between a voltage generated in a first detection element and a voltage generated in a second detection element adjacent to the first detection element within the detection area; a read control scanning line for supplying a read control signal to the detection elements arranged in the first direction; a drive circuit that sequentially selects the readout control scanning lines along a second direction different from the first direction; an output signal line to which a voltage generated in the detection elements arranged in the second direction is supplied; Equipped with the detection elements are arranged in a matrix in the first direction and the second direction within the detection region, The detection unit a differential amplifier circuit that outputs a potential difference between voltages generated in the detection elements adjacent to each other in the second direction; a first capacitance element connected to the non-inverting input of the differential amplifier circuit; a second capacitance element connected to the inverting input of the differential amplifier circuit; a switch circuit that switches between the non-inverting input and the inverting input of the differential amplifier circuit in synchronization with the selection and switching of the read control scanning line, and electrically connects the non-inverting input and the inverting input to the output signal line; Including, The sensor unit the number of detection elements arranged in the second direction in the detection area is N, The detection unit Inverting the sign of the (n+1)th output value of the differential amplifier circuit with respect to the nth (n is a natural number equal to or less than N) output value of the differential amplifier circuit; Detection device.

3. The differential amplifier circuit outputting a potential difference between the voltage charged in the first capacitance element and the voltage charged in the second capacitance element; The detection device according to claim 2 .

4. a signal line selection circuit that simultaneously selects a plurality of output signal lines from among all the output signal lines in the detection area and electrically connects them to the detection unit; The detection unit one differential amplifier circuit is provided for each of a plurality of output signal lines simultaneously selected by the signal line selection circuit; The detection device according to claim 2 .

5. The signal line selection circuit sequentially selecting, in the first direction, a plurality of output signal lines electrically connected to the differential amplifier circuit during a selection period of the read control scanning line; The differential amplifier circuit a plurality of the first capacitance elements are connected in parallel to the non-inverting input in correspondence with a plurality of output signal lines sequentially selected during a selection period of the read control scanning line; a plurality of the second capacitance elements are connected in parallel to the inverting input in correspondence with a plurality of output signal lines sequentially selected during a selection period of the read control scanning line; The detection device according to claim 4 .

6. The differential amplifier circuit a potential difference between a voltage generated in the first detection element and a voltage generated in a second detection element adjacent to the first detection element in the second direction within the detection region is amplified and output; 6. A detection device according to any one of claims 2 to 5.

7. A sensor section in which a plurality of detection elements each having a photoelectric conversion element are provided within a detection area; a detection unit that detects a potential difference between a voltage generated in a first detection element and a voltage generated in a second detection element adjacent to the first detection element within the detection area; a read control scanning line for supplying a read control signal to the detection elements arranged in the first direction; a drive circuit that sequentially selects the readout control scanning lines along a second direction different from the first direction; an output signal line to which a voltage generated in the detection elements arranged in the second direction is supplied; Equipped with the detection elements are arranged in a matrix in the first direction and the second direction within the detection region, a signal line selection circuit that sequentially selects a plurality of output signal lines from all of the output signal lines in the detection region along the first direction during a selection period of the readout control scanning line, and electrically connects the selected output signal lines to the detection unit; The detection unit a differential amplifier circuit that outputs a potential difference between voltages generated in the detection elements adjacent to each other in the first direction; a first capacitance element connected to the non-inverting input of the differential amplifier circuit; a second capacitance element connected to the inverting input of the differential amplifier circuit; a switch circuit that switches between the non-inverting input and the inverting input of the differential amplifier circuit in synchronization with the selection and switching of the plurality of output signal lines, and electrically connects the non-inverting input and the inverting input to the output signal lines; Including, The sensor unit the number of detection elements arranged in the first direction in the detection region is M, The detection unit Inverting the sign of the (m+1)th output value of the differential amplifier circuit with respect to the mth (m is a natural number equal to or less than M) output value of the differential amplifier circuit; Detection device.

8. The differential amplifier circuit outputting a potential difference between the voltage charged in the first capacitance element and the voltage charged in the second capacitance element; The detection device according to claim 7.

9. The detection unit one differential amplifier circuit is provided for a plurality of output signal lines sequentially selected by the signal line selection circuit; 9. The detection device according to claim 7 or 8.

10. The differential amplifier circuit amplified and output a potential difference between a voltage generated in a first detection element and a voltage generated in a second detection element adjacent to the first detection element in the first direction within the detection region; 10. A detection device according to any one of claims 7 to 9.

11. The detection element is a reset transistor that applies a reset voltage to the cathode of the photoelectric conversion element; a source follower transistor that outputs a signal corresponding to a voltage generated by the photoelectric conversion element; a read transistor that reads out an output signal of the source follower transistor; Equipped with Detecting device according to any one of claims 1 to 10.

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