Semiconductor device and manufacturing method thereof

Abstract

To realize a semiconductor device in which a formation failure of a coating material coating a semiconductor chip is suppressed.SOLUTION: A semiconductor device 1A comprises: an insulation circuit substrate 10 having a conductive pattern layer 12; a sinter member 20 arranged on the conductive pattern layer 12; a semiconductor chip 30 arranged on the sinter member 20; and a coating material 40 coating the semiconductor chip 30. The sinter member 20 includes: a concave part 21 to a surface opposite to the conductive pattern layer 12; and a frame part 22 forming an outer edge thereof. The semiconductor chip 30 is mounted on the concave part 21, and an upper surface 30a is arranged so as to be positioned on a side closer to the conductive pattern layer 12 than an upper end 22a of the frame part 22. Thus, the frame part 22 of the sinter member 20 functions as a dam part for accumulating the coating material 40 on the semiconductor chip 30 on its inner side, and can suppress exposure from the coating material 40 of the semiconductor chip 30.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] 2. Description of the Related Art With respect to semiconductor devices, a technique is known in which a semiconductor chip or semiconductor element mounted on a predetermined substrate is covered with a resin. For example, a technique is known in which a dam resin is provided on a circuit board on which an IC chip is mounted, seamlessly surrounding the periphery of the IC chip, and a sealing resin that seals the IC chip is filled inside the dam resin (Patent Document 1).

[0003] Also known is a technology in which a semiconductor chip is mounted in a recess provided in the die pad of a lead frame, the recess is filled with junction coating resin to coat the surface of the semiconductor chip, and a resin package is formed around the semiconductor chip (Patent Document 2).

[0004] Also, a technique is known in which a ring-shaped frame made of adhesive or solder is formed on a support plate on which a semiconductor element is mounted so as to surround the semiconductor element, and a protective resin that covers the semiconductor element is placed in a reservoir formed by the frame (Patent Document 3).

[0005] Also, a technology is known in which an outflow suppression member consisting of a copper strip pattern and a gold-plated layer with low wettability to the sealing resin is placed near the periphery of the semiconductor element on a circuit board on which the semiconductor element is mounted, and the gold-plated layer prevents the injected sealing resin from leaking outside the sealing area (Patent Document 4).

[0006] Also, in a semiconductor device in which a semiconductor chip is mounted on a lead frame via solder, a circuit board is mounted via a resin adhesive, and the periphery of these is sealed with a molded resin, a technique is known in which a protective resin is coated on the top surface and periphery of the semiconductor chip for the purpose of strengthening adhesion with the molded resin and alleviating thermal stress (Patent Document 5). Furthermore, in such a semiconductor device, a technique is known in which a convex portion (dam portion) is provided on the lead frame along the boundary between the mounting areas of the semiconductor chip and the circuit board, thereby preventing the protective resin coated on the top surface and periphery of the semiconductor chip from flowing into the mounting area of ​​the circuit board (Patent Document 5).

[0007] In addition, a technique is known for semiconductor devices, in which a multilayer semiconductor chip is mounted on a circuit board, a dam material composition is molded and applied around the multilayer semiconductor chip, an underfill material composition is allowed to penetrate into the gap between the multilayer semiconductor chip and the circuit board from between the multilayer semiconductor chip and the dam material composition, and the dam material composition and the underfill material composition are hardened (Patent Document 6).

[0008] Also known is a technique for flip-chip mounting a semiconductor chip on a circuit board by placing a resin such as an anisotropic conductive film between the chip and the circuit board, and a technique for compressing voids by pressurizing the resin that flows out of the semiconductor chip when it is pressed during flip-chip mounting, thereby improving adhesion to the circuit board (Patent Document 7).To pressurize the semiconductor chip and resin, it has been proposed to use a bonding pressure jig that has an opening on the contact surface with the semiconductor chip that has approximately the same shape as the outer shape of the semiconductor chip, a depth that is less than the height from the top surface of the circuit board to the top surface of the semiconductor chip after connection, and a recess that fits into the semiconductor chip directly or via a sheet member when pressure is applied (Patent Document 7). [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Application Publication No. 9-69591 [Patent Document 2] Japanese Patent Application Publication No. 7-38027 [Patent Document 3] Japanese Patent Application Publication No. 11-135686 [Patent Document 4] Japanese Patent Application Laid-Open No. 2004-214255 [Patent Document 5] Japanese Patent Application Laid-Open No. 2005-93635 [Patent Document 6] Japanese Patent Application Laid-Open No. 2011-14885 [Patent Document 7] Japanese Patent Application Laid-Open No. 2001-127105 Summary of the Invention [Problem to be solved by the invention]

[0010] One type of semiconductor device known in the art is one in which a semiconductor chip is mounted via a sintered member on an insulating circuit board having a conductive pattern layer. The semiconductor chip mounted on the insulating circuit board is encapsulated with an encapsulant such as an epoxy resin. In such semiconductor devices, internal stress is generated due to heat generation during operation and the temperature load associated with cooling. In this case, if stress exceeds the adhesive strength of the encapsulant due to the difference in thermal expansion coefficients between the semiconductor chip and the encapsulant encapsulating it, the encapsulant may peel off from the semiconductor chip. Peeling of the encapsulant from the semiconductor chip may result in reduced reliability and insulation performance of the semiconductor chip and the semiconductor device on which it is mounted.

[0011] To prevent the encapsulant from peeling off from the semiconductor chip, a coating material is sometimes applied between the semiconductor chip and the encapsulant to improve adhesion and relieve stress. One method for applying the coating material involves placing a fluid coating material on the semiconductor chip and spreading it over the surface of the semiconductor chip. However, if the viscosity of the coating material is too high, the coating material may not spread sufficiently over the surface of the semiconductor chip. If the viscosity of the coating material is too low, the coating material may run off, exposing parts of the semiconductor chip (such as corners) or resulting in an insufficient coating thickness. Such poor coating material formation can lead to contact between the semiconductor chip and the encapsulant, or to a reduction in the adhesion improvement and stress relief effects. This, in turn, can lead to peeling of the encapsulant due to stress caused by temperature loads, which can result in reduced reliability and insulation performance of the semiconductor chip and semiconductor device.

[0012] In one aspect, the present invention aims to provide a semiconductor device in which defects in the formation of a coating material that covers a semiconductor chip are suppressed. [Means for solving the problem]

[0013] In one aspect, a semiconductor device is provided, comprising: an insulating circuit board having a conductive pattern layer; a sintered member disposed on the conductive pattern layer and having a recess on the surface opposite the conductive pattern layer and a frame portion forming the outer edge of the recess; a semiconductor chip having an upper surface, a lower surface, and a side surface, the lower surface being mounted in the recess, and the upper surface opposite the sintered member being positioned closer to the conductive pattern layer than the upper end of the frame portion; and a coating material covering the semiconductor chip inside the frame portion.

[0014] In another aspect, there is provided a method for manufacturing a semiconductor device, comprising the steps of: preparing an insulating circuit board having a conductive pattern layer, and a semiconductor chip having an upper surface, a lower surface, and side surfaces; arranging a sintered member on the conductive pattern layer; arranging the lower surface of the semiconductor chip on the sintered member and pressing the area of ​​the sintered member that contacts the lower surface of the semiconductor chip toward the conductive pattern layer via the upper surface of the semiconductor chip, thereby forming a recess in the sintered member in which the semiconductor chip is mounted and a frame portion that forms the outer edge of the recess and has an upper end higher than the upper surface of the semiconductor chip; and a coating step of arranging a coating material inside the frame portion so as to cover the semiconductor chip. [Effects of the Invention]

[0015] In one aspect, it is possible to realize a semiconductor device in which defects in the formation of a coating material that covers a semiconductor chip are suppressed. [Brief explanation of the drawings]

[0016] [Figure 1] 1A and 1B are diagrams illustrating an example of a semiconductor device according to a first embodiment. [Figure 2] 1A to 1C are diagrams (part 1) illustrating an example of a semiconductor chip bonding step according to the first embodiment; [Figure 3] 10A to 10C are diagrams (part 2) illustrating an example of the semiconductor chip bonding step according to the first embodiment; [Figure 4] 3A to 3C are diagrams illustrating an example of a coating step according to the first embodiment. [Figure 5] 10A to 10C are diagrams illustrating an example of a coating step according to another embodiment. [Figure 6] 5A to 5C are diagrams illustrating an example of a sealing step according to the first embodiment. [Figure 7] 5A to 5C are diagrams illustrating another example of the semiconductor device according to the first embodiment. [Figure 8] 10A to 10C are diagrams illustrating a first modified example of the formation of the semiconductor device according to the first embodiment. [Figure 9] 10A to 10C are diagrams illustrating a second modified example of the semiconductor device formation according to the first embodiment. [Figure 10] 10A and 10B are diagrams illustrating an example of a semiconductor device according to a second embodiment. [Figure 11] 10A and 10B are diagrams illustrating an example of a jig used in forming a semiconductor device according to a second embodiment. [Figure 12] 10A to 10C are diagrams (part 1) illustrating an example of a semiconductor chip bonding step according to the second embodiment. [Figure 13] 10A to 10C are diagrams (part 2) illustrating an example of a semiconductor chip bonding step according to the second embodiment. [Figure 14] 10A to 10C are diagrams illustrating an example of a coating step according to the second embodiment. [Figure 15] 10A to 10C are diagrams illustrating an example of a sealing step according to the second embodiment. [Figure 16] 10A and 10B are diagrams illustrating a modified example of the jig according to the second embodiment. [Figure 17] 10A to 10C are diagrams illustrating an example of a method for manufacturing a semiconductor device according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0017] [First embodiment] Fig. 1 is a diagram illustrating an example of a semiconductor device according to a first embodiment. Fig. 1(A) is a schematic plan view of a main part of the semiconductor device, and Fig. 1(B) is a schematic cross-sectional view of a main part of the semiconductor device. Fig. 1(B) is a cross-sectional view taken along line II of Fig. 1(A).

[0018] A semiconductor device 1A shown in FIGS. 1(A) and 1(B) includes an insulating circuit board 10, a sintered member 20, a semiconductor chip 30, and a coating material 40.

[0019] As shown in FIGS. 1A and 1B, the insulating circuit board 10 includes an insulating substrate 11 and conductive pattern layers 12 and 13 provided on both main surfaces of the insulating substrate 11 in predetermined shapes. The insulating substrate 11 is made of a material with excellent electrical insulation and thermal conductivity. For example, the insulating substrate 11 may be made of alumina, alumina-based composite ceramics, aluminum nitride, silicon nitride, or the like. The conductive pattern layers 12 and 13 are made of a material with excellent electrical conductivity and processability. For example, the conductive pattern layers 12 and 13 may be made of metals such as copper and aluminum. The conductive pattern layers 12 and 13 may be made of copper, aluminum, or the like that has been treated with nickel plating or the like for rust prevention or other purposes. Methods for providing the conductive pattern layers 12 and 13 on the insulating substrate 11 include direct copper bonding and active metal brazing.

[0020] As shown in FIGS. 1A and 1B, the sintered member 20 is disposed on the conductive pattern layer 12 of the insulating circuit board 10. The sintered member 20 is an example of a material that electrically and mechanically connects the conductive pattern layer 12 of the insulating circuit board 10 and the semiconductor chip 30 disposed on the sintered member 20. For example, a paste-type material using nano- or micro-sized conductive particles is used, and the conductive particles are sintered together by applying pressure and heat. The conductive particles of such a sintered member 20 may be made of metals such as gold, silver, or copper, or materials based on such metals. However, the material of the conductive particles of the sintered member 20 is not limited to these.

[0021] 1(A) and 1(B), the semiconductor chip 30 is disposed on a sintered member 20 disposed on the conductive pattern layer 12 of the insulating circuit board 10. The semiconductor chip 30 is embedded in the sintered member 20 such that at least the lower surface 30b of the semiconductor chip 30 is in contact with the sintered member 20 and at least the upper surface 30a is exposed from the sintered member 20, among its upper surface 30a, lower surface 30b opposite to the upper surface 30a, side surface 30c between the upper surface 30a and the lower surface 30b, and corner portion 30d between the upper surface 30a and the side surface 30c. The positional relationship between the semiconductor chip 30 and the sintered member 20 will be described later.

[0022] The semiconductor chip 30 may include semiconductor elements such as an insulated gate bipolar transistor (IGBT) or a metal oxide semiconductor field effect transistor (MOSFET). The semiconductor chip 30 may include other semiconductor elements such as a junction field effect transistor (JFET) or a high electron mobility transistor (HEMT). Diode elements such as a free wheeling diode (FWD) or a Schottky barrier diode (SBD) may be mounted or connected to semiconductor elements such as an IGBT or a MOSFET. The semiconductor chip 30 may include various devices such as a silicon device, a silicon carbide device, or a gallium nitride device.

[0023] In addition to the semiconductor chip 30, other semiconductor chips of the same or different type as the semiconductor chip 30, various electronic components, etc. may be mounted on the insulating circuit board 10. The semiconductor chip 30 mounted on the insulating circuit board 10 may be connected to other conductive pattern layers, semiconductor chips, etc. provided on the insulating circuit board 10 using conductive members such as wires and clips.

[0024] As shown in FIGS. 1A and 1B, the coating material 40 is disposed so as to cover the semiconductor chip 30. The coating material 40 is disposed so as to cover, for example, the sintered member 20 and the insulating circuit board 10 in addition to the semiconductor chip 30. An organic material is used for the coating material 40. The coating material 40 is made of a material that has excellent adhesion to the sealing material, such as an epoxy resin composition, used to seal the semiconductor chip 30 and that has the property of alleviating stress generated in the semiconductor chip 30 and the sealing material. For example, the coating material 40 is made of a resin material such as a polyimide resin, a polyetheramide resin, a polyetherimide resin, or a polyamideimide resin. However, the material of the coating material 40 is not limited to these.

[0025] The insulating circuit board 10 may further be mounted with terminal components and the like that are connected to the semiconductor chip 30, etc. Furthermore, the insulating circuit board 10 may have the conductive pattern layer 13 on the opposite side of the conductive pattern layer 12 on which the semiconductor chip 30 is mounted via the sintered member 20 joined to another substrate such as a heat dissipation base or a lead frame via another joining member such as a solder member or a sintered member.

[0026] Next, the positional relationship between the semiconductor chip 30 and the sintered member 20 in the semiconductor device 1A having the above-described configuration will be described. The semiconductor chip 30 is embedded in a sintered member 20 arranged on the conductive pattern layer 12 of the insulating circuit board 10 so that its upper surface 30a is exposed. The sintered member 20 has a recess 21 and a frame portion 22 forming the outer edge of the recess 21 on the surface opposite to the conductive pattern layer 12. The recess 21 in the sintered member 20 is formed when the sintered member 20 on the conductive pattern layer 12 is pressed by the lower surface 30b of the semiconductor chip 30, forcing the semiconductor chip 30 into the sintered member 20. The frame portion 22 of the sintered member 20 is formed by the sintered member 20 being extruded around the semiconductor chip 30 as the recess 21 is formed. The semiconductor chip 30 is embedded in the recess 21 of the sintered member 20 so that its upper surface 30a is exposed, and the periphery of the semiconductor chip 30 is surrounded by the frame portion 22 of the sintered member 20.

[0027] Here, the semiconductor chip 30 is embedded in the recess 21 of the sintered member 20 so that its upper surface 30a is located closer to the conductive pattern layer 12 than the upper end 22a of the frame portion 22 of the sintered member 20. That is, the semiconductor chip 30 is embedded in the sintered member 20 so that its upper surface 30a and the upper end 22a of the frame portion 22 of the sintered member 20 have this positional relationship. Figure 1(B) illustrates an example in which the semiconductor chip 30 is embedded in the sintered member 20 so that the upper surface 30a of the semiconductor chip 30 is located lower on the conductive pattern layer 12 side than the upper end 22a of the frame portion 22 of the sintered member 20 by a height difference T1.

[0028] A coating material 40 is placed on the semiconductor chip 30 thus placed on the sintered member 20. For example, the fluid coating material 40 is placed on the upper surface 30a of the semiconductor chip 30, and as the fluid coating material 40 flows, the semiconductor chip 30 is covered with the coating material 40. As shown in FIGS. 1(A) and 1(B), the coating material 40 covers not only the semiconductor chip 30 but also the sintered member 20 and the insulating circuit board 10. The coating material 40 provided to cover the semiconductor chip 30 and the like is then hardened.

[0029] In the semiconductor device 1A, the top surface 30a of the semiconductor chip 30 is located closer to the conductive pattern layer 12 than the top end 22a of the frame portion 22 of the sintered member 20. Therefore, in the semiconductor device 1A, the coating material 40 provided on the semiconductor chip 30 remains inside the frame portion 22 of the sintered member 20 (in the recess 21), and is prevented from flowing out of the frame portion 22. In other words, the frame portion 22 of the sintered member 20 functions as a dam portion for the coating material 40. In this way, in the semiconductor device 1A, the coating material 40 remains inside the frame portion 22 of the sintered member 20, and therefore the semiconductor chip 30 (its top surface 30a, side surface 30c, and corners 30d between the top surface 30a and side surface 30c) is prevented from being exposed from the coating material 40.

[0030] Therefore, even if the semiconductor chip 30 and the like are encapsulated with an encapsulant after the coating material 40 is formed, direct contact between the semiconductor chip 30 and the encapsulant is prevented, and the coating material 40 interposed between the semiconductor chip 30 and the encapsulant enhances their adhesion and relieves stress therebetween. This prevents peeling of the encapsulant due to stress caused by the temperature load associated with heat generation during operation and subsequent cooling, as well as the difference in thermal expansion coefficients between the semiconductor chip 30 and the encapsulant. Preventing peeling of the encapsulant prevents a decrease in the reliability and insulation performance of the semiconductor chip 30 and the semiconductor device 1A incorporating it.

[0031] A method for forming the semiconductor device 1A having the above-described configuration will now be described in more detail. 2 and 3 are diagrams illustrating an example of a semiconductor chip bonding process according to the first embodiment. Fig. 2(A) shows a schematic cross-sectional view of an example of a state before semiconductor chip bonding, and Fig. 2(B) and 3 show schematic cross-sectional views of an example of a state after semiconductor chip bonding. Fig. 3 is a diagram for explaining the conductive particle density and porosity in the sintered member in an example of a state after semiconductor chip bonding.

[0032] First, an insulating circuit board 10 and a semiconductor chip 30 are prepared as shown in FIG. 2A. The insulating circuit board 10 has a sintered member 20 disposed on a conductive pattern layer 12 provided on one main surface of the insulating substrate 11. For example, a paste-type sintered member 20 containing conductive particles is disposed on the conductive pattern layer 12 of the insulating circuit board 10. The semiconductor chip 30 is then disposed so that its lower surface 30b faces the sintered member 20 on the conductive pattern layer 12. For example, a sintered member 20 having a planar size larger than the planar size of the lower surface 30b of the semiconductor chip 30 disposed opposite it is disposed on the conductive pattern layer 12. The thickness of the sintered member 20 disposed on the conductive pattern layer 12 is set to, for example, approximately 130 μm or more and 140 μm or less. The thickness of the semiconductor chip 30 is, for example, approximately 100 μm.

[0033] The semiconductor chip 30, which is arranged so that its lower surface 30b faces the sintered member 20 on the conductive pattern layer 12, is brought close to the sintered member 20, and the lower surface 30b comes into contact with the sintered member 20. Then, the region of the sintered member 20 that contacts the lower surface 30b of the semiconductor chip 30 is pressed toward the conductive pattern layer 12 via the upper surface 30a of the semiconductor chip 30. This pressurization forces the semiconductor chip 30 into the sintered member 20 on the conductive pattern layer 12, as shown in FIG. 2(B). As the semiconductor chip 30 is pressed by the pressurization, a recess 21 in which the semiconductor chip 30 is mounted is formed in the sintered member 20, and a frame portion 22 that forms the outer edge of the recess 21 is formed by a part of the sintered member 20 that is extruded around the semiconductor chip 30 as the recess 21 is formed. When the semiconductor chip 30 is pressed into the sintered member 20, the upper surface 30a thereof is pressed into the sintered member 20 so that it is positioned lower than the upper end 22a of the frame portion 22 of the sintered member 20, i.e., on the conductive pattern layer 12 side. The semiconductor chip 30 is pressed into the sintered member 20 so that the distance between the lower surface 30b (or the recess 21 of the sintered member 20) and the conductive pattern layer 12 (the thickness of the sintered member 20 below the recess 21) is approximately 10 μm or more and 30 μm or less.

[0034] After the semiconductor chip 30 is pressed against the sintered member 20, or while the semiconductor chip 30 is being pressed against the sintered member 20, the sintered member 20 is heated. If the surface of the conductive pattern layer 12 is not plated, the sintered member 20 is preferably heated in an inert gas atmosphere such as nitrogen. If the surface of the conductive pattern layer 12 is silver-plated, the sintered member 20 may be heated in an air atmosphere. The heating temperature of the sintered member 20 is set based on the temperature at which the conductive particles contained in the sintered member 20 can be sintered. For example, the heating temperature of the sintered member 20 may be 200°C or higher and 300°C or lower. Preferably, the heating temperature is 220°C or higher and 280°C or lower, and more preferably, the heating temperature is 240°C or higher and 260°C or lower.

[0035] When the semiconductor chip 30 is pressed into the sintered member 20, the conductive particles 23 contained therein come into contact with each other at a relatively high density in the region AR1 between the recess 21 on which the semiconductor chip 30 is mounted and the conductive pattern layer 12, as shown in Fig. 3. When heating is performed after pressing the semiconductor chip 30 onto the sintered member 20, or when heating is performed while pressing the semiconductor chip 30 onto the sintered member 20, the conductive particles 23 that are in contact with each other at a relatively high density in the region AR1 of the sintered member 20 are sintered. The conductor formed by sintering the conductive particles 23, i.e., the conductor into which the conductive particles 23 are integrated by sintering, forms a conductive path (and a heat conduction path) between the underside 30b of the semiconductor chip 30 and the conductive pattern layer 12 of the insulating circuit board 10.

[0036] On the other hand, in the region AR2 of the frame portion 22, which is formed by being extruded around the semiconductor chip 30 when the semiconductor chip 30 is pressed against the sintered member 20, the conductive particles 23 contained therein have a relatively low density compared to the region AR1. By heating, the conductive particles 23 that are in contact with each other at a relatively low density in the region AR2 of the sintered member 20 are also sintered together, forming a conductor, i.e., a conductor formed by sintering the conductive particles 23. Note that the density of the conductive particles 23 contained in the region AR2 of the frame portion 22 of the sintered member 20 before sintering by heating does not necessarily have to be as high as the density of the conductive particles 23 contained in the region AR1 below the recess 21. This is because a conductive path (and a heat conduction path) between the underside 30b of the semiconductor chip 30 and the conductive pattern layer 12 of the insulating circuit board 10 can be formed in the region AR1 below the recess 21.

[0037] In the sintered component 20 after heating and pressurization, voids are formed in the region AR1 between the recess 21 on which the semiconductor chip 30 is mounted and the conductive pattern layer 12, and in the region AR2 of the frame portion 22, due to the formation of a conductor by sintering the conductive particles 23. Here, since the region AR1 after heating and pressurization contains the conductive particles 23 at a relatively high density, the density of the conductor formed in the region AR1 by sintering the conductive particles 23 due to heating is relatively high, and the number of voids formed in the region AR1 is relatively small. On the other hand, since the region AR2 after heating and pressurization contains the conductive particles 23 at a relatively low density, the density of the conductor formed in the region AR2 by sintering the conductive particles 23 due to heating is relatively low, and the number of voids formed in the region AR2 is relatively large. Therefore, in the cross-sectional view shown in FIG. 3, the porosity of the region AR1 in the sintered component 20 after heating is lower than the porosity of the region AR2 in the sintered component 20 after heating. Due to the region AR1 where the void ratio is relatively low, a good electrical conduction path (and a heat conduction path) between the lower surface 30b of the semiconductor chip 30 and the conductive pattern layer 12 of the insulating circuit board 10 is realized.

[0038] The semiconductor chip bonding process shown in Figures 2(A) and 2(B) is an example of a sintered member molding process in which a semiconductor chip 30 is bonded to the conductive pattern layer 12 of the insulating circuit board 10 using a sintered member 20, and a recess 21 and a frame portion 22 forming the outer edge of the recess 21 are formed in the sintered member 20.

[0039] Figure 4 is a diagram illustrating an example of the coating process according to the first embodiment. Figure 4(A) shows a schematic cross-sectional view of a main part of an example of the coating material placing process, and Figure 4(B) shows a schematic cross-sectional view of a main part of an example of the coating material flowing process.

[0040] After the sintered member 20 is pressurized and heated, a coating material 40 is placed on the upper surface 30a of the semiconductor chip 30, as shown in FIG. 4(A). The coating material 40 to be placed has fluidity. The coating material 40 is applied to the upper surface 30a of the semiconductor chip 30 by dispensing or spraying, for example, and then placed. Note that the coating material 40 may be placed not only on the upper surface 30a of the semiconductor chip 30, but also on the sintered member 20 or the insulating circuit board 10, as shown in FIG. 4(A).

[0041] The coating material 40 placed on the upper surface 30a of the semiconductor chip 30 flows around the semiconductor chip 30 due to gravity, as shown in FIG. 4(B). The applied coating material 40 is set to have a viscosity that allows it to flow around the semiconductor chip 30 after being placed. As the coating material 40 flows around the semiconductor chip 30, the semiconductor chip 30 is covered with the coating material 40. In addition to the semiconductor chip 30, the coating material 40 also covers the sintered member 20 and the insulating circuit board 10, as shown in FIG. 4(B).

[0042] In this coating process, the semiconductor chip 30 on which the coating material 40 is placed is pressed into the sintered member 20 so that its upper surface 30a is lower than the upper end 22a of the frame 22 of the sintered member 20. Therefore, the frame 22 of the sintered member 20 functions as a dam, preventing excess coating material 40 from flowing out from the semiconductor chip 30 and ensuring that a certain amount of coating material 40 remains on the semiconductor chip 30. Since the upper end 22a of the frame 22 of the sintered member 20 is higher than the upper surface 30a of the semiconductor chip 30 and the coating material 40 remains inside the frame 22, the coating material 40 covers not only the upper surface 30a of the semiconductor chip 30 but also the side surface 30c of the semiconductor chip 30 exposed from the sintered member 20 and the corner 30d between the upper surface 30a and the side surface 30c. This prevents the semiconductor chip 30 from being exposed from the coating material 40 and ensures that the semiconductor chip 30 is covered with a sufficient thickness of coating material 40.

[0043] Here, Fig. 5 is a diagram illustrating an example of a coating step according to another embodiment. Fig. 5(A) shows a schematic cross-sectional view of a main part of an example of a coating material placing step, and Fig. 5(B) shows a schematic cross-sectional view of a main part of an example of a coating material flowing step.

[0044] For example, consider a configuration such as that shown in Figures 5(A) and 5(B), i.e., a configuration in which a sintered member 20a is interposed between the underside 30b of the semiconductor chip 30 and the conductive pattern layer 12, the semiconductor chip 30 is not pressed into the sintered member 20a, and the frame portion 22 as described above is not formed on the sintered member 20a.

[0045] In this configuration, as shown in FIG. 5(A), the coating material 40 is placed on the top surface 30a of the semiconductor chip 30. As shown in FIG. 5(B), when the coating material 40 flows around the semiconductor chip 30, a portion of the semiconductor chip 30 may be exposed from the coating material 40 or may not be covered with a sufficient thickness of the coating material 40. For example, the coating material 40 on the top surface 30a of the semiconductor chip 30 may flow down from the corners 30d to the side surfaces 30c, resulting in the corners 30d of the semiconductor chip 30 and their surrounding areas being exposed from the coating material 40 or insufficient thickness of the coating material 40 remaining at the corners 30d and their surrounding areas. Such defective formation of the coating material 40 is more likely to occur as the viscosity of the coating material 40 is lowered in order to ensure that the coating material 40 is sufficiently distributed over the surfaces of the semiconductor chip 30, the sintered component 20, and the insulating circuit board 10.

[0046] 4(A) and 4(B), if the semiconductor chip 30 is pressed into the sintered member 20 so that its upper surface 30a is lower than the upper end 22a of the frame portion 22 of the sintered member 20, and the frame portion 22 formed thereby functions as a dam portion, a certain amount of coating material 40 can be retained inside the frame portion 22. This makes it possible to prevent the semiconductor chip 30 from being exposed to the coating material 40 and to cover the semiconductor chip 30 with a sufficient thickness of coating material 40. In other words, it is possible to prevent poor formation of the coating material 40.

[0047] The coating material 40 formed to cover the semiconductor chip 30, the sintered member 20, and the insulating circuit board 10 is then cured using a predetermined method, such as heating, depending on the material of the coating material 40.

[0048] 6A to 6C are diagrams illustrating an example of the sealing step according to the first embodiment, and are schematic cross-sectional views of essential parts of an example of the sealing step. After the coating material 40 is formed, the insulating circuit board 10, sintered member 20, semiconductor chip 30, and coating material 40 are sealed with a sealing material 50, as shown in FIG. 6. For example, an epoxy resin composition containing an epoxy resin base and a curing agent is used for the sealing material 50. The epoxy resin composition of the sealing material 50 may contain fillers using inorganic materials and other additives. An aliphatic epoxy or alicyclic epoxy is used as the epoxy resin base. Furthermore, maleimide resin, cyanate resin, etc. can also be used for the sealing material 50, and a mixture of two or more resin materials including an epoxy resin can also be used.

[0049] The sealing material 50 formed to seal the insulating circuit board 10, the sintered member 20, the semiconductor chip 30, and the coating material 40 is then cured using a predetermined method, such as heating, depending on the material of the sealing material 50. This results in a semiconductor device 1A in which the insulating circuit board 10, the sintered member 20, the semiconductor chip 30, and the coating material 40 are sealed with the sealing material 50, as shown in FIG.

[0050] In the semiconductor device 1A, the semiconductor chip 30 mounted in the recess 21 inside the frame 22 of the sintered member 20 is not exposed from the coating material 40 but is covered with a sufficient thickness of the coating material 40. This prevents direct contact between the semiconductor chip 30 and the sealing material 50, and the coating material 40 interposed between the semiconductor chip 30 and the sealing material 50 enhances their adhesion and relieves stress therebetween. This prevents peeling of the sealing material 50 in the semiconductor device 1A due to stress caused by heat generation during operation and temperature loads associated with cooling, as well as differences in the thermal expansion coefficients of the semiconductor chip 30 and the sealing material 50. Preventing peeling of the sealing material 50 prevents degradation in the reliability and insulation performance of the semiconductor chip 30 and the semiconductor device 1A mounting it.

[0051] 7 is a diagram for explaining another example of the semiconductor device according to the first embodiment, which diagrammatically shows a cross-sectional view of a main part of the other example of the semiconductor device. The semiconductor device 1Aa shown in Figure 7 differs from the semiconductor device 1A shown in Figure 6 above in that it has a configuration in which a substrate 70 is joined via a joining member 60 to the conductive pattern layer 13 side of the insulating circuit board 10, opposite the conductive pattern layer 12 side on which the sintered member 20 and the semiconductor chip 30 are mounted.

[0052] In the case of a vertical element in which current flows in the thickness direction of the semiconductor chip 30, a sintered material is used for the bonding member 60. In the case of a horizontal element in which current flows in the width direction of the semiconductor chip 30, a material such as a conductive adhesive or a compound with good thermal conductivity may be used for the bonding member 60.

[0053] For example, a heat dissipation base is used for the substrate 70. The heat dissipation base is made of a material that has high thermal conductivity and is resistant to warping even after relatively high-temperature processing such as bonding using the bonding member 60, such as a copper plate or an aluminum composite silicon carbide plate. The heat dissipation base may also be equipped with a heat dissipation structure such as a cooling fin. In this case, in addition to the above materials, a material such as aluminum may also be used.

[0054] A lead frame may also be used for the substrate 70. A lead frame may be joined to the conductive pattern layer 13 side of the insulating circuit board 10 via a joining member 60, and the semiconductor chip 30 mounted on the conductive pattern layer 12 side of the insulating circuit board 10 via a sintered member 20 may be connected to the lead frame using a conductive member such as a wire or a clip, thereby forming a circuit including the lead frame, etc.

[0055] When the substrate 70 is bonded to the conductive pattern layer 13 side of the insulating circuit board 10 via a bonding member 60 as in the semiconductor device 1Aa, the substrate 70 is bonded to the conductive pattern layer 13 side of the insulating circuit board 10 via the bonding member 60 before ( FIG. 2(A) ) or after ( FIG. 2(B) ) the semiconductor chip 30 is bonded in the semiconductor chip bonding step (sintered member molding step) shown in FIGS. 2(A) and 2(B) above. Alternatively, the substrate 70 may be bonded to the conductive pattern layer 13 side of the insulating circuit board 10 via the bonding member 60 after the coating material 40 has flowed and hardened ( FIG. 4(B) ) in the coating step shown in FIGS. 4(A) and 4(B) above. The structure mounted on the substrate 70 via the bonding member 60, i.e., the insulating circuit board 10, sintered member 20, and semiconductor chip 30, and the coating material 40 covering them, are sealed with a sealing material 50 to obtain the semiconductor device 1Aa shown in FIG. 7.

[0056] In the semiconductor device 1Aa, the semiconductor chip 30 is also covered with a coating material 40 of sufficient thickness, which prevents peeling of the sealing material 50 due to stress caused by temperature load during operation and the difference in thermal expansion coefficient between the semiconductor chip 30 and the sealing material 50. This prevents a decrease in the reliability and insulation performance of the semiconductor chip 30 and the semiconductor device 1Aa on which it is mounted.

[0057] Modifications relating to the formation of the semiconductor device 1A and the like will be further described. 8A and 8B are diagrams illustrating a first modified example of the method for forming a semiconductor device according to the first embodiment. Fig. 8A shows a schematic cross-sectional view of an example of a main part before bonding a semiconductor chip, and Fig. 8B shows a schematic cross-sectional view of an example of a main part after bonding the semiconductor chip.

[0058] 8(A), on the conductive pattern layer 12 of the insulating circuit board 10, a continuous protrusion 80 may be provided outside the region AR3 where the sintered member 20 is disposed so as to surround the region AR3, or a plurality of protrusions 80 may be provided intermittently so as to surround the region AR3. The protrusions 80 are formed using a resin material such as epoxy resin. For example, the protrusions 80 are formed by dispensing or other methods of placing a predetermined resin material on the conductive pattern layer 12 of the insulating circuit board 10 and then curing it.

[0059] A sintered member 20 is placed in an area AR3 inside the protrusion 80 on the conductive pattern layer 12 of the insulating circuit board 10, and the semiconductor chip 30 is brought close to the sintered member 20 with its lower surface 30b facing the sintered member 20, as shown in FIG. 8(A). Then, the area of ​​the sintered member 20 that contacts the lower surface 30b of the semiconductor chip 30 is pressed toward the conductive pattern layer 12 via the upper surface 30a of the semiconductor chip 30, thereby forcing the semiconductor chip 30 into the sintered member 20, as shown in FIG. 8(B). As a result, a recess 21 in which the semiconductor chip 30 is mounted is formed in the sintered member 20, and a frame portion 22 is formed by part of the sintered member 20 that is extruded around the semiconductor chip 30 as the recess 21 is formed. The semiconductor chip 30 is pressed into the sintered member 20 so that its upper surface 30a is lower than the upper end 22a of the frame portion 22.

[0060] When the semiconductor chip 30 is pressed into the sintered member 20, the part of the sintered member 20 pressed out around the semiconductor chip 30 is prevented from spreading laterally (in a direction parallel to the conductive pattern layer 12) by the outer protrusion 80 acting as a wall, and is more likely to protrude upward (in a direction perpendicular to the conductive pattern layer 12). In other words, the protrusion 80 functions as a dam that holds the sintered member 20 inside. The protrusion 80 functions as a dam for the sintered member 20, making it easier to obtain a structure in which the upper end 22a of the frame portion 22 is positioned higher than the upper surface 30a of the semiconductor chip 30.

[0061] The semiconductor chip 30, protrusion 80, sintered member 20, and insulating circuit board 10 arranged as shown in FIG. 8(B) are covered with the coating material 40 according to the above example, and then sealed with the sealing material 50.

[0062] 9A and 9B are diagrams illustrating a second modified example of the semiconductor device formation according to the first embodiment. Fig. 9A is a schematic cross-sectional view of an example of a main part before bonding a semiconductor chip, and Fig. 9B is a schematic cross-sectional view of an example of a main part after bonding the semiconductor chip.

[0063] 9(A), a recess 90 may be provided in the conductive pattern layer 12 of the insulating circuit board 10 in an area AR4 where the sintered member 20 is disposed. The recess 90 is formed, for example, by etching the conductive pattern layer 12.

[0064] The sintered member 20 is placed in an area AR4 of a recess 90 provided in the conductive pattern layer 12 of the insulating circuit board 10, and the semiconductor chip 30, arranged with its lower surface 30b facing the sintered member 20, is brought close to the sintered member 20, as shown in FIG. 9(A). Then, the area of ​​the sintered member 20 that contacts the lower surface 30b of the semiconductor chip 30 is pressed toward the conductive pattern layer 12 via the upper surface 30a of the semiconductor chip 30, thereby forcing the semiconductor chip 30 into the sintered member 20, as shown in FIG. 9(B). As a result, a recess 21 in which the semiconductor chip 30 is mounted is formed in the sintered member 20, and a frame portion 22 is formed by a part of the sintered member 20 that is extruded around the semiconductor chip 30 as the recess 21 is formed. The semiconductor chip 30 is pressed into the sintered member 20 so that its upper surface 30a is lower than the upper end 22a of the frame portion 22.

[0065] When the semiconductor chip 30 is pressed into the sintered member 20, part of the sintered member 20 pressed out around the semiconductor chip 30 is prevented from spreading laterally by the inner walls 91 of the recessed portions 90 of the conductive pattern layer 12, and is therefore more likely to protrude upward. That is, the inner walls 91 of the recessed portions 90 function as dam portions that hold the sintered member 20 therein. The inner walls 91 of the recessed portions 90 function as dam portions for the sintered member 20, making it easier to obtain a structure in which the upper end 22a of the frame portion 22 is positioned higher than the upper surface 30a of the semiconductor chip 30.

[0066] The semiconductor chip 30, sintered member 20, and insulating circuit board 10 arranged as shown in FIG. 9(B) are covered with the coating material 40 and then sealed with the sealing material 50 according to the above example.

[0067] 8(A) and 8(B) may be provided on the conductive pattern layer 12, on which the recessed portion 90 as shown in FIG. 9(A) and FIG. 9(B) is provided, outside the region AR4 where the sintered portion 20 is disposed. In this way, the inner wall 91 of the recessed portion 90 and the protruding portion 80 function as a dam portion, which suppresses the lateral expansion of the sintered portion 20 and promotes its upward protrusion, making it easier to obtain a structure in which the upper end 22a of the frame portion 22 is positioned higher than the upper surface 30a of the semiconductor chip 30.

[0068] [Second embodiment] 10A and 10B are diagrams illustrating an example of a semiconductor device according to the second embodiment. Fig. 10A is a schematic plan view of a main part of the semiconductor device, and Fig. 10B is a schematic cross-sectional view of a main part of the semiconductor device. Fig. 10B is a cross-sectional view taken along line XX in Fig. 10A.

[0069] 10(A) and 10(B) includes an insulating circuit board 10, a sintered member 20, a semiconductor chip 30, and a coating material 40. The sintered member 20 of the semiconductor device 1B has a recess 21 in which the semiconductor chip 30 is mounted and a frame portion 22 that forms the outer edge of the recess 21, and has a shape such that the inner wall of the frame portion 22 (or the recess 21) does not come into contact with the side surface 30c of the semiconductor chip 30. The semiconductor device 1B differs from the semiconductor device 1A described in the first embodiment above in that it includes such a sintered member 20.

[0070] In the semiconductor device 1B, the semiconductor chip 30 is embedded in the sintered member 20 so that its top surface 30a, side surfaces 30c, and corners 30d are exposed from the sintered member 20, and the top end 22a of the frame portion 22 is positioned higher than the top surface 30a of the semiconductor chip 30. Figure 10(B) illustrates a case where the semiconductor chip 30 is embedded in the sintered member 20 so that the top surface 30a of the semiconductor chip 30 is positioned lower on the conductive pattern layer 12 side than the top end 22a of the frame portion 22 of the sintered member 20 by a height difference T2.

[0071] The semiconductor chip 30, sintered member 20, and insulating circuit board 10 arranged in this manner are covered with a coating material 40. In the semiconductor device 1B, similar to the semiconductor device 1A, the upper surface 30a of the semiconductor chip 30 is located closer to the conductive pattern layer 12 than the upper end 22a of the frame portion 22 of the sintered member 20, so the coating material 40 remains inside (in the recess 21) of the frame portion 22. This prevents the semiconductor chip 30 (the upper surface 30a, the side surface 30c, and the corners 30d between the upper surface 30a and the side surface 30c) from being exposed from the coating material 40.

[0072] A method for forming the semiconductor device 1B having the above-described configuration will be described. Figure 11 is a diagram illustrating an example of a jig used in forming a semiconductor device according to the second embodiment. Figure 11(A) is a schematic plan view of a main part of the example of the jig, and Figure 11(B) is a schematic cross-sectional view of a main part of the example of the jig. Figure 11(B) is a cross-sectional view taken along line XI-XI of Figure 11(A).

[0073] A jig 100 as shown in Figures 11(A) and 11(B) is used to form the semiconductor device 1B. The jig 100 has a plate portion 103, and a surrounding portion 101 (first surrounding portion) and a surrounding portion 102 (second surrounding portion) provided on one surface (inner surface) 103a of the plate portion 103. Note that Figure 11(A) is a plan view of the jig 100 as seen from the inner surface 103a side of the plate portion 103 on which the surrounding portion 101 and the surrounding portion 102 are provided. The jig 100 further has a through hole 104 provided in the plate portion 103 inside the surrounding portion 101.

[0074] The surrounding portion 101 of the jig 100 protrudes from the inner surface 103a of the plate portion 103 at a height H1. The surrounding portion 102 of the jig 100 is provided on the inner surface 103a of the plate portion 103 outside the surrounding portion 101, and protrudes from the inner surface 103a at a height H2 that is higher than the height H1 of the surrounding portion 101. The semiconductor chip 30 is held inside the surrounding portion 101 of the jig 100 when the semiconductor device 1B is formed as described below. The surrounding portion 102 is provided at a certain distance from the surrounding portion 101 provided inside it. The inner surface 103a between the surrounding portions 101 and 102 is provided at a deeper position than the inner surface 103a inside the surrounding portion 101 when viewed from the inner surface 103a side. The jig 100 can be made of various materials such as metal, ceramic, carbon, and resin.

[0075] 12 and 13 are diagrams illustrating an example of a semiconductor chip bonding process according to the second embodiment. Fig. 12(A) shows a schematic cross-sectional view of a main part of an example of a state before semiconductor chip bonding, and Fig. 12(B) shows a schematic cross-sectional view of a main part of an example of a jig abutment process. Fig. 13(A) shows a schematic cross-sectional view of a main part of an example of a jig separation process, and Fig. 13(B) shows a schematic cross-sectional view of a main part of an example of a state after semiconductor chip bonding.

[0076] When joining the semiconductor chip 30 to the sintered member 20 arranged on the conductive pattern layer 12 of the insulating circuit board 10, the semiconductor chip 30 is held inside the surrounding portion 101 of the jig 100 so that the top surface 30a of the semiconductor chip 30 faces the inner surface 103a of the plate portion 103 of the jig 100, as shown in Fig. 12(A). At this time, the semiconductor chip 30 is sucked and held by the inner surface 103a due to negative pressure generated in the through-hole 104 by suction from the nozzle tip of a chip mounter provided on the surface of the jig 100 opposite the inner surface 103a.

[0077] The jig 100 holding the semiconductor chip 30 is transported by a chip mounter and brought close to the conductive pattern layer 12 of the insulating circuit board 10 and the sintered member 20 placed thereon. Pressurization causes the outer surrounding portion 102 of the surrounding portion 101 holding the semiconductor chip 30 to abut against the conductive pattern layer 12, as shown in FIG. 12(B). During this process, the semiconductor chip 30 and the surrounding portion 101 holding it are pressed into the sintered member 20, forming a recess 21 in the sintered member 20. A portion of the sintered member 20 is pushed outward as the recess 21 is formed, and is pushed into a gap between the surrounding portion 101 holding the semiconductor chip 30 and the outer surrounding portion 102, filling the gap. This forms a frame portion 22 in the sintered member 20.

[0078] By making the height of the surrounding portion 101 that holds the semiconductor chip 30 from the inner surface 103a of the plate portion 103 lower than the height of the surrounding portion 102 outside it from the inner surface 103a of the plate portion 103, it becomes possible to extrude a portion of the sintered member 20 from the area sandwiched between the semiconductor chip 30 and the conductive pattern layer 12 into the area of ​​the gap between the surrounding portion 101 and the surrounding portion 102 until the surrounding portion 102 abuts against the conductive pattern layer 12. Furthermore, the inner surface 103a between the surrounding portions 101 and 102 of the jig 100 is positioned deeper than the inner surface 103a inside the surrounding portion 101 when viewed from the inner surface 103a side, and the semiconductor chip 30 is held inside the surrounding portion 101, so that the upper end 22a of the frame portion 22 formed when the surrounding portion 102 abuts against the conductive pattern layer 12 can be positioned higher than the upper surface 30a of the semiconductor chip 30.

[0079] After the semiconductor chip 30 is pressed against the sintered member 20 using the jig 100, or while the semiconductor chip 30 is being pressed against the sintered member 20 using the jig 100, the sintered member 20 is heated. As a result, the conductive particles that are in contact within the sintered member 20 are sintered together, and a conductive path (and a heat conductive path) is formed between the underside 30b of the semiconductor chip 30 and the conductive pattern layer 12 of the insulating circuit board 10. As described above with reference to FIG. 3, the porosity of the sintered member 20 in which the conductive particle groups have been sintered by heating may be lower between the recess 21 in which the semiconductor chip 30 is mounted and the conductive pattern layer 12 than between the frame portion 22.

[0080] After the semiconductor chip 30 is pressed and heated against the sintered member 20 using the jig 100, the jig 100 is separated from the semiconductor chip 30, the sintered member 20, and the conductive pattern layer 12, as shown in FIG. 13(A). At this time, the semiconductor chip 30 becomes releasable from the inner surface 103a due to the positive pressure generated in the through hole 104 when the suction (negative pressure in the through hole 104) by the nozzle tip of the chip mounter provided on the surface opposite the inner surface 103a of the jig 100 is released. From this state, the jig 100 is lifted and separated from the semiconductor chip 30, the sintered member 20, and the conductive pattern layer 12. As a result, a structure as shown in FIG. 13(B) is formed.

[0081] The semiconductor chip bonding process shown in Figures 12(A) and 12(B) and Figures 13(A) and 13(B) is an example of a sintered member molding process in which a semiconductor chip 30 is bonded to a conductive pattern layer 12 using a sintered member 20, and a recess 21 and a frame portion 22 forming its outer edge are formed in the sintered member 20.

[0082] Figure 14 is a diagram illustrating an example of a coating process according to the second embodiment. Figure 14(A) shows a schematic cross-sectional view of a main part of an example of a coating material placing process, and Figure 14(B) shows a schematic cross-sectional view of a main part of an example of a coating material flowing process.

[0083] After the jig 100 is separated, as shown in FIG. 14(A), the coating material 40 is applied to the upper surface 30a of the semiconductor chip 30 by dispensing, spraying, or the like, and then placed. The coating material 40 may be placed on the sintered member 20 or the insulating circuit board 10 in addition to the semiconductor chip 30. The coating material 40 placed on the upper surface 30a of the semiconductor chip 30 flows to the periphery of the semiconductor chip 30 due to gravity, as shown in FIG. 14(B). As the coating material 40 flows to the periphery of the semiconductor chip 30, the semiconductor chip 30 is covered with the coating material 40. The coating material 40 covers the sintered member 20 and the insulating circuit board 10 in addition to the semiconductor chip 30.

[0084] In this coating process, the semiconductor chip 30 on which the coating material 40 is placed is pressed into the sintered member 20 so that its upper surface 30a is lower than the upper end 22a of the frame 22 of the sintered member 20. Therefore, the frame 22 of the sintered member 20 functions as a dam, preventing excess coating material 40 from flowing out from the semiconductor chip 30, and a certain amount of coating material 40 remains on the semiconductor chip 30 and around it (the gap between the side surface 30c and the surrounding portion 101). Since the upper end 22a of the frame 22 of the sintered member 20 is higher than the upper surface 30a of the semiconductor chip 30 and the coating material 40 remains inside the frame 22, the upper surface 30a of the semiconductor chip 30 as well as the side surface 30c and corners 30d are covered with the coating material 40. This prevents the semiconductor chip 30 from being exposed to the coating material 40, and ensures that the semiconductor chip 30 is covered with a sufficient thickness of coating material 40.

[0085] The coating material 40 formed to cover the semiconductor chip 30, the sintered member 20, and the insulating circuit board 10 is then cured using a predetermined method, such as heating, depending on the material of the coating material 40.

[0086] Fig. 15 is a diagram illustrating an example of a sealing step according to the second embodiment, and shows a schematic cross-sectional view of a main part of an example of the sealing step. After the coating material 40 is formed, the insulating circuit board 10, the sintered member 20, the semiconductor chip 30, and the coating material 40 are sealed with a sealing material 50, as shown in Fig. 15. The sealing material 50 is hardened using a predetermined method, such as heating, depending on the material of the sealing material 50. In this way, a semiconductor device 1B as shown in Fig. 15 is obtained.

[0087] In the semiconductor device 1B, the semiconductor chip 30 mounted in the recess 21 inside the frame 22 of the sintered member 20 is not exposed from the coating material 40 but is covered with a sufficient thickness of the coating material 40. This prevents direct contact between the semiconductor chip 30 and the sealing material 50, and the coating material 40 interposed between the semiconductor chip 30 and the sealing material 50 enhances their adhesion and relieves stress therebetween. This prevents peeling of the sealing material 50 in the semiconductor device 1B due to stress caused by heat generation during operation and temperature loads associated with cooling, as well as differences in the thermal expansion coefficients of the semiconductor chip 30 and the sealing material 50. Preventing peeling of the sealing material 50 prevents degradation in the reliability and insulation performance of the semiconductor chip 30 and the semiconductor device 1B mounting it.

[0088] Furthermore, a substrate 70 such as a heat dissipation base or a lead frame may be joined via a joining member 60 to the conductive pattern layer 13 side of the insulating circuit board 10 of the semiconductor device 1B, opposite to the conductive pattern layer 12 side on which the sintered member 20 and the semiconductor chip 30 are mounted, as in the example of Figure 7 above.

[0089] A further description will be given of a modified example of the jig 100 used in forming the semiconductor device 1B and the like. 16A to 16D are diagrams illustrating a modified example of the jig according to the second embodiment. Each of Fig. 16A to Fig. 16D is a schematic cross-sectional view of a main part of an example of the jig holding a semiconductor chip.

[0090] The jig 100a shown in FIG. 16(A) is an example made of a material softer than the semiconductor chip 30. In the jig 100a, a plate portion 103, a surrounding portion 101, and a surrounding portion 102 are made of a soft material, and the plate portion 103 is provided with a through-hole 104 for suction-holding and releasing the semiconductor chip 30. For example, the jig 100a is made of silicone resin, polyimide resin, graphite, or the like. The top surface 30a of the semiconductor chip 30 is provided with terminals for electrically connecting the semiconductor chip to other components, a protective film (passivation film) for protecting the top surface 30a except for the exposed portions of such terminals, and the like. Therefore, the top surface 30a of the semiconductor chip 30 may have irregularities. When a jig 100a softer than the semiconductor chip 30 is used as a jig for holding the semiconductor chip 30, which may have unevenness on its upper surface 30a, the unevenness on the upper surface 30a can be absorbed by the soft inner surface 103a even when the upper surface 30a of the opposing semiconductor chip 30 comes into contact with the inner surface 103a of the plate portion 103. Furthermore, when a jig 100a softer than the semiconductor chip 30 is used, it becomes possible to prevent damage to the semiconductor chip 30 due to collision with the plate portion 103 or the surrounding portion 101 during holding.

[0091] 16B shows an example of a jig 100b in which a portion 103b of the plate portion 103, inside the surrounding portion 101 where the semiconductor chip 30 is held, is made of a soft material. In the jig 100b, the portion 103b made of a soft material is provided with a through-hole 104 for suction-holding and releasing the semiconductor chip 30. For example, the portion 103b of the jig 100b is made of silicone resin, polyimide resin, graphite, or the like. The jig 100b having such a soft portion 103b also allows the portion 103b to absorb irregularities on the upper surface 30a of the semiconductor chip 30. Furthermore, it is possible to prevent damage to the semiconductor chip 30 due to collision with the plate portion 103 during holding.

[0092] 16(C) is an example of a jig 100c in which a layer 110 made of a soft material is provided inside the surrounding portion 101 in which the semiconductor chip 30 is held. In the jig 100c, a plate portion 103 inside the surrounding portion 101 and a layer 110 formed thereon are provided with through-holes 104 for suction-holding and releasing the semiconductor chip 30. For example, the layer 110 of the jig 100c may be made of a silicone resin, a polyimide resin, graphite, or the like. The jig 100c having such a soft layer 110 also allows the layer 110 to absorb unevenness on the top surface 30a of the semiconductor chip 30. Furthermore, the layer 110 can prevent damage to the semiconductor chip 30 due to collisions during holding.

[0093] 16(D) is an example of a jig 100d in which a layer 120 made of a soft material is provided to cover the inner surface 103a of the plate portion 103 on which the surrounding portion 101 and the surrounding portion 102 are provided. In the jig 100d, the plate portion 103 inside the surrounding portion 101 and the layer 120 formed thereon are provided with through-holes 104 for suction-holding and releasing the semiconductor chip 30. For example, the layer 120 of the jig 100d may be made of silicone resin, polyimide resin, graphite, or the like. The jig 100d having such a soft layer 120 can also absorb unevenness on the upper surface 30a of the semiconductor chip 30. Furthermore, the layer 120 can prevent damage to the semiconductor chip 30 due to collisions during holding. If a material having low adhesion to the sintered member 20 is used for the layer 120, it becomes possible to improve the separability, i.e., the ease of peeling from the sintered member 20, when the jig 100d holding the semiconductor chip 30 is separated after being pressed against the sintered member 20 side on the insulating circuit board 10 (Figure 13).

[0094] [Third embodiment] Here, an example of a method for manufacturing the semiconductor devices 1A, 1B and the like as described above will be described as the third embodiment. FIG. 17 is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the third embodiment.

[0095] In the manufacture of semiconductor devices 1A, 1B, etc., an insulating circuit board 10 is prepared in which conductive pattern layers 12 and 13 are provided on both main surfaces of an insulating substrate 11 (step S1). Also, a semiconductor chip 30 to be mounted on the insulating circuit board 10 is prepared (step S2). The order of steps S1 and S2 does not matter.

[0096] The sintered member 20 is placed on the conductive pattern layer 12 of the prepared insulating circuit board 10 (step S3). When providing a protrusion 80 on the conductive pattern layer 12 to function as a dam portion for the sintered member 20 (FIG. 8), the protrusion 80 is formed on the conductive pattern layer 12 before the sintered member 20 is placed on the conductive pattern layer 12, and the sintered member 20 is placed inside the formed protrusion 80. When providing a recess 90 on the conductive pattern layer 12 to function as a dam portion for the sintered member 20 (FIG. 9), the recess 90 is formed in the conductive pattern layer 12 before the sintered member 20 is placed on the conductive pattern layer 12, and the sintered member 20 is placed inside the formed recess 90.

[0097] Next, the prepared semiconductor chip 30 is placed on the sintered member 20 placed on the conductive pattern layer 12, and pressure is applied to form a recess 21 and a frame portion 22 in the sintered member 20 (step S4). More specifically, the lower surface 30b of the semiconductor chip 30 is placed on the conductive pattern layer 12, and a region of the sintered member 20 that contacts the lower surface 30b of the semiconductor chip 30 is pressed toward the conductive pattern layer 12 via the upper surface 30a of the semiconductor chip 30. This pressure forms a recess 21 in which the semiconductor chip 30 is mounted in the sintered member 20, and also forms a frame portion 22 that forms the outer edge of the recess 21 and has an upper end 22a positioned higher than the upper surface 30a of the semiconductor chip 30. A jig 100 such as that shown in FIG. 11 may be used to apply pressure to the semiconductor chip 30 and the sintered member 20, thereby forming the recess 21 and frame portion 22 of the sintered member 20. After the semiconductor chip 30 is pressed against the sintered member 20, or while the semiconductor chip 30 is being pressed against the sintered member 20, the sintered member 20 is heated. This causes the conductive particles 23 contained in the sintered member 20 to be sintered.

[0098] After the sintered member 20 is pressurized and heated, a coating material 40 is formed to cover the semiconductor chip 30, the sintered member 20, and the insulating circuit board 10 (step S5). At this time, the upper surface 30a of the semiconductor chip 30 is located closer to the conductive pattern layer 12 than the upper end 22a of the frame portion 22 of the sintered member 20, so the coating material 40 remains inside the frame portion 22 (recess 21). This prevents the semiconductor chip 30 (its upper surface 30a, side surface 30c, and corners 30d between the upper surface 30a and side surface 30c) from being exposed from the coating material 40. The coating material 40 covering the semiconductor chip 30 is hardened using a method such as heating.

[0099] When a substrate 70 such as a heat dissipation base or a lead frame is joined to the conductive pattern layer 13 side of the insulating circuit board 10 via a joining member 60 (FIG. 7), the substrate 70 is joined via the joining member 60 to the conductive pattern layer 13 side before or after the semiconductor chip 30 is placed in step S4 (FIG. 2), or to the conductive pattern layer 13 side after the coating material 40 is formed in step S5 (FIG. 4).

[0100] After the coating material 40 is formed, the insulating circuit board 10, the sintered member 20, the semiconductor chip 30, and the coating material 40 are sealed with a sealing material 50 (step S6). In this way, the semiconductor devices 1A, 1B, etc. as described above are obtained.

[0101] In the semiconductor devices 1A, 1B, etc., the semiconductor chip 30 mounted in the recess 21 inside the frame 22 of the sintered member 20 is not exposed from the coating material 40 but is covered with a sufficient thickness of the coating material 40. Therefore, the coating material 40 interposed between the semiconductor chip 30 and the sealing material 50 increases their adhesion and relieves stresses that occur therebetween. This prevents peeling of the sealing material 50 due to stress caused by temperature loads during operation and differences in the thermal expansion coefficients of the semiconductor chip 30 and the sealing material 50. By preventing peeling of the sealing material 50, deterioration in the reliability and insulation performance of the semiconductor chip 30 and the semiconductor device 1A, 1B, etc. mounting the same is prevented. [Explanation of symbols]

[0102] 1A, 1Aa, 1B Semiconductor device 10. Insulated circuit board 11 Insulating substrate 12,13 Conductive pattern layer 20, 20a Sintered material 21 Recess 22 Frame 22a top end 23 Conductive particles 30 Semiconductor Chips 30a top surface 30b Bottom side 30c side 30d corner 40 Coating Materials 50 Encapsulating material 60 Joint material 70 boards 80 Protrusion 90 recess 91 Inner wall 100, 100a, 100b, 100c, 100d Jig 101,102 Surrounding area 103 Plate section 103a Inner surface 103b Part 104 Through hole 110,120 layers AR1,AR2,AR3,AR4 area H1, H2 height T1,T2 height difference

Claims

1. an insulating circuit board having a conductive pattern layer; a sintered member disposed on the conductive pattern layer and having a recess on a surface opposite to the conductive pattern layer and a frame portion forming an outer edge of the recess; a semiconductor chip having an upper surface, a lower surface, and a side surface, the lower surface being mounted in the recess, and the upper surface opposite to the sintered member being positioned closer to the conductive pattern layer than the upper end of the frame; a coating material that covers the semiconductor chip inside the frame; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, wherein the coating material covers the top surface, the side surfaces, and corners between the top surface and the side surfaces of the semiconductor chip mounted in the recess of the sintered member.

3. 3. The semiconductor device according to claim 1, wherein the sintered member has a porosity between the recess and the conductive pattern layer that is lower than a porosity of the frame portion in a cross-sectional view.

4. The semiconductor device according to claim 1 , further comprising a protrusion disposed on the conductive pattern layer outside the frame portion so as to protrude from the conductive pattern layer.

5. the conductive pattern layer has a recessed portion, The semiconductor device according to claim 1 , wherein the sintered member is disposed in the recessed portion of the conductive pattern layer.

6. providing an insulating circuit board having a conductive pattern layer and a semiconductor chip having a top surface, a bottom surface, and a side surface; placing a sintered member on the conductive pattern layer; a sintered member molding process in which the lower surface of the semiconductor chip is placed on the sintered member, and a region of the sintered member that contacts the lower surface of the semiconductor chip is pressed against the conductive pattern layer via the upper surface of the semiconductor chip, thereby forming a recess in the sintered member in which the semiconductor chip is mounted and a frame portion that forms the outer edge of the recess and has an upper end higher than the upper surface of the semiconductor chip; a coating step of disposing a coating material on the inside of the frame portion so as to cover the semiconductor chip; A method for manufacturing a semiconductor device comprising:

7. The coating step includes: placing the fluid coating material on the upper surface of the semiconductor chip mounted in the recess; allowing the deposited coating material to flow; The method for manufacturing a semiconductor device according to claim 6 , comprising:

8. The coating step includes:

8. The method for manufacturing a semiconductor device according to claim 6, further comprising the step of covering the top surface, the side surfaces, and corners between the top surface and the side surfaces of the semiconductor chip mounted in the recess with the coating material.

9. The sintered member forming step includes:

9. The method for manufacturing a semiconductor device according to claim 6, further comprising the step of heating the sintered member after applying pressure to the sintered member.

10. The sintered member forming step includes: The method for manufacturing a semiconductor device according to claim 6 , further comprising the step of heating the sintered member while applying pressure thereto.

11. The sintered member forming step includes: a jig including a plate portion, a first surrounding portion provided on a first surface of the plate portion and protruding from the first surface at a first height, and a second surrounding portion provided on the first surface of the plate portion outside the first surrounding portion and protruding from the first surface at a second height higher than the first height, holding the semiconductor chip inside the first surrounding portion so that the top surface faces the first surface; a step of pressing the sintered member against the conductive pattern layer on which the sintered member is disposed by bringing the second surrounding portion of the jig holding the semiconductor chip into contact with the conductive pattern layer, thereby forming the recess, and extruding the sintered member between the first surrounding portion and the second surrounding portion to form the frame portion; Separating the jig from the semiconductor chip, the sintered member, and the conductive pattern layer; 11. The method for manufacturing a semiconductor device according to claim 6, further comprising:

12. The method for manufacturing a semiconductor device according to claim 11 , wherein the jig is softer than the semiconductor chip.

13. 12. The method for manufacturing a semiconductor device according to claim 11, wherein the jig has a layer softer than the semiconductor chip at least in a region surrounded by the first surrounding portion on the first surface side of the plate.

Images