Semiconductor Devices

Abstract

To provide a semiconductor device in which a resistance element with a small temperature coefficient can be made compact.SOLUTION: A semiconductor device comprises: a polysilicon layer 1, a resistance region 1a provided in the polysilicon layer 1, a first contact region which is provided in the resistance region 1a, and has the same conductivity type with the resistance region 1a and higher impurity density than that of the resistance region 1a; first wiring 2 electrically connected to one end of the resistance region 1a through a plurality of first vias 2a to 2d; and second wiring 3 electrically connected to the other end of the resistance region 1a through a plurality of second vias 3a to 3d. The first via 2a and second via 3a constitute a low-resistance contact structure in contact with the first contact region, and the first vias 2b to 2d and second vias 3b to 3d constitute a high-resistance contact structure having higher resistance than that of the low-resistance contact structure.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] A known conventional resistor element (resistor unit) is one that consists of a p-type polysilicon resistor and an n-type polysilicon resistor connected in series or parallel to form a single resistor. In such resistor elements, the temperature-dependent characteristic changes are offset (cancelled) by appropriately selecting the number of sheets of p-type polysilicon resistors with a positive temperature coefficient and n-type polysilicon resistors with a negative temperature coefficient, resulting in a resistor with a small temperature coefficient overall.

[0003] The contact portions of the p-type polysilicon resistor and the n-type polysilicon resistor are configured to reduce the contact resistance as much as possible by forming contact regions with high impurity concentrations and increasing the number of parallel contacts, so that the contact resistance component does not affect the characteristics of the resistor element.

[0004] Patent Documents 1 to 8 each disclose a configuration in which two types of resistors, such as polysilicon resistors or diffusion layers with different temperature coefficients, are connected in series or in parallel to adjust the temperature coefficient of the entire resistor. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-147380 [Patent Document 2] Japanese Patent Application Laid-Open No. 60-128651 [Patent Document 3] Japanese Patent Application Publication No. 61-191061 [Patent Document 4] Japanese Patent Application Publication No. 61-256756 [Patent Document 5] Japanese Patent Application Publication No. 3-85758 [Patent Document 6] Japanese Patent Application Publication No. 6-53417 [Patent Document 7] Japanese Patent Application Publication No. 9-17952 [Patent Document 8] Japanese Patent Application Publication No. 9-36310 Summary of the Invention [Problem to be solved by the invention]

[0006] However, in the configurations described in Patent Documents 1 to 8, it is necessary to combine two types of resistors with different temperature coefficients, making it difficult to reduce the size of the resistance element.

[0007] In view of the above problems, an object of the present invention is to provide a semiconductor device that can reduce the size of a resistor element with a small temperature coefficient. [Means for solving the problem]

[0008] One aspect of the present invention is a semiconductor device comprising: (a) a polysilicon layer; (b) a resistive region provided in the polysilicon layer; (c) a first contact region provided in the resistive region, the first contact region having the same conductivity type as the resistive region but a higher impurity concentration than the resistive region; (d) a first wiring electrically connected to one end of the resistive region via a plurality of first vias; and (e) a second wiring electrically connected to the other end of the resistive region via a plurality of second vias, wherein some of the plurality of first vias and the plurality of second vias are in contact with the first contact region to form a low-resistance contact structure, and other some of the plurality of first vias and the plurality of second vias form a high-resistance contact structure higher than the low-resistance contact structure. [Effects of the Invention]

[0009] According to the present invention, it is possible to provide a semiconductor device that can reduce the size of a resistor element with a small temperature coefficient. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a plan view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along line AA′ in FIG. [Figure 3] FIG. 2 is a cross-sectional view taken along line BB′ in FIG. [Figure 4] FIG. 2 is a cross-sectional view taken along line CC′ in FIG. [Figure 5] FIG. 2 is a cross-sectional view taken along line DD′ in FIG. [Figure 6] 10 is a graph showing the temperature dependence of the contact resistance of a low-resistance contact structure, the contact resistance of a high-resistance contact structure, and the sheet resistance of a resistance region. [Figure 7] 1 is a graph showing the temperature dependence of resistance values ​​of an example, comparative examples A and B. [Figure 8] 1 is a graph showing the temperature dependence of the resistance value fluctuation rate for the example, comparative example A, and comparative example B. [Figure 9] FIG. 2 is a plan view of a semiconductor device according to a first comparative example. [Figure 10] FIG. 10 is a plan view of a semiconductor device according to a second comparative example. [Figure 11] FIG. 10 is a cross-sectional view of a semiconductor device according to a second embodiment. [Figure 12] FIG. 10 is a plan view of a semiconductor device according to a third embodiment. [Figure 13] FIG. 10 is a plan view of a semiconductor device according to a fourth embodiment. [Figure 14] FIG. 10 is a plan view of a semiconductor device according to a fifth embodiment. [Figure 15] FIG. 15 is a cross-sectional view taken along line AA′ in FIG. [Figure 16] FIG. 10 is a cross-sectional view of a semiconductor device according to a sixth embodiment. [Figure 17] FIG. 13 is a plan view of a semiconductor device according to a seventh embodiment. [Figure 18] FIG. 18 is a cross-sectional view taken along line AA′ in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, first to seventh embodiments of the present invention will be described with reference to the drawings. In the description of the drawings, identical or similar parts are designated by identical or similar reference numerals, and redundant explanations will be omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Furthermore, parts with different dimensional relationships and ratios may be included between the drawings. Furthermore, the first to seventh embodiments shown below are examples of devices and methods for embodying the technical concept of the present invention, and the technical concept of the present invention does not limit the materials, shapes, structures, arrangements, etc. of component parts to those described below.

[0012] Furthermore, the definitions of directions such as up and down in this specification are merely for the convenience of explanation and do not limit the technical concept of the present invention. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read as such, and if an object is rotated 180 degrees and observed, up and down are inverted and read as such.

[0013] Furthermore, in this specification, the "+" or "-" attached to the "p" or "n" indicating the conductivity type of a semiconductor region means that the semiconductor region has a relatively higher or lower impurity concentration, respectively, compared to a semiconductor region without the "+" or "-" attached. However, even if the same "p" and "p" are attached to semiconductor regions, this does not mean that the impurity concentrations of the respective semiconductor regions are strictly the same. Furthermore, in the following explanation, components or regions that are limited to "p-type" or "n-type" refer to components or regions made of semiconductor material, even if there is no specific explicit limitation.

[0014] (First embodiment) As shown in Fig. 1, the semiconductor device according to the first embodiment includes a polysilicon layer 1. The polysilicon layer 1 has a rectangular planar pattern with its longitudinal direction extending in the left-right direction of Fig. 1. The polysilicon layer 1 is provided with a p-type resistance region (p-type diffusion region) 1a. The p-type resistance region 1a is formed over the entire upper surface of the polysilicon layer 1, and has a rectangular planar pattern.

[0015] A first wiring 2 is provided above one end of the rectangular shape formed by the p-type resistance region 1a in the longitudinal direction. The first wiring 2 has an elongated planar pattern and extends in a direction perpendicular to the longitudinal direction of the rectangular shape formed by the p-type resistance region 1a. The first wiring 2 is electrically connected to the p-type resistance region 1a through a plurality of vias 2a to 2d located below the first wiring 2. The vias 2a to 2d are provided spaced apart from one another along the longitudinal direction of the first wiring 2.

[0016] A second wiring 3 is provided above the other longitudinal end of the rectangle formed by the p-type resistance region 1a. The second wiring 3 has an elongated planar pattern and extends in a direction perpendicular to the longitudinal direction of the rectangle formed by the p-type resistance region 1a. The second wiring 3 is electrically connected to the p-type resistance region 1a through a plurality of vias 3a to 3d located below the second wiring 3. The vias 3a to 3d are provided spaced apart from one another along the longitudinal direction of the second wiring 3.

[0017] 1, vias 2a to 2d below the first wiring 2 and vias 3a to 3d below the second wiring 3 are schematically shown by dashed lines. Note that, although Fig. 1 illustrates an example in which four vias 2a to 2d and four vias 3a to 3d are connected to the first wiring 2 and the second wiring 3, the number of vias connected to the first wiring 2 and the second wiring 3 is not particularly limited.

[0018] A cross section taken along line AA' in Fig. 1 is shown in Fig. 2, a cross section taken along line BB' in Fig. 1 is shown in Fig. 3, a cross section taken along line CC' in Fig. 1 is shown in Fig. 4, and a cross section taken along line DD' in Fig. 1 is shown in Fig. 5. As shown in Figs. 2 to 5, the polysilicon layer 1 is provided on a substrate 8 via an insulating film 7. The substrate 8 is made of a semiconductor substrate such as a silicon (Si) substrate. The insulating film 7 is made of, for example, an element isolation insulating film.

[0019] A p-type resistance region 1a is provided on the upper part of the polysilicon layer 1. The p-type resistance region 1a is formed by ion-implanting p-type impurities such as boron (B) into the polysilicon layer 1 and then heat-treating the polysilicon layer 1. The impurity concentration of the p-type resistance region 1a can be adjusted appropriately by adjusting the dose amount during ion implantation.

[0020] As shown in FIGS. 2, 4, and 5, a p-type resistive region 1a is formed above the p-type resistive region 1a. The p-type resistive region 1a has the same conductivity type as the p-type resistive region 1a but has a higher impurity concentration than the p-type resistive region 1a. + Type contact region (p + The diffusion regions 4a and 5a are spaced apart from each other. + The p-type contact regions 4a and 5a are formed by ion-implanting p-type impurities such as boron (B) into the polysilicon layer 1 and then heat-treating the polysilicon layer 1. + The impurity concentration of the mold contact regions 4a and 5a can be adjusted appropriately by adjusting the dose amount during ion implantation.

[0021] As shown in FIGS. 2 to 5, an insulating film (interlayer insulating film) 6 is provided on a polysilicon layer 1. A first wiring 2 and a second wiring 3 are provided on the interlayer insulating film 6. An opening (through hole) is provided in the interlayer insulating film 6. The first wiring 2 is electrically connected to the p-type resistance region 1a through vias 2a to 2d that penetrate the opening of the interlayer insulating film 6. The second wiring 3 is electrically connected to the p-type resistance region 1a through vias 3a to 3d that penetrate the opening of the interlayer insulating film 6.

[0022] The first wiring 2, the second wiring 3, and the vias 2a to 2d, 3a to 3d can be made of metals such as aluminum (Al) and Al alloys. Examples of Al alloys include Al-silicon (Si), Al-copper (Cu)-Si, and Al-Cu.

[0023] In the semiconductor device according to the first embodiment, the contact resistance of some of the contact portions among the vias 2a to 2d and 3a to 3d is different from the contact resistance of other parts of the vias 2a to 2d and 3a to 3d. Here, among the contact structures formed by the vias 2a to 2d and 3a to 3d, a contact structure with a relatively low contact resistance is defined as a "low-resistance contact structure," and a contact structure with a relatively high contact resistance is defined as a "high-resistance contact structure."

[0024] That is, as shown in FIGS. 2 and 4, on the first wiring 2 side, the lower end of the via 2a is p + The via 2a is in direct physical contact with the p-type contact region 4a. + 3 and 4, the lower ends of the vias 2b to 2d are in direct and physical contact with the p-type resistance region 1a, and the vias 2b to 2d form high-resistance contact structures (2b, 1a), (2c, 1a), and (2d, 1a) with the p-type resistance region 1a. The contact resistances of the high-resistance contact structures (2b, 1a), (2c, 1a), and (2d, 1a) are higher than the contact resistance of the low-resistance contact structure (2a, 4a). The low-resistance contact structure (2a, 4a) and the high-resistance contact structures (2b, 1a), (2c, 1a), and (2d, 1a) are short-circuited via the first wiring 2.

[0025] As shown in FIGS. 2 and 5, on the second wiring 3 side, the bottom end of the via 3a is p + The via 3a is in direct physical contact with the p-type contact region 5a. + 3 and 5, the lower ends of the vias 3b to 3d are in direct and physical contact with the p-type resistance region 1a, and the vias 3b to 3d form high-resistance contact structures (3b, 1a), (3c, 1a), and (3d, 1a) with the p-type resistance region 1a. The low-resistance contact structure (3a, 5a) and the high-resistance contact structures (3b, 1a), (3c, 1a), and (3d, 1a) are short-circuited via the second wiring 3.

[0026] 1, vias 2a and 3a constituting the low-resistance contact structures (2a, 4a) and (3a, 5a) are hatched, while vias 2b-2d and 3b-3d constituting the high-resistance contact structures (2b, 1a), (2c, 1a), (2d, 1a), (3b, 1a), (3c, 1a), and (3d, 1a) are not hatched. As shown in FIG. 1, the low-resistance contact structure (2a, 4a) and high-resistance contact structures (2b, 1a), (2c, 1a), and (2d, 1a) on the first wiring 2 side are symmetrically (line-symmetrically) arranged with the low-resistance contact structure (3a, 5a) and high-resistance contact structures (3b, 1a), (3c, 1a), and (3d, 1a) on the second wiring 3 side.

[0027] Here, the p-type resistive region 1a and p + The contact resistance between the p-type polysilicon of the contact regions 4a, 5a, etc. and the metal of the vias 2a-2d, 3a-3d, etc. decreases as the impurity concentration of the p-type polysilicon increases, and increases as the impurity concentration of the p-type polysilicon decreases. Furthermore, the contact resistance of the p-type polysilicon with the metal has a negative temperature coefficient when the impurity concentration of the p-type polysilicon is relatively low, but as the impurity concentration of the p-type polysilicon increases, the sign of the positive and negative coefficients is reversed, and when the impurity concentration of the p-type polysilicon is relatively high, the temperature coefficient becomes positive.

[0028] Furthermore, the sheet resistance of p-type polysilicon decreases as the impurity concentration of the p-type polysilicon increases, and increases as the impurity concentration of the p-type polysilicon decreases. Furthermore, the sheet resistance of p-type polysilicon has a negative temperature coefficient when the impurity concentration of the p-type polysilicon is relatively low, but as the impurity concentration of the p-type polysilicon increases, the sign of the positive and negative coefficients reverses, and when the impurity concentration of the p-type polysilicon is relatively high, the temperature coefficient becomes positive.

[0029] The impurity concentration of p-type polysilicon when the temperature coefficient of the contact resistance of p-type polysilicon is reversed is different from the impurity concentration of p-type polysilicon when the temperature coefficient of the sheet resistance of p-type polysilicon is reversed.

[0030] For example, when p-type polysilicon has a predetermined impurity concentration (first concentration), the sheet resistance of the p-type polysilicon and the contact resistance of the p-type polysilicon with a metal may both be negative. Also, when p-type polysilicon has a predetermined impurity concentration (second concentration) higher than the first concentration, the sheet resistance of the p-type polysilicon may be positive and the contact resistance of the p-type polysilicon with a metal may both be negative. Also, when p-type polysilicon has a predetermined impurity concentration (third concentration) higher than the second concentration, the sheet resistance of the p-type polysilicon and the contact resistance of the p-type polysilicon with a metal may both be positive.

[0031] In the semiconductor device according to the first embodiment, the entire resistor is composed of the low-resistance contact structures (2a, 4a), (3a, 5a) between the first wiring 2 and the second wiring 3, the high-resistance contact structures (2b, 1a), (2c, 1a), (2d, 1a), (3b, 1a), (3c, 1a), (3d, 1a), and the p-type resistance region 1a.

[0032] The p-type resistance region 1a and the p-type resistance region 1b are arranged such that at least one of the temperature coefficients of the contact resistance of the high resistance contact structures (2b, 1a), (2c, 1a), (2d, 1a), (3b, 1a), (3c, 1a), and (3d, 1a), the contact resistance of the low resistance contact structures (2a, 4a), and (3a, 5a), and the sheet resistance of the p-type resistance region 1a has a different sign of positive or negative from at least one other temperature coefficient. +The impurity concentrations of the p-type contact regions 4a and 5a are adjusted. Note that the temperature coefficient of one of the contact resistances of the high-resistance contact structures (2b, 1a), (2c, 1a), (2d, 1a), (3b, 1a), (3c, 1a), and (3d, 1a), the contact resistance of the low-resistance contact structures (2a, 4a) and (3a, 5a), and the sheet resistance of the p-type resistance region 1a may be opposite in sign to the temperature coefficient of the other, and the remaining temperature coefficient may be zero. For example, the contact resistances of the high-resistance contact structures (2b, 1a), (2c, 1a), (2d, 1a), (3b, 1a), (3c, 1a), and (3d, 1a) may have a negative temperature coefficient, the contact resistances of the low-resistance contact structures (2a, 4a) and (3a, 5a) may have a positive temperature coefficient, and the sheet resistance of the p-type resistance region 1a may have a positive temperature coefficient.

[0033] The temperature coefficient of the entire resistor element can be adjusted by adjusting the number (proportion) of vias 2b-2d and 3b-3d constituting the high-resistance contact structures (2b,1a), (2c,1a), (2d,1a), (3b,1a), (3c,1a), and (3d,1a), the number (proportion) of vias 2a and 3a constituting the low-resistance contact structures (2a,4a) and (3a,5a), and the number of sheets connected in series in the p-type resistance region 1a. There is no particular restriction on the number of high-resistance contact structures (2b,1a), (2c,1a), (2d,1a), (3b,1a), (3c,1a), and (3d,1a) and the number of low-resistance contact structures (2a,4a) and (3a,5a). Furthermore, the ratio of the high-resistance contact structures (2b, 1a), (2c, 1a), (2d, 1a), (3b, 1a), (3c, 1a), and (3d, 1a) to the low-resistance contact structures (2a, 4a) and (3a, 5a) is not particularly limited. In Figure 1, the number of high-resistance contact structures (2b, 1a), (2c, 1a), (2d, 1a), (3b, 1a), (3c, 1a), and (3d, 1a) is greater than the number of low-resistance contact structures (2a, 4a) and (3a, 5a), but the reverse relationship may also be true.

[0034] Here, it is preferable to adjust the number of low-resistance contact structures (2a, 4a), (3a, 5a), the number of high-resistance contact structures (2b, 1a), (2c, 1a), (2d, 1a), (3b, 1a), (3c, 1a), (3d, 1a), and the number of sheets connected in series in the p-type resistance region 1a so that the temperature coefficient of the overall resistance value of the resistor composed of the low-resistance contact structures (2a, 4a), (3a, 5a), the high-resistance contact structures (2b, 1a), (2c, 1a), (2d, 1a), (3b, 1a), (3c, 1a), (3d, 1a), and the p-type resistance region 1a becomes approximately zero (in other words, so that it approaches approximately zero or becomes small).

[0035] In the semiconductor device according to the first embodiment, when the high-resistance contact structure and the low-resistance contact structure on both ends of the p-type resistance region 1a are arranged symmetrically, the resistance value R of the entire resistance element can be expressed by the following equation (1).

[0036] R=[(RC1 / n1) / / (RC2 / n2)]×2+Rbd×S …(1)

[0037] In equation (1), (RC1 / n1) / / (RC2 / n2) are the parallel contact resistance components on one side of the p-type resistance region 1a. RC1 is the contact resistance of the high-resistance contact structure, RC2 is the contact resistance of the low-resistance contact structure, n1 is the number of high-resistance contact structures on one side of the p-type resistance region 1a, n2 is the number of low-resistance contact structures on one side of the p-type resistance region 1a, Rbd is the sheet resistance of the p-type resistance region 1a, and S is the number of sheets in the p-type resistance region 1a.

[0038] Figure 6 shows an example of the temperature dependence of the contact resistance RC1 of the high-resistance contact structure, the contact resistance RC2 of the low-resistance contact structure, and the sheet resistance Rbd of the p-type resistance region 1a. As shown in Figure 6, the contact resistance RC1 of the high-resistance contact structure has a negative temperature coefficient, meaning that the resistance value decreases as the temperature increases. The contact resistance RC2 of the low-resistance contact structure has a positive temperature coefficient, meaning that the resistance value increases as the temperature increases. The sheet resistance Rbd of the p-type resistance region 1a has a positive temperature coefficient, meaning that the resistance value increases as the temperature increases.

[0039] 7 shows an example of the temperature dependence of resistance value for an example corresponding to the semiconductor device according to the first embodiment, and comparative examples A and B for comparison with the example. The example has a configuration in which a high-resistance contact structure and a low-resistance contact structure are combined, as shown in FIG. 1, with three high-resistance contact structures and one low-resistance contact structure on each end of the p-type resistance region 1a, and the number of sheets in the p-type resistance region 1a is one sheet.

[0040] Comparative Example A has a configuration with only high-resistance contact structures and no low-resistance contact structures, with four high-resistance contact structures and zero low-resistance contact structures on each end of the p-type resistance region 1a, and one sheet of p-type resistance region 1a. Comparative Example B has a configuration with only low-resistance contact structures and no high-resistance contact structures, with zero high-resistance contact structures and four low-resistance contact structures on each end of the p-type resistance region 1a, and one sheet of p-type resistance region 1a.

[0041] As shown in Figure 7, the resistance value of Comparative Example A decreases as the temperature increases. The resistance value of Comparative Example B increases as the temperature increases. The resistance value of the Example increases slightly as the temperature increases, but the slope of the Example is intermediate between that of Comparative Example A and Comparative Example B.

[0042] FIG. 8 shows an example of the temperature dependence of the resistance variation rate ΔR from 25°C for each of Comparative Example A, Comparative Example B, and Example, similar to FIG. 7. For Comparative Example A, the resistance variation rate ΔR increases in the negative direction as the temperature increases. For Comparative Example B, the resistance variation rate ΔR increases in the positive direction as the temperature increases. For Example, the resistance variation rate ΔR increases slightly in the positive direction as the temperature increases, but this is smaller than in the first and second comparative examples.

[0043] Here, semiconductor devices according to first and second comparative examples will be described. As shown in FIG. 9, the semiconductor device according to the first comparative example differs from the semiconductor device according to the first embodiment in that it uses two types of polysilicon layers: a first polysilicon layer 101a and a second polysilicon layer 101b. The first polysilicon layer 101a is made of p-type polysilicon, and the sheet resistance of the first polysilicon layer 101a has a positive temperature coefficient. The second polysilicon layer 101b is made of n-type polysilicon, and the sheet resistance of the second polysilicon layer 101b has a negative temperature coefficient.

[0044] One end of the first polysilicon layer 101a is electrically connected to the first wiring 102 through vias 102a to 102d. The other end of the first polysilicon layer 101a is electrically connected to the relay wiring 104 through vias 104a to 104d. The vias 102a to 102d and 104a to 104d are connected to the p + It contacts a mold contact area (not shown).

[0045] One end of the second polysilicon layer 101b is electrically connected to the relay wiring 104 through vias 104e to 104h. The other end of the second polysilicon layer 101b is electrically connected to the second wiring 103 through vias 103a to 103d. The vias 103a to 103d and 104e to 104h are formed in the n-type polysilicon layer 101b. + It contacts a mold contact area (not shown).

[0046] In Figure 9, p + Vias 102a to 102d, 104a to 104d, and n-type contact regions (not shown) + The vias 103a to 103d and 104e to 104h that contact the mold contact region (not shown) are hatched.

[0047] In the semiconductor device according to the first comparative example, p + type contact region (not shown) and n +The mold contact region (not shown) has a high impurity concentration, and the contact resistance components of the vias 102a to 102d, 103a to 103d, and 104a to 104h are reduced to a negligible level.

[0048] 10, the semiconductor device according to the second comparative example is common to the semiconductor device according to the first comparative example shown in FIG. 9 in that it includes a p-type first polysilicon layer 101a and an n-type second polysilicon layer 101b. However, the semiconductor device according to the second comparative example does not include p-type first polysilicon layer 101a and n-type second polysilicon layer 101b. + No type contact region is provided, and the second polysilicon layer 101b has an n-type contact region. + The semiconductor device according to the first comparative example differs from the semiconductor device according to the first comparative example in that no mold contact region is provided.

[0049] The vias 102a to 102d and 104a to 104d are in contact with the first polysilicon layer 101a. The vias 103a to 103d and 104e to 104h are in contact with the second polysilicon layer 101b. In Fig. 10, the vias 102a to 102d and 104a to 104d in contact with the first polysilicon layer 101a and the vias 103a to 103d and 104e to 104h in contact with the second polysilicon layer 101b are not hatched for illustrative purposes.

[0050] In the semiconductor device according to the second comparative example, the first polysilicon layer 101a and the second polysilicon layer 101b have a relatively high impurity concentration, and p + type contact region and n + No mold contact region is provided.

[0051] In the semiconductor devices according to the first and second comparative examples, the temperature coefficient of the entire resistor element is adjusted by combining a first polysilicon layer 101a with a positive temperature coefficient and a second polysilicon layer 101b with a negative temperature coefficient. However, the use of two types of polysilicon layers, the first polysilicon layer 101a and the second polysilicon layer 101b, results in a large area. On the other hand, the semiconductor device according to the first embodiment uses one type of polysilicon layer 1, eliminating the need to prepare two types of polysilicon layers, and thus enabling the miniaturization of a resistor element with a small temperature coefficient.

[0052] In the semiconductor device according to the first embodiment, the contact resistances of the high-resistance contact structures (2b, 1a), (2c, 1a), (2d, 1a), (3b, 1a), (3c, 1a), and (3d, 1a) have a negative temperature coefficient, the contact resistances of the low-resistance contact structures (2a, 4a) and (3a, 5a) have a positive temperature coefficient, and the sheet resistance of the p-type resistance region 1a has a positive temperature coefficient. However, it is sufficient that at least one of the temperature coefficients of the contact resistances of the high-resistance contact structures (2b, 1a), (2c, 1a), (2d, 1a), (3b, 1a), (3c, 1a), and (3d, 1a), the contact resistances of the low-resistance contact structures (2a, 4a) and (3a, 5a), and the sheet resistance of the p-type resistance region 1a has a positive or negative sign different from that of at least one of the other temperature coefficients.

[0053] For example, the contact resistance of the high-resistance contact structures (2b, 1a), (2c, 1a), (2d, 1a), (3b, 1a), (3c, 1a), and (3d, 1a) may have a negative temperature coefficient, the contact resistance of the low-resistance contact structures (2a, 4a) and (3a, 5a) may have a positive temperature coefficient, and the sheet resistance of the p-type resistance region 1a may have a negative temperature coefficient. To make the sheet resistance of the p-type resistance region 1a have a negative temperature coefficient, for example, the impurity concentration of the p-type resistance region 1a may be lowered.

[0054] (Second embodiment) The semiconductor device according to the second embodiment differs from the semiconductor device according to the first embodiment in that a p-type resistance region 1a is formed over the entire polysilicon layer 1, as shown in FIG.

[0055] The cross section of the semiconductor device according to the second embodiment shown in FIG. 11 corresponds to the cross section of the semiconductor device according to the first embodiment shown in FIG. 2. The p-type resistance region 1a may be made of doped polysilicon obtained by doping p-type impurities into the polysilicon layer 1. Other configurations of the semiconductor device according to the second embodiment are substantially the same as those of the semiconductor device according to the first embodiment, and therefore, redundant explanations will be omitted.

[0056] According to the semiconductor device of the second embodiment, even when the p-type resistance region 1a is formed over the entire polysilicon layer 1, the same effects as those of the semiconductor device of the first embodiment can be achieved.

[0057] (Third embodiment) As shown in FIG. 12, the semiconductor device of the third embodiment differs from the semiconductor device of the first embodiment in that the low-resistance contact structure and high-resistance contact structure formed by vias 2a to 2d connected to the first wiring 2 are asymmetric with the low-resistance contact structure and high-resistance contact structure formed by vias 3a to 3d connected to the second wiring 3.

[0058] 12, vias 2d and 3a that constitute the low-resistance contact structure are hatched, while vias 2a to 2c and 3b to 3d that constitute the high-resistance contact structure are not. Of the vias 2a to 2d connected to the first wiring 2, vias 2a to 2c constitute the high-resistance contact structure, and via 2d constitutes the low-resistance contact structure. On the other hand, of the vias 3a to 3d connected to the second wiring 3, via 3a facing via 2a constitutes the low-resistance contact structure, and vias 3b to 3d facing vias 2b to 2d constitute the high-resistance contact structure. Other configurations of the semiconductor device according to the third embodiment are substantially the same as those of the semiconductor device according to the first embodiment, and therefore, redundant explanations will be omitted.

[0059] According to the semiconductor device of the third embodiment, the same effects as those of the semiconductor device of the first embodiment can be achieved even when the low-resistance contact structure and high-resistance contact structure formed by vias 2a to 2d connected to the first wiring 2 and the low-resistance contact structure and high-resistance contact structure formed by vias 3a to 3d connected to the second wiring 3 are asymmetric.

[0060] In addition, the number (proportion) of low-resistance contact structures and high-resistance contact structures formed by vias 2a to 2d connected to the first wiring 2 may be different from the number (proportion) of low-resistance contact structures and high-resistance contact structures formed by vias 3a to 3d connected to the second wiring 3.

[0061] (Fourth embodiment) The semiconductor device of the fourth embodiment differs from the semiconductor device of the first embodiment in that, as shown in Figure 13, vias 2a to 2d connected to the first wiring 2 form only low-resistance contact structures, and vias 3a to 3d connected to the second wiring 3 form only high-resistance contact structures.

[0062] 13, vias 2a to 2d that constitute the low-resistance contact structure are hatched, and vias 3a to 3d that constitute the high-resistance contact structure are not hatched. Other configurations of the semiconductor device according to the fourth embodiment are substantially the same as those of the semiconductor device according to the first embodiment, and therefore, redundant explanations will be omitted.

[0063] According to the semiconductor device of the fourth embodiment, even when the vias 2a to 2d connected to the first wiring 2 form only low-resistance contact structures and the vias 3a to 3d connected to the second wiring 3 form only high-resistance contact structures, the same effects as those of the semiconductor device of the first embodiment can be achieved. That is, it is sufficient that some of the vias 2a to 2d and 3a to 3d form low-resistance contact structures and other some of the vias 2a to 2d and 3a to 3d form high-resistance contact structures.

[0064] (Fifth embodiment) The semiconductor device according to the fifth embodiment is common to the semiconductor device according to the first embodiment in that the vias 2a and 3a form a low-resistance contact structure, and the vias 2b to 2d and 3b to 3d form a high-resistance contact structure, as shown in Fig. 14. In Fig. 14, the vias 2a and 3a that form the low-resistance contact structure and the vias 2b to 2d and 3b to 3d that form the high-resistance contact structure are schematically shown with different hatching.

[0065] 15 shows a cross section taken along line AA′ in FIG. 14. As shown in FIG. 15, in the semiconductor device according to the fifth embodiment, vias 2b to 2d are formed of p-type impurities having the same conductivity type as the p-type resistance region 1a but a lower impurity concentration than the p-type resistance region 1a. -The semiconductor device differs from the semiconductor device according to the first embodiment in that high-resistance contact structures (2b, 4b), (2c, 4c), and (2d, 4d) are formed in contact with the contact regions 4b to 4d.

[0066] p - The p-type contact regions 4b to 4d are provided above the p-type resistance region 1a. - The contact regions 4b to 4d can be formed by, for example, ion-implanting (counter-doping) n-type impurities into the polysilicon layer 1 to compensate for the p-type impurities.

[0067] In the semiconductor device of the fifth embodiment, for example, similar to the semiconductor device of the first embodiment, the contact resistance of the high-resistance contact structures (2b, 4b), (2c, 4c), and (2d, 4d) may have a negative temperature coefficient, the contact resistance of the low-resistance contact structures (2a, 4a) may have a positive temperature coefficient, and the sheet resistance of the p-type resistance region 1a may have a positive temperature coefficient.

[0068] Alternatively, the contact resistance of the high-resistance contact structures (2b, 4b), (2c, 4c), and (2d, 4d) may have a negative temperature coefficient, the contact resistance of the low-resistance contact structures (2a, 4a) may have a positive temperature coefficient, and the sheet resistance of the p-type resistance region 1a may have a negative temperature coefficient.

[0069] The vias 3b to 3d are also p-type resistors provided above the p-type resistor region 1a. - The semiconductor device according to the fifth embodiment is substantially similar to the semiconductor device according to the first embodiment in other respects, and therefore, a duplicated description will be omitted.

[0070] The semiconductor device according to the fifth embodiment has the same effects as the semiconductor device according to the first embodiment. -Since the high-resistance contact structures (2b, 4b), (2c, 4c), (2d, 4d) are formed in contact with the p-type contact regions 4b to 4d, the contact resistance of the high-resistance contact structures (2b, 4b), (2c, 4c), (2d, 4d) and the sheet resistance of the p-type resistance region 1a can be adjusted individually, and the temperature coefficient of the contact resistance of the high-resistance contact structures (2b, 4b), (2c, 4c), (2d, 4d) and the temperature coefficient of the sheet resistance of the p-type resistance region 1a can be adjusted individually.

[0071] The via 2a has the same conductivity type as the p-type resistance region 1a, a lower impurity concentration than the p-type resistance region 1a, and - p-type contact regions 4b to 4d having a higher impurity concentration - A low-resistance contact structure may be formed in contact with the p-type contact region (not shown). In this case, for example, the contact resistance of the high-resistance contact structures (2b, 4b), (2c, 4c), and (2d, 4d) may have a negative temperature coefficient, the contact resistance of the low-resistance contact structure formed by via 2a may have a negative temperature coefficient, and the sheet resistance of p-type resistance region 1a may have a positive temperature coefficient.

[0072] (Sixth embodiment) As shown in FIG. 16, in the semiconductor device according to the sixth embodiment, vias 2b to 2d are formed of p-type impurities having the same conductivity type as the p-type resistance region 1a but a higher impurity concentration than the p-type resistance region 1a. + The semiconductor device according to the sixth embodiment differs from the semiconductor device according to the fifth embodiment in that high-resistance contact structures (2b, 4b), (2c, 4c), and (2d, 4d) are formed in contact with the contact regions 4b to 4d. The cross section of the semiconductor device according to the sixth embodiment shown in FIG. 16 corresponds to the cross section of the semiconductor device according to the fifth embodiment shown in FIG.

[0073] p + The p-type contact regions 4b to 4d are provided above the p-type resistance region 1a. + The p-type contact regions 4b to 4d have a higher impurity concentration than the p-type resistance region 1a. ++ The impurity concentration is lower than that of the p-type contact region 4a. +The contact regions 4b to 4d can be formed by ion-implanting p-type impurities into the polysilicon layer 1, for example.

[0074] In the semiconductor device of the sixth embodiment, for example, similar to the semiconductor device of the first embodiment, the contact resistance of the high-resistance contact structures (2b, 4b), (2c, 4c), and (2d, 4d) may have a negative temperature coefficient, the contact resistance of the low-resistance contact structures (2a, 4a) may have a positive temperature coefficient, and the sheet resistance of the p-type resistance region 1a may have a positive temperature coefficient.

[0075] Alternatively, the contact resistance of the high-resistance contact structures (2b, 4b), (2c, 4c), and (2d, 4d) may have a negative temperature coefficient, the contact resistance of the low-resistance contact structures (2a, 4a) may have a positive temperature coefficient, and the sheet resistance of the p-type resistance region 1a may have a negative temperature coefficient.

[0076] Alternatively, the contact resistance of the high resistance contact structures (2b, 4b), (2c, 4c), (2d, 4d) may have a positive temperature coefficient, the contact resistance of the low resistance contact structure (2a, 4a) may have a positive temperature coefficient, and the sheet resistance of the p-type resistance region 1a may have a negative temperature coefficient. + The same p-type contact regions 4b to 4d + The semiconductor device according to the sixth embodiment is substantially similar to the semiconductor device according to the fifth embodiment in other respects, and therefore, a duplicated description will be omitted.

[0077] The semiconductor device according to the sixth embodiment has the same effects as the semiconductor device according to the first embodiment. +Since the high-resistance contact structures (2b, 4b), (2c, 4c), (2d, 4d) are formed in contact with the p-type contact regions 4b to 4d, the contact resistance of the high-resistance contact structures (2b, 4b), (2c, 4c), (2d, 4d) and the sheet resistance of the p-type resistance region 1a can be adjusted individually, and the temperature coefficient of the contact resistance of the high-resistance contact structures (2b, 4b), (2c, 4c), (2d, 4d) and the temperature coefficient of the sheet resistance of the p-type resistance region 1a can be adjusted individually.

[0078] Seventh embodiment 17, the semiconductor device according to the seventh embodiment is similar to the semiconductor device according to the first embodiment in that vias 2a and 3a form a low-resistance contact structure and vias 2d and 3d form a high-resistance contact structure. However, the semiconductor device according to the seventh embodiment differs from the semiconductor device according to the first embodiment in that vias 2b, 2c, 3b, and 3c form a contact structure with a contact resistance intermediate between the contact resistance of the low-resistance contact structure and the contact resistance of the high-resistance contact structure (hereinafter referred to as a "medium-resistance contact structure").

[0079] 17, vias 2a and 3a constituting the low resistance contact structure and vias 2d and 3d constituting the high resistance contact structure are shown with different hatching, while vias 2b, 2c, 3b, and 3c constituting the medium resistance contact structure are not shown with hatching.

[0080] A cross section taken along line AA' in FIG. 17 is shown in FIG. 18. As shown in FIG. 18, the via 2a is + The low resistance contact structure (2a, 4a) is formed in contact with the contact region 4a. + The p-type contact region 4a has the same conductivity type as the p-type resistance region 1a, but has a higher impurity concentration than the p-type resistance region 1a.

[0081] The vias 2b and 2c contact the p-type resistance region 1a to form a medium resistance contact structure (2b, 1a), (2c, 1a). -A high resistance contact structure (2d, 4d) is formed in contact with the contact region 4d. - The p-type contact region 4d has the same conductivity type as the p-type resistance region 1a, but has a lower impurity concentration than the p-type resistance region 1a.

[0082] In the semiconductor device according to the seventh embodiment, for example, the contact resistance of the high-resistance contact structure (2d, 4d) may have a negative temperature coefficient, the contact resistance of the low-resistance contact structure (2a, 4a) may have a positive temperature coefficient, the sheet resistance of the p-type resistance region 1a may have a positive temperature coefficient, and the contact resistance of the medium-resistance contact structures (2b, 1a), (2c, 1a) may have a positive or negative temperature coefficient.

[0083] Alternatively, the contact resistance of the high-resistance contact structure (2d, 4d) may have a negative temperature coefficient, the contact resistance of the low-resistance contact structure (2a, 4a) may have a positive temperature coefficient, the sheet resistance of the p-type resistance region 1a may have a negative temperature coefficient, and the contact resistance of the medium-resistance contact structures (2b, 1a) and (2c, 1a) may have a positive or negative temperature coefficient. The vias 3a to 3d shown in FIG. 17 also have a contact structure similar to the vias 2a to 2d. Other configurations of the semiconductor device according to the seventh embodiment are substantially similar to those of the semiconductor device according to the first embodiment, and therefore, redundant description will be omitted.

[0084] The semiconductor device according to the seventh embodiment has the same effects as the semiconductor device according to the first embodiment. Furthermore, by further providing medium-resistance contact structures (2b, 1a) and (2c, 1a) in addition to the high-resistance contact structures (2d, 4d) and the low-resistance contact structures (2a, 4a), the resistance value and temperature coefficient of the entire resistor element can be adjusted more precisely.

[0085] (Other embodiments) As described above, the present invention has been described with reference to the first to seventh embodiments, but the descriptions and drawings that form part of this disclosure should not be construed as limiting the present invention. Various alternative embodiments, examples, and application techniques will become apparent to those skilled in the art from this disclosure.

[0086] For example, in the semiconductor devices according to the first to seventh embodiments, the p-type resistance region 1a formed in the polysilicon layer 1 is + In the above example, the p-type contact region 4a is provided, but an n-type diffusion region is provided instead of the p-type resistance region 1a. + A mold contact region may also be provided.

[0087] n-type diffusion region and n + The temperature coefficient of the sheet resistance of n-type polysilicon that constitutes the contact region differs from that of p-type polysilicon in terms of the impurity concentration at which the positive and negative signs are reversed. However, like p-type polysilicon, when the impurity concentration of n-type polysilicon is relatively low, the temperature coefficient is negative, and as the impurity concentration of n-type polysilicon is increased, the positive and negative signs are reversed, and when the impurity concentration of n-type polysilicon is relatively high, the temperature coefficient is positive.

[0088] Similarly to p-type polysilicon, the contact resistance between n-type polysilicon and the via has a negative temperature coefficient when the impurity concentration of the n-type polysilicon is relatively low, and as the impurity concentration of the n-type polysilicon is increased, the sign of positive and negative is reversed, and when the impurity concentration of the n-type polysilicon is relatively high, the temperature coefficient becomes positive. Therefore, the same configuration as that for p-type polysilicon is possible for n-type polysilicon.

[0089] Furthermore, the semiconductor devices according to the first to seventh embodiments are applicable to any configuration having a resistance element, and are applicable to power integrated circuits (power ICs) and general ICs other than power ICs.

[0090] Furthermore, the configurations disclosed in the first to seventh embodiments can be appropriately combined within a range that does not cause contradictions. As such, the present invention naturally includes various embodiments not described here. Therefore, the technical scope of the present invention is defined only by the invention-specifying matters according to the claims that are appropriate from the above description. [Explanation of symbols]

[0091] 1...Polysilicon layer 1a...Diffusion region 2a~2d, 3a~3d...Via 4a~4d, 5a...Contact area 6,7...Insulating film 8...Substrate 101a, 101b...Polysilicon layer 102a~102d, 103a~103d, 104a~104h...via 104...Relay wiring

Claims

1. a polysilicon layer; a resistive region provided in the polysilicon layer; a first contact region provided in the resistor region, the first contact region having the same conductivity type as the resistor region and a higher impurity concentration than the resistor region; a first wiring electrically connected to one end of the resistance region through a plurality of first vias; a second wiring electrically connected to the other end of the resistance region through a plurality of second vias; Equipped with some of the plurality of first vias and the plurality of second vias are in contact with the first contact region to form a low resistance contact structure; Another part of the plurality of first vias and the plurality of second vias constitutes a high resistance contact structure higher than the low resistance contact structure. A semiconductor device characterized by:

2. 2. The semiconductor device according to claim 1, wherein at least one of the temperature coefficients of the contact resistance of the low-resistance contact structure, the contact resistance of the high-resistance contact structure, and the sheet resistance of the resistive region has a different positive or negative sign from at least one of the other temperature coefficients.

3. the contact resistance of the low resistance contact structure has a positive temperature coefficient; the contact resistance of the high resistance contact structure has a negative temperature coefficient; The sheet resistance of the resistive region has a positive temperature coefficient 3. The semiconductor device according to claim 1, wherein the first insulating film is a semiconductor material.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that the number of low-resistance contact structures, the number of high-resistance contact structures, and the number of sheets connected in series to the resistance region are adjusted so that the temperature coefficient of the resistor composed of the low-resistance contact structure, the high-resistance contact structure, and the resistance region approaches zero.

5. Another part of the plurality of first vias and the plurality of second vias contacts the resistance region to form the high resistance contact structure.

5. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer and a second insulating layer.

6. a second contact region provided above the resistor region, the second contact region having the same conductivity type as the resistor region and a lower impurity concentration than the resistor region; Another part of the plurality of first vias and the plurality of second vias contacts the second contact region to form the high resistance contact structure.

5. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer and a second insulating layer.

7. a second contact region provided above the resistor region, the second contact region having the same conductivity type as the resistor region, a higher impurity concentration than the resistor region, and a lower impurity concentration than the first contact region; Another part of the plurality of first vias and the plurality of second vias contacts the second contact region to form the high resistance contact structure.

5. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer and a second insulating layer.

8. a second contact region provided above the resistor region, the second contact region having the same conductivity type as the resistor region and a lower impurity concentration than the resistor region; another part of the plurality of first vias and the plurality of second vias contacts the second contact region to form the high resistance contact structure; Further, some of the first vias and the second vias are in contact with the resistance region to form a medium resistance contact structure.

5. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer and a second insulating layer.

9. a part of the plurality of first vias constitutes the low resistance contact structure; Another part of the plurality of first vias constitutes the high resistance contact structure.

9. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

10. 10. The semiconductor device according to claim 9, wherein the low resistance contact structure and the high resistance contact structure formed by the plurality of first vias and the low resistance contact structure and the high resistance contact structure formed by the plurality of second vias are arranged symmetrically with each other.

11. 11. The semiconductor device according to claim 1, wherein the resistive region is a p-type diffusion region.

Images