Semiconductor device manufacturing method and semiconductor device

Abstract

This method for producing a semiconductor device comprises: a step for preparing a first semiconductor chip having a first chip body, and a first insulating film and a first electrode that are provided to one surface of the first chip body; a step for preparing a second semiconductor chip having a second chip body, and a second insulating film and a second electrode that are provided to one surface of the second chip body; a step for pasting together the first insulating film of the first semiconductor chip and the second insulating film of the second semiconductor chip; a step for joining together the first electrode of the first semiconductor chip and the second electrode of the second semiconductor chip; a step for sealing in, with a sealing resin, the second semiconductor chip installed on top of the first semiconductor chip; a step for forming a via hole in a sealing body formed of the sealing resin; and a step for filling the via hole with an electroconductive material so as to be electrically connected to the first electrode and / or the second electrode.

Description

[Technical Field]

[0001] The present disclosure relates to a method for manufacturing a semiconductor device and a semiconductor device. [Background technology]

[0002] In recent years, three-dimensional packaging has been studied to improve the integration density of LSIs. Patent Document 1 and Non-Patent Document 1 disclose examples of three-dimensional packaging of semiconductor chips. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2018 / 0082964 [Non-patent literature]

[0004] [Non-Patent Document 1] FC Chen et al., “System on Integrated Chips(SoIC TM) for 3D Heterogeneous Integration”, 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), p.594-599(2019) Summary of the Invention [Problem to be solved by the invention]

[0005] In such three-dimensional mounting of semiconductor chips, further improvements in the connection structure of the semiconductor chips are required.

[0006] An object of the present disclosure is to provide a semiconductor device manufacturing method that enables high-density packaging in three-dimensional packaging, and a semiconductor device. [Means for solving the problem]

[0007] The present disclosure relates to a method for manufacturing a semiconductor device, comprising the steps of: preparing a first semiconductor chip having a first chip body, a first insulating film and a first electrode provided on one surface of the first chip body; preparing at least one second semiconductor chip having a second chip body, a second insulating film and a second electrode provided on one surface of the second chip body; bonding the first insulating film of the first semiconductor chip and the second insulating film of the second semiconductor chip together; joining the first electrode of the first semiconductor chip and the second electrode of the second semiconductor chip; encapsulating the second semiconductor chip placed on the first semiconductor chip with a sealing resin; forming at least one via hole in the sealing body formed from the sealing resin; and filling a conductive material in the via hole to form a conductive via electrically connected to at least one of the first electrode and the second electrode.

[0008] In this semiconductor device manufacturing method, the first semiconductor chip and the second semiconductor chip are bonded together using a so-called hybrid bonding method, and then the second semiconductor chip is sealed and conductive vias are formed in the sealed body. In this case, since the conductive vias are formed after sealing, they can be formed at high density. This enables high-density packaging in three-dimensional packaging, such as placing the second semiconductor chip on the first semiconductor chip.

[0009] In the above-described method for manufacturing a semiconductor device, at least one of the first insulating film and the second insulating film may contain an inorganic insulating material. In this case, it is possible to manufacture a semiconductor device with a finer configuration. Furthermore, both the first insulating film and the second insulating film may contain an inorganic insulating material. In this case, since it is easy to bond inorganic materials to each other, the adhesive strength between semiconductor chips can be increased, thereby improving the connection reliability of the semiconductor device.

[0010] In the semiconductor device manufacturing method described above, at least one of the first insulating film and the second insulating film may contain an organic insulating material. In this case, the organic material, which is a relatively soft material, can absorb foreign matter (debris) adhering to the chip surface into the insulating film, thereby reducing connection failures between semiconductor chips. The organic insulating material contained in the insulating film may be polyimide, a polyimide precursor, polyamideimide, benzocyclobutene (BCB), polybenzoxazole (PBO), or a PBO precursor. These materials are liquid or soluble in solvents, making it easy to prepare the insulating film by, for example, spin coating, and to form a thin film. Furthermore, these materials have high heat resistance, so they can withstand the high temperatures required to bond the first semiconductor chip and the second semiconductor chip, enabling more reliable bonding between the chips. Note that a portion of each of the first insulating film and the second insulating film may be formed from an inorganic insulating material, and the other portion (e.g., the front side) may be formed from an organic insulating material.

[0011] In the above-described method for manufacturing a semiconductor device, the first insulating film and the second insulating film may be bonded by room temperature bonding in the bonding step. In this case, the first insulating film and the second insulating film can be easily bonded without considering thermal expansion, etc. Furthermore, since the bonding is performed at room temperature, the influence of heat on the first semiconductor chip and the second semiconductor chip can be reduced.

[0012] The method for manufacturing a semiconductor device described above may further include a step of polishing the surface of the encapsulant. In this case, variations in the steps or surface roughness on the surface of the encapsulant are reduced, allowing the rewiring layer or the normal wiring layer to be formed with greater precision and density. In this case, the encapsulant may be polished in the polishing step so that the surface roughness (Ra value) of the encapsulant is 1 μm or less, more preferably 0.5 μm or less, and most preferably 0.1 μm or less. This enables the formation of wiring having a fine pattern shape. Furthermore, in the polishing step, the encapsulant may be polished so that the thickness of the encapsulant between the surface of the encapsulant and the second semiconductor chip is 300 μm or less, more preferably 250 μm or less, and most preferably 200 μm or less. Alternatively, the surface of the second semiconductor chip (the side opposite the surface on which the terminal electrodes and insulating layer are formed) may be exposed. This allows the package to have a lower profile, less warpage, and improved heat dissipation. The surface roughness (Ra value) used here is calculated by observation with an electron microscope, for example, and means the arithmetic mean surface roughness (JIS B 0601-2001).

[0013] The method for manufacturing a semiconductor device may further include a step of forming a redistribution layer on the encapsulant. In this case, it is possible to easily convert the wiring pitch of the first semiconductor chip or the like to the wiring pitch of an external device such as a wiring board. In this case, the redistribution layer may be electrically connected to the first electrodes of the first semiconductor chip by conductive vias formed from a conductive material.

[0014] The method for manufacturing the semiconductor device may further include a step of forming bumps on the outer surface of the redistribution layer opposite to the encapsulant, which makes it possible to easily mount the semiconductor device on an external device such as a wiring board.

[0015] In the method for manufacturing a semiconductor device described above, the sealing material used in the sealing step may be epoxy resin or acrylic resin, in which case the second semiconductor chip can be sealed reliably and easily.

[0016] In the above-described method for manufacturing a semiconductor device, in the step of forming via holes, a plurality of via holes may be formed around the second semiconductor chip, and first electrodes of the first semiconductor chip may be exposed in the plurality of via holes. In the step of filling the conductive material, the conductive material may be filled into each of the plurality of via holes so as to be electrically connected to the first electrodes. In this case, the conductive vias can be provided at a higher density, and the first semiconductor chip can be more reliably connected to an external device, etc.

[0017] In the above-described method for manufacturing a semiconductor device, the second semiconductor chip may have a smaller surface area than the first semiconductor chip, and multiple second semiconductor chips may be bonded to the first semiconductor chip. In the sealing step, the multiple second semiconductor chips mounted on the first semiconductor chip may be collectively sealed with a sealing resin. In this case, two or more second semiconductor chips can be bonded to one first semiconductor chip, enabling higher-density three-dimensional packaging.

[0018] Another aspect of the present disclosure relates to a semiconductor device including: a first semiconductor chip having a first chip body and a first insulating film and a first electrode provided on one surface of the first chip body; a second semiconductor chip having a second chip body and a second insulating film and a second electrode provided on one surface of the second chip body and mounted on the first semiconductor chip; a sealing body covering the second semiconductor chip mounted on the first semiconductor chip; and a conductive via filled in a via hole provided in the sealing body and electrically connected to at least one of the first electrode and the second electrode.

[0019] In this semiconductor device, the first semiconductor chip and the second semiconductor chip are firmly bonded by a so-called hybrid bond, and conductive vias are formed in the sealing body that seals the second semiconductor chip. In this case, the conductive vias are formed in the sealing body, so that the conductive vias can be formed at high density. This enables high-density packaging in three-dimensional packaging, such as placing the second semiconductor chip on the first semiconductor chip.

[0020] The semiconductor device may further include a redistribution layer provided on the surface of the encapsulant opposite to the first semiconductor chip, and the redistribution layer may be electrically connected to the first electrodes of the first semiconductor chip by conductive vias. This makes it possible to easily convert the wiring pitch of the first semiconductor chip or the like to the wiring pitch of an external device such as a wiring board. [Effects of the Invention]

[0021] According to the present disclosure, high-density packaging in three-dimensional packaging can be achieved. [Brief explanation of the drawings]

[0022] [Figure 1] FIG. 1 is a cross-sectional view schematically showing an example of a semiconductor device according to an embodiment of the present invention. [Figure 2] 2A and 2B are cross-sectional views showing the cross sections of each semiconductor chip used in manufacturing the semiconductor device shown in FIG. 1, where (a) shows the cross section of one semiconductor chip and (b) shows the cross section of the other semiconductor chip. [Figure 3] FIG. 3 is a schematic cross-sectional view showing a step of a method for manufacturing a semiconductor device according to one embodiment of the present invention, illustrating the step of bonding one semiconductor chip to another semiconductor chip. [Figure 4] 4(a) to 4(c) are diagrams for explaining the joining of the semiconductor chips shown in FIG. 3 in order. [Figure 5] 5(a) to 5(c) are schematic cross-sectional views showing the steps of the method for manufacturing a semiconductor device according to one embodiment of the present invention, following FIG. [Figure 6] 6(a) to 6(c) are schematic cross-sectional views showing the steps of the method for manufacturing a semiconductor device according to one embodiment of the present invention, following FIG. DETAILED DESCRIPTION OF THE INVENTION

[0023] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In the following description, the same or equivalent parts will be denoted by the same reference numerals, and duplicate explanations will be omitted. Furthermore, unless otherwise specified, positional relationships such as up, down, left, and right will be based on the positional relationships shown in the drawings. Furthermore, the dimensional ratios of the drawings are not limited to those shown in the drawings.

[0024] In this specification, the term "layer" encompasses not only a structure with a shape formed over the entire surface when observed in a plan view, but also a structure with a shape formed on a portion of the surface. Furthermore, in this specification, the term "process" includes not only an independent process, but also a process that cannot be clearly distinguished from other processes, as long as the intended effect of the process is achieved. Furthermore, a numerical range indicated using "to" indicates a range that includes the numerical values ​​before and after "to" as the minimum and maximum values, respectively.

[0025] (Configuration of semiconductor device) FIG. 1 is a cross-sectional view schematically illustrating an example of a semiconductor device according to this embodiment. As shown in FIG. 1, the semiconductor device 1 is, for example, an example of a semiconductor package, and includes a first semiconductor chip 10, at least one second semiconductor chip 20, a sealing body 30, a redistribution layer 40, and a plurality of bumps 50. In the semiconductor device 1, one or more second semiconductor chips 20 (for example, two second semiconductor chips 20 in this embodiment) are mounted on the first semiconductor chip 10, forming a three-dimensional mounting structure. The first semiconductor chip 10 is, for example, an LSI (Large Scale Integrated Circuit) chip or a CMOS (Complementary Metal Oxide Semiconductor) sensor. The second semiconductor chip 20 is a chip with a smaller surface area than the first semiconductor chip 10, such as an LSI or a memory. The first semiconductor chip 10 and the second semiconductor chip 20 may be other types of semiconductor chips.

[0026] The first semiconductor chip 10 includes a chip body 11 (first chip body), an insulating film 12 (first insulating film), and terminal electrodes 13 (first electrodes) (see also FIG. 2(a)). The chip body 11 is a main part of the first semiconductor chip 10 on which integrated circuits and the like are formed. The insulating film 12 is formed of an inorganic insulating material or an organic insulating material and is an insulating film provided on the inner surface 11a (one surface) of the chip body 11. Examples of inorganic insulating materials that form the insulating film 12 include silicon dioxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON). Examples of organic insulating materials that form the insulating film 12 include polyimide, a polyimide precursor, polyamideimide, benzocyclobutene (BCB), polybenzoxazole (PBO), and a PBO precursor. A part of the insulating film 12 (for example, the front surface side) may be formed of an organic insulating material, and the remaining part may be formed of an inorganic insulating material. Since organic insulating materials have a lower modulus of elasticity (Young's modulus) and are softer than inorganic insulating materials, when placed on the front side, they can absorb foreign matter (debris, etc.) adhering to the surface of the first semiconductor chip 10.

[0027] Terminal electrodes 13 are electrodes formed from a conductive material such as copper (Cu) in insulating film 12. The diameter or width of each electrode constituting terminal electrodes 13 is, for example, 0.005 μm or more and 20 μm or less. One end of terminal electrode 13 is electrically connected to a connection terminal of chip body 11, and the other end of terminal electrode 13 is formed so as to be exposed to the outside from insulating film 12. The number of terminal electrodes 13 of first semiconductor chip 10 is provided according to the number of second semiconductor chips 20 to be mounted.

[0028] The second semiconductor chip 20 includes a chip body 21 (second chip body), an insulating film 22 (second insulating film), and terminal electrodes 23 (second electrodes) (see also FIG. 2(b)). The chip body 21 is a main part of the second semiconductor chip 20 on which integrated circuits and the like are formed. The insulating film 22 is made of an inorganic or organic insulating material and is an insulating film provided on the inner surface 21a (one surface) of the chip body 21. The inorganic or organic insulating material forming the insulating film 22 is the same as that of the insulating film 12 of the first semiconductor chip 10. The terminal electrodes 23 are electrodes formed in the insulating film 22 from a conductive material such as copper (Cu). The diameter or width of each electrode constituting the terminal electrodes 23 is, like that of the terminal electrodes 13, for example, 0.005 μm or more and 20 μm or less. One end of the terminal electrode 23 is electrically connected to a connection terminal of the chip body 21, and the other end of the terminal electrode 23 is formed so as to be exposed from the insulating film 22.

[0029] The first semiconductor chip 10 and the second semiconductor chip 20 are bonded together by hybrid bonding, which will be described later, such that the insulating film 12 around the terminal electrode 13 and the insulating film 22 around the terminal electrode 23 are firmly attached to each other, and the terminal electrodes 13 and 23 are joined together. By such hybrid bonding, in the semiconductor device 1, the terminal electrodes 13 and 23 are finely bonded together without any misalignment.

[0030] The encapsulant 30 is a portion that encapsulates the second semiconductor chip 20, which is mounted (placed) on the first semiconductor chip 10, with an encapsulating material. The encapsulant 30 encapsulates the entire second semiconductor chip 20 except for the surface that is placed on the first semiconductor chip 10. Examples of materials that constitute the encapsulant 30 include epoxy resin and acrylic resin. The encapsulant 30 can be formed by curing these resins with heat or light. The encapsulant 30 also has multiple via holes 31 formed therein. Each via hole 31 is a through-hole that penetrates from the first semiconductor chip 10 to the rewiring layer 40. At one end (the upper end in FIG. 1 ), a terminal electrode 13 of the first semiconductor chip 10 is exposed, and at the other end, an electrode of the rewiring layer 40 or a normal wiring layer is exposed. The via holes 31 are filled with a conductive material such as copper to form conductive vias 32. The conductive vias 32 electrically connect the terminal electrodes 13 of the first semiconductor chip 10 to wiring electrodes 42 of the rewiring layer 40 or the like. The semiconductor device 1 has at least one conductive via 32, and the conductive vias 32 may be provided in accordance with the number of second semiconductor chips 20, or multiple conductive vias 32 may be provided for one second semiconductor chip 20.

[0031] The redistribution layer 40 is a redistribution layer (RDL) for widening the terminal pitch of the terminal electrodes 13 of the first semiconductor chip 10, and is composed of an insulating layer 41 made of, for example, polyimide or the like, and wiring electrodes 42 made of copper wiring or the like. An outer insulating layer 43 may be provided on the redistribution layer 40 so that the terminals of the wiring electrodes 42 exposed to the outside from the insulating layer 41 are insulated from each other. Bumps 50 made of solder balls or the like are connected to the terminals of the wiring electrodes 42 whose terminal pitch has been widened by the redistribution layer 40. As a result, the terminal electrodes 13 of the first semiconductor chip 10 are pitch-converted (widened) and connected to the bumps 50.

[0032] (Method of manufacturing a semiconductor device) Next, a method for manufacturing the semiconductor device 1 will be described in order with reference to FIGS. 2 to 6. FIG. 2 is a cross-sectional view showing a cross section of each semiconductor chip used in manufacturing the semiconductor device, where (a) shows a cross section of a first semiconductor chip and (b) shows a cross section of a second semiconductor chip. FIG. 3 is a schematic cross-sectional view showing one step of the method for manufacturing the semiconductor device according to this embodiment, showing the step of bonding the second semiconductor chip to the first semiconductor chip. FIG. 4 (a) to (c) are views sequentially showing the bonding of the semiconductor chips shown in FIG. 3. FIG. 5 (a) to (c) and FIG. 6 (a) to (c) are schematic cross-sectional views showing each step of the method for manufacturing the semiconductor device according to this embodiment, following FIG. 3.

[0033] The semiconductor device 1 can be manufactured, for example, through the following steps (a) to (j). (a) A step of preparing a first semiconductor chip 10 having a chip body 11, and an insulating film 12 and terminal electrodes 13 provided on one surface of the chip body 11. (b) A step of preparing at least one second semiconductor chip 20 having a chip body 21, and an insulating film 22 and terminal electrodes 23 provided on one surface of the chip body 21. (c) A step of bonding the insulating film 12 of the first semiconductor chip 10 and the insulating film 22 of the second semiconductor chip 20 together. (d) A step of bonding the terminal electrodes 13 of the first semiconductor chip 10 to the terminal electrodes 23 of the second semiconductor chip 20. (e) A step of sealing the second semiconductor chip 20 placed on the first semiconductor chip 10 with a sealing resin to form a sealing body 30. (f) A step of polishing the surface 30a of the sealing body 30. (g) A step of forming at least one via hole 31 in a sealing body 30 formed from a sealing resin. (h) A step of filling the via hole 31 with a conductive material to form a conductive via 32 so as to be electrically connected to at least one of the terminal electrode 13 and the terminal electrode 23 . (i) A step of forming a rewiring layer 40 on the surface 30 a of the sealing body 30 . (j) A step of forming bumps 50 on the outer surface 40 a of the rewiring layer 40 located on the side opposite to the sealing body 30 . Although the following describes a manufacturing method for a semiconductor device 1 having two second semiconductor chips 20 attached to one first semiconductor chip 10, the combination of semiconductor chips to be bonded is not limited to this relationship. Alternatively, a manufacturing method may be used in which a second semiconductor chip 20 is bonded to a substrate including a plurality of first semiconductor chips 10 and then the substrate is finally singulated.

[0034] [Step (a) and Step (b)] Step (a) is a step of preparing a first semiconductor chip 10 on which an integrated circuit composed of semiconductor elements and wiring connecting them is formed. In step (a), as shown in FIG. 2(a), terminal electrodes 13 made of copper, aluminum, or the like are provided on the inner surface 11a of a chip body 11 made of silicon or the like, and an insulating film 12 made of an inorganic or organic material is provided. The terminal electrodes 13 are terminal electrodes for exposing the integrated circuits and the like formed on the first semiconductor chip 10 to the outside through the insulating film 12. Each of the terminal electrodes 13 corresponds to a second semiconductor chip 20. The insulating film 12 may be provided on the inner surface 11a of the chip body 11 before the terminal electrodes 13 are provided, or the insulating film 12 may be provided on the inner surface 11a of the chip body 11 before the terminal electrodes 13 are provided.

[0035] Step (b) is a step of preparing a second semiconductor chip 20 on which an integrated circuit composed of semiconductor elements and wiring connecting them is formed. In step (b), as shown in FIG. 2(b), terminal electrodes 23 made of copper, aluminum, or the like are provided on the inner surface 21a of a chip body 21 made of silicon or the like, and an insulating film 22 made of an inorganic or organic material is also provided. The terminal electrodes 23 are terminal electrodes for exposing the integrated circuits and the like formed on the second semiconductor chip 20 to the outside through the insulating film 22. The terminal electrodes 23 correspond to the terminal electrodes 13 of the first semiconductor chip 10. The insulating film 22 may be provided on the inner surface 21a of the chip body 21 before the terminal electrodes 23 are provided, or the insulating film 22 may be provided on the inner surface 21a of the chip body 21 before the terminal electrodes 23 are provided.

[0036] The insulating films 12 and 22 used in steps (a) and (b) are composed of inorganic or organic materials. Examples of inorganic materials used for the insulating films include silicon oxide (SiO2), silicon nitride (SiN), and silicon oxynitride (SiON). When an inorganic material such as silicon oxide is used for the insulating film, a semiconductor device with a finer structure can be fabricated. Furthermore, when the insulating films are bonded together in step (c) described below, the bonding strength between the semiconductor substrates can be increased, thereby improving the connection reliability of the semiconductor device.

[0037] Examples of organic materials used for the insulating films include polyimide, polyimide precursors (e.g., polyimide esters or polyamic acids), polyamideimide, benzocyclobutene (BCB), polybenzoxazole (PBO), and PBO precursors. These organic materials have a lower elastic modulus and are softer than inorganic materials such as silicon dioxide (SiO2). By using such organic materials, even if fine debris is present on the insulating film, it is absorbed into the insulating film when bonding the insulating films together in step (c) described below, preventing poor bonding due to the debris. This enables reliable bonding of the insulating films together. The elastic modulus of the organic material constituting the insulating films 12 and 22 may be, for example, 7.0 GPa or less, 5.0 GPa or less, 3.0 GPa or less, 2.0 GPa or less, or 1.5 GPa or less. The elastic modulus here refers to Young's modulus. Furthermore, the organic material constituting the insulating films 12 and 22 preferably has a thermal expansion coefficient of 70 ppm / K or less, more preferably 50 ppm / K or less.

[0038] Furthermore, the organic materials used for the insulating films are liquid or soluble in a solvent, allowing each insulating film to be easily formed as a thin film by spin coating or the like. Furthermore, these organic materials are heat-resistant, and can withstand the temperatures (e.g., high temperatures of 300°C or higher) encountered when bonding the terminal electrodes 13 and 23 in step (d) described below, preventing the bonding between the insulating films from deteriorating due to high temperatures. The organic material constituting the insulating films 12 and 22 may be a photosensitive resin, a thermosetting non-conductive film (NCF), or a thermosetting resin. This organic material may be an underfill material. The insulating films 12 and 22 may also be insulating films containing both inorganic and organic materials. For example, a portion (e.g., the surface side) may be formed from an organic insulating material, and the remaining portion may be formed from an inorganic insulating material.

[0039] In steps (a) and (b), the surface of the insulating film 12 on which the terminal electrodes 13 of the first semiconductor chip 10 are provided and the surface of the insulating film 22 on which the terminal electrodes 23 of the second semiconductor chip 20 are provided may be polished using a chemical mechanical polishing (CMP) method. In this polishing process, the first semiconductor chip 10 and the second semiconductor chip 20 may be polished by the CMP method under conditions that selectively and deeply polish the terminal electrodes 13 and 23 made of, for example, copper, or the like. Alternatively, the CMP method may be used to polish the surfaces of the terminal electrodes 13 and 23 so that they coincide with the surfaces of the insulating films 12 and 22. Note that this polishing also removes debris from the surfaces of the first semiconductor chip 10 and the second semiconductor chip 20. In the polishing process, the insulating film 12 and the insulating film 22 may be polished to have the same thickness. Alternatively, the insulating film 22 may be polished to have a thickness greater than that of the insulating film 12. Alternatively, the insulating film 22 may be polished to have a thickness less than that of the insulating film 12.

[0040] [Step (c) and step (d)] 3, the second semiconductor chip 20 is mounted (placed) on the first semiconductor chip 10. During this placement, the second semiconductor chip 20 is aligned so that the terminal electrodes 23 of the second semiconductor chip 20 face the corresponding terminal electrodes 13 of the first semiconductor chip 10. For this alignment, alignment marks or the like may be provided on the first semiconductor chip 10.

[0041] More specifically, as shown in FIGS. 4A and 4B, step (c) involves bonding the insulating film 12 of the first semiconductor chip 10 and the insulating film 22 of the second semiconductor chip 20 to each other. In step (c), after removing any organic matter or metal oxide adhering to the surface of the second semiconductor chip 20, the second semiconductor chip 20 is aligned with the first semiconductor chip 10. After this is complete, the insulating film 22 of each second semiconductor chip 20 is bonded to the insulating film 12 of the first semiconductor chip 10 using hybrid bonding. The insulating film 22 of the second semiconductor chip 20 and the insulating film 12 of the first semiconductor chip 10 may be uniformly heated before bonding. The temperature difference between the first semiconductor chip 10 and the second semiconductor chip 20 during bonding is preferably, for example, 10°C or less. This uniformly heated bonding creates an insulating bond S1 where the insulating film 12 and the insulating film 22 are bonded, thereby mechanically and firmly attaching the second semiconductor chip 20 to the first semiconductor chip 10. Furthermore, because the heat bonding is performed at a uniform temperature, misalignment at the bonding points is unlikely to occur, allowing for highly accurate bonding. At this attachment stage, terminal electrodes 13 of first semiconductor chip 10 and terminal electrodes 23 of second semiconductor chip 20 are spaced apart from each other and are not connected (but are aligned). Note that bonding of second semiconductor chip 20 to first semiconductor chip 10 may be performed by other bonding methods, such as room temperature bonding.

[0042] [Step (d)] Step (d) is a step of bonding the terminal electrodes 13 of the first semiconductor chip 10 to the terminal electrodes 23 of the second semiconductor chip 20. In step (d), after the bonding in step (c) is completed, as shown in FIG. 4(b), a predetermined heat and / or pressure is applied to bond the terminal electrodes 13 of the first semiconductor chip 10 to the terminal electrodes 23 of the second semiconductor chip 20 by hybrid bonding (see also FIG. 4(c)). When the terminal electrodes 13 and 23 are made of copper, the annealing temperature in step (d) is preferably 150°C to 400°C, more preferably 200°C to 300°C. This bonding process forms an electrode bonding portion S2 where the terminal electrodes 13 and the corresponding terminal electrodes 23 are bonded, and the terminal electrodes 13 and 23 are firmly bonded mechanically and electrically. FIG. 4(c) shows the state in which the insulating bonding portion S1 and the electrode bonding portion S2 are formed. The electrode bonding in step (d) is performed after the bonding in step (c), but may be performed simultaneously with the bonding in step (c). Thereafter, as shown in (a) of FIG. 5, a semi-finished product 1a is formed in which the second semiconductor chip 20 is bonded to the first semiconductor chip 10.

[0043] [Step (e)] Step (e) is a step of encapsulating the second semiconductor chip 20 placed on the first semiconductor chip 10 with encapsulating resin to form a encapsulated body 30. In step (e), as shown in FIG. 5(a), once the second semiconductor chip 20 is placed on the first semiconductor chip 10, the second semiconductor chip 20 is encapsulated with an encapsulating material so as to cover the second semiconductor chip 20. As a result, as shown in FIG. 5(b), the encapsulated body 30 that covers the second semiconductor chip 20 is formed. Examples of materials that constitute the encapsulated body 30 include epoxy resin and acrylic resin, and the encapsulated body 30 can be formed by encapsulating the second semiconductor chip 20 with these resins and then curing the encapsulating resin material with heat or light.

[0044] [Process (f)] Step (f) is a step of polishing the surface 30a of the encapsulant 30. In step (f), after the encapsulant 30 is formed as shown in FIG. 5B, the surface 30a of the encapsulant 30 is polished. In this polishing step, the encapsulant 30 is polished so that the surface roughness (Ra value) of the surface 30a of the encapsulant 30 is 1 μm or less, more preferably 0.5 μm or less, and most preferably 0.1 μm or less. For example, a grinder for electronic materials processing or CMP (Chemical Mechanical Polishing) can be used as the polishing method. Furthermore, the polishing can be performed to a degree that does not expose the encapsulated second semiconductor chip 20. The thickness of the encapsulant 30 between the surface 30a of the encapsulant 30 and the second semiconductor chip 20 is preferably 300 μm or less, more preferably 250 μm or less, and most preferably 200 μm or less. Alternatively, the encapsulant 30 may be polished to an extent that the surface of the encapsulated second semiconductor chip (the side opposite the surface on which the terminal electrodes and insulating layer are formed) is exposed. The surface roughness (Ra value) used here is calculated by observation with an electron microscope, for example, and means the arithmetic mean surface roughness (JIS B 0601-2001).

[0045] [Process g] Step (g) is a step of forming at least one via hole 31 in the sealing body 30 formed from a sealing resin. In step (g), after the sealing body 30 is formed as shown in FIG. 5(b), the via hole 31 is formed at a predetermined location in the sealing body 30 by laser, wet etching, dry etching, or the like as shown in FIG. 5(c). The via hole 31 is a through hole extending from the surface 30a of the sealing body 30 to the terminal electrode 13 of the first semiconductor chip 10, and a part of the terminal electrode 13 is exposed in the via hole 31. Note that the method for forming the via hole is not limited to the above method, and other methods may be used.

[0046] [Process (h)] Step (h) is a step of filling the via hole 31 with a conductive material to form a conductive via 32 so as to be electrically connected to at least one of the terminal electrode 13 and the terminal electrode 23. In step (h), after the via hole 31 is formed in the encapsulant 30 as shown in FIG. 5(c), the via hole 31 is filled with a conductive paste by printing or the like as shown in FIG. 6(a). The conductive paste contains, for example, copper. This forms the conductive via 32. Such a conductive via 32 has a pillar element and can achieve a high aspect ratio. One end of the conductive via 32 is exposed on the surface 30a of the encapsulant 30, and the other end is electrically connected to the terminal electrode 13 (or the terminal electrode 23). The conductive via 32 may be formed by plating. Furthermore, in step (h), after the conductive via 32 is formed, a wiring layer 33 is formed on the surface 30a of the encapsulant 30. The wiring layer 33 may be formed together with the conductive vias 32 by plating or printing a conductive paste, or may be formed separately after the conductive vias 32 are formed.

[0047] [Step (i)] Step (i) is a step of forming a rewiring layer 40 on the surface 30a of the encapsulant 30. In step (i), after the conductive vias 32 and the wiring layer 33 are formed in the encapsulant 30 as shown in FIG. 6A, the rewiring layer 40 is formed on the surface 30a of the encapsulant 30 as shown in FIG. 6B. The rewiring layer 40 is a layer for widening the terminal pitch of the terminal electrodes 13 of the first semiconductor chip 10, and is composed of, for example, an insulating layer 41 made of polyimide or the like and wiring electrodes 42 made of copper wiring or the like in the insulating layer 41. In the rewiring layer 40 formation step, the formation of the insulating layer and the wiring layer is repeated a predetermined number of times to form a wiring layer for pitch conversion. One end 42a of the wiring electrodes 42 in the rewiring layer 40 is connected to the conductive vias 32 or the wiring layer 33, and the other end 42b is exposed to the outside from the insulating layer 41. A bump 50, which will be described later, is connected to the other end 42b of the wiring electrode 42. An outer insulating layer 43 may be further provided on the outside of the rewiring layer 40, and is configured so that the other ends 42b of the wiring electrodes 42 connected to each bump 50 are not electrically connected to each other. In this manufacturing method, after the encapsulant 30 is formed, a polishing process is performed to reduce steps or surface roughness on the surface of the encapsulant 30, making it easier to build a fine rewiring layer on the encapsulant 30.

[0048] [Process (j)] Step (j) is a step of forming bumps 50 on the outer surface 40a of the rewiring layer 40 located on the opposite side from the encapsulant 30. In step (j), once the rewiring layer 40 is formed, bumps 50 are formed on the outer surface 40a of the rewiring layer 40 so as to connect to the other ends 42b of the wiring electrodes 42 exposed from the insulating layer 41, as shown in (b) and (c) of FIG. 6. The bumps 50 are, for example, solder balls, and are connected to terminals at the ends 42a whose terminal pitch has been widened by the rewiring layer 40, whereby the terminal electrodes 13 of the first semiconductor chip 10 are pitch-converted (widened) and connected to the bumps 50. Through the above steps, the semiconductor device 1 shown in FIG. 1 can be obtained.

[0049] As described above, according to the method for manufacturing a semiconductor device according to this embodiment, after the first semiconductor chip 10 and the second semiconductor chip 20 are bonded by so-called hybrid bonding, the second semiconductor chip 20 is sealed, and the conductive vias 32 are formed in the sealing body 30. Because the conductive vias 32 are formed after sealing, the conductive vias 32 can be formed with high density and a high aspect ratio. This enables high-density packaging in three-dimensional packaging, such as placing the second semiconductor chip 20 on the first semiconductor chip 10.

[0050] In the method for manufacturing a semiconductor device according to this embodiment, at least one of the insulating films 12 and 22 may contain an inorganic insulating material. In this case, it is possible to manufacture a semiconductor device with a finer configuration. In addition, both the insulating films 12 and 22 may contain an inorganic insulating material. In this case, since it is easy to bond inorganic materials together, the adhesive strength between semiconductor chips can be increased, thereby improving the connection reliability of the semiconductor device.

[0051] In the method for manufacturing a semiconductor device according to this embodiment, at least one of the insulating films 12 and 22 may contain an organic insulating material. In this case, the organic material is a relatively soft material, and unwanted particles (debris) adhering to the chip surface can be absorbed by the insulating film, thereby reducing connection defects between semiconductor chips.

[0052] Furthermore, in the method for manufacturing a semiconductor device according to this embodiment, the insulating film 12 and the insulating film 22 may be bonded by room temperature bonding in the bonding step. In this case, the bonding of the insulating film 12 and the insulating film 22 can be easily performed without considering thermal expansion, etc. Furthermore, since the bonding is performed at room temperature, it is not necessary to consider the influence of heat on the first semiconductor chip 10 and the second semiconductor chip 20.

[0053] The method for manufacturing a semiconductor device according to this embodiment may further include a step of polishing the surface 30a of the encapsulant 30. In this case, variations in the level difference or surface roughness on the surface 30a of the encapsulant 30 are reduced, making it possible to easily form the redistribution layer 40 or the normal wiring layer 33 with greater precision and density. In this case, the encapsulant 30 may be polished in the polishing step so that the surface roughness (Ra) of the encapsulant 30 is 1 μm or less, more preferably 0.5 μm or less, and most preferably 0.1 μm or less. This allows for the formation of wiring having a fine pattern. In the polishing step, the encapsulant 30 may be polished in the polishing step so that the thickness of the encapsulant 30 between the surface 30a of the encapsulant 30 and the second semiconductor chip 20 is 300 μm or less, more preferably 250 μm or less, and most preferably 200 μm or less. Alternatively, the surface of the second semiconductor chip (the side opposite the terminal electrode surface) may be exposed. This allows for a more reliable reduction in the package height, warpage, and heat dissipation.

[0054] Moreover, the method for manufacturing a semiconductor device according to this embodiment further includes a step of forming a redistribution layer 40 on the sealing body 30. In this case, it becomes possible to easily convert the wiring pitch of the first semiconductor chip 10, etc. to the wiring pitch of an external device such as a wiring board.

[0055] The method for manufacturing a semiconductor device according to this embodiment further includes a step of forming bumps 50 on the outer surface 40a of the redistribution layer 40 located on the opposite side from the sealing body 30. This allows the semiconductor device 1 to be easily attached to an external device such as a wiring board.

[0056] In the method for manufacturing a semiconductor device according to this embodiment, the sealing material used in the sealing step may be epoxy resin or acrylic resin, which allows the second semiconductor chip 20 to be sealed reliably and easily.

[0057] Furthermore, in the method for manufacturing a semiconductor device according to this embodiment, in the step of forming via holes, a plurality of via holes 31 may be formed around the second semiconductor chip 20, and the terminal electrodes 13 of the first semiconductor chip 10 are exposed in the plurality of via holes 31. Then, in the step of filling with a conductive material, the conductive material is filled into each of the plurality of via holes 31 so as to be electrically connected to the terminal electrodes 13. This allows the conductive vias 32 to be provided at a higher density, and allows the first semiconductor chip 10 to be more reliably connected to external devices, etc. Furthermore, conductive vias 32 with a high aspect ratio can also be easily fabricated.

[0058] Furthermore, in the method for manufacturing a semiconductor device according to this embodiment, the second semiconductor chip 20 has a smaller surface area than the first semiconductor chip 10, and multiple second semiconductor chips 20 are bonded to the first semiconductor chip 10. In the sealing process, the multiple second semiconductor chips 20 placed on the first semiconductor chip 10 are collectively sealed with sealing resin. This allows two or more second semiconductor chips 20 to be bonded to one first semiconductor chip 10, enabling higher-density three-dimensional packaging.

[0059] Furthermore, in the semiconductor device according to this embodiment, the first semiconductor chip 10 and the second semiconductor chip 20 are firmly bonded by so-called hybrid bonding, and conductive vias 32 are formed in the sealing body 30 that seals the second semiconductor chip 20. Since the conductive vias 32 are formed in the sealing body 30, the conductive vias 32 can be formed at high density. This enables high-density mounting in three-dimensional mounting, such as placing the second semiconductor chip 20 on the first semiconductor chip 10.

[0060] The semiconductor device according to this embodiment further includes a redistribution layer 40 provided on the surface of the sealing body 30 opposite to the first semiconductor chip 10. The redistribution layer 40 is electrically connected to the terminal electrodes 13 of the first semiconductor chip 10 by conductive vias 32. This makes it possible to easily convert the wiring pitch of the first semiconductor chip 10, etc., to the wiring pitch of an external device such as a wiring board.

[0061] Although the embodiments of the present disclosure have been described above, the present invention is not limited to the above-described embodiments, and appropriate modifications may be made without departing from the spirit of the present invention. [Explanation of symbols]

[0062] 1...semiconductor device, 10...first semiconductor chip, 11...chip body (first chip body), 12...insulating film (first insulating film), 13...terminal electrode (first electrode), 20...second semiconductor chip, 21...chip body (second chip body), 22...insulating film (second insulating film), 23...terminal electrode (second electrode), 30...encapsulant, 30a...surface, 31...via hole, 32...conductive via, 33...wiring layer, 40...rewiring layer, 50...bump.

Claims

1. preparing a first semiconductor chip having a first chip body, and a first insulating film and a first electrode provided on one surface of the first chip body; preparing at least one second semiconductor chip having a second chip body, and a second insulating film and a second electrode provided on one surface of the second chip body; a step of bonding the first insulating film of the first semiconductor chip and the second insulating film of the second semiconductor chip to each other; a step of bonding the first electrodes of the first semiconductor chip to the second electrodes of the second semiconductor chip; a step of sealing the second semiconductor chip placed on the first semiconductor chip with a sealing resin; forming at least one via hole in a sealing body formed from the sealing resin; forming a conductive via by filling the via hole with a conductive material so as to be electrically connected to at least one of the first electrode and the second electrode; A method for manufacturing a semiconductor device, comprising:

2. At least one of the first insulating film and the second insulating film contains an inorganic insulating material. The method for manufacturing a semiconductor device according to claim 1 .

3. At least one of the first insulating film and the second insulating film contains an organic insulating material. The method for manufacturing a semiconductor device according to claim 1 or 2.

4. Further comprising a step of polishing the surface of the encapsulant. The method for manufacturing a semiconductor device according to any one of claims 1 to 3.

5. In the polishing step, the sealant is polished so that the surface roughness of the sealant is 0.1 μm or less. The method for manufacturing a semiconductor device according to claim 4 .

6. In the polishing step, the sealing body is polished so that the thickness of the sealing body between the surface of the sealing body and the second semiconductor chip is 300 μm or less. The method for manufacturing a semiconductor device according to claim 4 or 5.

7. Further comprising a step of forming a redistribution layer on the encapsulation body. The method for manufacturing a semiconductor device according to any one of claims 1 to 6.

8. the redistribution layer is electrically connected to the first electrode of the first semiconductor chip by a conductive via formed from the conductive material; The method for manufacturing a semiconductor device according to claim 7 .

9. The method further includes forming a bump on an outer surface of the redistribution layer opposite to the encapsulant.

9. The method for manufacturing a semiconductor device according to claim 7 or 8.

10. The sealing resin used in the sealing step is an epoxy resin or an acrylic resin. The method for manufacturing a semiconductor device according to any one of claims 1 to 9.

11. In the step of forming the via holes, a plurality of the via holes are formed around the second semiconductor chip, the first electrodes of the first semiconductor chip are exposed to the via holes; In the step of filling the conductive material, the conductive material is filled into each of the plurality of via holes so as to be electrically connected to the first electrode. The method for manufacturing a semiconductor device according to any one of claims 1 to 10.

12. the second semiconductor chip has a smaller surface area than the first semiconductor chip, a plurality of second semiconductor chips are bonded to the first semiconductor chip; In the sealing step, the second semiconductor chips placed on the first semiconductor chip are collectively sealed with the sealing resin. The method for manufacturing a semiconductor device according to any one of claims 1 to 11.

13. a first semiconductor chip having a first chip body, a first insulating film and a first electrode provided on one surface of the first chip body; a second semiconductor chip having a second chip body, a second insulating film and a second electrode provided on one surface of the second chip body, the second semiconductor chip being mounted on the first semiconductor chip; a sealing body covering the second semiconductor chip on the first semiconductor chip; a conductive via that is filled in a via hole provided in the sealing body and is electrically connected to at least one of the first electrode and the second electrode, the first insulating film and the second insulating film are bonded to each other, The semiconductor device, wherein the first electrode and the second electrode are directly bonded to each other.

14. a rewiring layer provided on a surface of the sealing body opposite to the first semiconductor chip; the rewiring layer is electrically connected to the first electrode of the first semiconductor chip by the conductive via; The semiconductor device according to claim 13.

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