Integrated structure having an antenna element and an IC chip employing edge contact connections

Abstract

To provide an antenna apparatus that electrically connects an IC chip to a substrate having a cavity.SOLUTION: In an antenna apparatus 100 having a cavity 140 in a first top face 135, the substrate 130 has side walls 144-1, 144-2 defining a portion of the cavity 140, and forms a first edge contact 132 at the side walls 144-1, 144-2. An IC chip 110 is arranged within the cavity 140, and has side faces 117-1, 117-2 facing the side walls 144-1, 144-2 and a second edge contact 112 formed on the side faces 117-1, 117-2 electrically connected with the first edge contact 132. Antenna element 120-1, 120-2, arranged at a second lower face 139 of the substrate 130 opposite the first top face 135, is electrically connected with an RF circuit within the IC chip 110 through conductive vias 122-1, 122-2 extending within the substrate 130.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] TECHNICAL FIELD This disclosure relates generally to connection techniques and arrangements between IC chips and other circuit components supported by a substrate, such as printed antenna elements. Related Technology Considerations

[0002] In wireless communications, it is typically desirable to provide compact antenna equipment in which antenna elements are integrated with an IC chip containing beamforming components. Satellite applications, for example, typically use phased arrays with many microstrip patch antenna elements on a substrate. The antenna elements can be electrically connected to distributed power amplifiers that provide RF power and processor-controlled phase shifters, allowing the resulting antenna beam to be dynamically steered. Other front-end equipment, such as power amplifiers, phase shifters, and receiver circuitry, can be provided on an IC chip integrated with the antenna elements in a single structure. Summary of the Invention [Problem to be solved by the invention]

[0003] In one aspect of the disclosed technology, an antenna device includes a substrate having a cavity on a first outer surface. The substrate has a sidewall defining a portion of the cavity, and a first edge contact formed on the sidewall. An IC chip is disposed within the cavity and has a side surface facing the sidewall and a second edge contact formed on the side surface electrically connected to the first edge contact. An antenna element disposed on a second outer surface of the substrate opposite the first outer surface is electrically connected to RF circuitry in the IC chip through a conductive via extending into the substrate.

[0004] Electrical connection of the antenna element to RF circuitry within the IC chip can be made through the first and second edge contacts, or alternatively, connection of the antenna element can be made through electrical contacts on the bottom surface of the IC chip.

[0005] In another aspect, a method for manufacturing an antenna device includes forming a cavity on a first outer surface of a substrate and forming an antenna element on a second outer surface of the substrate opposite the first outer surface. A first edge contact is formed on a sidewall of the cavity. An IC chip is disposed in the cavity, the IC chip having a second edge contact formed on a side surface thereof and including an RF circuit. The first edge contact and the second edge contact are electrically connected. A conductive via is formed in the substrate extending from the second outer surface, and the antenna element is electrically connected to the RF circuit through the conductive via.

[0006] In another aspect, a method for fabricating an electronically steerable antenna array includes forming a plurality of cavities in a substrate, the cavities being spatially arranged along a first outer surface of the substrate; forming a plurality of antenna elements spatially arranged on a second outer surface of the substrate opposite the first outer surface; providing a plurality of IC chips, each having a side surface with a respective first edge contact, each IC chip including a beam-forming component; forming, for each of the cavities, a second edge contact on a sidewall of the cavity; disposing a respective one of the plurality of IC chips in the cavity; electrically connecting the respective first edge contact and second edge contact; and electrically connecting the beam-forming component of the IC chip disposed therein to at least one of each of the antenna elements. [Brief explanation of the drawings]

[0007] The above and other aspects and features of the disclosed technology will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which like reference numerals indicate like elements or features. Various elements of the same or similar type can be distinguished by adding a dash and a second label (e.g., -1, -2) to the reference label to distinguish between the same / similar elements. However, if a given description uses only a first reference label, it is applicable to any one of the same / similar elements having the same first reference label, regardless of the second reference label. Elements and features may not be drawn to scale in the drawings.

[0008] [Figure 1] FIG. 1 is an exploded perspective view of an exemplary antenna apparatus according to one embodiment.

[0009] [Figure 2] FIG. 2 is a plan view of the antenna device of FIG. 1 in an assembled state.

[0010] [Figure 3] FIG. 3 is a perspective view illustrating an exemplary first edge contact on a cavity sidewall.

[0011] [Figure 4] FIG. 4 is a perspective view showing an example of a second edge contact formed on a side surface of an IC chip.

[0012] [Figure 5] FIG. 5 is a cross-sectional view of the antenna device of FIG. 2 taken along line 5-5.

[0013] [Figure 6] FIG. 6 is a flow diagram of an exemplary method for forming the antenna apparatus of FIGS.

[0014] [Figure 7A] FIG. 7A is a top view of a portion of a lower substrate forming part of a multi-layer substrate of an exemplary antenna apparatus, showing an intermediate configuration after step S602 of the method of FIG.

[0015] [Figure 7B] FIG. 7B is a cross-sectional view of the lower substrate of FIG. 7A taken along line 7B-7B.

[0016] [Figure 7C] FIG. 7C is a bottom view of the lower substrate of FIG. 7A.

[0017] [Figure 7D]FIG. 7D is a plan view of a portion of the top substrate of a multi-layer substrate in intermediate process after step S604 of FIG. 6, showing the configuration after notches for forming edge contacts have been cut and metallized.

[0018] [Figure 7E] FIG. 7E is a cross-sectional view of the top substrate of FIG. 7D taken along line 7E-7E.

[0019] [Figure 7F] FIG. 7F is a plan view of the top substrate of FIG. 7D after step S606 of FIG.

[0020] [Figure 7G] FIG. 7G is a cross-sectional view of the top substrate of FIG. 7F taken along line 7G-7G.

[0021] [Figure 7H] FIG. 7H is a top view of a portion of an exemplary multilayer substrate formed after step S612 of the method of FIG.

[0022] [Figure 7I] FIG. 7I is a cross-sectional view of FIG. 7H taken along line 7I-7I.

[0023] [Figure 7J] FIG. 7J is a cross-sectional view corresponding to the cross-sectional view of FIG. 7I after step S614 of FIG.

[0024] [Figure 8A] FIG. 8A is a plan view of an electronic device according to another embodiment.

[0025] [Figure 8B] FIG. 8B is a cross-sectional view taken along line 8B-8B' of FIG. 8A.

[0026] [Figure 9] FIG. 9 is a flow chart illustrating an exemplary method for manufacturing the electronic device of FIGS. 8A-8B.

[0027] [Figure 10A] FIG. 10A is an exploded cross-sectional view of an electronic device with an embedded chip, according to one embodiment.

[0028] [Figure 10B] FIG. 10B is a cross-sectional view of the electronic device of FIG. 10A in an assembled state. DETAILED DESCRIPTION OF THE INVENTION

[0029] The following description, with reference to the accompanying drawings, is provided for illustrative purposes to assist in a comprehensive understanding of certain exemplary embodiments of the technology disclosed herein. Although this specification includes various specific details to assist those skilled in the art in understanding the technology, these details should be considered as merely exemplary. For the sake of brevity and clarity, the description of well-known functions and structures may be omitted if it may obscure the understanding of the technology by those skilled in the art.

[0030] 1 is an exploded perspective view of an exemplary antenna apparatus 100, according to one embodiment. The antenna apparatus 100 includes a substrate 130 and at least one antenna element 120 (e.g., two antenna elements 120-1, 120-2) electrically connected to RF circuitry within an IC chip 110. Each antenna element 120 is illustrated as a microstrip patch element printed on a bottom surface 139 ("second outer surface") of the substrate 130. While depicted as rectangular in shape, the antenna elements 120 may have any other suitable shape for forming a desired radiation pattern. Additionally, other types of antenna elements, such as dipole or slot antenna elements, may be substituted to achieve target performance metrics.

[0031] The substrate 130 has a cavity 140 formed in its top surface 135 ("first outer surface"), the cavity having a depth extending to a bottom surface that may coincide with the top surface of the ground plane 170. In the assembled state of the antenna device 100, the IC chip 110 is disposed within the cavity 140, with the top surface 115 of the IC chip 110 being substantially coplanar with the top surface 135 of the substrate 130. In the assembled state, the bottom surface 119 of the IC chip 110 faces and may be adjacent to the ground plane 170. At least one first edge contact 132 is disposed on a sidewall 144 of the cavity 140. At least one second edge contact 112 is disposed on a side surface 117 of the IC chip 110 and is electrically connected to an adjacent first edge contact 132. One antenna element 120 may be fed with an RF signal (in the transmit and / or receive direction) by a probe feed embodied as a through-substrate via (TSV) (hereinafter "conductive via" or simply "via") 122. The via 122 may be electrically connected to a short conductive trace 168, which is in turn electrically connected to the first edge contact 132, thereby completing the electrical connection between the antenna element 120 and the RF circuitry within the IC chip 110 connected to the second edge contact 112.

[0032] As used herein, the term IC chip refers to one or more electronic circuits embodied in a small, planar portion of semiconductor material. For example, IC chip 110 may be a monolithic microwave integrated circuit (MMIC) made of gallium arsenide (GaAs), indium phosphide (InP), silicon germanium (SiGe), or gallium nitride (GaN). IC chip 110 may include a power amplifier for amplifying a transmit path signal output to antenna element 120 and / or a low noise amplifier (LNA) for amplifying a receive path signal received by antenna element 120.

[0033] In the illustrated example, the two antenna elements 120-1, 120-2 are connected to a single IC chip 110 through a combination of vias 122-1, 122-2, first edge contacts 132 on opposing sidewalls 144-1, 144-2 of the cavity 140, and second edge contacts 112 on opposing side surfaces 117-1, 117-2 of the IC chip 110. The IC chip 110 also includes another pair of second edge contacts 112, each connected to one conductive trace 165 through adjacent first edge contacts 132. Each conductive trace 165 may be electrically connected to a component (not shown), such as a terminal that receives a bias voltage or control signal to be applied to an RF component within the IC chip 110, such as an amplifier or a dynamically controlled phase shifter. In other examples, IC chip 110 may include more or fewer edge contacts 112 for more or fewer connections to components, as desired for a particular application, and more or fewer antenna elements 120 may be connected to IC chip 110. For RF connections, microstrip or coplanar waveguide (CPW) transmission may be implemented. For example, conductive traces 165 and 168 in the drawings herein are shown as single lines; in the case of microstrip, conductive trace 165 may be a microstrip line on a ground plane (e.g., 170). In the case of CPW, conductive traces 165 may each be an inner conductive trace between a pair of outer conductive ground traces (not shown).

[0034] The antenna device 100, as shown in FIG. 1 , is composed of at least one IC chip 110 and at least one antenna element 120. In a typical application, the antenna device 110 is composed of several, tens, or even hundreds of IC chips 110. Each of the IC chips 110 resides within a respective cavity 140 spatially arranged along a substrate 130. In this typical application, at least some or all of the IC chips 110 are respectively connected to one or more antenna elements 120 spatially arranged along a bottom surface 139 of the substrate 130, thereby forming an antenna array. The antenna array may be an electronically steered antenna, such as a phased array, that is dynamically steered by phase shifters collectively arranged within the IC chips 110 or elsewhere in the antenna device 100. The substrate 130 may include beamforming circuitry electrically connected to the IC chip 110 to split an input RF signal during a transmit operation and / or to combine multiple RF signals received from the antenna elements 120 and processed (e.g., amplified, filtered, phase-shifted, downconverted, etc.) by the IC chip 110 during a receive operation.

[0035] FIG. 2 is a plan view of the antenna device 100 of FIG. 1 in an assembled state. FIG. 3 is a perspective view illustrating an exemplary first edge contact 132 on a cavity sidewall. FIG. 4 is a perspective view illustrating an exemplary second edge contact 112 formed on a side surface of the IC chip 110. FIG. 5 is a cross-sectional view taken along line 5-5 in FIG. 2. Referring collectively to FIGS. 1-5, the first edge contact 132 and an adjacent second edge contact 112 can have complementary geometric shapes. Each first edge contact 132 can have a three-dimensional (3D) structure, e.g., a metal peripheral surface of the 3D structure plated to form metal peripheral surfaces on the side, base, and backside. The dimensions of the complementary geometric structures can form an interference fit to enable placement of the IC chip 110 within the cavity 140, such that the second edge contact 112 "snaps into" the first edge contact 132. This can help secure the IC chip 110 in place within the cavity 140 before strengthening the electrical connection between the edge contacts 112, 132 by soldering, thermocompression, thermosonic bonding, or the like. Alternatively, a complete electrical connection can be made solely by a press-fit between the edge contact structures, without soldering or the like. An interference fit between adjacent first and second edge contacts 132, 112 can interlock the respective edge contacts. For example, as seen in FIG. 3, the first edge contact 132 can have a slotted, flared opening 149 that is a recess in the cavity sidewall 144-2. As best seen in FIG. 4, the adjacent second edge contact 112 can be in the form of a flared protrusion from the side surface 117-2, which fits tightly within the slotted opening 149. With the outer surfaces of the second edge contacts 112 in intimate contact with the inner surfaces of the corresponding first edge contacts 132, solder or other conductive bonding material 190 (see FIG. 2) may be applied therebetween to complete or strengthen the electrical connection. The conductive bonding material may also serve, at least in part, as a mechanical connection of the IC chip 110 to the substrate 130. The outer dimensions of the IC chip 110 may also form an interference fit, or even a press-fit, with the sidewalls 144 of the cavity 140.A small gap "g" may exist between the side 117 of the IC chip 110 and the sidewall 144 to allow for thermal expansion or manufacturing tolerances.

[0036] As previously mentioned, when coplanar waveguide (CPW) transmission is used for the edge contacts 112, 132, a ground-signal-ground (GSG) snap connection may be made between the corresponding edge contacts 112, 132. In this configuration, there are three connection points per electrical connection. In other words, the second edge contact 112 can be composed of three contacts: two "ground" contacts and one "signal" contact between them, electrically isolated from them. The corresponding first edge contact 132 also includes three connection points consisting of one signal contact between the two ground contacts.

[0037] In an alternative embodiment, the corresponding first and second edge contacts 112, 132 are each embodied in a dielectric waveguide structure, such as an optical conduit similar to an optical fiber. In this case, the conductive trace 165 is replaced by an optical conduit (hereinafter optical conduit 165 in this context), allowing an externally provided RF modulated laser to propagate to the electronics within the IC chip 110 via the optical conduit connection of the first and second edge contacts 112, 132. An optical-to-RF converter within the IC chip 110 converts the optical signal to an RF signal, which is output to the antenna element 120 via another pair of edge contacts 112, 132. Thus, in this embodiment, the signal is input to the IC chip 110 as "RF over fiber," then converted to RF within the IC chip 110 and radiated via the antenna element 120 in the transmit direction. In the receive direction, the RF signal received by the antenna element 120 is routed to the IC chip 110 via the pair of edge contacts 112, 132. The IC chip 110 then converts the receive path RF signal into an optical signal that is routed to an external system for processing through the same or a different optical conduit 165. With this approach, a high bandwidth system can be achieved.

[0038] In the tapered slot design of the first edge contact 132 shown in FIG. 3, the first edge contact 132 is formed by first forming a notch in the top surface 135 of the substrate 130 in the desired shape for the edge contact, such as by laser drilling, photolithography, and etching. The notch is then metallized by electroplating to form conductive sidewalls and a conductive base, and the front of the notch is sliced ​​away to form a front opening. This results in the first edge contact 132 having a front surface 146 that is substantially flush with the side surface 144-2, a depth d1 (see FIG. 5), and a back surface 171. Alternatively, the notch can be completely filled with metal and later laser drilled to form a conductive structure having the desired shape. Further discussion of forming the first edge contact 132 is provided below in connection with FIG. 6. Regarding the second edge contacts 112, they may be formed using a variety of techniques. For example, the edge contacts 112 may be quilted package nodules.

[0039] Other shapes and types of structures for the first and second edge contacts 132, 112 are also contemplated. For example, the recess / protrusion shape may be rectangular, circular, oval, triangular, and / or some other shape instead of the flared shape described above. Instead of a single converging slot 149, the edge contact 132 may have an interdigitating structure with several metal “fingers” or ridges and channels. In this case, adjacent edge contacts 112 may also have interdigitating structures with complementary interlocking fingers or channels and ridges. In another example, the interlocking structures on one or more sidewalls 144 of the cavity 140 and one or more side surfaces 117 of the chip 110 may be formed mostly or entirely from a dielectric or semiconductor material. In this case, the edge contacts 132, 112 may be smaller than the interlocking structures, may be located on the surface of the interlocking structures themselves, on other portions of the sidewalls 144 / side surfaces 117, or they may form other complete interlocking structures. The smaller edge contacts, if present, may have flat edges adjacent to each other or may have small, complementary shapes. In yet another example, instead of forming the second contact 132 as a recess, the second edge contact 112 may be formed as a recess and the second contact 132 as a protrusion. Alternatively, each of the edge contacts 112, 132 may be a flat or angled protrusion, for example, that abuts the adjacent edge contact 132, 112, respectively. In general, the edge contacts 112, 132 can be used to transfer energy from DC to mm-wave frequencies and are particularly useful for forming low-loss connections at mm-wave frequencies. The electrical connection between adjacent edge contacts 112, 132 is made without the use of bond wires or ribbon bonds, thereby eliminating the inductance added by those techniques. This results in a very low-loss connection at frequencies up to at least 200 GHz. Furthermore, the entire configuration including the IC chip 110 with the cavity 140, the first edge contact 132, and the second edge contact 112 forms a compact and thin structure in which the top surface 115 of the chip 110 is substantially coplanar with the top surface of the substrate 130.The electrical and mechanical connection of IC chip 110 to substrate 130 is simplified because IC chip 110 may simply be snapped into cavity 140 via interlocking edge contacts 112, 132, completing both the mechanical and electrical connections.

[0040] The substrate 130 may be a multilayer substrate with circuits arranged on different layers. The substrate 130 may be composed of any suitable dielectric material. In some embodiments, the substrate 130 is a rigid substrate, such as quartz, alumina, glass, or fused silica, suitable for thin film plating and forming fine features. As seen in FIG. 5 , for example, the substrate 130 may be composed of a lower layer (interchangeably, “lower substrate”) 130a and an upper layer (“upper substrate”) 130b, with a ground plane 170 sandwiched between them. The substrate 130 may be formed by first providing the lower layer 130a, metalizing the top surface of the lower layer 130a to form the ground plane 170, and then forming or bonding the upper layer 130b onto the ground plane 170 using a suitable method. Some exemplary methods for such bonding include dbi bonding, frit bonding, gold bump bonding, solder bump bonding, and copper pillar bonding. Alternatively, the upper layer 130b may be provided separately and adhered to the ground plane 170 using a suitable adhesive. Ground plane 170 may have circular openings 182 to accommodate vias 122-1 and 122-2. Openings 182 are large enough in diameter to allow vias 122-1, 122-2 to pass through ground plane 170 without contacting it, thereby allowing vias 122-1, 122-2 to function as probe feeds for antenna elements 120-1, 120-2. Ground plane 170 may function as a microstrip ground plane to reflect RF energy transmitted / received by antenna elements 120. The microstrip ground plane may also form the ground plane for microstrip transmission lines in which conductive traces 165 are conductors.

[0041] The IC chip 110 may have a thickness approximately equal to a depth d2 from the top surface 135 of the substrate 130 to the top surface of the ground plane 170 at the base of the cavity 140. With such dimensions, the bottom surface 119 of the IC chip 110 may rest on the ground plane 170, and the top surface 115 of the IC chip 110 may be approximately flush with the top surface 135 of the substrate 130. Alternatively, the thickness of the IC chip 110 may be less than the depth d2, and a gap may exist between the ground plane 170 and the bottom surface 119. Such a gap may be an air gap or a gap filled with a layer of insulating material. In some designs, it may be desirable for the IC chip 110 to have one or more electrical contacts on the bottom surface 119 of the IC chip 110 to provide electrical connection to other components of the antenna apparatus 100. In this case, a corresponding opening may be formed in the ground plane 170 to facilitate electrical connection.

[0042] Conductive vias 122-1, 122-2 are examples of conductors and form the probe feeds of antenna elements 120-1, 120-2. As described further below, vias 122 may be formed by first forming pads on the outer surface of substrate 130, then drilling holes in substrate 130 and filling the holes with metal, such as by electroplating. A short conductive trace 168 on top surface 135 of substrate 130 may be an extension of such a via pad (or conductive trace 168 itself may be considered a via pad) and may interconnect via 122 with an adjacent first edge contact 132, for example, by an edge 171 overlapping first edge contact 132. Other conductive traces 165 connected to circuit components or terminals (not shown) other than antenna element 120 may also be formed on surface 135 overlapping edge 171 of first edge contact 132 for electrical connection to the connected second edge contact 112. Optional conductive traces 165 may make such electrical connections through other vias (not shown) through substrate 130 or through side ports. Optional conductive traces 165 may route RF signals, DC bias voltages, or time-varying control signals to and from IC chip 110 and other circuit components.

[0043] 6 is a flow diagram of an exemplary method 600 of forming the antenna device 100. Figures 7A-7I each show a cross-sectional view or a plan view illustrating a structure corresponding to each step of the method 600. It should be noted that the order of the various process steps described below for the method 600 may be changed as needed in other exemplary embodiments.

[0044] To form the multilayer substrate 130 of the antenna device 100, the lower substrate 130a and the upper substrate 130b can be processed separately and then bonded together. FIG. 7A is a top view of a portion of the lower substrate 130a during this process stage after pattern metallization of the top and bottom surfaces. FIG. 7B is a cross-sectional view of the lower substrate 130a of FIG. 7A along line 7B-7B, and FIG. 7C is a bottom view of the lower substrate 130a of FIG. 7A. Referring to FIGS. 6 and 7A-7C, the lower substrate 130a is provided (S602), and the top and bottom surfaces of the lower substrate 130a are masked and metallized in selective areas to form the antenna element 120 on the bottom surface and the ground plane 170 on the top surface. Prior to this metallization, areas for forming openings 182 in the ground plane 170 can be masked on the top surface, and areas outside the boundaries of the antenna element 120 can be masked on the bottom surface. The opening 182 has a first diameter to accommodate a second via hole having a smaller diameter that will be formed later. The larger diameter opening 182 prevents the subsequent via 122 (shown in FIGS. 1-5) that forms the probe feed to the antenna element 120 from electrically shorting to the ground plane 170.

[0045] An upper substrate having a top surface and a bottom surface is separately provided and processed (S604). This process may include cutting left and right notches in the upper surface, each having a first geometric shape, using laser drilling, mechanical drilling, photolithography or etching, or other suitable techniques. The notches are then metallized to form first edge contacts 132 (after which some of the metallization is sliced ​​away during a separate notch-cutting process). For example, FIG. 7D is a plan view of a portion of upper substrate 130b after notch 711 has been cut to a depth d1 (less than thickness d2 of upper substrate 130b) and metallized. FIG. 7E is a cross-sectional view of upper substrate 130b of FIG. 7D along line 7E-7E. In this example, notch 711 is in the form of a flare, although other structures, such as multiple fingers, for forming an interdigitated connection may also be used. As seen in enlargement A, metallization of any notch 711, such as by electroplating, can form sidewall metallization regions 717s, frontwall metallization regions 717f, rearwall metallization regions 717r, and base metallization regions 717b within the notch 711.

[0046] Next, a central cutout for the IC chip is formed through the top substrate (S604). For example, FIG. 7F is a plan view of substrate 130b after a rectangular cutout 740 has been created between left notch 711 and right notch 711. FIG. 7G is a cross-sectional view of top substrate 130b at this stage along line 7G-7G. Cutout 740 will later form the aforementioned cavity 140. As shown in close-up B, the front of notch 711 may be scraped away as cutout 740 is formed, thereby removing front metallization 717f of notch 711. This opens a slot in notch 711, thereby forming first edge contact 132, into which second edge contact 112 of IC chip 110 will later be inserted.

[0047] The area adjacent the notch 711 may be metallized (S608) with patterned metallization to form either adjacent upper via pads 168 or conductive traces 165 electrically connected to the metallization in the notch. Before or after such metallization, the upper substrate 130b is attached / bonded to the lower substrate 130a (S610) using a suitable bonding method or non-conductive adhesive to form the multi-layer substrate 130. Via holes are then drilled (S612) between each via pad 168 and the corresponding antenna element 120, and the via holes may be metallized to complete the probe feed.

[0048] For example, Figure 7H is a top view of a portion of a multilayer substrate in an exemplary configuration after step S612. Figure 7I is a cross-sectional view of Figure 7H along line 7I-7I. In this example, a pair of conductive traces 165 and a pair of via pads 168 are each formed on the top surface of the upper substrate 130b. The via pads 168 / conductive traces 165 can thereby overlap and electrically connect to the backwall metallization surface 717r of the adjacent first edge contact 132. Alternatively, if the notch 711 is formed first, the same laser drilling or etching process may be used to simultaneously form adjacent shallow channels for forming the via pads 168 / conductive traces 165. Then, once the notch 711 is metallized, the shallower channels are metallized during the same metallization process, thereby forming the via pads 168 / conductive traces 165 having upper surfaces flush with the upper surface of the backwall metallization 717r. In yet another alternative, the via pad 168 and conductive trace 165 are completed before forming the notch 711 and first edge contact 132 .

[0049] Once the via pads 168 are formed, via holes may be drilled through the multi-layer structure in step S612. Each via hole may be drilled in a vertical path through the via pad 168, the upper substrate 130b, the opening 182, the lower substrate 130a, and the antenna elements 120. The via holes may then be electroplated to complete the probe feed vias to the respective antenna elements 120. In this process, metallization may be formed in the via regions 731 of the antenna elements 120, and then a planarization process, such as chemical mechanical polishing (CMP), planarizes the undersides of the antenna elements 120 and the via regions 731, resulting in a flat, continuous lower metal surface for the antenna elements 120.

[0050] With the multilayer substrate 130 thus formed, the IC chip 110 can be provided with second edge contacts 112 (S614), each having a second geometric shape complementary to the first geometric shape of an adjacent first edge contact 132. The IC chip is snap-fit ​​into the cavity 140 as shown in FIG. 1, resulting in the structure shown in FIG. 7J, which shows the second edge contacts 112 in electrical contact with the metallized walls 717r, 717s, and 717b of the first edge contact 132.

[0051] As previously mentioned, the second edge contact 112 can snap-fit ​​into the first edge contact 132, thereby forming an interlocking relationship. The press-fit between the contacts 112, 132 is, in some cases, sufficient to form an electrical connection therebetween and completely form the antenna device 100. In other cases, the electrical connection between the first edge contact 112 and the second edge contact 132 is strengthened using solder or other conductive bonding material 190, as shown in FIG. 2, previously described.

[0052] Method 600 can be extended to a method of manufacturing an electronically steerable antenna array using the same procedures as above, but on an expanded scale, by (i) forming a plurality of cavities 140 in a substrate 130, each having at least one second edge contact 132, where the plurality of cavities 140 are spatially arranged along the top surface of the substrate 130; (ii) forming a plurality of antenna elements 120 or a plurality of sets of antenna elements 120 spatially arranged along the bottom surface of the cavities 130 (i.e., along the bottom surface of the lower substrate 130a); and (iii) snap-fitting each of a plurality of IC chips 110 into a respective cavity 140 such that the beam-forming components in each IC chip 110 are electrically connected to at least one antenna element 120 through at least one respective conductive via 122. In other words, the expanded method includes, for each of the cavities 140, forming a second edge contact 132 on the sidewall of the cavity 140, placing a respective one of the IC chips 110 in the cavity 140, electrically connecting the respective first edge contact 132 and second edge contact 112 (this can be done when the IC chip 110 is snap-fitted into the cavity 140), and electrically connecting the beam forming component of the IC chip 110 placed therein to at least one of the respective antenna elements 120 (this can also be done when the IC chip 110 is snap-fitted into the cavity 140).

[0053] FIG. 8A is a plan view of an electronic device 800 according to another embodiment. FIG. 8B is a cross-sectional view taken along line 8B-8B in FIG. 8A. In one implementation, the electronic device 800 is an antenna apparatus having at least one antenna element, e.g., antenna elements 820-1, 820-2, 820-3, and 820-4, electrically connected to the IC chip 110′. This example is primarily described below. In other embodiments discussed below, the electronic device 800 is a non-antenna implementation in which the antenna elements 820-1 to 820-4 are omitted. Hereinafter, when discussing an antenna implementation, the electronic device 800 will be referred to as the antenna apparatus 800.

[0054] Antenna apparatus 800 differs from antenna apparatus 100 described above primarily in that it utilizes a probe feed for connection to at least one component, e.g., an antenna element, via a connection at the bottom surface of IC chip 110′ rather than via edge contacts 112, 132. Substrate 130′ may be a multi-layer substrate with a lower substrate 130a′ bonded to an upper substrate 130b′ and may be substantially identical to substrate 130 except for the location of openings 840-1, 840-2, 840-3, 840-4 in embedded ground plane 870. For example, first through fourth antenna elements 820-1 through 820-4 may be disposed on bottom surface 139 of substrate 130′. IC chip 110′ can include at least one bottom contact, e.g., first through fourth bottom contacts 830-1, 830-2, 830-3, and 830-4, centrally located within respective openings 840-1 through 840-4 in ground plane 870. Bottom contacts 830-1 through 830-4 can each include a connection element, such as a solder bump or copper pillar, on an outer surface thereof for electrical connection to vias 822-1, 822-2, 822-3, and 822-4, respectively. Alternatively, the connection element (e.g., solder bump / copper pillar) is initially formed at the edge of via 822 (in which case each illustrated contact 830 is understood to include a bottom contact and a connection element of IC chip 110′). Vias 822-1 through 822-4 are probe feeds electrically connected between respective feed points of antenna elements 820-1 through 820-4 and electrical contacts 830-1 through 830-4, respectively. Electrical contacts 830 may each be connected to RF transmit and / or receive circuitry located within IC chip 110' for handling the transmission and reception of signals associated with antenna elements 820.

[0055] The antenna device 800 includes at least one first edge contact 132 formed on the sidewall 144 of the cavity 140 for connecting to a corresponding at least one second edge contact 112 on the IC chip 110′. Each conductive trace 165 is connected to an adjacent first edge contact 132 in the same manner as described above to complete an electrical connection between another component / terminal of the antenna device 800 and the RF circuitry within the IC chip 110′. In the illustrated example, four conductive traces 165 are provided for connection to the second edge contacts 112, respectively. Any conductive trace 165 may be connected to a component / terminal via a side contact on the substrate 130′ or through a via (not shown).

[0056] 8A and 8B, up to three bottom contacts 830 are connected to up to three antenna elements 820 through vias 822, while at least one other antenna element 820 is electrically connected to the IC chip 110' through a set of edge contacts 132, 112 and a via extending from the top surface of the substrate 130'. In any of these cases, the at least one other bottom contact 830 can be connected to a conductive trace 165 (not shown) embedded in the lower substrate 130a' for connection to another component for exchanging RF signals, control signals, or DC bias, or to a ground plane 870 for making a ground connection.

[0057] In one non-antenna implementation, at least one bottom contact 830 is connected to an interlayer via (e.g., a shortened version of via 822-1) that connects to a conductive trace 165 (both not shown) that extends into lower substrate layer 130a'. In yet another non-antenna implementation, ground plane 870 or a portion thereof is replaced by a metal layer configured as a thermal heat sink for cooling IC chip 110', while at least one bottom contact 830 is connected to an interlayer via that is similarly connected to a conductive trace 165.

[0058] 9 is a flow chart illustrating an exemplary method 900 for manufacturing electronic device 800. In method 900, lower substrate 130a' and upper substrate 130b' can be processed separately and then bonded together. IC chip 110' is then snap-fit ​​into central cavity 140, and electrical connections are made between respective contacts of IC chip 110' and contacts formed in substrates 130'.

[0059] Specifically, a lower substrate 130a' having a top and bottom surface is provided (S902). Areas of the top and bottom surfaces are masked for pattern metallization to form the antenna element 120 on the bottom surface and a ground plane 870 on the top surface with openings 840 and via pads (top of vias 830) within the openings. Via holes are then drilled through the via pads to the bottom surface at the feed points to the antenna elements (S903). The via holes are metallized to complete the probe feed. The upper substrate 130b' can then be processed in steps S904, S906, S908, and S908 in the same manner as steps S604, S606, S608, and S608, except that each edge contact 132 may connect to a conductive trace 165 instead of a via 168. To form an alternative configuration in which some edge contacts 132 are connected to adjacent vias 168, process steps S904-S908 may be the same as S604-S608.

[0060] The upper substrate 130b' is then attached / bonded to the lower substrate 130a' (S910) using a bonding method or non-conductive adhesive 789. As mentioned above, suitable bonding methods for this purpose include dbi bonding, frit bonding, gold bump bonding, solder bump bonding, and copper pillar bonding.

[0061] The IC chip 110' may include complementary (second) edge contacts 112 and bottom contacts 830-1 through 830-4 with solder bumps or copper pillars attached (S912). The IC chip 110' is snap-fit ​​into the cavity 140, and electrical connections are made between the corresponding first and second edge contacts 132, 112 in the manner described above. Electrical connections between the bottom electrical contacts 830 and the respective vias 822 may be made by heating and cooling the solder bumps / copper pillars attached to the electrical contacts 830. Note that the solder bumps / copper pillars may alternatively be attached to the edges of the vias 822 rather than the electrical contacts 830 after their formation, and then electrical connection of the vias 822 to the electrical contacts 830 may be made using the same heating and cooling techniques.

[0062] FIG. 10A is an exploded cross-sectional view of an electronic device 10 with an embedded IC chip according to another embodiment. FIG. 10B is a cross-sectional view of the electronic device 10 in an assembled state. Referring to FIGS. 10A and 10B, the electronic device 10 includes a multilayer substrate 30 having a dual cavity structure formed in its top surface 35, a first IC chip 60, and a second IC chip 50. The first and second IC chips 60, 50 are disposed within respective first and second cavity portions 80, 70 of the dual cavity structure. The first cavity portion 80 is directly below the second cavity portion 70 and has a perimeter that is smaller than the perimeter of the second cavity portion 70.

[0063] The first cavity portion 80 has at least one sidewall 81 on which one or more first edge contacts 132 are disposed, and each first edge contact 132 can be electrically connected to an adjacent second edge contact 112 disposed on the side surface 62 of the IC chip 60. Similarly, the second cavity portion 60 has at least one first edge contact 132' electrically connected to at least one second edge contact 112' on the side surface 52 of the IC chip 50. In the illustrated example, the cavity portion 80 includes at least one first edge contact 132 on each of the opposing sidewalls 81-1, 81-2, and the second cavity portion 70 includes at least one first edge contact 132' on each of the opposing sidewalls 71-1, 71-2 for connection to a corresponding second edge contact. The edge contacts 132, 132', 112, 112' may have the same or similar structure as those previously described and may be fabricated and electrically connected to one another in the same or similar manner as previously described.

[0064] Any edge contact 132 or 132' may be electrically connected to another component of electronic device 10 through vias and / or conductive traces in substrate 30. For example, IC chips 50 and 60 may be electrically connected to each other through one or more sets of edge contacts 112, 132, 132', and 112'. For example, as shown in Figures 10A and 10B, substrate 30 is composed of bottom layer 30a, middle layer 30b, and top layer 30c. Conductive traces 165 may be disposed between layers 30a and 30b and between layers 30b and 30c. In the example shown, the circuitry in the first IC chip 60 can be electrically connected to the circuitry in the second IC chip 50 via a path including the second edge contact 112, the first edge contact 132, the first conductive trace 165, the blind via 22 extending through the substrate layer 30c, the via pad / second conductive trace 168, the first edge contact 132', and the second edge contact 112'.

[0065] In one exemplary implementation, the first IC chip 60 includes an amplifier electrically connected to one or more antenna elements (not shown) disposed on the underside of the substrate layer 30a. In this case, the amplifier of the first IC chip 60 can be electrically connected to the beam forming network circuitry contained in the second IC chip 50 via the connection paths described above. Furthermore, several, tens, or even many IC chips 50 and 60 can be spatially arranged in a cavity across the substrate 30 to drive an antenna array, such as a phased array.

[0066] The first IC chip 60 may be composed of a different semiconductor material than the semiconductor material of the second IC chip 50. In one example, the first IC chip 60 is composed of InP and the second IC chip 50 is composed of SiGe.

[0067] The first IC chip 60 may have a top surface that is substantially flush with the top surface of the first cavity portion 80 when assembled within the first cavity portion 80. The second IC chip 50 may have a thickness dimension that is less than the depth of the second cavity portion 70, such that when assembled within the second cavity portion 70, its top surface may be substantially flush with the top surface 35 of the substrate 30, but its bottom surface may be separated from the top surface of the second cavity portion 70 by a gap 97. In one example, the gap 97 is an air gap. In another example, the gap 97 is an insulating underfill material that is formed on the first IC chip 60 after assembly within the first cavity portion 80; in the latter case, the second IC chip 50 may be positioned on top of the underfill material for assembly within the second cavity portion 50. For example, the underfill material may have openings that allow electrical connection between top contacts formed on the first IC chip 60 and bottom contacts formed on the second IC chip 50 .

[0068] A layer of material 87 may be disposed on the bottom surface of first cavity portion 80. In one example, layer 87 is part of a ground plane similar to ground plane 170 or 870 in the above-described embodiment. In this case, other ground plane portions (not shown) are disposed around layer 87 between layers 30a and 30b, and all of the ground plane portions together serve as a ground plane for antenna elements disposed on the bottom surface of substrate layer 30a. In non-antenna implementations, the collective ground plane may form the only ground plane for circuit paths between circuit components. Alternatively, layer 87 may be configured to function as a thermal heat sink.

[0069] In other examples, layer 87 is not a ground plane, but is patterned to form one or more conductive traces for connecting RF, DC, or control signals between circuitry within first IC 60 and other circuit elements within electronic device 10.

[0070] Electronic devices and antenna apparatus according to the presently disclosed technology, as described above, may exhibit certain advantages over conventional devices. For example, due to the compact configuration as described, embodiments may enable high-performance signal routing at very high frequencies, e.g., on the order of 200 GHz. Such high performance is due, at least in part, to the elimination or minimization of inductance from bond wires between the chip and conductive traces / vias on the substrate that might otherwise be used. Embodiments may support next-generation such ultra-high frequency phased arrays and other components. The compact, thin configuration can be achieved by having the outer surface of the IC chip be substantially coplanar with the outer substrate surface. Fabrication is simplified by simply snapping the IC chip into a cavity in the multilayer substrate, simultaneously completing both mechanical and electrical connections through the interlocking first and second edge contacts.

[0071] While the technology described herein has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit and scope of the claimed subject matter as defined by the following claims and their equivalents.

Claims

1. a substrate having a cavity on an outer surface thereof, the substrate having a sidewall defining a portion of the cavity, the first edge contact formed on the sidewall; an integrated circuit (IC) chip disposed within the cavity, the IC chip having a bottom surface facing a bottom surface of the cavity, a side surface facing the sidewall, a second edge contact formed on the side surface electrically connected to the first edge contact, and circuitry within the IC chip connected to connection elements on the bottom surface; a circuit element supported by the substrate and connected to the circuit via the connecting element; a ground plane at least partially disposed on the bottom surface of the cavity, extending continuously from a first side of the IC chip to an opposite second side of the IC chip, the ground plane having an opening therein in which the connection element is disposed; An electronic device comprising:

2. A substrate having a cavity on an outer surface thereof, the substrate having a sidewall defining a portion of the cavity, and a first edge contact formed on the sidewall; an integrated circuit (IC) chip disposed within the cavity, the IC chip having a bottom surface facing a bottom surface of the cavity, a side surface facing the sidewall, a second edge contact formed on the side surface electrically connected to the first edge contact, and circuitry within the IC chip connected to connection elements on the bottom surface; a circuit element connected to the circuit through the connection element, the circuit element being attached to a bottom surface of the substrate and connected to the connection element through a conductive via extending from the connection element to the bottom surface of the substrate; An electronic device comprising:

3. The electronic device of claim 1 , wherein the circuit elements are conductive traces within the substrate.

4. The electronic device of claim 1 , wherein the connection elements include solder bumps.

5. The electronic device of claim 1 , wherein the connecting element comprises a conductive pillar.

6. An electronic device as described in claim 1, wherein a further portion of the ground plane extends within the substrate and outside the boundary of the cavity.

7. 10. The electronic device of claim 1, wherein the circuitry within the IC chip is radio frequency (RF) circuitry that includes beamforming components for directing beams formed by an antenna array.

8. The electronic device of claim 1 further comprising a heat sink on the bottom surface of the IC chip.

9. The electronic device of claim 1 , wherein the first edge contact and the second edge contact are soldered together.

10. A substrate having a cavity on an outer surface thereof, the substrate having a sidewall defining a portion of the cavity, a first edge contact formed on the sidewall; an integrated circuit (IC) chip disposed within the cavity, the IC chip having a bottom surface facing a bottom surface of the cavity, a side surface facing the sidewall, a second edge contact formed on the side surface electrically connected to the first edge contact, and circuitry within the IC chip connected to connection elements on the bottom surface; a circuit element supported by the substrate and connected to the circuit via the connecting element; Equipped with The sidewall and the side surface have first and second interlocking shapes, respectively, having complementary shapes, and the first and second interlocking shapes are interlocked with each other.

11. 11. The electronic device of claim 10, wherein the first interlocking feature is a recess in or a protrusion from the sidewall, and the second interlocking feature is a complementary protrusion from or a complementary recess in the sidewall, respectively.

12. The electronic device of claim 10 , wherein the first edge contact and the second edge contact are disposed on respective surfaces of the first interlocking shape and the second interlocking shape.

13. the sidewall is a first sidewall, the cavity has a second sidewall opposite the first sidewall, and a third edge contact is formed on the second sidewall; 11. The electronic device of claim 10, wherein the side is a first side, and the IC chip has a second side opposite the first side and a fourth edge contact on the second side connected to the third edge contact.

14. a substrate having a cavity on an outer surface thereof and a dual cavity structure having a first cavity portion directly below a second cavity portion, the first cavity portion having a first perimeter that is smaller than a second perimeter of the second cavity portion; a first integrated circuit (IC) chip disposed within the first cavity portion, the first cavity portion having a first sidewall on which a first edge contact is formed, the first sidewall having a second edge contact connected to the first edge contact; a second IC chip disposed within the second cavity portion, the second cavity portion having a second sidewall on which a third edge contact is formed, the second IC chip having a fourth edge contact electrically connected to the third edge contact.

15. The electronic device of claim 14 , wherein the first IC chip and the second IC chip are electrically connected to each other.

16. 16. The electronic device of claim 15, wherein the first IC chip and the second IC chip are electrically connected to each other through a via in the substrate, the via connecting the first edge contact and the third edge contact.

17. 17. The electronic device of claim 16, further comprising a conductive trace disposed within the substrate and electrically connecting one end of the via and the third edge contact.

18. 15. The electronic device of claim 14, wherein the first IC chip includes a top contact and the second IC chip includes a bottom contact connected to the top contact of the first IC chip.

19. 15. The electronic device of claim 14, wherein a top surface of the first IC chip is separated from a bottom surface of the IC chip by an air gap or an underfill material.

20. 15. The electronic device of claim 14, further comprising a conductive layer facing a bottom surface of the first IC chip, the conductive layer being a ground plane or a layer forming a plurality of conductive traces for connecting RF, DC, or control signals between the first IC chip and other circuit elements within the electronic device.

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