Semiconductor Devices

Abstract

To provide a semiconductor device that makes it difficult to reproduce a semiconductor device by reverse engineering.SOLUTION: A semiconductor device includes: a plurality of first signal output circuits each having a first area of a second conductivity type that is formed on a surface of a substrate or a well of a first conductivity type and is connected with first wiring receiving input of a signal from a first logical circuit, and a second area of a second conductivity type that is formed in contact with the first area on the surface of the substrate or the well of a first conductivity type and is connected with second wiring outputting a first signal; and a plurality of second signal output circuits each having a third area of a second conductivity type that is formed on the surface of the substrate or the well of a first conductivity type in the same layout as that of the first area and is connected with third wiring receiving input of a signal from a second logical circuit, and a fourth area of a first conductivity type that is formed in contact with the third area on the surface of the substrate or the well of a first conductivity type in the same layout as that of the second area and is connected with fourth wiring outputting a second signal.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, and more particularly to a technique for protecting a semiconductor device from reverse engineering. [Background technology]

[0002] In recent years, there has been an increase in the illegal reverse engineering of semiconductor devices. Reverse engineering techniques include not only optical analysis of the surface of the chip on which the semiconductor device is mounted, but also a technique in which wiring layers are peeled off one by one, photographed, the resulting images are superimposed, and the wiring information is extracted using software tools to reconstruct the circuit diagram.

[0003] Various methods have been proposed to prevent reverse engineering (see, for example, Patent Documents 1 to 9). To prevent reverse engineering, methods have been proposed that change the characteristics and connection information of transistors by, for example, modifying the wiring layer or using a diffusion layer or bulk below the wiring layer, so that the function cannot be reproduced by simply reading the wiring layer. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent No. 9,437,555 [Patent Document 2] Japanese Patent Application Publication No. 6-163539 [Patent Document 3] Japanese Patent Application Publication No. 9-92727 [Patent Document 4] U.S. Patent No. 6,117,762 [Patent Document 5] U.S. Patent No. 6,979,606 [Patent Document 6] U.S. Patent No. 7,128,271 [Patent Document 7] U.S. Patent No. 9,337,156 [Patent Document 8] Special Publication No. 2004-518273 [Patent Document 9] Japanese Patent Application Laid-Open No. 2014-135386 Summary of the Invention [Problem to be solved by the invention]

[0005] In order to make it difficult to reproduce a semiconductor device by reverse engineering, a special process is generally required, which increases the process development time and costs. An object of the present invention is to provide a semiconductor device that makes it difficult to reproduce a semiconductor device by reverse engineering. [Means for solving the problem]

[0006] A semiconductor device according to the present invention includes a plurality of first signal output circuits and a plurality of second signal output circuits, each of the first signal output circuits having a first wiring formed above a substrate or well of a first conductivity type and receiving an input of a signal from a first logic circuit, a second wiring formed above the substrate or well of the first conductivity type and outputting a first signal, a first region of a second conductivity type formed on a surface of the substrate or well of the first conductivity type and connected to the first wiring, and a second region of the second conductivity type formed on the surface of the substrate or well of the first conductivity type in contact with the first region and connected to the second wiring, The second signal output circuit has a third wiring formed above the first conductivity type substrate or well and receiving a signal from a second logic circuit, a fourth wiring formed above the first conductivity type substrate or well and outputting a second signal, a third region of the second conductivity type formed on the surface of the first conductivity type substrate or well in the same layout as the first region and connected to the third wiring, and a fourth region of the first conductivity type formed on the surface of the first conductivity type substrate or well in the same layout as the second region and in contact with the third region and connected to the fourth wiring. 。 [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a semiconductor device that makes it difficult to reproduce the semiconductor device by reverse engineering. [Brief explanation of the drawings]

[0008] [Figure 1] 1A to 1C are diagrams illustrating an example of a semiconductor device according to a first embodiment. [Figure 2] 1A to 1C are diagrams illustrating an example of a semiconductor device according to a first embodiment. [Figure 3] 1A and 1B are diagrams illustrating a configuration of a semiconductor device according to a first embodiment. [Figure 4] 1A to 1C are diagrams illustrating an example of a semiconductor device according to a first embodiment. [Figure 5] 1A to 1C are diagrams illustrating an example of a semiconductor device according to a first embodiment. [Figure 6] 1A and 1B are diagrams illustrating a configuration of a semiconductor device according to a first embodiment. [Figure 7] 1A and 1B are diagrams illustrating an application example of a semiconductor device according to an embodiment of the present invention. [Figure 8] FIG. 2 is a schematic plan view showing a first application example of the semiconductor device according to the first embodiment. [Figure 9] FIG. 10 is a schematic plan view showing a second application example of the semiconductor device according to the first embodiment. [Figure 10] FIG. 10 is a schematic plan view showing a third application example of the semiconductor device according to the first embodiment. [Figure 11] FIG. 10 is a schematic plan view showing a fourth application example of the semiconductor device according to the first embodiment. [Figure 12] 10A and 10B are diagrams illustrating an example of a semiconductor device according to a second embodiment. [Figure 13] FIG. 10 is a schematic plan view showing a configuration of a semiconductor device according to a second embodiment. [Figure 14] FIG. 10 is a diagram illustrating another example of the semiconductor device according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0010] (First embodiment) A first embodiment of the present invention will be described. The semiconductor device in the first embodiment has a plurality of signal output circuits as shown in Figures 1, 2, 4, and 5. Figures 1, 2, 4, and 5 are diagrams showing examples of signal output circuits included in the semiconductor device in the first embodiment.

[0011] The signal output circuit shown in Fig. 1 will be described. Fig. 1(A) is a schematic cross-sectional view showing the configuration of a signal output circuit 102A as a first example. In Fig. 1(A), a logic circuit A101 receives a signal IN1 as input and outputs a signal OUT1. A logic circuit B103 receives a signal IN2 as input and outputs a signal OUT2. The signal output circuit 102A is connected between the logic circuit A101 and the logic circuit B103, receives a signal OUT1 output from the logic circuit A101 as input, and outputs a signal IN2 that is input to the logic circuit B103.

[0012] In the signal output circuit 102A, an N-well 112 having an N-type conductivity is formed on a substrate (P-type semiconductor substrate) 111. P+ regions 113 and 114A having a P-type conductivity and an N+ region 115 having an N-type conductivity are formed on the surface of the N-well 112. The P+ region 113 and the P+ region 114A are not separated but are formed in contact with each other (as a single region). The N+ region 115 is formed separately from the P+ regions 113 and 114A. Furthermore, a P+ region 116 having a P-type conductivity is formed on the surface of the substrate (P-type semiconductor substrate) 111. The P+ region 113 is connected to a signal line for a signal OUT1, and the P+ region 114A is connected to a signal line for a signal IN2. The N+ region 115 is connected to a signal line for supplying a power supply voltage VDD, and the P+ region 116 is connected to a signal line for supplying a reference voltage VSS.

[0013] In the example shown in FIG. 1A, the signal line for signal OUT1 output from logic circuit A101 and the signal line for signal IN2 input to logic circuit B103 are connected via P+ region 113 and P+ region 114A that are not separated (are in contact) in signal output circuit 102A. That is, as shown in FIG. 1B, logic circuit A101 and logic circuit B103 are connected via parasitic resistance R11 formed by P+ region 113 and P+ region 114A. Therefore, the signal output from logic circuit A101 is input to logic circuit B103 with its original logical value (logic level) via signal output circuit 102A. That is, signal output circuit 102A transmits and outputs signal OUT1 output from logic circuit A101 with its original logical value (logic level).

[0014] Next, the signal output circuit shown in Fig. 2 will be described. Fig. 2(A) is a schematic cross-sectional view showing the configuration of a signal output circuit 102B as a second example. In Fig. 2(A), the same components as those shown in Fig. 1(A) are given the same reference numerals, and duplicated explanations will be omitted. The signal output circuit 102B as the second example differs from the signal output circuit 102A as the first example in that an N+ region 114B is formed on the surface of the N well 112 instead of the P+ region 114A.

[0015] In the signal output circuit 102B, a P+ region 113 having a P-type conductivity, an N+ region 114B having an N-type conductivity, and an N+ region 115 having an N-type conductivity are formed on the surface of an N-well 112. The P+ region 113 and the N+ region 114B are formed in contact with each other (to form a PN junction). The N+ region 115 is formed separately from the P+ region 113 and the N+ region 114B. The N+ region 114B is connected to the signal line of the signal IN2.

[0016] In the example shown in FIG. 2A, the signal line for signal OUT1 output from logic circuit A101 and the signal line for signal IN2 input to logic circuit B103 are connected via P+ region 113 and N+ region 114B of signal output circuit 102B. Furthermore, N+ region 114B of signal output circuit 102B is connected via N-well 112 to N+ region 115, which is connected to a signal line supplying power supply voltage VDD. That is, as shown in FIG. 2B, logic circuit A101 and logic circuit B103 are connected via parasitic diode D11 formed by a PN junction between P+ region 113 and N+ region 114B. Furthermore, signal line IN2 is connected to the signal line supplying power supply voltage VDD via parasitic resistance R12 formed by N-well 112. Therefore, regardless of the logic value (logic level) of the signal output from logic circuit A101, a signal of power supply voltage VDD (high level) is input to logic circuit B103 as signal IN2. That is, the signal output circuit 102B outputs a signal of the power supply voltage VDD (high level) regardless of the signal OUT1 output from the logic circuit A101.

[0017] Here, as shown in FIGS. 3A and 3B, the signal output circuit 102A as the first example and the signal output circuit 102B as the second example differ only in the conductivity type of the diffusion region formed on the surface of the N-well 112, and have the same shape, including the connecting wiring and contacts. That is, the signal output circuit 102A and the signal output circuit 102B have the same layout. FIG. 3A is a schematic plan view showing the configuration of the signal output circuit 102A as the first example, and FIG. 3B is a schematic plan view showing the configuration of the signal output circuit 102B as the second example. FIGS. 3A and 3B show portions of the signal output circuits 102A and 102B.

[0018] As shown in FIG. 3A, in the signal output circuit 102A, a P+ region 113 and a P+ region 114A are formed on the surface of an N well 112 so as to be in contact with each other. The P+ region 113 is connected to the signal line for signal OUT1 via a contact 121, and the P+ region 114A is connected to the signal line for signal IN2 via a contact 122. As shown in FIG. 3B, in the signal output circuit 102B, the P+ region 113 and the N+ region 114B are formed on the surface of the N well 112 so as to be in contact with each other, in a layout similar to that of the P+ region 113 and the P+ region 114A of the signal output circuit 102A. The P+ region 113 is connected to the signal line for signal OUT1 via a contact 123, and the N+ region 114B is connected to the signal line for signal IN2 via a contact 124.

[0019] As described above, the signal output circuits 102A and 102B have the same layout and wiring shape. By switching the conductivity type of the diffusion region formed on the surface of the N-well 112, parasitic resistors and parasitic diodes can be realized with the same layout. The conductivity type of the diffusion region can be switched, for example, by changing the mask pattern used when doping impurities during fabrication. This allows the signal output circuits to be switched between outputting an input signal directly and outputting a fixed potential (power supply voltage VDD) so that they are indistinguishable from one another. This makes it possible to disguise the logical function of a series of circuits including the signal output circuit, making it difficult to reproduce a semiconductor device through reverse engineering.

[0020] Next, the signal output circuit shown in Fig. 4 will be described. Fig. 4(A) is a schematic cross-sectional view showing the configuration of a signal output circuit 202A as a third example. In Fig. 4(A), a logic circuit A201 receives a signal IN1 as input and outputs a signal OUT1. A logic circuit B203 receives a signal IN2 as input and outputs a signal OUT2. The signal output circuit 202A is connected between the logic circuit A201 and the logic circuit B203, receives the signal OUT1 output from the logic circuit A201 as input, and outputs the signal IN2 that is input to the logic circuit B203.

[0021] In the signal output circuit 202A, N+ regions 212 and 213A having N-type conductivity and P+ region 214 having P-type conductivity are formed on the surface of a substrate (P-type semiconductor substrate) 211. N+ region 212 and N+ region 213A are not separated but are formed in contact (as a single region). P+ region 214 is formed separately from N+ regions 212 and 213A. N+ region 212 is connected to the signal line of signal OUT1, and N+ region 213A is connected to the signal line of signal IN2. P+ region 214 is connected to a signal line that supplies a reference voltage VSS.

[0022] In the example shown in FIG. 4(A), the signal line of signal OUT1 output from logic circuit A201 and the signal line of signal IN2 input to logic circuit B203 are connected via non-isolated (contacting) N+ region 212 and N+ region 213A of signal output circuit 202A. That is, as shown in FIG. 4(B), logic circuit A201 and logic circuit B203 are connected via parasitic resistance R21 formed by N+ region 212 and N+ region 213A. Therefore, the signal output from logic circuit A201 is input to logic circuit B203 via signal output circuit 202A with its logic value (logic level) unchanged. That is, signal output circuit 202A transmits and outputs signal OUT1 output from logic circuit A201 with its logic value (logic level) unchanged.

[0023] Next, the signal output circuit shown in Fig. 5 will be described. Fig. 5(A) is a schematic cross-sectional view showing the configuration of a signal output circuit 202B as a fourth example. In Fig. 5(A), the same components as those shown in Fig. 4(A) are given the same reference numerals, and duplicated explanations will be omitted. The signal output circuit 202B as the fourth example differs from the signal output circuit 202A as the third example in that a P+ region 213B is formed on the surface of the substrate (P-type semiconductor substrate) 211 instead of the N+ region 213A.

[0024] In signal output circuit 202B, an N+ region 212 having an N-type conductivity, a P+ region 213B having a P-type conductivity, and a P+ region 214 having a P-type conductivity are formed on the surface of substrate (P-type semiconductor substrate) 211. N+ region 212 and P+ region 213B are formed in contact with each other (to form a PN junction). P+ region 214 is formed separately from N+ region 212 and P+ region 213B. P+ region 213B is connected to the signal line of signal IN2.

[0025] In the example shown in FIG. 5(A), the signal line for signal OUT1 output from logic circuit A201 and the signal line for signal IN2 input to logic circuit B203 are connected via N+ region 212 and P+ region 213B of signal output circuit 202B. Furthermore, P+ region 213B of signal output circuit 202B is connected via substrate (P-type semiconductor substrate) 211 to P+ region 214 connected to a signal line supplying reference voltage VSS. That is, as shown in FIG. 5(B), logic circuit A201 and logic circuit B203 are connected via parasitic diode D21 formed by a PN junction between N+ region 212 and P+ region 213B. Furthermore, signal line IN2 is connected to the signal line supplying reference voltage VSS via parasitic resistance R22 formed by P-type semiconductor substrate 211. Therefore, regardless of the logical value (logical level) of the signal output from the logic circuit A201, a signal of the reference voltage VSS (low level) is input as the signal IN2 to the logic circuit B203. In other words, the signal output circuit 202B outputs a signal of the reference voltage VSS (low level) regardless of the signal OUT1 output from the logic circuit A201.

[0026] Here, as shown in FIGS. 6A and 6B, the signal output circuit 202A as the third example and the signal output circuit 202B as the fourth example differ only in the conductivity type of the diffusion region formed on the surface of the substrate (P-type semiconductor substrate) 211, and have the same shape, including the connecting wiring and contacts. That is, the signal output circuit 202A and the signal output circuit 202B have the same layout. FIG. 6A is a schematic plan view showing the configuration of the signal output circuit 202A as the third example, and FIG. 6B is a schematic plan view showing the configuration of the signal output circuit 202B as the fourth example. FIGS. 6A and 6B show portions of the signal output circuits 202A and 202B.

[0027] As shown in FIG. 6A, in signal output circuit 202A, N+ region 212 and N+ region 213A are formed in contact with each other on the surface of substrate (P-type semiconductor substrate) 211. N+ region 212 is connected to the signal line of signal OUT1 via contact 221, and N+ region 213A is connected to the signal line of signal IN2 via contact 222. Also, as shown in FIG. 6B, in signal output circuit 202B, N+ region 212 and P+ region 213B are formed in contact with each other on the surface of substrate (P-type semiconductor substrate) 211 in a layout similar to that of N+ region 212 and N+ region 213A in signal output circuit 202A. N+ region 212 is connected to the signal line of signal OUT1 via contact 223, and P+ region 213B is connected to the signal line of signal IN2 via contact 224.

[0028] As described above, the signal output circuit 202A and the signal output circuit 202B have the same layout and wiring shape. By switching the conductivity type of the diffusion region formed on the surface of the substrate (P-type semiconductor substrate) 211, parasitic resistors and parasitic diodes can be realized with the same layout. The conductivity type of the diffusion region can be switched, for example, by changing the mask pattern used when doping impurities during fabrication. This makes it possible to disguise the logical function of a series of circuits including the signal output circuit by switching between a signal output circuit that outputs an input signal as is and a signal output circuit that outputs a fixed potential (reference voltage VSS) so that the circuits are indistinguishable from each other, thereby making it difficult to reproduce the semiconductor device through reverse engineering.

[0029] Furthermore, by making the layout and wiring shape of the signal output circuits 102A, 102B, 202A, and 202B the same and switching the conductivity type of the diffusion regions, the signal output circuits may be switched to output the input signal as is, output a fixed potential of the power supply voltage VDD, or output a fixed potential of the reference voltage VSS, so that they are indistinguishable from each other in appearance.

[0030] FIG. 7 is a diagram showing an application example of a semiconductor device according to this embodiment. In FIG. 7, 301, 303, 311, 313, 321, and 323 are logic circuits that realize predetermined logic functions, and 302, 312, and 322 are signal output circuits according to this embodiment. As described above, the signal output circuits 302, 312, and 322 have the same layout and wiring, but can realize different functions by switching the conductivity type of the diffusion region. As shown in FIG. 7, by connecting the signal output circuit according to this embodiment between logic circuits and appropriately controlling the conductivity type of the diffusion region in the signal output circuit, it is possible to disguise the logic function of a series of circuits including the signal output circuit.

[0031] Specific application examples of the semiconductor device according to the first embodiment will be described with reference to Figures 8 to 11. Below, an example having a signal output circuit according to this embodiment and four inverters as a logic circuit will be described, but this is just one example, and the present invention is not limited to this example.

[0032] 8 is a schematic plan view showing a first application example. Each of four inverters (INV) 401, 402, 403, and 404 has a P+ region 413 serving as a source of a P-channel field-effect transistor and a P+ region 414 serving as a drain formed on the surface of an N-well 411 having N-type conductivity formed in a substrate. The P+ region 413 and the P+ region 414 are isolated from each other. Each of inverters (INV) 401, 402, 403, and 404 has a P-well 412 having P-type conductivity formed in the substrate, and an N+ region 415 serving as a source of an N-channel field-effect transistor and an N+ region 416 serving as a drain formed on the surface of the P-well 412. The N+ region 415 and the N+ region 416 are isolated from each other. A gate electrode 417 is formed on a region between the P+ region 413 and the P+ region 414 and on a region between the N+ region 415 and the N+ region 416, with a gate insulating film (not shown) interposed therebetween. The gate electrode 417 is made of, for example, polysilicon.

[0033] A P+ region 413 serving as a source is connected to metal wiring 418 that supplies a power supply voltage VDD via contact 420, and an N+ region 415 serving as a source is connected to metal wiring 419 that supplies a reference voltage VSS via contact 421. A gate electrode 417 is connected to metal wiring 422 that serves as input wiring via contact 423. A P+ region 414 and an N+ region 416 that serve as drains are connected to metal wiring 424 that serves as output wiring via contacts 425 and 426.

[0034] In signal output circuit 405A, P+ region 431 and P+ region 432 are formed in contact (as one region) on the surface of N well 411 formed in the substrate. Also, in signal output circuit 405A, N+ region 433 and N+ region 434 are formed in contact (as one region) on the surface of P well 412 formed in the substrate.

[0035] An output wiring 424 of the first inverter (INV#1) 401 is connected to an N+ region 433 of the signal output circuit 405A via a via 441, a metal wiring 442, a via 443, a metal wiring 444, and a contact 445. An output wiring 424 of the second inverter (INV#2) 402 is connected to a P+ region 431 of the signal output circuit 405A via a contact 437. An input wiring 422 of the third inverter (INV#3) 403 is connected to a P+ region 432 of the signal output circuit 405A via a contact 438. An input wiring 422 of the fourth inverter (INV#4) 404 is connected to an N+ region 434 of the signal output circuit 405A via a contact 466, a metal wiring 447, a via 448, a metal wiring 449, and a via 450.

[0036] 8, the output wiring 424 of the first inverter (INV#1) 401 and the input wiring 422 of the fourth inverter (INV#4) 404 are connected via an N+ region 433 and an N+ region 434 of the signal output circuit 405A. Also, the output wiring 424 of the second inverter (INV#2) 402 and the input wiring 422 of the third inverter (INV#3) 403 are connected via a P+ region 431 and a P+ region 432 of the signal output circuit 405A. That is, as shown in the circuit configuration, the first inverter (INV#1) 401 and the fourth inverter (INV#4) 404 are connected via a parasitic resistance R41 formed by the N+ region 433 and the N+ region 434. The second inverter (INV#2) 402 and the third inverter (INV#3) 403 are connected via a parasitic resistance R42 formed by the P+ region 431 and the P+ region 432. Therefore, in the example shown in Figure 8, the fourth inverter (INV#4) 404 outputs a signal having the same logical value (logical level) as the signal input to the first inverter (INV#1) 401, and the third inverter (INV#3) 403 outputs a signal having the same logical value (logical level) as the signal input to the second inverter (INV#2) 402.

[0037] Fig. 9 is a schematic plan view showing a second application example. In Fig. 9, the same components as those shown in Fig. 8 are assigned the same reference numerals, and duplicated explanations will be omitted. The semiconductor device shown in Fig. 9 has the same layout as the semiconductor device shown in Fig. 8, including the shape of the wiring. The example shown in Fig. 9 differs from the example shown in Fig. 8 in that an N+ region 435 is formed on the surface of N well 411 instead of P+ region 432, and a P+ region 436 is formed on the surface of P well 412 instead of N+ region 434.

[0038] 9 is formed on the surface of an N well 411 formed in a substrate, with a P+ region 431 and an N+ region 435 in contact with each other (to form a PN junction). Also, on the surface of a P well 412 formed in the substrate, with an N+ region 433 and a P+ region 436 in contact with each other (to form a PN junction). An input wiring 422 of a third inverter (INV#3) 403 is connected to the N+ region 435 of the signal output circuit 405B via a contact 438, and an input wiring 422 of a fourth inverter (INV#4) 404 is connected to the P+ region 436 of the signal output circuit 405B via a contact 466, a metal wiring 447, a via 448, a metal wiring 449, and a via 450.

[0039] 9, the output wiring 424 of the first inverter (INV#1) 401 and the input wiring 422 of the fourth inverter (INV#4) 404 are connected via an N+ region 433 and a P+ region 436 of the signal output circuit 405B. Also, the output wiring 424 of the second inverter (INV#2) 402 and the input wiring 422 of the third inverter (INV#3) 403 are connected via a P+ region 431 and an N+ region 435 of the signal output circuit 405B. That is, as shown in the circuit configuration, the first inverter (INV#1) 401 and the fourth inverter (INV#4) 404 are connected via a parasitic diode D41 formed by a PN junction between the N+ region 433 and the P+ region 436. The second inverter (INV#2) 402 and the third inverter (INV#3) 403 are connected via a parasitic diode D42 formed by a PN junction between a P+ region 431 and an N+ region 435. Therefore, in the example shown in Figure 9, the fourth inverter (INV#4) 404 outputs a high-level signal (power supply voltage VDD) regardless of the signal input to the first inverter (INV#1) 401, and the third inverter (INV#3) 403 outputs a low-level signal (reference voltage VSS) regardless of the signal input to the second inverter (INV#2) 402.

[0040] FIG. 10 is a schematic plan view showing a third application example. In FIG. 10, the same components as those shown in FIG. 8 are denoted by the same reference numerals, and redundant explanations will be omitted. The semiconductor device shown in FIG. 10 has the same layout as the semiconductor devices shown in FIGS. 8 and 9, including the shape of the wiring. The example shown in FIG. 10 differs from the example shown in FIG. 8 in that an N+ region 435 is formed on the surface of an N well 411 instead of a P+ region 432. That is, in the signal output circuit 405C shown in FIG. 10, the P+ region 431 and the N+ region 435 are formed in contact with each other (to form a PN junction) on the surface of an N well 411 formed on a substrate. An input wiring 422 of a third inverter (INV#3) 403 is connected to the N+ region 435 of the signal output circuit 405C via a contact 438.

[0041] 10, the output wiring 424 of the first inverter (INV#1) 401 and the input wiring 422 of the fourth inverter (INV#4) 404 are connected via an N+ region 433 and an N+ region 434 of the signal output circuit 405C. Also, the output wiring 424 of the second inverter (INV#2) 402 and the input wiring 422 of the third inverter (INV#3) 403 are connected via a P+ region 431 and an N+ region 435 of the signal output circuit 405C. That is, as shown in the circuit configuration, the first inverter (INV#1) 401 and the fourth inverter (INV#4) 404 are connected via a parasitic resistance R41 formed by the N+ region 433 and the N+ region 434. The second inverter (INV#2) 402 and the third inverter (INV#3) 403 are connected via a parasitic diode D42 formed by a PN junction between the P+ region 431 and the N+ region 435. Therefore, in the example shown in Figure 10, the fourth inverter (INV#4) 404 outputs a signal of the same logical value (logical level) as the signal input to the first inverter (INV#1) 401, and the third inverter (INV#3) 403 outputs a signal of low level (reference voltage VSS) regardless of the signal input to the second inverter (INV#2) 402.

[0042] FIG. 11 is a schematic plan view illustrating a fourth application example. In FIG. 11, components identical to those shown in FIG. 8 are denoted by the same reference numerals, and redundant description will be omitted. The semiconductor device shown in FIG. 11 has the same layout, including the wiring shape, as the semiconductor devices shown in FIGS. 8, 9, and 10. The example shown in FIG. 11 differs from the example shown in FIG. 8 in that a P+ region 436 is formed on the surface of a P-well 412 instead of an N+ region 434. That is, in the signal output circuit 405D shown in FIG. 11, an N+ region 433 and a P+ region 436 are formed on the surface of a P-well 412 formed on a substrate, with the N+ region 433 and the P+ region 436 in contact with each other (to form a PN junction). The input wiring 422 of the fourth inverter (INV#4) 404 is connected to the P+ region 436 of the signal output circuit 405D via a contact 466, a metal wiring 447, a via 448, a metal wiring 449, and a via 450.

[0043] 11, the output wiring 424 of the first inverter (INV#1) 401 and the input wiring 422 of the fourth inverter (INV#4) 404 are connected via an N+ region 433 and a P+ region 436 of the signal output circuit 405D. Also, the output wiring 424 of the second inverter (INV#2) 402 and the input wiring 422 of the third inverter (INV#3) 403 are connected via a P+ region 431 and a P+ region 432 of the signal output circuit 405D. That is, as shown in the circuit configuration, the first inverter (INV#1) 401 and the fourth inverter (INV#4) 404 are connected via a parasitic diode D41 formed by a PN junction between the N+ region 433 and the P+ region 436. The second inverter (INV#2) 402 and the third inverter (INV#3) 403 are connected via a parasitic resistance R42 formed by the P+ region 431 and the P+ region 432. Therefore, in the example shown in Figure 11, the fourth inverter (INV#4) 404 outputs a signal of high level (power supply voltage VDD) regardless of the signal input to the first inverter (INV#1) 401, and the third inverter (INV#3) 403 outputs a signal of the same logical value (logical level) as the signal input to the second inverter (INV#2) 402.

[0044] As shown in the examples of Figures 8 to 11, by switching the conductivity type of the diffusion region of the signal output circuit provided between logic circuits with the same layout and wiring shape, it is possible to disguise the logic function of the circuit, making it difficult to reproduce the semiconductor device by reverse engineering.

[0045] (Second embodiment) Next, a second embodiment of the present invention will be described. The semiconductor device in the second embodiment has a plurality of signal output circuits as shown in Figures 12(A) and 12(B). Figures 12(A) and 12(B) are diagrams showing examples of signal output circuits included in the semiconductor device in the second embodiment.

[0046] 12A includes P-channel field-effect transistors (hereinafter also referred to as "P-channel transistors") MP1 and MP2 and N-channel field-effect transistors (hereinafter also referred to as "N-channel transistors") MN1 and MN2. Between a signal line supplying a power supply voltage VDD and a signal line supplying a reference voltage VSS, the P-channel transistor MP1 and the N-channel transistor MN1 are connected in series in this order from the signal line supplying the power supply voltage VDD. Furthermore, between the signal line supplying the power supply voltage VDD and the signal line supplying the reference voltage VSS, the P-channel transistor MP2 and the N-channel transistor MN2 are connected in series in this order from the signal line supplying the power supply voltage VDD.

[0047] The gates of P-channel transistor MP1 and N-channel transistor MN1 are connected to a connection point ND2 between P-channel transistor MP2 and N-channel transistor MN2, and the gates of P-channel transistor MP2 and N-channel transistor MN2 are connected to a connection point ND1 between P-channel transistor MP1 and N-channel transistor MN1. The voltage at the connection point ND2 between P-channel transistor MP2 and N-channel transistor MN2 is output as an output signal SOUT.

[0048] Specifically, the source of the P-channel transistor MP1 is connected to a signal line that supplies a power supply voltage VDD, the gate is connected to the junction between the drain of the P-channel transistor MP2 and the drain of the N-channel transistor MN2, and the drain is connected to the drain of the N-channel transistor MN1. The source of the N-channel transistor MN1 is connected to a signal line that supplies a reference voltage VSS, and the gate is connected to the junction between the drain of the P-channel transistor MP2 and the drain of the N-channel transistor MN2. The source of the P-channel transistor MP2 is connected to a signal line that supplies a power supply voltage VDD, the gate is connected to the junction between the drain of the P-channel transistor MP1 and the drain of the N-channel transistor MN1, and the drain is connected to the drain of the N-channel transistor MN2. The source of the N-channel transistor MN2 is connected to a signal line that supplies the reference voltage VSS, and the gate is connected to the junction between the drain of the P-channel transistor MP1 and the drain of the N-channel transistor MN1. The voltage at the junction between the drain of the P-channel transistor MP1 and the drain of the N-channel transistor MN1 is output as a signal SOUT.

[0049] Here, the threshold voltages of the P-channel transistors MP1, MP2, and the N-channel transistor MN1 are general (standard) threshold voltages, and the threshold voltage of the N-channel transistor MN2 is higher than the general (standard) threshold voltage. The threshold voltages of the transistors can be controlled by channel implant doping control, which changes the amount of doping in the channel. By using a transistor with a high threshold voltage as the N-channel transistor MN2, after power-on, the voltage of the connection point ND1 between the P-channel transistor MP1 and the N-channel transistor MN1 is fixed to a low level (L), and the voltage of the connection point ND2 between the P-channel transistor MP2 and the N-channel transistor MN2 is fixed to a high level (H), and the first signal output circuit 500A outputs a fixed high level (H) signal as the output signal SOUT.

[0050] The second signal output circuit 500B shown in FIG. 12B has P-channel transistors MP1 and MP2 and N-channel transistors MN1 and MN2 connected in the same manner as the first signal output circuit 500A shown in FIG. 12A. In the second signal output circuit, the threshold voltages of the P-channel transistors MP1 and MP2 and the N-channel transistor MN2 are general (standard) threshold voltages, and the threshold voltage of the N-channel transistor MN1 is higher than the general (standard) threshold voltage. By using a transistor with a high threshold voltage as the N-channel transistor MN1, after power-on, the voltage of the connection point ND1 between the P-channel transistor MP1 and the N-channel transistor MN1 is fixed to a high level (H), and the voltage of the connection point ND2 between the P-channel transistor MP2 and the N-channel transistor MN2 is fixed to a low level (L), and the second signal output circuit 500B outputs a fixed low-level (L) signal as the output signal SOUT.

[0051] 13(A) is a schematic plan view showing the configuration of a first signal output circuit 500A. In the first signal output circuit 500A, a P+ region 503 serving as the source of P-channel transistors MP1 and MP2 is formed on the surface of an N-well 501 having N-type conductivity formed on a substrate. A P+ region 504 serving as the drain of P-channel transistor MP1 and a P+ region 505 serving as the drain of P-channel transistor MP2 are formed on the surface of the N-well 501. The P+ region 503, P+ region 504, and P+ region 505 are isolated from each other.

[0052] Furthermore, an N+ region 506 serving as the source of N-channel transistors MN1 and MN2 is formed on the surface of a P-well 502 having P conductivity type formed in the substrate. An N+ region 507 serving as the drain of N-channel transistor MN1 and an N+ region 508 serving as the drain of N-channel transistor MN2 are formed on the surface of the P-well 502. N+ region 506, N+ region 507, and N+ region 508 are isolated from each other.

[0053] Gate electrodes 509 of P-channel transistor MP1 and N-channel transistor MN1 are formed, via gate insulating films (not shown), on the region between P+ region 503 and P+ region 504 and on the region between N+ region 506 and N+ region 507. Gate electrodes 510 of P-channel transistor MP2 and N-channel transistor MN2 are formed, via gate insulating films (not shown), on the region between P+ region 503 and P+ region 505 and on the region between N+ region 506 and N+ region 508. The gate electrodes 509, 510 are made of, for example, polysilicon.

[0054] A P+ region 503 serving as the source of P-channel transistors MP1 and MP2 is connected to metal wiring 511, which supplies a power supply voltage VDD, via contact 512. An N+ region 506 serving as the source of N-channel transistors MN1 and MN2 is connected to metal wiring 513, which supplies a reference voltage VSS, via contact 514. A metal wiring 515 is connected to a P+ region 504 serving as the drain of P-channel transistor MP1 and an N+ region 507 serving as the drain of N-channel transistor MN1 via contacts 516 and 517, respectively, and is also connected to gate electrodes 510 of P-channel transistor MP2 and N-channel transistor MN2 via contact 518. A metal wiring 519 is connected to a P+ region 505 serving as the drain of P-channel transistor MP2 and an N+ region 508 serving as the drain of N-channel transistor MN2 via contacts 520 and 521, respectively, and is also connected to gate electrodes 509 of P-channel transistor MP1 and N-channel transistor MN1 via contact 522. The metal wiring 519 also serves as a signal line for outputting the output signal OUT.

[0055] Here, the channel 531A between the N+ region 506 and the N+ region 508 of the N-channel transistor MN2 in the first signal output circuit 500A is doped with a controlled amount during the manufacturing of the transistor so as to increase the threshold voltage of the N-channel transistor MN2.

[0056] 13B is a schematic plan view showing the configuration of the second signal output circuit 500B. In FIG. 13B, the same components as those shown in FIG. 13A are denoted by the same reference numerals, and redundant explanations will be omitted. The second signal output circuit 500B has the same shape as the first signal output circuit 500A shown in FIG. 13A, including the layout of the transistors MP1, MP2, MN1, and MN2 and the associated wiring. However, in the second signal output circuit 500B, the doping amount of the channel 531B between the N+ region 506 and the N+ region 507 of the N-channel transistor MN1 in the second signal output circuit 500B is controlled during the fabrication of the transistor so as to increase the threshold voltage of the N-channel transistor MN1.

[0057] In this way, the signal output circuits 500A, 500B are configured so that the layout of the transistors MP1, MP2, MN1, and MN2, including the associated wiring, are the same, and by controlling the threshold voltages of the N-channel transistors MN1 and MN2, it is possible to switch between outputting a fixed high-level (H) signal or a fixed low-level (L) signal as the output signal SOUT. This makes it possible to appropriately set whether to output a high-level (H) signal or a low-level (L) signal so that they are indistinguishable from each other on the surface, making it difficult to reproduce the semiconductor device by reverse engineering.

[0058] In the above description, the threshold voltages of the N-channel transistors MN1 and MN2 are controlled, but the present invention is not limited to this example. For example, even if the threshold voltages of the transistors MP1, MP2, MN1, and MN2 are controlled as shown in Figure 14, it is possible to appropriately set whether to output a high-level (H) signal or a low-level (L) signal so that they are indistinguishable from each other on the outside, making it difficult to reproduce the semiconductor device through reverse engineering.

[0059] For example, the threshold voltages of the P-channel transistors MP1 and MP2 may be controlled as in the signal output circuit 500C shown in FIG. 14A and the signal output circuit 500D shown in FIG. 14B. As in the signal output circuit 500C shown in FIG. 14A, when the threshold voltages of the P-channel transistor MP2 and the N-channel transistors MN1 and MN2 are set to typical (standard) threshold voltages and the threshold voltage of the P-channel transistor MP1 is set to a value higher than the typical (standard) threshold voltage, a high-level (H) signal is output as the output signal SOUT. On the other hand, as in the signal output circuit 500D shown in FIG. 14B, when the threshold voltages of the P-channel transistor MP1 and the N-channel transistors MN1 and MN2 are set to typical (standard) threshold voltages and the threshold voltage of the P-channel transistor MP2 is set to a value higher than the typical (standard) threshold voltage, a low-level (L) signal is output as the output signal SOUT.

[0060] Furthermore, for example, the threshold voltages of the P-channel transistors MP1 and MP2 and the N-channel transistors MN1 and MN2 may be controlled as in the signal output circuit 500E shown in FIG. 14(C) and the signal output circuit 500F shown in FIG. 14(D). When the threshold voltages of the P-channel transistor MP2 and the N-channel transistor MN1 are set to typical (standard) threshold voltages and the threshold voltages of the P-channel transistor MP1 and the N-channel transistor MN2 are set to values ​​higher than the typical (standard) threshold voltages as in the signal output circuit 500E shown in FIG. 14(C), a high-level (H) signal is output as the output signal SOUT. When the threshold voltages of the P-channel transistor MP1 and the N-channel transistor MN2 are set to typical (standard) threshold voltages and the threshold voltages of the P-channel transistor MP2 and the N-channel transistor MN1 are set to values ​​higher than the typical (standard) threshold voltages as in the signal output circuit 500F shown in FIG. 14(D), a low-level (L) signal is output as the output signal SOUT.

[0061] It should be noted that the above-described embodiments are merely examples of specific embodiments of the present invention, and the technical scope of the present invention should not be construed as being limited by these embodiments. In other words, the present invention can be embodied in various forms without departing from its technical concept or main features. [Explanation of symbols]

[0062] 101, 103, 201, 203 logic circuits 102A, 102B, 202A, 202B signal output circuit 111, 211 board 112 N-well 113, 114A, 116, 213B, 214 P+ region 115, 212, 213A N+ area

Claims

1. a plurality of first signal output circuits and a plurality of second signal output circuits; The first signal output circuit includes: a first wiring formed above a substrate or well of a first conductivity type, to which a signal from a first logic circuit is input; a second wiring formed above the first conductivity type substrate or well and outputting a first signal; a first region of a second conductivity type formed on a surface of the substrate or well of the first conductivity type and connected to the first wiring; a second region of the second conductivity type formed on a surface of the substrate or well of the first conductivity type in contact with the first region and connected to the second wiring; The second signal output circuit includes: a third wiring formed above the first conductivity type substrate or well, to which a signal from a second logic circuit is input; a fourth wiring formed above the first conductivity type substrate or well and outputting a second signal; a third region of the second conductivity type formed on a surface of the substrate or well of the first conductivity type in the same layout as the first region and connected to the third wiring; a fourth region of the first conductivity type formed in contact with the third region on the surface of the substrate or well of the first conductivity type with the same layout as the second region, and connected to the fourth wiring.

2. 2. The semiconductor device according to claim 1, wherein the layout of the first wiring and the third wiring for each of the first region and the third region is the same, and the layout of the second wiring and the fourth wiring for each of the second region and the fourth region is the same.

3. 3. The semiconductor device according to claim 1, wherein the first signal output circuit and the second signal output circuit have the same layout.

4. the first conductivity type is an N-type conductivity type, and the second conductivity type is a P-type conductivity type; The semiconductor device according to any one of claims 1 to 3, characterized in that the first signal output circuit and the second signal output circuit are formed separately on the surface of the first conductivity type substrate or well, and each have a fifth region connected to a signal line that supplies a power supply voltage.

5. the first conductivity type is a P-type conductivity type, and the second conductivity type is an N-type conductivity type; The semiconductor device according to any one of claims 1 to 3, characterized in that the first signal output circuit and the second signal output circuit are formed separately on the surface of the first conductivity type substrate or well, and each have a fifth region connected to a signal line that supplies a reference voltage.

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