Vacuum packaging crossover

Abstract

In some embodiments, an electromechanical system is disclosed that includes a semiconductor layer having a planar surface and including a conductive region and an adjacent non-conductive region, and a hermetic seal disposed over the planar surface, as well as a method for manufacturing the system. In some embodiments, an electromechanical device is disclosed that includes first and second planar semiconductor layers. Each semiconductor layer includes a conductive region, and at least one conductive region in each layer is electrically coupled to each other. Methods for manufacturing the electromechanical device are also disclosed. TIFF2023515465000002.tif32170

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Application No. 62 / 980,096, filed February 21, 2020, and U.S. Provisional Application No. 63 / 002,229, filed March 30, 2020, the contents of each of which are incorporated herein by reference in their entirety.

[0002] FIELD OF THE INVENTION The present disclosure relates generally to electronic packaging, and more particularly to vacuum packaging over conductive crossovers. [Background technology]

[0003] Background of the Invention MEMS devices may operate in a vacuum, for example, a bolometer array, to ensure the device's longevity and accuracy.

[0004] Vacuum packaging techniques such as hermetic sealing generally require a flat surface topography in the sealing area. A hermetic seal is an air-tight seal that prevents gases or liquids from entering or leaving a volume. In general, flat interfaces are preferable to uneven interfaces (e.g., interfaces with protrusions) in hermetic sealing because uneven interfaces can result in a poor seal. In some cases, a poor seal can reduce the efficiency of the vacuum and reduce the performance and lifetime of the device (e.g., a bolometer).

[0005] In some applications, patterned conductive wiring may be required to cross the sealing area (e.g., crossovers). For example, patterned conductive wiring can create power and signal routing for a bolometer array located within a vacuum. Patterning the wiring may require the removal of conductive material between adjacent wiring, resulting in a non-planar surface. This non-planar topography is undesirable in hermetic sealing processes, for example, because depositing a seal ring on top of such a topography creates undesirable protrusions on the seal ring, degrading its sealing (e.g., bonding). To address seal degradation, additional material can be added between adjacent wiring, but this increases production costs. Furthermore, the added material does not create a planar topography, and additional processing steps (e.g., chemical mechanical planarization or chemical mechanical polishing (CMP)) are required to create a planar topography.

[0006] When bonding conductive layers of an integrated circuit, each of the bonded layers may require either additional metal or dielectric material. In some applications, each of the bonded layers requires a flat surface at the bonding interface to ensure good bonding. To create a flat surface in the metal or dielectric material, planarization techniques such as CMP are used. As mentioned above, planarization can become costly (and in some cases impossible) as the area of ​​the flat surface increases. Therefore, bonding techniques that do not require planarization may be desirable. Summary of the Invention

[0007] Examples of the present disclosure include methods for forming conductive crossovers in planar encapsulation areas, and devices made by these methods. Exemplary methods can eliminate material removal between adjacent traces in the crossover, thereby preserving a shape suitable for encapsulating the topography or reducing the need for additional material (and processing) to create a planar topography.

[0008] In some embodiments, a method of manufacturing an electromechanical system includes providing a semiconductor layer having a planar surface; creating conductive regions and adjacent non-conductive regions in the semiconductor layer by modifying a composition of the semiconductor layer, wherein the planar surface includes a surface of the conductive region and a surface of the non-conductive region; and applying a hermetic seal over the planar surface to create a hermetically sealed space, wherein one conductive region of the plurality of conductive regions includes a first portion and a second portion, and the first portion of the conductive region is below the hermetically sealed space and the second portion of the conductive region is not below the hermetically sealed space.

[0009] In some embodiments, creating conductive regions in the semiconductor layer includes doping regions of the semiconductor layer to create the conductive regions.

[0010] In some embodiments, doping the region of the semiconductor layer further comprises N-type doping the region.

[0011] In some embodiments, the method further comprises P-type doping regions of the semiconductor layer to create non-conductive regions.

[0012] In some embodiments, the hermetically sealed space is a vacuum.

[0013] In some embodiments, the conductive regions are created without altering the topography of the semiconductor layer.

[0014] In some embodiments, creating a conductive region in the semiconductor layer includes forming a silicide in a region of the semiconductor layer to create the conductive region.

[0015] In some embodiments, forming the silicide further comprises depositing a patterned metal on top of the semiconductor layer.

[0016] In some embodiments, the surface of the semiconductor layer spans dimensions greater than 620 mm x 750 mm.

[0017] In some embodiments, the non-conductive region of the semiconductor layer comprises an undoped semiconductor.

[0018] In some embodiments, the conductive regions are created without removing material from the semiconductor layer.

[0019] In some embodiments, the method further comprises electrically coupling the via to the conductive region.

[0020] In some embodiments, the method further comprises electrically coupling the conductive region to a bolometer circuit.

[0021] In some embodiments, providing a semiconductor layer having a flat surface comprises depositing the semiconductor layer on a glass substrate.

[0022] In some embodiments, the method further comprises providing an insulating layer over the semiconductor layer and below the hermetic seal.

[0023] In some embodiments, the method includes oxidizing the non-conductive region.

[0024] In some embodiments, the method further comprises dividing the semiconductor layer into a plurality of divided portions, and the step of applying a hermetic seal further comprises applying a hermetic seal to a top of the divided portions.

[0025] In some embodiments, an electromechanical system includes a semiconductor layer having a planar surface, the semiconductor layer including a conductive region and an adjacent non-conductive region, the conductive region including a modified material and the adjacent non-conductive region including the material; and a hermetic seal disposed over the planar surface, the hermetic seal creating a hermetic sealed space, wherein one conductive region of the plurality of conductive regions includes a first portion and a second portion, the first portion of the conductive region underlying the hermetic sealed space and the second portion of the conductive region not underlying the hermetic sealed space.

[0026] In some embodiments, the conductive region of the semiconductor layer is doped.

[0027] In some embodiments, the conductive region comprises an N-type dopant.

[0028] In some embodiments, the non-conductive region comprises a P-type dopant.

[0029] In some embodiments, the conductive regions are created without altering the topography of the semiconductor layer.

[0030] In some embodiments, the conductive region comprises a silicide.

[0031] In some embodiments, the silicide is formed by depositing a patterned metal on top of a semiconductor layer.

[0032] In some embodiments, the surface of the semiconductor layer spans dimensions greater than 620 mm x 750 mm.

[0033] In some embodiments, the non-conductive region of the semiconductor layer comprises an undoped semiconductor.

[0034] In some embodiments, the conductive regions are created without removing material from the semiconductor layer.

[0035] In some embodiments, the system further includes a via electrically coupled to the conductive region.

[0036] In some embodiments, at least one of the conductive regions is electrically coupled to a bolometer circuit.

[0037] In some embodiments, the system further includes a glass substrate on which the semiconductor layer is deposited.

[0038] In some embodiments, the system further includes an insulating layer above the semiconductor layer and below the hermetic seal.

[0039] In some embodiments, the non-conductive region is oxidized.

[0040] In some embodiments, the non-conductive regions are modified differently than the conductive regions.

[0041] Embodiments of the present disclosure include methods for bonding two planar semiconductor layers and devices made by these methods. Exemplary methods can eliminate a planarization step before bonding.

[0042] In some embodiments, a method of manufacturing an electromechanical system includes providing a first semiconductor layer having a first planar surface; creating conductive regions and adjacent non-conductive regions in the first semiconductor layer by modifying the composition of the first semiconductor layer; providing a second semiconductor layer having a second planar surface; creating conductive regions and adjacent non-conductive regions in the second semiconductor layer by modifying the composition of the second semiconductor layer; bonding the first semiconductor layer and the second semiconductor layer, wherein the second planar surface is parallel to the first planar surface; and electrically coupling the second semiconductor layer to the first semiconductor layer.

[0043] In some embodiments, creating conductive regions in the first and second semiconductor layers includes doping regions of the semiconductor layers to create the conductive regions.

[0044] In some embodiments, doping the region of the semiconductor layer further comprises N-type doping the region.

[0045] In some embodiments, the method further comprises P-type doping a region of the semiconductor layer to create a non-conductive region.

[0046] In some embodiments, the conductive regions are created without altering the topography of the semiconductor layer.

[0047] In some embodiments, creating a conductive region in the semiconductor layer includes forming a silicide in a region of the semiconductor layer to create the conductive region.

[0048] In some embodiments, the non-conductive region of the semiconductor layer comprises an undoped semiconductor.

[0049] In some embodiments, the conductive regions are created without removing material from the semiconductor layer.

[0050] In some embodiments, the method further comprises the step of surface treating the first and second flat surfaces.

[0051] In some embodiments, the method further comprises activating the surface-treated planar surface prior to bonding the first and second semiconductor layers together.

[0052] In some embodiments, electrically coupling the second semiconductor layer to the first semiconductor layer comprises electrically coupling a conductive region of the second semiconductor layer to a conductive region of the first semiconductor layer.

[0053] In some embodiments, the method further includes electrically coupling a second conductive region in the conductive region of the first semiconductor layer to a second conductive region in the conductive region of the second semiconductor layer, the second conductive region being electrically isolated from the first conductive region.

[0054] In some embodiments, the electrically coupled conductive regions form signal lines.

[0055] In some embodiments, the method further comprises oxidizing the non-conductive region.

[0056] In some embodiments, the method further comprises dividing the bonded semiconductor layer into a plurality of divided portions, each divided portion associated with one electromechanical system.

[0057] In some embodiments, the first and second planar surfaces have a root mean square roughness of less than 1 nm.

[0058] In some embodiments, an electromechanical system includes a first semiconductor layer having a first planar surface, the first semiconductor layer including a conductive region and an adjacent non-conductive region, the conductive region including a modified first material, and the adjacent non-conductive region including the first material; and a second planar semiconductor layer having a second planar surface, the second semiconductor layer including a conductive region and an adjacent non-conductive region, the conductive region including a modified second material, and the adjacent non-conductive region including the second material, wherein the first planar surface is parallel to the second planar surface, and the conductive region of the first semiconductor layer is electrically coupled to the conductive region of the second semiconductor layer.

[0059] In some embodiments, the conductive regions of the first and second semiconductor layers are doped.

[0060] In some embodiments, the conductive region comprises an N-type dopant.

[0061] In some embodiments, the non-conductive region comprises a P-type dopant.

[0062] In some embodiments, the conductive regions are created without altering the topography of the semiconductor layer.

[0063] In some embodiments, the conductive region comprises a silicide.

[0064] In some embodiments, the non-conductive region of the semiconductor layer comprises an undoped semiconductor.

[0065] In some embodiments, the conductive regions are created without removing material from the semiconductor layer.

[0066] In some embodiments, the first and second planar semiconductor layers are surface treated.

[0067] In some embodiments, the conductive region of the second semiconductor layer is electrically coupled to the conductive region of the first semiconductor layer.

[0068] In some embodiments, a second conductive region in the conductive region of the first semiconductor layer is electrically coupled to a second conductive region in the conductive region of the second semiconductor layer, and the second conductive region is electrically isolated from the first conductive region.

[0069] In some embodiments, the electrically coupled conductive regions are signal lines.

[0070] In some embodiments, the non-conductive region is oxidized.

[0071] In some embodiments, the first and second planar surfaces have a root mean square roughness of less than 1 nm.

[0072] Examples of the present disclosure include methods of bonding first and second portions of an electromechanical device. Exemplary methods can improve bond strength and / or uniformity compared to bonding without the disclosed features.

[0073] In some embodiments, a method of manufacturing an electromechanical device includes providing a first portion of the device having a bonding region; adding a feature to a surface of the first portion at the bonding region; depositing an interface layer on the feature; positioning a second portion of the device over the bonding region; and bonding the first and second portions of the device at the bonding region.

[0074] In some embodiments, the method includes depositing an insulating layer between the feature and the interface layer.

[0075] In some embodiments, the first portion comprises a non-silicon material.

[0076] In some aspects, the features comprise a conductive material. [The present invention 1001] providing a semiconductor layer having a planar surface; creating a conductive region and an adjacent non-conductive region in the semiconductor layer by modifying a composition of the semiconductor layer, wherein the planar surface includes a surface of the conductive region and a surface of the non-conductive region; and applying an airtight seal onto the flat surface to create an airtight sealed space; one of the conductive regions includes a first portion and a second portion; the first portion of the conductive region underlies the hermetically sealed space; the second portion of the conductive region is not below the hermetically sealed space; Process 1. A method for manufacturing an electromechanical system, comprising: [The present invention 1002] 1001. The method of claim 1001, wherein the step of creating a conductive region in the semiconductor layer comprises doping a region of the semiconductor layer to create a conductive region. [The present invention 1003] 10. The method of claim 10, wherein doping said region of said semiconductor layer further comprises N-type doping said region. [The present invention 1004] 1003. The method of claim 1002, further comprising P-type doping a region of said semiconductor layer to create said non-conductive region. [The present invention 1005] 1001. The method of claim 1001, wherein the hermetically sealed space is a vacuum. [The present invention 1006] 1001. The method of claim 1001, wherein said conductive regions are fabricated without modifying the topography of said semiconductor layer. [The present invention 1007] 1001. The method of claim 1001, wherein the step of creating a conductive region in the semiconductor layer comprises forming a silicide in a region of the semiconductor layer to create a conductive region. [The present invention 1008] 1007. The method of claim 10, wherein said forming a silicide further comprises depositing a patterned metal on top of said semiconductor layer. [The present invention 1009] 1001. The method of claim 1001, wherein the surface of said semiconductor layer spans dimensions greater than 620 mm x 750 mm. [The present invention 1010] 1001. The method of claim 1001, wherein said non-conductive region of said semiconductor layer comprises an undoped semiconductor. [The present invention 1011] 1001. The method of claim 1001, wherein said conductive regions are created without removing material from said semiconductor layer. [The present invention 1012] 1001. The method of claim 1001, further comprising the step of electrically coupling a via to said conductive region. [The present invention 1013] 1001. The method of claim 1001, further comprising the step of electrically coupling said conductive region to a bolometer circuit. [The present invention 1014] 1001. The method of claim 1001, wherein the step of providing a semiconductor layer having a flat surface comprises depositing the semiconductor layer on a glass substrate. [The present invention 1015] 1001. The method of claim 1001, further comprising the step of providing an insulating layer over said semiconductor layer and below said hermetic seal. [The present invention 1016] 1001. The method of claim 1001, further comprising the step of oxidizing said non-conductive region. [The present invention 1017] 1001. The method of claim 1001, further comprising the step of dividing said semiconductor layer into a plurality of divided portions, and wherein said step of applying a hermetic seal further comprises applying a hermetic seal to an upper portion of the divided portions. [The present invention 1018] 1. A method of manufacturing an electromechanical device, comprising: providing a first portion of a device having a bonding region; adding a feature to a surface of the first portion in the bonding area; depositing an interface layer over the feature; placing a second portion of the device over the bonding area; and bonding the first and second portions of the device at the bonding region. A method comprising: [The present invention 1019] The method of claim 1018, further comprising depositing an insulating layer between said feature and said interface layer. [The present invention 1020] a semiconductor layer having a planar surface, the semiconductor layer including a conductive region and an adjacent non-conductive region, the conductive region including the modified material and the adjacent non-conductive region including the material; a hermetic seal disposed on the flat surface, The hermetic seal creates a hermetically sealed space; one of the conductive regions includes a first portion and a second portion; a first portion of the conductive region below the hermetically sealed space; a second portion of the conductive region not under the hermetically sealed space; Airtight seal and Electromechanical systems, including: [Brief explanation of the drawings]

[0077] [Figure 1] 1A and 1B are a plan view and a cross-sectional view, respectively, of a conductive crossover in the encapsulation region of a device shown in FIG. 1A. [Figure 2A] FIG. 1B is a plan view of a conductive crossover in an encapsulation region of a device having a flat topography, according to an embodiment of the present disclosure. [Figure 2B] FIG. 2B is a cross-sectional view of a conductive crossover in the encapsulation region of the device shown in FIG. 2A. [Figure 2C] FIG. 1 illustrates one embodiment of a conductive crossover. [Figure 2D] FIG. 1 illustrates one embodiment of a conductive crossover. [Figure 3] 1A-1C illustrate a method of forming conductive crossovers in a sealed region having a flat topography according to an embodiment of the present disclosure. [Figure 4A] 1A-1C illustrate exemplary known joining methods. [Figure 4B] 1A-1C illustrate exemplary known joining methods. [Figure 4C] 1A-1C illustrate exemplary known joining methods. [Figure 4D] 1A-1C illustrate exemplary known joining methods. [Figure 5A] 1A-1C illustrate a method for bonding two planar semiconductor layers according to an embodiment of the present disclosure. [Figure 5B] 1A-1C illustrate a method for bonding two planar semiconductor layers according to an embodiment of the present disclosure. [Figure 5C] 1A-1C illustrate a method for bonding two planar semiconductor layers according to an embodiment of the present disclosure. [Figure 5D]1A-1C illustrate a method for bonding two planar semiconductor layers according to an embodiment of the present disclosure. [Figure 5E] 1A-1C illustrate a method for bonding two planar semiconductor layers according to an embodiment of the present disclosure. [Figure 5F] 1A-1C illustrate a method for bonding two planar semiconductor layers according to an embodiment of the present disclosure. [Figure 6] 1A-1C illustrate a method of fabricating an electromechanical device including two bonded planar semiconductor layers according to an embodiment of the present disclosure. [Figure 7A] 1A and 1B illustrate exemplary sealing structures for electromechanical devices. [Figure 7B] 1A to 1C illustrate a method for forming an encapsulation structure. [Figure 8] 1 illustrates a method of manufacturing an electromechanical system according to an embodiment. [Figure 9] FIG. 1 illustrates an exemplary sensor. DETAILED DESCRIPTION OF THE INVENTION

[0078] DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS In the following description of the aspects, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific aspects which may be practiced. It is to be understood that other aspects may be utilized and structural changes may be made without departing from the scope of the disclosed aspects.

[0079] Examples of the present disclosure include methods for forming conductive crossovers in planar encapsulation areas, and devices made by these methods. Exemplary methods can eliminate material removal between adjacent traces in the crossover, thereby preserving a shape suitable for encapsulating the topography or reducing the need for additional material (and processing) to create the planar topography.

[0080] 1A shows a plan view of a conductive crossover in the encapsulation region of a semiconductor device. The illustrated stack includes a conductive crossover 102, an insulating layer 104 (see FIG. 1B), and a seal metal ring 106. The stack is deposited on a substrate 110. For clarity and better illustration of the conductive crossover, some of the stack details (e.g., insulating layer 104) are not shown in FIG. 1A.

[0081] 1B shows a cross-sectional view of the stack in the sealing region, for example, in the area of ​​the device indicated by the dashed circle in FIG. 1A. The stack shown includes a conductive crossover 102, an insulating layer 104, and a seal metal ring 106. The seal metal ring 106 includes a protrusion 108.

[0082] In some cases, the conductive crossovers 102 are fabricated by depositing a metal layer on the substrate 110 before depositing the insulating layer 104 and before applying the seal metal ring 106. After the metal layer is deposited, the crossovers 102 are patterned by removing the conductive material between adjacent traces. After the conductive material is removed, the insulator 104 is deposited on the crossovers 102, and the seal metal ring 106 is deposited on the insulator 104. Depositing the seal ring on top of such a topography can result in protrusions 108 on the seal ring. In some cases, this step can result in poor sealing.

[0083] Alternatively, additional material can be added between adjacent interconnects to create a flat topography so that the protrusions 108 can be eliminated (e.g., so that the insulator and seal ring are flat). In these examples, adding additional material alone cannot create a flat topography. Creating a flat topography requires additional processing steps, such as chemical mechanical planarization or CMP. However, adding additional materials and processing steps can increase manufacturing costs.

[0084] FIG. 2A shows a plan view of conductive crossovers in a sealing region of an electromechanical device 200 having a flat topography, according to an embodiment of the present disclosure. The sealing region may be part of a device such as, for example, a thermal imaging device. In some embodiments, the device is a bolometer. In some embodiments, the device includes a glass substrate, and the illustrated stack is deposited on the glass substrate (e.g., an LCD glass substrate). For example, the device includes a bolometer array and peripheral circuitry. In some cases, the glass substrate is a Generation 3.5 glass substrate having dimensions of 620 mm x 750 mm.

[0085] In some embodiments, the packaging step is performed before the sensor is placed on the device (e.g., at the bolometer level). In some embodiments, the packaging step is performed after the sensor is placed on the device.

[0086] The illustrated stack includes a conductive crossover 202A, an insulating layer 204 (see FIG. 2B), and a seal metal ring 206. The stack is deposited on a substrate 210. In some embodiments, the seal interface region has a length 212, which is the length of the interface between the seal and the crossover region. For clarity and better illustration of the conductive crossover, some of the stack details (e.g., insulating layer 204) are not shown in FIG. 2A.

[0087] In some embodiments, the seal metal ring 206 surrounds the vacuum region 208. For example, the vacuum region is hermetically sealed, and the seal metal ring 206 functions as the hermetic seal. In some embodiments, the vacuum region 208 is a hermetic sealed space created by the hermetic seal over the crossover. In some embodiments, the non-vacuum region 228 is outside the vacuum region. For example, the non-vacuum region is not below the hermetic sealed space. That is, a first portion of the semiconductor layer (e.g., a first portion of the conductive region) may be inside the vacuum region, and a second portion of the semiconductor layer (e.g., a second portion of the conductive region) may be outside the hermetic sealed space. In some embodiments, the hermetic seal is a non-conductive seal.

[0088] FIG. 2B shows a cross-sectional view of a conductive crossover in a sealed region (e.g., the area indicated by the dashed circle in FIG. 2A) having a flat topography according to an embodiment of the present disclosure. In this embodiment, the sealed region is the interface between the vacuum region and the non-vacuum region. In some embodiments, the surface below the seal metal ring in the sealed region is flat. In some embodiments, the conductive crossover has a width 214 and a height 216.

[0089] In some embodiments, at least one of the conductive crossovers 202A includes a portion within a vacuum region and a portion within a non-vacuum region, and the conductive crossover is passed from the non-vacuum region to the vacuum region by traversing a sealed region.

[0090] The illustrated stack includes conductive crossovers 202A, non-conductive regions 202B, insulating layers 204, and sealing metal rings 206. In some embodiments, the layers are flat so that the foregoing steps do not substantially degrade the properties (e.g., hermeticity) of the device.

[0091] In some embodiments, conductive crossover 202A is in a conductive region of a semiconductor layer, and non-conductive region 202B is an adjacent non-conductive region of the semiconductor layer. In some embodiments, the conductive region comprises a modified material (e.g., a doped N-type semiconductor, a silicide), and the non-conductive region comprises the material (e.g., a doped P-type semiconductor, an undoped semiconductor). As used herein, if a region comprises a material and the region is modified by doping or silicide formation, the region still comprises the material.

[0092] In some embodiments, the semiconductor layer of the stack includes a planar surface 218, which includes the surfaces of the conductive crossover 202A and the non-conductive region 202B. In some embodiments, the conductive region includes a first portion (e.g., first portion 202B illustrated in FIG. 2A) that is below the hermetically sealed space (e.g., in the vacuum region 208) and a second portion (e.g., second portion 202C illustrated in FIG. 2B) that is not below the hermetically sealed space (e.g., in the non-vacuum region 228).

[0093] As an example, the length 212 of the seal interface region may be about 100 μm. If the conductive crossovers were straight and perpendicular to the seal interface, the conductive crossovers would have a length of about 100 μm. In some embodiments, the width 214 of each conductive crossover may be about 20 μm, and the conductive crossovers are spaced about 20 μm apart from one another. The semiconductor layer may have a height 216 of about 200 nm.

[0094] The conductive crossovers described and illustrated herein are not limiting unless otherwise specified, and it is understood that the conductive crossovers may have different spacing, dimensions, and properties than the described embodiments.

[0095] In some embodiments, the layer including conductive crossovers 202A and non-conductive regions 202B is a planar semiconductor layer. In some embodiments, conductive crossovers 202A are created by modifying the composition of a planar surface of a semiconductor layer to make it conductive. For example, the planar semiconductor layer before composition modification is an amorphous silicon layer. In some embodiments, the composition of the semiconductor layer below the planar surface is also modified to make it conductive. In some embodiments, modifying the composition of a layer (e.g., a semiconductor layer) does not involve removing material from the modified layer and then adding another material in its place. For example, the semiconductor layer is doped. As another example, a silicide is formed from the semiconductor layer.

[0096] In some embodiments, prior to singulation, the semiconductor layer used to fabricate the conductive crossovers spans dimensions greater than 620 mm × 750 mm. For example, prior to singulation, a semiconductor layer is deposited on a Generation 3.5 glass substrate having dimensions of 620 mm × 750 mm, and the semiconductor layer includes multiple semiconductor portions arranged in an array, each portion corresponding to a single device. The semiconductor layer may be continuous or discontinuous (e.g., the layer includes discontinuities or gaps between adjacent portions). In some cases, prior to singulation, the dimensions of the semiconductor layer may be too large for cost-effective planarization (e.g., chemical mechanical planarization, CMP). Therefore, embodiments described herein advantageously enable fabrication of a planar semiconductor layer including crossovers without planarization. In some embodiments, after formation of devices (e.g., bolometers) coupled to the semiconductor layer, the stack of glass substrate, semiconductor layer, and devices may be divided into smaller portions (e.g., wafer-sized portions) for hermetic sealing.

[0097] In some embodiments, planarization (e.g., chemical mechanical planarization) of the semiconductor layer is not necessary because the semiconductor layer is flat (e.g., no protrusions are created during the formation of the conductive crossovers). An exemplary advantage is that the complexity and cost of device fabrication can be reduced because a planarization step is no longer required. In some cases, creating conductive crossovers in the semiconductor layer (e.g., without depositing metal) can be sufficient to meet the electrical requirements of the device (e.g., delay, noise, voltage drop). Thus, in these instances, the device requirements can be met without the need for planarization, thereby reducing the cost and complexity of the device. In cases where planarization is not a viable alternative (e.g., at plate-level processing scales), embodiments disclosed herein can facilitate processing by eliminating the planarization step.

[0098] In some embodiments, the conductive crossovers 202A are created by doping specific regions of a planar semiconductor layer. For example, the specific regions are patterns of conductive crossovers. In some embodiments, the specific regions of the planar semiconductor layer are doped with N-type dopants.

[0099] In some embodiments, non-conductive region 202B has a lower conductivity compared to conductive crossover 202A. In some embodiments, non-conductive region 202B comprises undoped silicon, while conductive crossover 202A comprises a more conductive material (e.g., doped silicon, silicide). In some embodiments, non-conductive region 202B is doped with a P-type dopant. In some embodiments, non-conductive region 202B is oxidized. In some embodiments, the resistivity of the non-conductive region is about 10 12 Ω·cm.

[0100] For example, amorphous silicon can be doped by precursor vapor doping in a chemical vapor deposition (CVD) chamber or by implantation. The N-type dopant can be phosphorus or arsenic. In the vapor phase, phosphorus can correspond to phosphine (PH3), and arsenic can correspond to arsine (AsH3). The P-type dopant can be boron, which in the vapor phase can correspond to diborane (B2H6).

[0101] As an example, for microcrystalline silicon in the gas phase, a low resistivity of about 10 mΩ·cm can be achieved with a doping ratio (PH3 / SiH4) of about 0.1. -5 This can be achieved by lightly p-doping with a gas phase ratio (B2H6 / SiH4) of

[0102] In some aspects, the conductive crossovers include silicide, for example, the conductive crossovers are silicide feedthroughs in an amorphous silicon layer.

[0103] In some embodiments, the silicide is formed by depositing a patterned metal on an amorphous silicon layer. Non-limiting examples of silicide formation are described in International Publication No. 2019 / 178402, the entire contents of which are incorporated herein by reference for all purposes. The pattern corresponds to the location of the feedthrough or crossover. For example, a patterned metal is deposited on top of an amorphous silicon layer. The patterned metal and amorphous silicon can be reacted by annealing. Upon annealing, the patterned metal diffuses with the silicon to form a silicide. Silicide formation results in an overall volume reduction compared to the combined volume of the patterned metal and silicon before diffusion. Given the dimensions (e.g., width, height, thickness) and mass of the patterned metal and amorphous silicon, the dimensions of the formed silicide and conductive crossover can be derived based on the patterned metal, and a patterned metal with the appropriate dimensions and mass can be used to create a silicide crossover with the desired dimensions.

[0104] In some embodiments, the silicide forms laterally. An insulating layer underlies the amorphous silicon layer. In some embodiments, the insulating layer limits silicide formation in the lateral direction (i.e., parallel to the insulating layer). Given the dimensions and mass of the patterned metal, the lateral dimensions (e.g., width) of the silicide crossover can be derived when the insulating layer limits silicide formation in the lateral direction. Thus, using patterned metal with the appropriate dimensions and mass, silicide crossovers with desired widths can be fabricated.

[0105] 2C, patterned metal 222 is deposited on top of amorphous silicon layer 220. Silicide conductive crossovers 224 are formed using any of the described methods (e.g., using patterned metal having appropriate dimensions and mass to create the desired crossover dimensions). After the conductive crossovers are formed, a seal 226 can be deposited over the silicon layer and conductive crossovers using any of the described methods.

[0106] In some embodiments, the formation of the silicide may result in a thickness offset compared to adjacent amorphous silicon portions, but the offset may be small enough to allow bonding to occur without the need for planarization (e.g., the offset is significantly smaller than the step). In some embodiments, the offset has an RMS value of less than 40 nm, which is less than 15×10 between the environment around the seal and the space inside the seal. 3 Atm pressure differential may be sufficient to maintain. Thus, in some embodiments, depending on device requirements, it may be advantageous to form a silicide crossover to reduce resistivity. For example, NiSi has a resistivity of about 4 μΩ·cm. As another example, Ni2Si has a resistivity of about 24 μΩ·cm.

[0107] 2D shows one embodiment of a conductive crossover. In some embodiments, the silicide crossover can be formed without an offset. The silicide crossover can be formed by first creating a patterned first trench 230 on an insulating layer (e.g., a glass substrate). In some embodiments, the patterned trench is the space between the patterned insulators 232. In some embodiments, the patterned insulators are formed on the same insulating layer. In some embodiments, the patterned insulators are deposited on an insulating layer (e.g., insulating layer 220).

[0108] An amorphous silicon layer 234 is then deposited over the first trench and the patterned insulator. In some embodiments, the thickness of the amorphous silicon is substantially uniform and less than the height of the first trench (e.g., the amorphous silicon does not fill the first trench). Thus, the amorphous silicon layer includes a second trench 236 above the first trench. A patterned metal 238 can be deposited on top of the second trench 236, and silicide 240 can be formed using the methods described above. The insulating layer below the patterned insulator and amorphous silicon layer may confine the formed silicide within the first trench. In one embodiment, given the dimensions and mass of the patterned metal and amorphous silicon, the dimensions and mass can be controlled so that the height of the formed silicide is substantially the same as the height of the first trench, thereby creating a silicide crossover without offset. In some embodiments, a seal 242 may be applied over the silicide crossover, and the seal may be substantially similar to the seals described herein (eg, seal metal ring 206, seal 226).

[0109] Although specific dopants, silicides, and resistivities are described, it is understood that the planar semiconductor layer may have different properties than those described above. For example, depending on device requirements (e.g., timing requirements such as delay, power requirements such as IR drop), the conductive crossovers may be more or less conductive than those described for optimization purposes.

[0110] Although a particular method of silicide formation is described, it is understood that other methods of silicide formation can form conductive crossovers without departing from the scope of the present disclosure.

[0111] In some embodiments, once the crossovers are formed (e.g., once the conductive regions are defined) using the methods described above, each set of crossovers corresponding to a device can be divided, and insulating layers and sealing metal rings can be deposited over the crossovers to create the vacuum and non-vacuum regions of the devices described herein.

[0112] In some embodiments, at least one of the crossovers is electrically coupled to a via, e.g., a via allows the crossover to be electrically coupled to another electrical element (e.g., a routing, pin, or input on a different layer of the device).

[0113] In some embodiments, at least one of the crossovers is electrically coupled to the bolometer array. In some embodiments, the bolometer array is in a vacuum region. In some embodiments, at least one of the conductive crossovers is electrically coupled to a circuit associated with the bolometer array. In some embodiments, the circuit is a bolometer readout circuit in a non-vacuum region. In some embodiments, the circuit is a voltage drive circuit. In some embodiments, the crossover is a signal line that crosses the sealed region and transmits a signal between the vacuum region and the non-vacuum region.

[0114] 3 illustrates a method 300 for forming conductive crossovers in an encapsulation region having a flat topography, according to an embodiment of the present disclosure. Method 300 includes providing a semiconductor layer having a flat surface (step 302). For example, the semiconductor layer can be the semiconductor layer described with respect to FIGS. 2A-2D. In some embodiments, the semiconductor layer is an amorphous silicon layer.

[0115] Method 300 includes creating conductive regions (e.g., conductive crossovers) in the semiconductor layer by modifying the composition of the semiconductor layer to make it conductive (step 304). In some embodiments, creating conductive regions in the semiconductor layer further includes modifying the composition of regions of the semiconductor layer below a planar surface to make them conductive. For example, the conductive regions are created by increasing the conductivity of defined regions of the semiconductor layer, as described herein.

[0116] In some embodiments, the step of creating the conductive region does not include planarization of the semiconductor layer, for example, if metal deposition is not required to create the conductive region, then no step would be created and no planarization would be required, as described herein.

[0117] In some embodiments, the conductive regions are created without altering the topography of the semiconductor layer, hi some embodiments, the conductive regions are created without removing material from the semiconductor layer.

[0118] In some embodiments, creating a conductive region in the semiconductor layer comprises doping the conductive region. In some embodiments, doping the conductive region further comprises N-type doping the region (e.g., doping the conductive region with an N-type dopant). In some embodiments, the method further comprises doping the non-conductive region with a P-type dopant. In some embodiments, the non-conductive region in the semiconductor layer comprises an undoped semiconductor. In some embodiments, the method further comprises oxidizing the non-conductive region. For brevity, exemplary semiconductor materials, dopants, and doping methods are described above with respect to Figures 2A and 2B. For brevity, that description will not be repeated here.

[0119] In some embodiments, creating a conductive region in the semiconductor layer includes forming a silicide in the conductive region. For brevity, an exemplary method for forming a silicide in the conductive region is described above with respect to Figures 2C-2D. For brevity, that description will not be repeated here.

[0120] Method 300 includes a step of applying a seal (step 306). In some embodiments, the step of applying a seal includes applying a hermetic seal onto a flat surface to create a hermetically sealed space. For example, as described with respect to FIGS. 2A-2D, a vacuum region is created by bonding a seal metal ring to a device including a semiconductor layer. As another example, as described with respect to FIGS. 2A-2D, a vacuum region is created by bonding a non-conductive seal to a device including a semiconductor layer.

[0121] In some embodiments, one conductive region of the plurality of conductive regions includes a first portion and a second portion, wherein the first portion of the conductive region is within the hermetically sealed space (e.g., a vacuum region) and the second portion of the conductive region is not below the hermetically sealed space (e.g., a non-vacuum region). For example, as described with respect to Figures 2A-2D, at least one of the conductive crossovers includes a portion within a vacuum region and a portion within a non-vacuum region.

[0122] In some embodiments, the non-vacuum region surrounds the vacuum region and the interface between the vacuum region and the non-vacuum region is flat, for example, as described with respect to Figure 2A, the non-vacuum region surrounds the vacuum region and the sealing area is flat.

[0123] In some embodiments, the semiconductor layer spans dimensions greater than 620 mm x 750 mm. In some embodiments, the semiconductor layer includes multiple portions, each corresponding to a single device, and the semiconductor layer shown is one portion of the semiconductor layer.

[0124] In some embodiments, the method 300 includes electrically coupling the via to a conductive region. In some embodiments, the method 300 includes electrically coupling the conductive region to a bolometer circuit.

[0125] In some embodiments, method 300 includes providing an insulating layer over the semiconductor layer. For example, as described with respect to FIG. 2B , the insulating layer is insulating layer 204. As used herein, a second layer (e.g., insulating layer 204) is “over” a first layer (e.g., semiconductor layer 202) when the second layer is located in an opposite direction to the substrate (e.g., substrate 210) relative to the first layer.

[0126] In some embodiments, the method 300 includes depositing the semiconductor layer on a glass substrate. For example, as described with respect to Figures 2A-2D, the device 200 including the semiconductor layer can be deposited on a glass substrate.

[0127] Embodiments of the present disclosure include methods for bonding two planar semiconductor layers and devices fabricated by these methods. Exemplary methods according to embodiments of the present disclosure can eliminate a planarization step before bonding.

[0128] 4A-4D illustrate an exemplary known bonding method: Figure 4A shows a first layer 400 including a starting wafer 402, copper interconnects 404, a seed layer 406, and patterned metal 408.

[0129] 4B shows the first layer 400 after an oxide layer 410 has been deposited over the wafer and patterned metal. As shown, the oxide layer 410 fills the gaps between adjacent patterned metal 408 and includes steps from the patterned metal. The first layer 400 must be planarized to create a flat surface for bonding.

[0130] 4C shows the first layer 400 after planarization. For example, the first layer is planarized using CMP. After planarization, a portion of the oxide layer over the patterned metal is removed, exposing the patterned metal, and the remaining oxide layer and patterned metal are planar.

[0131] 4D shows the first layer 400 bonded to the second layer 412. The second layer 412 is substantially similar to the first layer 400. That is, the second layer 412 is fabricated by the method described with respect to FIGS. 4A-4C. Specifically, the interface between the first and second layers is planarized to ensure good bonding between the first and second layers.

[0132] 5A-5D illustrate a method for bonding two planar semiconductor layers according to an embodiment of the present disclosure.

[0133] 5A shows a first semiconductor layer 502 deposited on a substrate 500. In some embodiments, the first semiconductor layer 502 includes a flat surface. In some embodiments, the first semiconductor layer 502 is undoped amorphous silicon. It is understood that the illustrated configuration is merely exemplary. Additional layers, or different layer combinations, may be included with the semiconductor layer without departing from the scope of the present disclosure.

[0134] In some embodiments, the semiconductor layer has a flat surface, so planarization (e.g., CMP) of the semiconductor layer is not required (e.g., removal of an oxide layer is not required, as illustrated in FIG. 1C ). In some embodiments, when the semiconductor layer has a flat surface, the use of CMP can be reduced. As an exemplary advantage, if the planarization step is omitted from the manufacturing process, the complexity and cost of device manufacturing can be reduced. In some cases, creating conductive regions in the semiconductor layer (e.g., without depositing metal or oxide) can be sufficient to meet the electrical requirements (e.g., delay, noise, voltage drop) of an electrical device including the semiconductor layer. Thus, in these instances, the device requirements can be met without the need for planarization, thereby reducing the cost and complexity of the device.

[0135] 5B shows the first semiconductor layer 502 after a conductive region 504A has been created. In some embodiments, the layer includes a conductive region 504A and a non-conductive region 504B adjacent to the conductive region 504A.

[0136] In some embodiments, the conductive regions 504A are created by modifying the composition of a planar surface of the semiconductor layer to make it conductive. For example, the planar semiconductor layer before composition modification is an amorphous silicon layer. In some embodiments, the composition of the semiconductor layer below the planar surface is modified to make it conductive (e.g., the conductive regions are conductive volumes).

[0137] As an example, the width of each conductive region can be 0.1 to 5 μm, and the conductive regions may be spaced apart by 0.1 to 5 μm. The semiconductor layer may have a height of 10 to 500 nm. The conductive regions described and illustrated herein are not limiting unless otherwise specified. It is understood that the conductive regions may have different spacing, dimensions, and properties than those in the described embodiments.

[0138] In some embodiments, the conductive region 504A is created by doping specific areas of a planar semiconductor layer. For example, the specific areas are a pattern of conductive regions in bonded semiconductor layers, as described in more detail below. In some embodiments, the specific areas of the planar semiconductor layer are doped with an N-type dopant (e.g., carriers are electrons). In some embodiments, the conductive region 504A is doped with a P-type dopant (e.g., carriers are holes).

[0139] In some embodiments, non-conductive region 504B has a lower conductivity compared to conductive region 504A. In some embodiments, non-conductive region 504B comprises undoped silicon, while conductive region 504A comprises a more conductive material (e.g., doped silicon, silicide). In some embodiments, non-conductive region 504B is doped with a P-type dopant. In some embodiments, non-conductive region 504B is oxidized. As one example, the non-conductive region is oxidized to increase the resistivity of the region.

[0140] For example, amorphous silicon can be doped by precursor vapor doping in a CVD chamber or by implantation. The N-type dopant can be phosphorus or arsenic. In the vapor phase, phosphorus can correspond to phosphine (PH3), and arsenic can correspond to arsine (AsH3). The P-type dopant can be boron, which in the vapor phase can correspond to diborane (B2H6).

[0141] In some embodiments, the resistivity of the conductive region is about 10 12 As an example, for microcrystalline silicon, a lower resistivity approaching 10 mΩ·cm can be achieved with a gas phase doping ratio of 0.1 (PH3 / SiH4). The lower conductivity is approximately 10 -5 This can be achieved by lightly p-doping with a gas phase ratio (B2H6 / SiH4) of

[0142] In some embodiments, the conductive region comprises a silicide, for example, the conductive region is a conductive silicide channel in an amorphous silicon layer.

[0143] In some embodiments, the silicide is formed by depositing a patterned metal on an amorphous silicon layer. Non-limiting examples of silicide formation are described in International Publication No. 2019 / 178402, the entire contents of which are incorporated herein by reference for all purposes. The pattern corresponds to the location of the conductive region. For example, a patterned metal is deposited on top of an amorphous silicon layer. The patterned metal and amorphous silicon can be reacted by annealing. Upon annealing, the patterned metal diffuses with the silicon to form a silicide. Silicide formation results in an overall volume reduction compared to the combined volume of the patterned metal and silicon before diffusion. Given the dimensions (e.g., width, height, thickness) and mass of the patterned metal and amorphous silicon, the dimensions of the formed silicide and conductive region can be derived based on the patterned metal, and a patterned metal with the appropriate dimensions and mass can be used to create a silicide region with the desired dimensions.

[0144] In some embodiments, the silicide forms laterally. An insulating layer underlies the amorphous silicon layer. In some embodiments, the insulating layer limits silicide formation in the lateral direction (i.e., parallel to the insulating layer). Given the dimensions and mass of the patterned metal, the lateral dimensions (e.g., width) of the silicide conductive region can be derived when the insulating layer limits silicide formation in the lateral direction. Thus, using patterned metal with the appropriate dimensions and mass, a silicide conductive region with a desired width can be created.

[0145] 5C, patterned metal 522 is deposited on top of amorphous silicon layer 520. Using any of the methods described (e.g., using patterned metal having appropriate dimensions and mass to create the desired dimensions), silicide conductive regions 524 are formed. This semiconductor layer including silicide conductive regions 524 may be used as the first semiconductor layer 502.

[0146] In some embodiments, the formation of a silicide may result in a thickness offset compared to adjacent amorphous silicon portions, but the offset may be small enough to allow bonding to occur without the need for planarization (e.g., the offset is significantly smaller than a step). In some embodiments, the offset has an RMS value of less than 40 nm. Thus, in some embodiments, depending on the device requirements, it may be advantageous to form conductive regions with silicide to reduce resistivity. For example, the resistivity of NiSi is approximately 4 μΩ·cm. As another example, Ni2Si has a resistivity of approximately 24 μΩ·cm.

[0147] 5D shows one embodiment of a conductive region. In some embodiments, the silicide conductive region can be formed without an offset. The silicide conductive region can be formed by first creating a patterned first trench 530 on an insulating layer (e.g., a glass substrate). In some embodiments, the patterned trench is the space between patterned insulators 532. In some embodiments, the patterned insulators are formed on the same insulating layer. In some embodiments, the patterned insulator is deposited on an insulating layer (e.g., insulating layer 520).

[0148] An amorphous silicon layer 534 is then deposited over the first trench and the patterned insulator. In some embodiments, the thickness of the amorphous silicon is substantially uniform and less than the height of the first trench (e.g., the amorphous silicon does not fill the first trench). Thus, the amorphous silicon layer includes a second trench 536 above the first trench. A patterned metal 538 can be deposited on top of the second trench 536, and silicide 540 can be formed using the methods described above. The insulating layer below the patterned insulator and amorphous silicon layer may confine the formed silicide within the first trench. In one embodiment, given the dimensions and mass of the patterned metal and amorphous silicon, the dimensions and mass can be controlled so that the height of the formed silicide is substantially the same as the height of the first trench, thereby creating a silicide conductive region without offset. This semiconductor layer including the silicide conductive regions 524 may be used as the first semiconductor layer 502 .

[0149] Although specific dopants, silicides, and resistivities are described, it is understood that the planar semiconductor layer may have different properties than those described above. For example, depending on the device requirements (e.g., timing requirements such as delay, power requirements such as IR drop), the conductive regions may be more or less conductive than described.

[0150] Although a particular method of silicide formation is described, it is understood that other methods of silicide formation can form conductive regions without departing from the scope of the present disclosure.

[0151] FIG. 5E shows the first semiconductor layer 502 after surface treatment 506 has been applied. In some embodiments, after the conductive region 504A is formed, the top of the first semiconductor layer 502 is treated. For example, the surface may be prepared for bonding with a second semiconductor layer to enhance adhesion between the two layers. In some embodiments, the surface treatment is a cleaning process that removes contaminants (e.g., native oxides) from the surface. In some embodiments, the surface treatment is a cleaning process that uses irradiation or chemical processes to remove weakly bonded materials on the layer. In some embodiments, the surface treatment is an adhesion-promoting material that does not interfere with the conductivity of the semiconductor layer. In some embodiments, the surface treatment is a cleaning process that activates the surface before bonding while the semiconductor layer is in a vacuum. In some embodiments, the flat surface of the first semiconductor layer is treated with plasma. It is understood that the labels and illustrated areas associated with surface treatments in the figures are merely exemplary and that the labels and illustrated areas may not be representative of the physical characteristics of the surface treatment.

[0152] FIG. 5F shows the first semiconductor layer 502 bonded to the second semiconductor layer 508. In some embodiments, each surface-treated semiconductor layer is activated to initiate bonding between the two semiconductor layers. For example, surface activated bonding can be performed using argon plasma at low pressure (e.g., 0.1 mTorr to 1 Torr) and room temperature. As another example, surface activated bonding can be performed using ultra-low pressure (e.g., 10 -8 ~10 -5 This can be performed using fast atom bombardment of argon or neon at low pressures (e.g., 0.1 mTorr to 1 Torr) and room temperature. As another example, surface activated bonding can be performed by exposing the surfaces to acidic or basic reactants at low pressures (e.g., 0.1 mTorr to 1 Torr). Other examples of bonding methods include thermocompression bonding (high forces (e.g., 10-80 kN) at high temperatures (e.g., 100-300°C)).

[0153] In some embodiments, the second semiconductor layer 508 is bonded on top of the first semiconductor layer 502. In some embodiments, the bonded semiconductor layer is part of an electromechanical device. For example, the bonded conductive region is a signal line of the electromechanical device. In some embodiments, the bonded semiconductor layer is used in flip-chip bonding.

[0154] In some embodiments, the second semiconductor layer is substantially similar to the first semiconductor layer. For example, the second semiconductor layer 508 is fabricated using the methods described with respect to Figures 5A-5E. Specifically, the second semiconductor layer 508 is a planar semiconductor layer including conductive regions fabricated using methods according to embodiments of the present disclosure.

[0155] In some embodiments, the conductive region 504A of the first semiconductor layer 502 is electrically coupled to the conductive region 510A of the second semiconductor layer 508. For example, the conductive region 504A of the first semiconductor layer 502 and the conductive region 510A of the second semiconductor layer 508 overlap in area and are thereby electrically coupled together.

[0156] In some embodiments, two or more conductive regions 504A are electrically coupled to two or more conductive regions 510A. In some embodiments, each set of coupled conductive regions is electrically isolated from the others. For example, each set of coupled conductive regions is a different signal line or power line.

[0157] In some embodiments, the bonded semiconductor layer is part of an electromechanical system, and the electromechanical device may be formed by dividing a portion of the electromechanical system. For example, prior to division, the semiconductor layer used to create the conductive regions spans dimensions greater than 620 mm x 750 mm. For example, prior to singulation, the semiconductor layer is deposited on a Generation 3.5 glass substrate having dimensions of 620 mm x 750 mm, and the semiconductor layer includes multiple semiconductor portions arranged in an array, each portion corresponding to a single device. The semiconductor layer may be continuous or discontinuous (e.g., the layer includes discontinuities or gaps between adjacent portions). In some cases, prior to singulation, the dimensions of the semiconductor layer may be too large for cost-effective planarization (e.g., chemical mechanical planarization, CMP). Thus, embodiments described herein advantageously enable the creation of a planar semiconductor layer including the conductive regions without planarization. In some embodiments, after formation of devices (e.g., bolometers) coupled to the semiconductor layer, the stack of glass substrate, semiconductor layer, and devices may be divided into smaller portions (e.g., wafer-sized portions) for subsequent manufacturing steps.

[0158] Although the conductive regions of the silicon layers are illustrated as being rectangular and evenly spaced, it is understood that the bonded silicon layers may include conductive region patterns of other shapes and spacings. The exemplary device includes five conductive regions, but it is understood that the device may include any number of conductive regions.

[0159] FIG. 6 illustrates a method 600 for fabricating an electromechanical system including two bonded planar semiconductor layers, according to an embodiment of the present disclosure. Method 600 includes providing a first semiconductor layer having a first planar surface (step 602). For example, the first semiconductor layer can be the first semiconductor layer described with respect to FIGS. 5A-5E. In some embodiments, the semiconductor layer is an amorphous silicon layer. While method 600 is described with respect to fabricating an electromechanical system, it is understood that method 600 may be used in other fabrication processes, such as flip-chip bonding.

[0160] Method 600 includes creating a conductive region in the first semiconductor layer (step 604) by modifying the composition of a first planar surface of the semiconductor layer to make it conductive. In some embodiments, creating a conductive region in the semiconductor layer further includes modifying the composition of the semiconductor layer below the planar surface to make it conductive. For example, the conductive region is created by increasing the conductivity of a defined region of the first semiconductor layer, as described with respect to FIGS. 5A-5D.

[0161] Method 600 includes providing a second semiconductor layer having a second planar surface (step 606). For example, the second semiconductor layer can be the second semiconductor layer described with respect to Figures 5A-5F. In some embodiments, the second semiconductor layer is an amorphous silicon layer.

[0162] Method 600 includes creating a conductive region in the second semiconductor layer (step 608) by modifying the composition of a second planar surface of the semiconductor layer to make it conductive. In some embodiments, creating a conductive region in the second semiconductor layer further includes modifying the composition of the second semiconductor layer below the planar surface to make it conductive. For example, the second conductive region is created by increasing the conductivity of a defined region of the second semiconductor layer, as described with respect to FIGS. 5A-5D.

[0163] In some embodiments, the step of creating the conductive regions does not involve altering the topography of the first and second semiconductor layers. For example, if metal or oxide deposition is not required to create the conductive regions (as described with respect to Figures 4A-4D), no steps would be created and planarization would not be required, as described herein. In some embodiments, the conductive regions are created without removing material from the semiconductor layers.

[0164] In some embodiments, creating conductive regions in the first and second semiconductor layers includes doping the conductive regions. In some embodiments, doping the conductive regions further includes doping the conductive regions with an N-type dopant. In some embodiments, the method further includes doping the non-conductive regions with a P-type dopant. In some embodiments, the non-conductive regions in the first and second semiconductor layers comprise an undoped semiconductor. In some embodiments, the method further includes oxidizing the non-conductive regions. For brevity, exemplary semiconductor materials, dopants, and doping methods (e.g., as described with respect to Figures 5A and 5B) will not be described again.

[0165] In some embodiments, creating a conductive region in the semiconductor layer includes forming a silicide in the conductive region (e.g., as described with respect to Figures 5C and 5D). For brevity, an exemplary method of forming a silicide in the conductive region will not be described again.

[0166] In some embodiments, the method includes surface treating the first and second planar layers, for example, as described with respect to Figures 5E and 5F, where the tops of the first and second semiconductor layers 502 and 508 are surface treated.

[0167] Method 600 includes bonding a first semiconductor layer and a second semiconductor layer (step 610), where the second planar surface is parallel to the first planar surface. For example, as described with respect to FIG. 5F, each surface-treated semiconductor layer is activated to initiate bonding between the two semiconductor layers. For example, surface activated bonding can be performed using argon plasma at low pressure (e.g., 0.1 mTorr to 1 Torr) and room temperature. As another example, surface activated bonding can be performed at ultra-low pressure (e.g., 10 -8 ~10 -5 This can be performed using fast atom bombardment of argon or neon at low pressures (e.g., 0.1 mTorr to 1 Torr) and room temperature. As another example, surface activated bonding can be performed by exposing the surfaces to acidic or basic reactants at low pressures (e.g., 0.1 mTorr to 1 Torr). Other examples of bonding methods include thermocompression bonding (high forces (e.g., 10-80 kN) at high temperatures (e.g., 100-300°C)).

[0168] Method 600 includes electrically coupling the second semiconductor layer to the first semiconductor layer (step 612). For example, as described with respect to FIG. 5F, conductive regions 504A and 510A are electrically coupled to one another and second semiconductor layer 508 is bonded to the top of first semiconductor layer 502. In some embodiments, the electrically coupled conductive regions form signal lines of an electromechanical system.

[0169] In some embodiments, electrically coupling the second semiconductor layer with the first semiconductor layer includes electrically coupling a conductive region of the second semiconductor layer with a conductive region of the first semiconductor layer. For example, as described with respect to FIG. 5F, conductive region 504A and conductive region 510A substantially overlap each other in area.

[0170] In some embodiments, the method further includes electrically coupling a second conductive region in the conductive region of the first semiconductor layer with a second conductive region in the conductive region of the second semiconductor layer, wherein the second conductive region (e.g., the second set of electrically coupled conductive regions) is electrically isolated from the first conductive region (e.g., the first set of electrically coupled conductive regions). For example, as described with respect to FIG. 5F, second conductive region 504A is electrically coupled to second conductive region 510A, and the second set of conductive regions is electrically isolated from the first set of coupled conductive regions.

[0171] In some embodiments, the method further includes dividing the bonded semiconductor layer into a plurality of divided portions, each of which is associated with one electromechanical system. For example, prior to division, the semiconductor layer used to create the conductive regions spans dimensions greater than 620 mm x 750 mm. For example, prior to singulation, the semiconductor layer is deposited on a Generation 3.5 glass substrate having dimensions of 620 mm x 750 mm, and the semiconductor layer includes multiple semiconductor portions arranged in an array, each portion corresponding to a single device. The semiconductor layer may be continuous or discontinuous (e.g., the layer includes discontinuities or gaps between adjacent portions). In some cases, prior to singulation, the dimensions of the semiconductor layer may be too large for cost-effective planarization (e.g., chemical mechanical planarization, CMP). Thus, embodiments described herein advantageously enable the creation of planar semiconductor layers including conductive regions without planarization. In some embodiments, after formation of devices (e.g., bolometers) coupled to the semiconductor layer, the stack of glass substrate, semiconductor layer, and devices may be divided into smaller portions (e.g., wafer-sized portions) for subsequent manufacturing steps.

[0172] In some embodiments, planarization (e.g., chemical mechanical planarization) of the semiconductor layer is not necessary because the semiconductor layer is flat (e.g., no protrusions are created during the formation of the conductive regions). An exemplary advantage is that the complexity and cost of device fabrication can be reduced because a planarization step is no longer required. In some cases, creating conductive regions in the semiconductor layer (e.g., without depositing metal) can be sufficient to meet the electrical requirements of the device (e.g., delay, noise, voltage drop). Thus, in these instances, the device requirements can be met without the need for planarization, thereby reducing the cost and complexity of the device. In cases where planarization is not a viable alternative (e.g., at plate-level processing scales), embodiments disclosed herein can facilitate processing by eliminating the planarization step.

[0173] FIG. 7A illustrates an exemplary encapsulation structure for an electromechanical device 700. In some embodiments, FIG. 7A illustrates a method of forming a encapsulation structure for vacuum packaging. For example, the encapsulation structure is a portion of an electromechanical device 700 that includes vacuum packaging. In some embodiments, the illustrated area is a bonding area (e.g., a sealing region) of electromechanical device 200 or electromechanical device 900, and the disclosed method of forming the encapsulation structure advantageously improves adhesion (e.g., reduces delamination) and / or improves adhesion uniformity of a package lid (e.g., for vacuum packaging) to a substrate. It is understood that FIG. 7A is exemplary, and electromechanical device 700 may include more or less of the illustrated and / or described features.

[0174] As illustrated in FIG. 7A , in some embodiments, adhesion of an interface layer 702 (e.g., an interface layer of a package lid configured to ensure a vacuum inside the package) may be promoted by introducing features 704 in the bonding area on a substrate 706 (e.g., a non-silicon substrate, a glass substrate). In some embodiments, the features comprise a conductive (e.g., metallic) material. In some embodiments, the features comprise a non-conductive (e.g., non-metallic) material. In some embodiments, the material of the features is selected to be compatible with subsequent processing.

[0175] In some embodiments, the features are fabricated using the methods described with respect to FIGS. 2A-2D and 3 (e.g., the features may be fabricated using the methods for fabricating crossovers). In some embodiments, the features are fabricated using the methods described with respect to FIGS. 2A-2D and 3, and the height between adjacent regions formed by the methods described with respect to FIGS. 2A-2D and 3 is increased (e.g., by etching). Forming features with increased height between adjacent regions advantageously improves adhesion to an interface (e.g., a package lid, a seal ring, a second portion of an electromechanical device) and / or uniformity of adhesion to an interface (e.g., a package lid, a seal ring, a second portion of an electromechanical device). This can be particularly advantageous in combination with other aspects herein that enhance the planarity of a semiconductor surface. In some embodiments, the features align with the seal metal ring 206 or the package lid at a location that lacks a functional conductive crossover (e.g., a conductive crossover that conducts a signal to operate the electromechanical device). In some embodiments, the features are electrically isolated from the device. For example, the feature includes a conductive crossover that is electrically isolated (e.g., insulated) from a signal line of a device. As another example, the feature includes a non-conductive material (e.g., fabricated using a method described with respect to FIGS. 2A-2D). In some embodiments, the feature does not extend beyond the length of a functional conductive crossover (e.g., a conductive crossover that conducts a signal to operate an electromechanical device (e.g., described with respect to FIGS. 2A-2D)). For example, the feature includes a sealing region of a device, or a conductive crossover that terminates on one side of a sealing region (e.g., a non-functional conductive crossover). In some embodiments, for simplicity, areas that do not include features (e.g., non-conductive areas, areas of lower height than the features) are not shown.

[0176] In some embodiments, electromechanical device 700 does not include an insulating layer. In some embodiments, insulating layer 708 is added depending on the application and the sidewall slope of feature 704. For example, the deposited interfacial layer 702 may require complete isotropic coverage of an interior corner (e.g., formed by feature 704), and if feature 704 has 90-degree sidewalls, insulating layer 708 may be added to fill potential voids between feature 704 and interfacial layer 702.

[0177] In some embodiments, electrical shorting of the solder (e.g., corresponding to preform 710) to feature 704 (e.g., the feature is conductive) can be detrimental to device performance. In some embodiments, to avoid this electrical shorting, feature 704 is coated (e.g., by PECVD or other high pressure techniques) with a dielectric layer (e.g., insulating layer 708) before interface layer 702 is attached. By coating the feature with a dielectric layer, a conformal coating can be achieved, which can advantageously reduce systematic voiding at corners.

[0178] 7B illustrates a method 750 of forming an encapsulation structure. In some embodiments, the method 750 of manufacturing an electromechanical device includes providing a first portion of the device having a bonding region (step 752). For example, a portion of an electromechanical device 700 is provided, the portion of the device including the bonding region, as illustrated in FIG.

[0179] In some embodiments, the method includes adding a feature to the surface of the first portion in the bonding region (step 754). For example, feature 704 is added on substrate 706. In some embodiments, feature 704 is added using the method described with respect to Figures 2A-2D and 3. In some embodiments, feature 704 is added using the method described with respect to Figures 2A-2D and 3, and increases the height (e.g., by etching) between adjacent regions formed by the method described with respect to Figures 2A-2D and 3.

[0180] In some embodiments, the method includes depositing an interface layer over the feature (step 756). For example, interface layer 702 is deposited over electromechanical device 700. In some embodiments, the method includes disposing a second portion of the device over the bonding region (step 758). For example, a package lid is disposed over the bonding region of electromechanical device 700 (e.g., to bond the package lid to a first portion of the device).

[0181] In some embodiments, the method includes bonding the first and second portions of the device at a bonding region (step 760). For example, a package lid is bonded to the first portion of the electromechanical device 700.

[0182] In some embodiments, the method includes depositing an insulating layer between the feature and the interface layer. For example, insulating layer 708 is deposited between feature 704 and interface layer 702. In some embodiments, the first portion does not include a silicon substrate. For example, substrate 706 is a non-silicon substrate. In some embodiments, the feature includes a conductive material. For example, feature 704 includes a conductive material (e.g., a conductive material formed by the methods described with respect to Figures 2A-2D and 3, a metallic material).

[0183] Although the method of manufacturing an electromechanical device has been described as including the steps referenced, it is understood that the method may include steps in addition to or fewer than those described, or may include the steps described in a different order, and that the method may be performed with steps of other methods disclosed herein.

[0184] As used herein, a physical feature is "flat" if the surface corresponding to the physical feature is substantially flat over some extent. For example, the surface of a semiconductor layer has a root-mean-square (RMS) roughness of a height (e.g., less than 1 nm, less than 40 nm) across the surface.

[0185] For example, the disclosed semiconductor layer is flat at least at an interface region (e.g., with the seal ring 206, with the package lid, or with the second semiconductor layer (e.g., the second semiconductor layer described with reference to FIG. 5F)). For example, the interface region is a sealing interface region, and the surface of the interface region is “flat” if the seal ring or the second interface region of the device (e.g., the second portion of the device, the package lid) can bond to the interface region and maintain a specific vacuum (e.g., within the seal ring, the package lid, or within an enclosure formed by the second portion of the device). As another example, the interface region is a second semiconductor layer interface region, and the surface of the interface region is “flat” if the surface is substantially flat so that two interface conductive regions (e.g., the interface conductive region of the first semiconductor layer and the interface conductive region of the second semiconductor layer) can bond to each other and maintain a specific conductivity between the electrically coupled conductive regions. In some embodiments, the surface of the semiconductor layer is “flat” without planarizing the semiconductor layer surface.

[0186] As used herein, a material is "conductive" if it has greater electrical conductivity than a material with less electrical conductivity (e.g., an insulator, an undoped semiconductor, a p-type semiconductor). A material with less electrical conductivity may also be "non-conductive." Specifically, at an equivalent potential, a conductive material will conduct more current than a non-conductive material. For example, as described with respect to FIGS. 2A-2D, 5A-5F, or 7A, the disclosed conductive regions are more conductive than the disclosed non-conductive regions, such that at the same voltage, substantially more current will flow through the conductive regions than through the non-conductive regions. The conductivity of the conductive material may be sufficient to meet the electrical requirements (e.g., delay, noise, voltage drop, sufficient current to meet device requirements) of a device (e.g., electromechanical device 200, electromechanical device described with respect to FIGS. 5A-5F, electromechanical device 700, electromechanical device 900).

[0187] In this disclosure, "electrically coupled" and "coupled" are used to describe an electrical connection between two electrical elements, but it is understood that an electrical connection does not necessarily require a direct connection between the terminals of the components that are coupled together. Different combinations and connections of the referenced components may exist without departing from the scope of this disclosure. For example, the terminals of the components are electrically coupled together using electrical routing. In another example, a closed (conductive) switch is connected between the terminals of the components that are coupled together. In yet another example, additional elements are connected between the terminals of the components that are coupled together without affecting the characteristics of the circuit. For example, buffers, amplifiers, and passive circuit elements may be added without affecting the characteristics of the circuit and without departing from the scope of this disclosure.

[0188] Similarly, while "electrically uncoupled" is used in this disclosure to describe an electrical disconnection between two elements in a circuit, it is understood that electrical disconnection does not require a physical open between the terminals of the components being switched. It is also understood that "isolation" is not limited to meaning the prevention of electrical energy transfer between two elements. For example, a high-impedance element may be connected between the terminals of an isolating component. In another example, an open (non-conductive) switch may be connected between the terminals of an isolating component, effectively isolating the components.

[0189] Generally, as used herein, the term "substantially" is used to describe an element(s) or quantity(s) that ideally has a precise (e.g., fixed, same, uniform, equal, similar, balanced) quality, but in practice has a quality functionally equivalent to the precise quality. For example, when an element or quantity is described as substantially fixed or uniform, it can deviate from the fixed or uniform value, provided that the deviation is within a system tolerance (e.g., precision requirements, etc.). As another example, two elements or quantities described as substantially equal may be nearly equal, provided that the difference is within a tolerance that does not functionally affect the operation of the system.

[0190] Similarly, although some elements or quantities are described in an absolute sense without the term "substantially," it is understood that these elements and quantities may have functionally equivalent qualities to the absolute description. For example, in some embodiments, a ratio is described as being 1. However, unless the context dictates otherwise, it is understood that the ratio may be greater or less than 1, within the tolerances of the system (e.g., precision requirements, etc.).

[0191] 8 illustrates a method 800 for fabricating an electromechanical system according to an embodiment. As a non-limiting example, the electrochemical system may be associated with a device (e.g., electromechanical device 200, the electromechanical devices illustrated in FIGS. 5A-5F, electromechanical device 700) or system described herein. All or some of the process steps of method 800 may be used, and may be used in a different order, to fabricate an electromechanical system. As a non-limiting example, step 814 may be performed before step 812. In some embodiments, method 300 or method 600 may be performed in conjunction with method 800.

[0192] Method 800 includes step 802, providing a substrate. In some embodiments, the substrate is glass. In some embodiments, the substrate is low-temperature polycrystalline silicon. In some embodiments, the substrate is a borosilicate containing additional elements to fine-tune properties. An example of a borosilicate is Eagle™ by Corning, which produces alkaline earth boroaluminosilicates (silicates with boron, aluminum, and various alkaline earth elements). Other variations are available from Asahi Glass™ or Schott™.

[0193] In some embodiments, a flat panel glass process is used to fabricate the electromechanical system. In some embodiments, a liquid crystal display (LCD) process is used to fabricate the electromechanical system. In some embodiments, an OLED display process or an X-ray panel process is used. Employing a flat panel glass process allows for larger substrate sizes, thereby enabling a greater number of electrochemical systems per substrate and reducing processing costs. "Panel-level" substrate sizes include 620 mm x 750 mm, 680 mm x 880 mm, 1100 mm x 1300 mm, 1300 mm x 1500 mm, 1500 mm x 1850 mm, 1950 mm x 2250 mm, and 2200 mm x 2500 mm. Furthermore, panel-level thin film transistor (TFT) manufacturing can also reduce costs, so for example, an LCD-TFT process can be beneficial.

[0194] Method 800 includes step 804 of adding MEMS to the substrate. While MEMS is used to describe the addition of structures, it should be understood that other structures may be added without departing from the scope of this disclosure. In embodiments using panel-level processing, the MEMS structures may be added using an LCD-TFT process.

[0195] Step 804 may be followed by optional step 816, subplating. Step 816 may be used when the substrate is larger than the processing equipment used in subsequent steps. For example, when using panel-level processes (such as LCD), some embodiments will include cutting the panel to wafer size (in step 804) for further processing (e.g., using CMOS manufacturing equipment). In other embodiments, the same size substrate is used throughout method 800 (i.e., step 816 is not used).

[0196] The method 800 includes step 806, releasing the MEMS from the substrate.

[0197] Method 800 includes post-release processing, step 808. Such post-release processing can prepare the MEMS structure for further process steps, such as planarization. In wafer-level processing, planarization can include chemical-mechanical planarization. In some embodiments, a further process step includes etch-back, in which photoresist is spin-coated onto the topography to create a flatter surface, which is then etched. Greater control over the etching time can result in a smoother surface profile. In some embodiments, a further process step includes "spin-on glass." A glass-filled organic binder is spin-coated onto the topography, and the result is baked to remove the organic solvent, leaving a smoother surface.

[0198] Method 800 optionally includes vacuum encapsulation of the MEMS structure, step 810. Vacuum encapsulation is beneficial for extending the lifetime of the device.

[0199] Method 800 includes singulation, step 812. Some embodiments may include calibration and chip programming, which may take into account the properties of the sensor. Due to limited uniformity in glass lithography capabilities, the methods described herein may be advantageous in glass substrate manufacturing processes. As an additional advantage, glass has a lower thermal conductivity, making the glass substrate a better thermal insulator. By fabricating a thin structure that separates the bolometer pixels from the glass substrate, embodiments herein can better perform the function of thermally isolating the glass bolometer pixels from the packaging environment.

[0200] Method 800 includes step 814, mounting a readout integrated circuit (ROIC) and mounting the flex / PCB. As a non-limiting example, the readout circuit may be related to a device or system described herein. The processes and devices described herein may have the additional advantage that the area required for signal processing can be much smaller than the sensing area dictated by the sensing physics. Typically, sensors are integrated on top of CMOS circuits, and area-related costs lead to technology nodes that are not optimal for the signal processing task. The processes described herein can use more suitable CMOS, lowering the area required for signal processing and leveraging the low cost of FPD (flat panel display) manufacturing, thereby freeing the sensor from any area constraints. In some embodiments, the ROIC is specifically designed to sense specific electromagnetic wavelengths (such as X-rays, THz, and LWIR).

[0201] 9 shows an exemplary sensor. In some embodiments, sensor 900 is fabricated using method 800. Sensor 900 includes a glass substrate 906, a structure 904 less than 250 nm wide bonded to glass substrate 906, and a sensor pixel 902 bonded to structure 904. In some embodiments of sensor 900, structure 904 is a hinge that thermally isolates the active area from the glass. In some embodiments, sensor 900 receives an input current or charge and outputs an output current or charge based on the received radiation (e.g., a change in resistance between two terminals in the sensor in response to exposure to LWIR radiation).

[0202] In some embodiments, the sensor includes a glass substrate, a structure fabricated by any of the methods described herein and bonded to the glass substrate, and a sensor pixel bonded to the structure.

[0203] In some embodiments, the sensor includes a MEMS or NEMS device fabricated by an LCD-TFT fabrication process and a structure fabricated by any of the methods described herein.

[0204] For example, sensors can include resistive sensors and capacitive sensors. Bolometers can be used in a variety of applications. For example, long-wave infrared (LWIR, wavelengths approximately 8-14 μm) bolometers can be used in the automotive and commercial security industries. Examples include LWIR bolometers with QVGA, VGA, and other resolutions. Terahertz (THz, wavelengths approximately 1.0-0.1 mm) bolometers can be used in security (e.g., airport passenger screening) and medical imaging (e.g., THz bolometers with QVGA and other resolutions). Some electrochemical systems can include X-ray sensors or camera systems. Similarly, LWIR and THz sensors are used in camera systems. Some electromechanical systems are used in medical imaging applications such as endoscopy and exoscopy. X-ray sensors include direct and indirect sensing configurations.

[0205] Other electromechanical systems include scanners for light detection and ranging (LIDAR) systems. For example, optical scanners in which the spatial characteristics of a laser beam can be shaped (e.g., for beam pointing). Electromechanical systems include inertial sensors (e.g., where the input stimulus is linear or angular motion). Some systems may be used in biosensing and biotherapeutic platforms (e.g., where biochemical agents are detected).

[0206] It is understood that the diagrams depicting the devices are for illustrative purposes. It is understood that aspects of the disclosed invention may not be arranged rectangularly as shown. While the exemplary devices include a specific number of conductive regions, it is understood that the devices may include any number of conductive regions.

[0207] While some sections of the disclosed devices are illustrated with dashed circles, it is understood that the dashed circles are added merely for clarity and are not intended to be limiting, and it is understood that drawings of other sections of the disclosed devices may be substantially similar to the exemplary drawings.

[0208] In one aspect, a method for manufacturing an electromechanical system includes providing a semiconductor layer having a flat surface; creating conductive regions and adjacent non-conductive regions in the semiconductor layer by modifying a composition of the semiconductor layer, wherein the flat surface includes surfaces of the conductive regions and the non-conductive regions; and applying a hermetic seal over the flat surface to create a hermetically sealed space, wherein one conductive region of a plurality of conductive regions includes a first portion and a second portion, the first portion of the conductive region being below the hermetically sealed space and the second portion of the conductive region not being below the hermetically sealed space.

[0209] In one aspect of the above method, creating a conductive region in the semiconductor layer includes doping a region of the semiconductor layer to create the conductive region.

[0210] In some aspects of the above method, doping the region of the semiconductor layer further includes N-type doping the region.

[0211] In some aspects of the above method, the method further includes P-type doping a region of the semiconductor layer to create a non-conductive region.

[0212] In some aspects of the above method, the hermetically sealed space is a vacuum.

[0213] In some aspects of the above method, the conductive regions are created without altering the topography of the semiconductor layer.

[0214] In some aspects of the above method, creating a conductive region in the semiconductor layer includes forming a silicide in a region of the semiconductor layer to create the conductive region.

[0215] In some aspects of the above method, forming the silicide further includes depositing a patterned metal on top of the semiconductor layer.

[0216] In some aspects of the above method, the surface of the semiconductor layer spans dimensions greater than 620 mm by 750 mm.

[0217] In some aspects of the above method, the non-conductive region of the semiconductor layer comprises an undoped semiconductor.

[0218] In some aspects of the above method, the conductive regions are created without removing material from the semiconductor layer.

[0219] In some aspects of the above method, the method further includes electrically coupling the via to the conductive region.

[0220] In some aspects of the above method, the method further includes electrically coupling the conductive region to a bolometer circuit.

[0221] In some aspects of the above method, the step of providing a semiconductor layer having a flat surface includes depositing the semiconductor layer on a glass substrate.

[0222] In some aspects of the above method, the method further includes providing an insulating layer over the semiconductor layer and below the hermetic seal.

[0223] In some aspects of the above method, the method includes oxidizing the non-conductive region.

[0224] In some aspects of the above method, the method further includes dividing the semiconductor layer into a plurality of divided portions, and the step of applying a hermetic seal further includes applying a hermetic seal to tops of the divided portions.

[0225] In one aspect, an electromechanical system includes a semiconductor layer having a planar surface, the semiconductor layer including a conductive region and an adjacent non-conductive region, the conductive region including a modified material and the adjacent non-conductive region including the material; and a hermetic seal disposed over the planar surface, the hermetic seal creating a hermetic sealed space, wherein one conductive region of the plurality of conductive regions includes a first portion and a second portion, the first portion of the conductive region being below the hermetic sealed space and the second portion of the conductive region not being below the hermetic sealed space.

[0226] In one aspect of the above system, the conductive region of the semiconductor layer is doped.

[0227] In one aspect of the above system, the conductive region includes an N-type dopant.

[0228] In one aspect of the above system, the non-conductive region includes a P-type dopant.

[0229] In some aspects of the above system, the conductive regions are created without altering the topography of the semiconductor layer.

[0230] In some aspects of the above system, the conductive region includes a silicide.

[0231] In some aspects of the above system, the silicide is formed by depositing a patterned metal on top of the semiconductor layer.

[0232] In some aspects of the above system, the surface of the semiconductor layer spans dimensions greater than 620 mm x 750 mm.

[0233] In some aspects of the above system, the non-conductive region of the semiconductor layer comprises an undoped semiconductor.

[0234] In some aspects of the above system, the conductive regions are created without removing material from the semiconductor layer.

[0235] In some aspects of the above system, the system further includes a via electrically coupled to the conductive region.

[0236] In some aspects of the above system, at least one of the conductive regions is electrically coupled to a bolometer circuit.

[0237] In some aspects of the above system, the system further includes a glass substrate, and the semiconductor layer is deposited on the glass substrate.

[0238] In some aspects of the above system, the system further includes providing an insulating layer over the semiconductor layer and below the hermetic seal.

[0239] In some aspects of the above system, the non-conductive region is oxidized.

[0240] In some aspects of the above system, the non-conductive regions are modified differently than the conductive regions.

[0241] In one aspect, a method of manufacturing an electromechanical system includes providing a first semiconductor layer having a first planar surface; creating conductive regions and adjacent non-conductive regions in the first semiconductor layer by modifying the composition of the first semiconductor layer; providing a second semiconductor layer having a second planar surface; creating conductive regions and adjacent non-conductive regions in the second semiconductor layer by modifying the composition of the second semiconductor layer; bonding the first semiconductor layer and the second semiconductor layer, wherein the second planar surface is parallel to the first planar surface; and electrically coupling the second semiconductor layer to the first semiconductor layer.

[0242] In some aspects of the above method, creating conductive regions in the first and second semiconductor layers includes doping regions of the semiconductor layers to create the conductive regions.

[0243] In some aspects of the above method, doping the region of the semiconductor layer further includes N-type doping the region.

[0244] In some aspects of the above method, the method further includes P-type doping a region of the semiconductor layer to create a non-conductive region.

[0245] In some aspects of the above method, the conductive regions are created without altering the topography of the semiconductor layer.

[0246] In some aspects of the above method, creating a conductive region in the semiconductor layer includes forming a silicide in a region of the semiconductor layer to create the conductive region.

[0247] In some aspects of the above method, the non-conductive region of the semiconductor layer comprises an undoped semiconductor.

[0248] In some aspects of the above method, the conductive regions are created without removing material from the semiconductor layer.

[0249] In some aspects of the above method, the method further includes surface treating the first and second flat surfaces.

[0250] In some aspects of the above method, the method further includes activating the surface-treated flat surface before bonding the first semiconductor layer and the second semiconductor layer.

[0251] In some aspects of the above method, electrically coupling the second semiconductor layer to the first semiconductor layer includes electrically coupling a conductive region of the second semiconductor layer to a conductive region of the first semiconductor layer.

[0252] In some aspects of the above method, the method further includes electrically coupling a second conductive region in the conductive region of the first semiconductor layer to a second conductive region in the conductive region of the second semiconductor layer, the second conductive region being electrically isolated from the first conductive region.

[0253] In some aspects of the above method, the electrically coupled conductive regions form signal lines.

[0254] In some aspects of the above method, the method further includes oxidizing the non-conductive region.

[0255] In some aspects of the above method, the method further includes dividing the bonded semiconductor layer into a plurality of divided portions, each divided portion associated with one electromechanical system.

[0256] In some aspects of the above method, the first and second flat surfaces have a root mean square roughness of less than 1 nm.

[0257] In one aspect, an electromechanical system includes a first semiconductor layer having a first planar surface, the first semiconductor layer including a conductive region and an adjacent non-conductive region, the conductive region including a modified first material, the adjacent non-conductive region including the first material; and a second planar semiconductor layer having a second planar surface, the second semiconductor layer including a conductive region and an adjacent non-conductive region, the conductive region including a modified second material, the adjacent non-conductive region including the second material, wherein the first planar surface is parallel to the second planar surface, and the conductive region of the first semiconductor layer is electrically coupled to the conductive region of the second semiconductor layer.

[0258] In some aspects of the above system, the conductive regions of the first and second semiconductor layers are doped.

[0259] In one aspect of the above system, the conductive region includes an N-type dopant.

[0260] In one aspect of the above system, the non-conductive region includes a P-type dopant.

[0261] In some aspects of the above system, the conductive regions are created without altering the topography of the semiconductor layer.

[0262] In some aspects of the above system, the conductive region includes a silicide.

[0263] In some aspects of the above system, the non-conductive region of the semiconductor layer comprises an undoped semiconductor.

[0264] In some aspects of the above system, the conductive regions are created without removing material from the semiconductor layer.

[0265] In some aspects of the above system, the first and second planar semiconductor layers are surface treated.

[0266] In some aspects of the above system, the conductive region of the second semiconductor layer is electrically coupled to the conductive region of the first semiconductor layer.

[0267] In some aspects of the above system, a second conductive region in the conductive region of the first semiconductor layer is electrically coupled to a second conductive region in the conductive region of the second semiconductor layer, and the second conductive region is electrically isolated from the first conductive region.

[0268] In some aspects of the above system, the electrically coupled conductive regions are signal lines.

[0269] In some aspects of the above system, the non-conductive region is oxidized.

[0270] In some aspects of the above system, the first and second flat surfaces have a root mean square roughness of less than 1 nm.

[0271] In one aspect, a method of manufacturing an electromechanical device includes providing a first portion of the device having a bonding region; adding a feature to a surface of the first portion at the bonding region; depositing an interface layer on the feature; positioning a second portion of the device on the bonding region; and bonding the first and second portions of the device at the bonding region.

[0272] In some aspects of the above method, the method includes depositing an insulating layer between the feature and the interface layer.

[0273] In some aspects of the above method, the first portion comprises a non-silicon material.

[0274] In some aspects of the above method, the features comprise a conductive material.

[0275] Although the disclosed aspects have been fully described with reference to the accompanying drawings, it should be noted that various changes and modifications will be apparent to those skilled in the art, and such changes and modifications are understood to be included within the scope of the disclosed aspects, as defined by the appended claims.

[0276] The terminology used in the description of the various described embodiments herein is intended to describe particular embodiments only and is not intended to be limiting. As used in the description of the various described embodiments and in the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. Also, as used herein, the term "and / or" will be understood to refer to and encompass any and all possible combinations of one or more of the associated listed items. As used herein, it will be further understood that the terms "includes," "including," "comprises," and / or "comprising" specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

Claims

1. A method of forming a glass substrate from an amorphous silicon layer having a flat surface; creating a conductive region and an adjacent non-conductive region in the amorphous silicon layer by modifying a composition of the amorphous silicon layer, wherein the planar surface includes a surface of the conductive region and a surface of the non-conductive region; and applying an airtight seal onto the flat surface to create an airtight sealed space; one of the conductive regions includes a first portion and a second portion; the first portion of the conductive region underlies the hermetically sealed space; the second portion of the conductive region is not below the hermetically sealed space; Process 1. A method for manufacturing an electromechanical system, comprising:

2. 10. The method of claim 1, wherein creating the conductive regions in the amorphous silicon layer comprises doping regions of the amorphous silicon layer to create the conductive regions.

3. The method of claim 2 , wherein doping the region of the amorphous silicon layer further comprises N-type doping the region.

4. 3. The method of claim 2, further comprising P-type doping a region of the amorphous silicon layer to create the non-conductive region.

5. The method of claim 1 , wherein the hermetically sealed space is a vacuum.

6. The method of claim 1 , wherein the conductive regions are created without modifying the topography of the amorphous silicon layer.

7. 2. The method of claim 1, wherein creating the conductive regions in the amorphous silicon layer comprises forming a silicide in a region of the amorphous silicon layer to create the conductive region.

8. 8. The method of claim 7, wherein forming the silicide further comprises depositing a patterned metal on top of the amorphous silicon layer.

9. 10. The method of claim 1, wherein the surface of the amorphous silicon layer spans dimensions greater than 620 mm x 750 mm.

10. The method of claim 1 , wherein the non-conductive regions of the amorphous silicon layer comprise an undoped semiconductor.

11. The method of claim 1 , wherein the conductive regions are created without removing material from the amorphous silicon layer.

12. The method of claim 1 , further comprising electrically coupling a via to the conductive region.

13. The method of claim 1 , further comprising electrically coupling the conductive region to a bolometer circuit.

14. 10. The method of claim 1, wherein the step of providing an amorphous silicon layer having a flat surface comprises depositing the amorphous silicon layer on a glass substrate.

15. The method of claim 1 , further comprising providing an insulating layer over the amorphous silicon layer and below the hermetic seal.

16. The method of claim 1 , further comprising oxidizing the non-conductive region.

17. 10. The method of claim 1, further comprising dividing the amorphous silicon layer into a plurality of divided portions, and wherein the applying a hermetic seal further comprises applying a hermetic seal to tops of the divided portions.

18. 1. A method of manufacturing an electromechanical device, comprising: providing a first portion on an amorphous silicon layer of a device having a junction region; adding a feature to a surface of the first portion on the amorphous silicon layer in the junction region; depositing an interface layer over the feature; disposing a second portion of the amorphous silicon layer of the device over the junction region; and bonding the first portion and the second portion on the amorphous silicon layer of the device at the bonding region. A method comprising:

19. 20. The method of claim 18, further comprising depositing an insulating layer between the feature and the interface layer.

20. an amorphous silicon layer having a planar surface, the amorphous silicon layer including a conductive region and an adjacent non-conductive region, the conductive region including the modified material and the adjacent non-conductive region including the material; a hermetic seal disposed on the flat surface, The hermetic seal creates a hermetically sealed space; one of the conductive regions includes a first portion and a second portion; a first portion of the conductive region below the hermetically sealed space; a second portion of the conductive region not under the hermetically sealed space; Airtight seal and Electromechanical systems, including:

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