Chip Package

Abstract

In at least one embodiment, the chip package comprises at least one first compensation layer (31) that is conductive and a plurality of semiconductor chips (2) disposed on and electrically contacted by the at least one first compensation layer (31), wherein the at least one first compensation layer (31) comprises a plurality of pores (6), and the at least one first compensation layer (31) is elastically deformable such that the at least one first compensation layer (31) is configured to compensate for height differences (ΔH) between the semiconductor chips (2).

Description

[Technical Field]

[0001] A chip package is provided. [Background technology]

[0002] Document US Pat. No. 6,320,268 B1 refers to a power semiconductor module in which at least one semiconductor chip, the contact of which is made by pressure, is electrically connected to a main connection via contact elements.

[0003] The documents US 2002 / 0005578 A1, JP 2014-127536, JP 2005-209784, and US 2014 / 0110827 A1 refer to semiconductor devices. Summary of the Invention [Problem to be solved by the invention]

[0004] The problem to be solved is to provide a chip package in which a semiconductor chip can be efficiently mounted. [Means for solving the problem]

[0005] This object is achieved, inter alia, by a chip package as set forth in the independent claims. Exemplary further developments form the subject matter of the dependent claims.

[0006] For example, the chip package includes a conductive compensation layer that is mechanically elastically deformable. Therefore, when the semiconductor chips are pressed against, for example, a base plate by the compensation layer, the compensation layer can compensate for height differences between the semiconductor chips. Therefore, a common compensation layer can be used for multiple semiconductor chips to press the multiple semiconductor chips against the base plate without the need to assign a spring element to each semiconductor chip individually.

[0007] In at least one embodiment, a chip package includes at least one first compensation layer that is electrically conductive and a plurality of semiconductor chips disposed on and electrically contacted by the at least one first compensation layer, the at least one first compensation layer including a plurality of pores and elastically deformable such that the at least one first compensation layer is configured to compensate for height differences between the semiconductor chips.

[0008] Many different types of electrical converters utilize press-pack modules due to the ease of stacking them in a serial connection using a mechanical clamping system. For example, for facilitated mechanical clamping, the press-pack module is divided into submodules. Each submodule can contain a predetermined, identical number of chips. The required current rating is achieved by connecting the required number of submodules in parallel. In this module design, multiple chips are set in parallel both electrically and mechanically. To operate properly, this type of press-pack module requires uniform distribution of clamping force across all chips present in the module. One possible solution is to rely on a relatively complex and expensive individual spring system—i.e., one spring per semiconductor chip. Another possibility is to instead rely on very tight mechanical tolerances, which is also costly and complicates stack assembly.

[0009] Such press-pack modules are designed to require them to be clamped in a mechanical stack to connect their collector and emitter terminals. This concept offers the potential for very low contact resistance and high current-carrying capability. However, to do so, the module must achieve uniform distribution of clamping force across all semiconductor chips. If the clamping force is not evenly distributed, one chip may carry more current than the other chips, which significantly reduces the module's performance and its lifespan. In addition, if the press-pack module is not perfectly flat or does not compensate for uneven flatness, the stackability of the press-pack module is greatly reduced, greatly increasing the likelihood that the semiconductor chips may crack. This limits the number of modules that can be stacked.

[0010] In the semiconductor chip packages described herein, a spring-like structure, i.e., at least one compensation layer, is used to distribute the clamping force evenly across all semiconductor chips present in the chip package or in a module that includes the chip package.

[0011] This chip package allows for the elimination of expensive multi-spring packages used in other solutions while maintaining the stacking robustness of the package.

[0012] In summary, using the chip packages described herein, for example in a sub-module design, one or more compensation layers are used. At least one compensation layer may have the following characteristics, individually or in any combination: The compensation layer is elastic in order to compensate for uneven flatness and thickness differences resulting from the various components included in the submodule assembly, for example semiconductor chips with different heights.

[0013] The compensation layer may also have a spring-like performance, generating a predetermined force on each semiconductor chip after deformation to compensate for assembly tolerances.

[0014] - The compensation layer can also be an excellent thermal and electrical conductor. Metals such as copper or aluminum are excellent electrical and thermal conductors, but in their usual block form they lack flexibility and spring-like effect.

[0015] The latter two properties can be introduced into the metal of at least one compensation layer, for example, by creating a highly porous structure therein. In addition to achieving a spring-like effect, all pores can be elongated longitudinally and oriented in a predetermined direction. The exact orientation of the longitudinal pores can be determined depending on the spring constant required for a specific application. The number of pores introduced into the metal is a compromise between, for example, adaptability to uneven flatness and conductive properties.

[0016] According to at least one embodiment, the chip package further comprises a base plate. For example, the base plate is made of a metal such as copper, aluminum, or molybdenum. To prevent oxide layers from interfering with electrical contact, the base plate may comprise a coating containing nickel and / or phosphate, such as so-called NiP. The same applies to at least one compensation layer.

[0017] According to at least one embodiment, the semiconductor chip is placed directly between the base plate and the at least one first compensation layer, so that the semiconductor chip can be in physical contact with the base plate and the at least one first compensation layer, where contact can be made by dry contact, i.e., without solder, sintered layers, etc.

[0018] Here and hereinafter, a "first" compensation layer is at least one compensation layer that is in direct contact with the semiconductor chip. Additional compensation layers may also be present. All mechanical, electrical, and thermal properties discussed below with respect to the first compensation layer may also apply to other compensation layers, such as the second and third compensation layers, and vice versa.

[0019] According to at least one embodiment, the base plate is a rigid, inelastic plate. "Rigid and inelastic" refers to the proper or normal use of the chip package. For example, compared to the at least one compensation layer, the base plate has a Young's modulus that is at least three times or at least ten times greater than that of the at least one compensation layer. Here, and hereinafter, the respective Young's moduli may be measured along a direction perpendicular to the side of the base plate on which the semiconductor chip is disposed or along a direction perpendicular to the top surface of the semiconductor chip. Thus, the at least one compensation layer may be considered flexible relative to the base plate, and only the respective compensation layer, and not the base plate, may be deformed, e.g., elastically deformed.

[0020] According to at least one embodiment, the at least one compensation layer and the base plate are configured to be pressed together with the semiconductor chip therebetween. For example, the pressure used to press the at least one compensation layer and the base plate together is at least 0.1 MPa, at least 0.3 MPa, or at least 1 MPa. Alternatively, or in addition, the pressure is at most 15 MPa, or at most 3 MPa. The pressure may be calculated as the clamping force between each base plate and compensation layer divided by the sum of the cross-sectional areas of all assigned semiconductor chips, the cross-sectional areas being perpendicular to the clamping force.

[0021] According to at least one embodiment, the chip package further comprises at least one support pillar. For example, the support pillar is made of at least one type of metal. Compared to the at least one compensation layer, the at least one assigned support pillar may be rigid. For example, the at least one support pillar has a Young's modulus at least three times or at least ten times greater than that of the at least one compensation layer.

[0022] According to at least one embodiment, the chip package includes at least one second compensation layer. The at least one second compensation layer can also include pores and can be mechanically, electrically, and thermally configured identically or similarly to the at least one first compensation layer. For example, the Young's modulus of the at least one second compensation layer differs from the Young's modulus of the at least one first compensation layer by a factor of at most 1.5 or at most 1.2. The at least one second compensation layer and the at least one first compensation layer can be intentionally different from each other by a factor of at least 1.2 or at least 1.5, and / or at most 5 or at most 2.

[0023] When the support pillars and the at least one second compensation layer are present, the support pillars can be located between the at least one second compensation layer and the at least one first compensation layer, and thus the at least one second compensation layer can be at least one compensation layer disposed on a side of the at least one support pillar away from the at least one first compensation layer.

[0024] According to at least one embodiment, the chip package includes at least one third compensation layer. The at least one third compensation layer may also include pores and may be mechanically, electrically, and thermally configured equal to or similar to the at least one first compensation layer and / or equal to or similar to the at least one second compensation layer. For example, the Young's modulus of the at least one third compensation layer differs from the Young's modulus of the at least one first compensation layer by a factor of at most 1.5 or at most 1.2. The at least one third compensation layer and the at least one first compensation layer may be intentionally different from each other by a factor of at least 1.2 or at least 1.5, and / or at most 5 or at most 2.

[0025] For example, the at least one third compensation layer is at least one compensation layer that is disposed on a side of the semiconductor chip remote from the at least one first compensation layer, for example on a side of the base plate remote from the semiconductor chip.

[0026] According to at least one embodiment, the pores are non-spherical. For example, the pores are at least one of cylindrical, elliptical, and cylindrical with rounded bottom and top. Thus, the pores can have pillar-like or column-like shapes. It is possible that all pillars have the same shape, or there is intentional difference in the shape of the pillars. For example, spherical pores can be combined with cylindrical pores.

[0027] According to at least one embodiment, the aspect ratio of a pore is at least 1.5 or at least 4, and / or at most 20, at most 10, or at most 5. For example, the aspect ratio of a particular pore may be the longest extent of said pore along a straight line divided by the maximum lateral extent in a direction perpendicular to the longest extent, wherein the longest extent is greater than or equal to the maximum lateral extent.

[0028] According to at least one embodiment, the pores are aligned parallel to one another. This may mean that the longest-extending axes of the pores point away from the nearest semiconductor chip. For example, the axes are parallel to one another with a tolerance of at most 30°, at most 20°, or at most 10°. Alternatively, or in addition, the axes, or at least some of the axes, are oriented perpendicular to the side of the base plate on which the semiconductor chip is disposed, with a tolerance of at most 30°, at most 20°, or at most 10°, for example.

[0029] According to at least one embodiment, the volume ratio of pores on each compensation layer overall is at least 5%, at least 10%, or at least 20%. Alternatively, or in addition, the ratio is at most 80%, at most 70%, at most 60%, at most 45%, or at most 30%. For example, the ratio is 10% to 60%, or 10% to 30%. Thus, the volume ratio can be relatively small.

[0030] According to at least one embodiment, at least one compensation layer has a Young's modulus in the direction towards the semiconductor chip of at least 1 GPa, at least 2 GPa, or at least 5 GPa, or alternatively, at most 60 GPa, at most 40 GPa, at most 20 GPa, or at most 10 GPa.

[0031] The chip package described herein will now be described in more detail as an exemplary embodiment with reference to the drawings. Elements that are the same in the various figures are designated with the same reference numerals. The relationships between elements are not shown to scale; rather, individual elements may be shown greatly exaggerated to aid understanding. [Brief explanation of the drawings]

[0032] [Figure 1] 1 is a schematic cross-sectional view of an exemplary embodiment of a chip package described herein. [Figure 2] 1 is a schematic cross-sectional view of an exemplary embodiment of a chip package described herein. [Figure 3] 2 is a schematic cross-sectional view of an exemplary embodiment of a first compensation layer for a chip package described herein. [Figure 4] 2 is a schematic cross-sectional view of an exemplary embodiment of a first compensation layer for a chip package described herein. [Figure 5] 1 is a schematic cross-sectional view of an exemplary embodiment of a chip package described herein. [Figure 6] 1 is a schematic top view of an exemplary embodiment of a chip package described herein. DETAILED DESCRIPTION OF THE INVENTION

[0033] 1 shows an exemplary embodiment of a chip package 1. The chip package 1 comprises a first compensation layer 31 and a plurality of semiconductor chips 2 arranged on a mounting side 30 of the first compensation layer 31.

[0034] For example, the semiconductor chip 2 is selected from the following group: metal oxide semiconductor field effect transistor (MOSFET), insulated gate semiconductor field effect transistor (MISFET), insulated gate bipolar transistor (IGBT), bipolar junction transistor (BJT) and junction gate field effect transistor (JFET), thyristor such as gate turn-off thyristor (GTO) or gate commutated thyristor (GCT), diode.

[0035] For example, the semiconductor chip 2, or at least one or some of the semiconductor chips 2, is configured for a maximum current of at least 1 A, or at least 20 A. Alternatively, or in addition, the semiconductor chip 2 is configured for a maximum voltage of at least 0.2 kV, at least 0.6 kV, or at least 1.2 kV. In other words, the semiconductor chip 2 may be a power semiconductor chip.

[0036] For example, the chip package 1 may be for a power module in a vehicle, such as a hybrid or plug-in electric vehicle or a train, for converting direct current from a battery into alternating current for an electric motor. Furthermore, the power semiconductor device may be a fuse in a vehicle, such as an automobile. The chip package 1 may also be used in a power switch, such as a transformer. The chip package 1 may be a press-pack module or part of a press-pack module.

[0037] All the semiconductor chips 2 may be of the same type. In this case, due to manufacturing tolerances, the semiconductor chips 2 may have different heights H. Therefore, there may be a height difference ΔH between the semiconductor chips 2. The different heights H above the mounting side 30 may also result from unevenness or roughness of the mounting side 30. Furthermore, different types of semiconductor chips 2 may be used. For example, IGBTs and diodes may be used together to account for different current directions through the chip package. Using different types of semiconductor chips 2 may result in a relatively large height difference ΔH.

[0038] For example, the height difference ΔH reaches at least 1%, at least 5%, or at least 10% of the maximum height H of the semiconductor chip 2. Alternatively, or in addition, the height difference ΔH reaches at most 70%, 50%, or 30% of the maximum height H of the semiconductor chip 2.

[0039] For example, the maximum height H is at least 0.1 mm, or at least 0.4 mm. Alternatively, or in addition, the maximum height H is at most 2 mm, at most 0.7 mm, or at most 0.5 mm. For example, the maximum height H is at least 0.2 mm and not more than 0.5 mm.

[0040] The first compensation layer 31 is configured to compensate for the height difference ΔH when the semiconductor chip 2 is pressed against another component not shown in FIG. 1 to electrically contact the component, for example by a dry contact. Therefore, the first compensation layer 31 needs to be mechanically deformable to allow all sides of the semiconductor chip 2 facing away from the mounting side 30 to be contacted by a flat, hard surface. The first compensation layer 31 also needs to maintain pressure on the semiconductor chip 2. Therefore, the first compensation layer 31 needs to be elastically deformable, like a spring.

[0041] For this purpose, the first compensation layer 31 has an internal structure. For example, the internal structure of the first compensation layer 31 is foam-like. Thus, the first compensation layer 31 may comprise a plurality of pores 6. For example, the volume fraction of pores in the entire first compensation layer 31 may be at least 5%, or at most 80%, and may also be between 10% and 60%, or between 10% and 30%.

[0042] Since the semiconductor chip 2 may be a power semiconductor chip, the volume ratio may be relatively small to enable high current carrying characteristics and to achieve effective cooling of the semiconductor chip 2 through the first compensation layer 31. For example, the first compensation layer may have a current capacity of at least 1 A / cm 2 , at least 5A / cm 2 , at least 10A / cm 2 , or at least 50A / cm 2 These current densities may refer to a direction perpendicular to a backside 34 of the first compensation layer 31 opposite the mounting side 30. The backside 34 may be of a planar shape.

[0043] For example, the maximum thickness T of the first compensation layer 31 is at least 0.2 mm, at least 0.3 mm, or at least 0.8 mm. Alternatively, or in addition, the thickness T may be at most 5 mm, at most 3 mm, or at most 1.5 mm. For example, the thickness may be at least 0.3 mm and at most 3 mm. Thus, the thickness T of the at least one first compensation layer may be, for example, at least 0.2 mm and at most 5 mm, and the minimum diameter of the at least one first compensation layer may be at least three times greater than the thickness T.

[0044] The first compensation layer 31 may be disk-shaped. This may mean that the first compensation layer 31 has a width much greater than the thickness H. For example, the minimum diameter of the first compensation layer 31 is at least three times, at least ten times, or at least thirty times greater than the thickness T. Alternatively, or in addition, the aforementioned multiple is at most 300, or at most 100. In the case of a square first compensation layer 31, the minimum diameter may be the side length, and in the case of a rectangular back side 34, the minimum diameter may be the shortest side length, as viewed from the top view of the back side 34. In other cases, the minimum diameter d may be calculated as d=(4A / π) 0.5 It can be calculated from the areal capacitance A of the backside 34 as follows:

[0045] According to at least one embodiment, the height difference ΔH amounts to at least 1%, or at least 5%, and / or at most 70%, at most 50%, at most 30%, or at most 15% of the thickness T of the first compensation layer 31. For example, the height difference ΔH amounts to 1% or more and 30% or less of the thickness T of the at least one first compensation layer 31.

[0046] According to at least one embodiment, the first compensation layer 31 is made of pure copper, pure aluminum, or pure molybdenum. The term “pure” can mean that the first compensation layer 31 is at least 99% by weight or at least 99.8% by weight of the respective metal. Therefore, the mechanical properties of the first compensation layer 31 are obtained by its internal structure, i.e., the pores 6, and not by alloys or substantially by alloys. Alloying, e.g., Al with Be, can lower the Young's modulus in a desired manner, but can also significantly reduce the electrical conductivity. Therefore, when using, for example, a power semiconductor chip 2, such alloys should be avoided to maintain the desired high electrical conductivity of the first compensation layer 31. Alternatively, any other metal or metal alloy with excellent electrical conductivity can be used for the first compensation layer 31, the second compensation layer 32, and / or the third compensation layer 33.

[0047] 2 shows another exemplary embodiment of the chip package 1. In this case, the chip package 1 also includes a base plate 4. For example, the base plate 4 is a solid metal plate made of, for example, copper, molybdenum, or aluminum. Thus, the base plate 4 may not include any internal structure, but may be a homogenous piece of metal.

[0048] Therefore, the base plate 4 is much harder and less flexible than the first compensation layer 31. When the semiconductor chip 2 is brought into electrical and thermal contact by pressing the first compensation layer 31 and the base plate 4 together, essentially only the first compensation layer 31 deforms, and the base plate 4 does not deform.

[0049] That is, the height difference of the semiconductor chip 2 is compensated by the first compensation layer 31 by pressing the semiconductor chip 2 against the attachment side 30 of the first compensation layer 31. In this pressing, the back side 34 may be supported by a further layer, not shown, so that the back side 34 may still be of planar and uniform shape.

[0050] Therefore, by using the first compensation layer 31, height differences between the semiconductor chips 2 can be compensated for by a single component, so that individual springs assigned to the semiconductor chips 2 in a one-to-one manner can be omitted, for example.

[0051] Otherwise, the same may be true for FIG. 2 as for FIG. 3 and 4 show possible configurations of the first compensation layer 31. In all these configurations, the attachment side 30 and the planar backside 34 can be free of pores 6. Thus, the attachment side 30 and the planar backside 34 can be free of any voids or holes resulting from pores 6. Alternatively, there can be some pores 6 extending into the attachment side 30 or the backside 34, but for example, at least 90%, at least 95%, or at least 98% of the attachment side 30 and / or backside 34 can be free of pores 6. It is possible that there are no continuous pores or holes extending from the attachment side 30 to the planar backside 34.

[0052] The mounting side 30 and / or the back side 34 may be provided with a coating, not shown, for example to avoid an electrically insulating oxide film on those sides.

[0053] According to Figure 3, the pores 6 are of elongated shape. Thus, the aspect ratio of the pores 6 may be at least 1.5, or at least 4, and / or at most 20, at most 10, or at most 5, or may be between 1.5 and 10. It is possible that all of the pores 6 are of roughly the same shape, such as cylindrical or elliptical.

[0054] For example, there is only one layer of pores 6 in a direction perpendicular to the backside 34. All of the pores 6, or most of the pores 6, may be aligned parallel to one another or approximately parallel to one another. The term "approximately" may mean a tolerance of up to 30°, up to 20°, or up to 10°.

[0055] As an option, the longest extent of said pores, for example along a straight line perpendicular or approximately perpendicular to the backside 34, amounts to at least 60%, or at least 70%, and / or at most 95%, or at most 80% of the thickness of the first compensation layer 31. Thus, the pores 6 may penetrate almost completely through the first compensation layer 31 without reaching the mounting side 30 and the backside 34, to allow good thermal and electrical contact.

[0056] Such a first compensation layer 31 can be made, for example, by mixing metal particles and organic particles of appropriate sizes and then sintering or fusing the metal particles together while the organic particles disappear. The resulting material can then be anisotropically stretched to obtain elongated pores 6. By appropriately selecting the sizes and volume ratios of the metal and organic particles, the properties of the first compensation layer 31 can be adjusted.

[0057] For example, the average diameter of the pores 6 may be at least 0.1 mm, or at least 0.3 mm, and / or at most 2 mm, or at most 1.2 mm, and may be 0.1 mm or more and 2 mm or less. For example, the average diameter dm may be expressed as dm=(6V / π) 1 / 3 This can be calculated from the volume V of each pore 6 by:

[0058] 4 shows that there may be more than one layer of pores 6. For example, on average there may be two layers of pores 6, one above the other. Additionally, the pores 6 may have greater size variation and / or shape variation.

[0059] Otherwise, the same may apply to Figures 3 and 4 as to Figures 1 and 2, and vice versa.

[0060] 5 shows a more complex exemplary embodiment of the chip package 1. For example, the chip package 1 comprises multiple sub-modules 7. Each of the sub-modules 7 may comprise one semiconductor chip 2 or multiple semiconductor chips 2. For example, there may be at least six, or at least nine, and / or up to 36, or up to 16 of the semiconductor chips 2 per sub-module 7.

[0061] Furthermore, each of the sub-modules 7 may include its own first compensation layer 31, such that the chip package 1 comprises multiple first compensation layers 31, each of which contains some of the semiconductor chips 2.

[0062] As an option, the submodule 7 may include pillars 5. For example, the pillars 5 are solid metal blocks, which may be, for example, of copper, aluminum, or molybdenum. Thus, like the base plate 4, the pillars 5 are rigid compared to the first compensation layer 31. There may be a one-to-one ratio between the pillars 5 and the first compensation layer 31. The pillars 5 may in either case be in direct contact with the back side 34 of the first compensation layer 31.

[0063] The pillars 5 and the first compensation layer 1 may optionally be attached to an internal holder 82 to prevent misalignment of the pillars 5 and the first compensation layer 1. As a further option, the chip package 1 may include a module frame 83, for example made of ceramic, which may be ring-shaped when viewed from the top view of the back side 34.

[0064] The base plate 4 can be a common base plate for all submodules 7. Thus, all first compensation layers 31 can be mounted directly on the base plate 4. Alternatively, there can be a base plate 4 for each submodule 7 or for groups of submodules 7.

[0065] Additionally, there can be a second compensation layer 32. The second compensation layer 32 may be directly on the side of the support pillar 5 remote from the first compensation layer 31. All submodules 7 may be mounted on the same second compensation layer 32, or there may be multiple second compensation layers 32 other than those shown.

[0066] As a further option, the chip package 1 can include a cover plate 81 on the second compensation layer 32. For example, the cover plate 81 can be a common plate that covers all of the submodules 7 and can also be the emitter contact for the semiconductor chip 2. Thus, the base plate 4 can be the drain or collector contact. The second compensation layer 32 can apply uniform pressure and clamping force to all of the support posts 5, and can prevent the first compensation layer 31 from being damaged by the sides of the support posts 5.

[0067] As a further option, the chip package 1 may alternatively or additionally include a third compensation layer 33. For example, the third compensation layer 33 is located on a side of the base plate 4 away from the semiconductor chip 2. By having the third compensation layer 33, a uniform pressure and clamping force can be applied to the base plate 4.

[0068] All the compensation layers, i.e., the first compensation layer 31, the second compensation layer 32, and the third compensation layer 33, may have the same inner structure, i.e., the same type of pores 6, the same material, and the same thickness. Therefore, the only difference between the compensation layers 31, 32, and 33 may be their lateral dimensions or side lengths.

[0069] Alternatively, the compensation layers 31, 32, 33 may have different mechanical properties as intended. For example, the second and third compensation layers 32, 33 may be stiffer than the first compensation layer 31 to allow for a larger pressure gradient on the cover plate 81 and / or base plate 4.

[0070] For example, in a direction toward the semiconductor chip 2 and / or perpendicular to the backside 34, the compensation layers 31, 32, 33 each have a Young's modulus of 2 GPa or more and 20 GPa or less. The first compensation layer 31 can be configured for an elastic thickness gradient of at least 50 μm, at least 0.1 mm, or at least 0.3 mm of thickness change per mm of lateral length. That is, a thickness difference of at least 50 μm can be compensated over a distance of 1 mm in a direction parallel to the backside 34. Thus, the semiconductor chip 2 can be packed relatively densely on the first compensation layer 31. The same can be applied to the second and third compensation layers 32, 33 with regard to possible thickness gradients.

[0071] It is possible for only dry contacts to exist in chip package 1. Thus, there are no solder or sintered layers between semiconductor chip 2, compensation layers 31, 32, 33, base plate 4, support posts 5, and cover plate 81, but rather, these components are electrically connected only by pressure. The springs or clamps that provide such pressure may be within chip package 1 or may be external components not shown.

[0072] Otherwise, the same may apply to Figure 5 as to Figures 1 to 4, and vice versa.

[0073] 6 shows a top view of another exemplary embodiment of a chip package 1. On the mounting side 30 there are a plurality of semiconductor chips 2, for example arranged in a regular grid. There may be various types of semiconductor chips 2, such as IGBTs and diodes, with various thicknesses.

[0074] The semiconductor chip 2 may have a side length L. For example, the side length L is at least 0.2 mm and / or at most 2 mm, or at most 2 cm. The distance D between adjacent semiconductor chips 2 may be shorter than the side length L. For example, the distance D may be at least 10%, or at least 25%, and / or at most 100%, at most 80%, or at most 65% of the side length L.

[0075] Otherwise, the same may apply to Figure 6 as to Figures 1 to 5, and vice versa.

[0076] Components shown in the figures preferably follow directly in the order specified, unless indicated otherwise. Components that are not touching in the figures are preferably spaced apart from one another. Where lines are drawn parallel to one another, corresponding surfaces are preferably oriented parallel to one another. Similarly, unless indicated otherwise, the positions of drawn components relative to one another are accurately reproduced in the figures.

[0077] The chip packages described herein are not limited by the description based on the exemplary embodiments, but rather include any novel feature and any combination of features, including specifically any combination of features in the claims, even if that feature or combination of features is not explicitly named in the claims or exemplary embodiments.

[0078] This patent application claims priority from European Patent Application No. 2116 3949.7, the disclosure of which is incorporated herein by reference. [Explanation of symbols]

[0079] List of symbols 1 chip package 2. Semiconductor chips 30 Mounting side 31 First compensation layer 32 Second compensation layer 33 Third compensation layer 34 Flat back side 4 base plates 5 pillars 6 pores 7 Submodules 81 Cover plate 82 Internal holder 83 Module Frame D Distance between semiconductor chips ΔH Height difference between semiconductor chips H Maximum height of semiconductor chip L: Side length of semiconductor chip T is the thickness of the first compensation layer

Claims

1. a plurality of first compensation layers (31) that are electrically conductive, and a second compensation layer (32) that is electrically conductive; - a base plate (4) and a cover plate (81); - a plurality of support columns (5); a plurality of semiconductor chips (2) arranged on and electrically contacted by at least one said first compensation layer (31); A chip package (1) comprising: the first compensation layer (31) and the second compensation layer (32) each comprise a plurality of pores (6) and are elastically deformable such that the first compensation layer (31) and the second compensation layer (32) are configured to compensate for a height difference (ΔH) between the semiconductor chips (2); - the semiconductor chips (2) are grouped in submodules (7), some of the semiconductor chips (2) being arranged on each of the first compensation layers (31) so that each of the submodules (7) comprises exactly one of the first compensation layers (31) and one of the support pillars (5), so that the semiconductor chips (2) are directly located between the first compensation layers (31) and the base plate (4); - each of said first compensation layers (31) is placed directly between said support pillar (5) and said semiconductor chip (2) of each of said sub-modules (7); - the pillars (5) are attached directly to the second compensation layer (32) such that the pillars (5) are located directly between the second compensation layer (32) and the first compensation layer (31); the cover plate (81) is arranged directly on the side of the second compensation layer (32) remote from the sub-modules (7), the cover plate (81) being a common plate covering all the sub-modules (7); - said base plate (4) is also a common plate for all said sub-modules (7); - said first compensation layer (31) and said base plate (4) are configured to be pressed together with said semiconductor chip (2) therebetween with a pressure of between 0.1 MPa and 15 MPa, - in a direction perpendicular to a surface of the base plate (4) on which the semiconductor chip (2) is arranged, the plurality of support posts (5) and the base plate (4) have a Young's modulus that is at least three times greater than the Young's modulus of the first compensation layer (31); the Young's modulus of the second compensation layer (32) and the Young's modulus of the first compensation layer (31) differ from each other by a factor of at least 1.2 and at most 2, and the second compensation layer (32) is harder than the first compensation layer (31); Chip package (1).

2. further comprising a third compensation layer (33); the third compensation layer (33) also comprises the pores (6) and is also elastically deformable so that it is adapted to compensate for the height difference (ΔH) between the semiconductor chips (2); the third compensation layer (33) is applied to the side of the semiconductor chip (2) remote from the first compensation layer (31); A chip package (1) according to claim 1.

3. the first compensation layers (31) each have a mounting side (30) facing the semiconductor chip (2) of each of the sub-modules (7) and a planar back side (34) opposite the mounting side (30); The chip package (1) according to claim 1 or 2, wherein the mounting side (30) and the planar backside (34) are free of the perforations (6).

4. the first compensation layer (31) is of pure copper or pure aluminum; A chip package (1) according to any one of claims 1 to 3.

5. the thickness (T) of said first compensation layer (31) is in each case greater than or equal to 0.2 mm and less than or equal to 5 mm; and the minimum diameter d of said first compensation layers (31) exceeds in each case at least three times said respective thickness (T), and said minimum diameter d of each said first compensation layer (31) is d=(4A / π) ０．５ calculated from the area capacitance A of the major side of each of the first compensation layers (31) when viewed in top view as follows: The chip package (1) according to any one of claims 1 to 4, wherein the chip package (1) is at least one of:

6. the height difference (ΔH) amounts to less than 70% of the thickness (T) of the first compensation layer (31); A chip package (1) according to claim 5.

7. The height difference (ΔH) is less than 30% of the maximum height (H) of the semiconductor chip (2); A chip package (1) according to any one of claims 1 to 6.

8. - said pores (6) have at least one of the following shapes: cylindrical, elliptical, cylindrical with rounded bottom and top; and the aspect ratio of the pores (6) is between 1.5 and 20; The chip package (1) according to any one of claims 1 to 7, wherein the chip package (1) is at least one of:

9. The pores (6) are aligned parallel to one another, with the longest axis of the pores (6) pointing away from the nearest semiconductor chip (2); A chip package (1) according to claim 8.

10. The pores (6) have an average diameter of 0.1 mm or more and 2 mm or less, The volume ratio of the pores (6) is 5% or more and 80% or less. A chip package (1) according to any one of claims 1 to 9.

11. - said first compensation layers (31) each have a Young's modulus in the direction towards said semiconductor chip (2) of ≧1 GPa and ≦60 GPa; and - said first compensation layers (31) are each configured for a thickness variation of at least 50 μm per mm of lateral length; The chip package (1) according to any one of claims 1 to 10, wherein the chip package (1) is at least one of:

12. - said semiconductor chip (2) is a power semiconductor chip, and said first compensation layers (31) each have a current density of at least 1 A / cm ２ configured for a current density of The chip package (1) according to any one of claims 1 to 11, wherein the chip package (1) is at least one of:

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