Semiconductor module and manufacturing method thereof

Abstract

Provided are: a semiconductor module the thickness of which can be reduced; and a method for manufacturing the same. This method for manufacturing a semiconductor module that includes a plurality of chips comprises: a first chip arrangement step for arranging a first chip; a rewiring layer formation step for forming a rewiring layer that is disposed on one surface side of the first chip and that is electrically connected to a second chip; a second chip arrangement step for arranging the second chip on the other surface side of the rewiring layer, the other surface side being opposite to the rewiring layer surface facing the first chip, at a position overlapping the first chip in the opposing direction; a pillar formation step for forming a pillar that extends from the other surface of the rewiring layer; and a substrate arrangement step for arranging a substrate that is electrically connected to the pillar and the second chip.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor module and a method for manufacturing the same. [Background technology]

[0002] Volatile memories (RAMs) such as DRAMs (Dynamic Random Access Memory) have been widely used as storage devices. DRAMs are required to have higher capacity to accommodate the increasing performance of computing devices (hereinafter referred to as logic chips) and the increasing amount of data. To address this demand, efforts have been made to increase capacity by miniaturizing memory (memory cell arrays, memory chips) and adding cells in a planar manner. However, this type of capacity increase is reaching its limits due to factors such as increased vulnerability to noise caused by miniaturization and increased chip area.

[0003] Therefore, in recent years, technology has been developed to achieve large capacity by stacking multiple planar memories to create a three-dimensional (3D) structure. Furthermore, efforts are being made to increase the speed of data communication between chips (logic chips and memory chips) as the amount of data increases. For example, a semiconductor module in which logic chips and DRAMs are stacked is known (see, for example, Non-Patent Document 1). [Prior art documents] [Non-patent literature]

[0004] [Non-Patent Document 1] Taiwan Semiconductor Manufacturing Company R&D,2016 IEEE 66th Electronic Components and Technology Conference (ECTC) Summary of the Invention [Problem to be solved by the invention]

[0005] In the semiconductor module of Patent Document 1, an SOC (System-on-a-chip) and an LPDDR (Low Power DDR) are stacked in two layers. Furthermore, the SOC does not use flip-chip bumps. This allows for a thin semiconductor module. Therefore, it would be even more desirable if the semiconductor module could be made even thinner.

[0006] The present invention has been made in view of the above-mentioned problems, and has an object to provide a semiconductor module that can be made thinner and a method for manufacturing the same. [Means for solving the problem]

[0007] The present invention relates to a method for manufacturing a semiconductor module including multiple chips, comprising: a first chip placement process for placing a first chip; a rewiring layer formation process for forming a rewiring layer that is placed on one side of the first chip and electrically connected to a second chip; a second chip placement process for placing the second chip on the other side of the rewiring layer opposite to the surface facing the first chip, in a position that overlaps with the first chip in the facing direction; a pillar formation process for forming a pillar extending from the other side of the rewiring layer; and a substrate placement process for placing a substrate that is electrically connected to the pillar and the second chip.

[0008] It is also preferable that the first chip placement process is performed after the rewiring layer formation process, and the second chip placement process, the pillar formation process, and the substrate placement process are performed after the first chip placement process.

[0009] It is also preferable that the second chip placement process and the pillar formation process are performed after the substrate placement process, and that the redistribution layer formation process and the first chip placement process are performed after the second chip placement process and the pillar formation process.

[0010] It is also preferable that the second chip placement process and the pillar formation process are performed after the rewiring layer formation process, and the first chip placement process and the substrate placement process are performed after the second chip placement process and the pillar formation process.

[0011] Preferably, the method further includes, following the first chip placement step, a connection step of electrically connecting the first chip and the rewiring layer.

[0012] The connecting step is preferably a wire bonding step.

[0013] The present invention also relates to a semiconductor module including multiple chips, comprising: a substrate; a second chip arranged on one side of the substrate; a pillar extending from one side of the substrate; a redistribution layer arranged between the substrate and the second chip and electrically connected to the pillar; a first chip arranged on one side of the redistribution layer opposite to the side facing the second chip; and a connection terminal electrically connecting the one side of the redistribution layer to the first chip.

[0014] Preferably, the connection terminals include bonding wires and bonding pads. [Effects of the Invention]

[0015] According to the present invention, it is possible to provide a semiconductor module that can be made thin and a method for manufacturing the same. [Brief explanation of the drawings]

[0016] [Figure 1] 1 is a cross-sectional view showing a semiconductor module according to a first embodiment of the present invention. [Figure 2] 3A to 3C are cross-sectional views showing a process for manufacturing the semiconductor module of the first embodiment. [Figure 3] 3A to 3C are cross-sectional views showing a process for manufacturing the semiconductor module of the first embodiment. [Figure 4]3A to 3C are cross-sectional views showing a process for manufacturing the semiconductor module of the first embodiment. [Figure 5] 3A to 3C are cross-sectional views showing a process for manufacturing the semiconductor module of the first embodiment. [Figure 6] 5A to 5C are cross-sectional views showing a process for manufacturing a semiconductor module according to a second embodiment of the present invention. [Figure 7] 10A to 10C are cross-sectional views showing a process for manufacturing the semiconductor module of the second embodiment. [Figure 8] 10A to 10C are cross-sectional views showing a process for manufacturing a semiconductor module according to a third embodiment of the present invention. [Figure 9] 10A to 10C are cross-sectional views showing a process for manufacturing the semiconductor module of the third embodiment. [Figure 10] 10A to 10C are cross-sectional views showing a process for manufacturing the semiconductor module of the third embodiment. [Figure 11] 10A to 10C are cross-sectional views showing a process for manufacturing the semiconductor module of the third embodiment. [Figure 12] 10A to 10C are cross-sectional views showing a process for manufacturing the semiconductor module of the third embodiment. [Figure 13] 10A to 10C are cross-sectional views showing a process for manufacturing the semiconductor module of the third embodiment. [Figure 14] 10A to 10C are cross-sectional views showing a process for manufacturing the semiconductor module of the third embodiment. [Figure 15] 10A to 10C are cross-sectional views showing a process for manufacturing a semiconductor module according to a fourth embodiment of the present invention. [Figure 16] 10A to 10C are cross-sectional views showing a process for manufacturing the semiconductor module of the fourth embodiment. [Figure 17] 10A to 10C are cross-sectional views showing a process for manufacturing the semiconductor module of the fourth embodiment. [Figure 18] 10A to 10C are cross-sectional views showing a process for manufacturing the semiconductor module of the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0017] A semiconductor module 1 according to each embodiment of the present invention and a method for manufacturing the same will be described below with reference to FIGS. First, an overview of the semiconductor module 1 according to each embodiment will be described.

[0018] The semiconductor module 1 according to each embodiment is, for example, a memory unit including a plurality of stacked memories and a logic chip (e.g., SOC) stacked together. Specifically, the semiconductor module 1 is configured such that the memory unit and the logic chip are stacked in the stacking direction of the stacked memories. In the semiconductor module 1, for example, the memory unit and the logic chip are stacked together with a rewiring layer sandwiched between them. In the following embodiments, the memory unit and the logic chip are arranged with a rewiring layer sandwiched between them to make the semiconductor module 1 thinner. Furthermore, the memory unit and the logic chip are manufactured at the wafer level to enable inexpensive manufacturing of the semiconductor module 1. Note that in the following embodiments, the memory unit and the logic chip are described as a first chip and a second chip. Note that in the following embodiments, the upper side of FIG. 1 will be described as one chip, and the lower side of FIG. 1 will be described as the other chip.

[0019] [First embodiment] Next, a semiconductor module 1 according to a first embodiment of the present invention and a method for manufacturing the same will be described with reference to FIGS. 1, the semiconductor module 1 includes a substrate 11, a second chip 12, pillars 13, a second molded part 14, a rewiring layer 15, a first chip 16, connection terminals 17, and a first molded part 18.

[0020] The substrate 11 is, for example, an organic substrate. The substrate 11 may also be, for example, a rewiring layer. The substrate 11 is, for example, a plate-like body that is rectangular in plan view. The substrate 11 has, for example, an electronic circuit 111 inside. The substrate 11 has solder balls 112 on the other surface opposite to the one surface for electrically connecting to another electronic circuit (not shown).

[0021] The second chip 12 is disposed on, for example, one surface of the substrate 11. In this embodiment, the second chip 12 is, for example, a logic chip (SOC). The second chip 12 is disposed on, for example, one surface of the substrate 11 in an electrically connected state. The second chip 12 is, for example, surface-mounted on, for example, one surface of the substrate 11. The second chip 12 is surface-mounted on, for example, one surface of the substrate 11 by fan-out wafer-level packaging (FOWLP). The second chip 12 has, on the other surface, terminal portions 121 for electrically connecting to the substrate 11.

[0022] The pillars 13 are made of a conductive material (e.g., copper). The pillars 13 extend from one surface of the substrate 11. For example, the pillars 13 extend from one surface of the substrate 11 in an out-of-plane direction. For example, the pillars 13 have a length equal to or greater than the thickness of the second chip 12. For example, the pillars 13 are arranged around the second chip 12. In this embodiment, the pillars 13 are arranged along the in-plane direction of one surface of the substrate 11, sandwiching the second chip 12. The pillars 13 are arranged with one end electrically connected to one surface of the substrate 11.

[0023] Second molded section 14 is made of, for example, a mold resin. Second molded section 14 is disposed on one surface side of substrate 11. Second molded section 14 is made, for example, to have a thickness that matches the height (length) of pillars 13. Second molded section 14 covers second chip 12 and pillars 13 on one surface side of substrate 11. Second molded section 14 is made so that its outer shape matches the rectangular shape of substrate 11 in a plan view.

[0024] The redistribution layer 15 may be formed of, for example, an organic substrate. The redistribution layer 15 has an electronic circuit 151 therein. The redistribution layer 15 is disposed with the second chip 12 sandwiched between it and the substrate 11, and is electrically connected to the pillars 13. The redistribution layer 15 is disposed, for example, on one surface of the substrate 11. The redistribution layer 15 is disposed across the second chip 12 and the pillars 13 in the in-plane direction of the one surface of the substrate 11. In this embodiment, the redistribution layer 15 is formed, for example, in a rectangular shape similar to the substrate 11 in a planar view. Furthermore, the redistribution layer 15 is formed so that its outer shape is the same or approximately the same size as the outer shapes of the substrate 11 and the second molded part 14 in a planar view. The redistribution layer 15 is disposed in a state electrically connected to the other end side of the pillars 13. Furthermore, in this embodiment, the redistribution layer 15 is disposed so that its other surface side contacts one surface side of the second chip 12. The rewiring layer 15 is configured to have a rectangular shape in plan view to match the outer shape of the rectangular substrate 11.

[0025] The first chip 16 is disposed on one surface of the redistribution layer 15 opposite to the surface facing the second chip 12. In this embodiment, the first chip 16 is, for example, a memory unit having a plurality of stacked memories 161. The first chip 16 has, for example, a plurality of stacked memories 161 stacked with the out-of-plane direction of one surface of the redistribution layer 15 as the stacking direction. The first chip 16 also has a plurality of stacked memories 161 whose arrangement positions are shifted in the in-plane direction of one surface of the redistribution layer 15 (in a direction intersecting the stacking direction). The first chip 16 has, for example, a plurality of adjacent stacked memories 161 that are arranged with their positions shifted in the in-plane direction of one surface of the redistribution layer 15. In this embodiment, the first chip 16 has, for example, a plurality of stacked memories 161 that are stacked in order with their positions alternately shifted in one in-plane direction of the redistribution layer 15.

[0026] The connection terminals 17 are made of, for example, a conductive material (for example, copper, gold, or aluminum). The connection terminals 17 are, for example, wires and bonding pads. The connection terminals 17 electrically connect one surface of the redistribution layer 15 to the first chip 16. The connection terminals 17 electrically connect the redistribution layer 15 to the first chip 16 by, for example, wire bonding. The connection terminals 17 are provided, for example, for each stacked memory 161 of the first chip 16. The connection terminals 17 electrically connect, for example, one stacked memory to the redistribution layer 15. In this embodiment, the connection terminals 17 electrically connect one surface of the stacked memory 161 to one surface of the redistribution layer 15.

[0027] First mold part 18 is made of, for example, a mold resin. First mold part 18 is disposed on one surface side of rewiring layer 15. First mold part 18 is made to have a thickness, for example, greater than the height (thickness) of first chip 16 and connection terminals 17 relative to one surface of rewiring layer 15. First mold part 18 covers first chip 16 and connection terminals 17 on one surface side of rewiring layer 15. First mold part 18 is made to have, for example, a rectangular shape in plan view to match the outer shape of rectangular substrate 11.

[0028] Next, the operation of the semiconductor module 1 will be described. The semiconductor module 1 is electrically connected between the substrate 11 and an external electronic circuit via the solder balls 112. The second chip 12 is electrically connected to the substrate 11, and thereby electrically connected to the external electronic circuit. The first chip 16 is electrically connected to the substrate 11 via the connection terminals 17, the rewiring layer 15, and the pillars 13, and thereby electrically connected to the external electronic circuit.

[0029] Next, a method for manufacturing the semiconductor module 1 of this embodiment will be described. The manufacturing method of the semiconductor module 1 includes a first chip placement process, a connection terminal formation process, a first molding portion formation process, a rewiring layer formation process, a second chip placement process, a pillar formation process, a second molding portion formation process, and a substrate placement process.

[0030] In the first chip placement step, the first chip 16 is placed as shown in Fig. 2. Specifically, in the first chip placement step, the stacked memory is stacked on the carrier substrate 100, thereby placing the first chip 16.

[0031] In the connection terminal forming process, connection terminals 17 are formed that are electrically connected to first chip 16. In the connection terminal forming process, bonding pads are arranged on carrier substrate 100. Also, in the connection terminal forming process, the bonding pads are connected to one surface of each stacked memory with wires.

[0032] 3, in the first molding part forming step, a first molding part 18 is formed to cover the connection terminals 17 and the first chip 16. In the first molding part forming step, for example, after the first chip arrangement step and the connection terminal formation step, the first molding part 18 is formed using a molding resin. Then, the carrier substrate 100 is removed.

[0033] 4, in the rewiring layer formation step, rewiring layer 15 is formed, which is disposed on one surface side of first chip 16 and electrically connected to second chip 12. In the rewiring layer formation step, for example, rewiring layer 15 that is electrically connected to connection terminal 17 is formed.

[0034] In the second chip placement process, second chip 12 is placed on the other side of rewiring layer 15 opposite to the surface facing first chip 16, at a position overlapping first chip 16 in the facing direction. In the second chip placement process, second chip 12 is placed on the other side of rewiring layer 15 with terminal portions 121 positioned on the surface opposite to the other side (other side) of rewiring layer 15. In the second chip placement process, second chip 12 is placed at a position overlapping first chip 16 in the out-of-plane direction of rewiring layer 15.

[0035] In the pillar forming process, pillars 13 are formed extending from the other surface of redistribution layer 15. In the pillar forming process, pillars 13 are formed at positions around second chip 12 in the in-plane direction of redistribution layer 15. In this embodiment, in the pillar forming process, a pair of pillars 13 sandwiching second chip 12 therebetween are formed around second chip 12 in the in-plane direction of redistribution layer 15.

[0036] 5, in the second mold portion forming step, second mold portion 14 is formed to cover second chip 12 and pillars 13. In the second mold portion forming step, after the second chip arrangement step and the pillar formation step, second mold portion 14 is formed using a mold resin. Next, the mold resin of second mold portion 14 is ground so that the tip portions of terminal portions 121 of second chip 12 and the tip portions of pillars 13 are exposed.

[0037] In the substrate placement process, a substrate 11 is placed, which is electrically connected to the pillars 13 and the second chip 12. The substrate 11 may be formed using a rewiring layer. Also, in the substrate placement process, solder balls 112 are placed on the other surface side of the substrate 11. In the substrate placement process, terminal portions 121 of the second chip 12 and the pillars 13 are electrically connected to one surface side of the substrate 11.

[0038] Next, the flow of a manufacturing method for the semiconductor module 1 will be described. First, as shown in Fig. 2, a first chip placement step is performed. Then, a connection terminal formation step is performed. Then, a first molding part formation step is performed. Then, as shown in Fig. 3, the carrier substrate 100 is removed.

[0039] 4, the other surface of the first chip 16 and the exposed portions (bonding pads) of the connection terminals 17 are placed face up, and a rewiring layer forming process is performed. Next, a second chip placing process is performed. Next, a pillar forming process is performed.

[0040] 5, a second molding step is carried out, followed by a substrate placement step, thereby completing the manufacture of the semiconductor module 1.

[0041] The semiconductor module 1 according to the first embodiment and the manufacturing method thereof have the following advantages. (1) A method for manufacturing a semiconductor module 1 including multiple chips, the method comprising: a first chip placement step of placing a first chip 16; a rewiring layer formation step of forming a rewiring layer 15 that is placed on one side of the first chip 16 and electrically connected to a second chip 12; a second chip placement step of placing the second chip 12 on the other side of the rewiring layer 15 opposite the side facing the first chip 16, in a position that overlaps with the first chip 16 in the opposing direction; a pillar formation step of forming pillars 13 extending from the other side of the rewiring layer 15; and a substrate placement step of placing a substrate 11 that is electrically connected to the pillars 13 and the second chip 12. This allows for a semiconductor module 1 with a thinner form factor than when either the first chip 16 or the second chip 12 is manufactured as a package. Furthermore, because the method can be manufactured at the wafer level, the method can be manufactured inexpensively.

[0042] [Second embodiment] Next, a semiconductor module 1 according to a second embodiment of the present invention and a manufacturing method thereof will be described with reference to Figures 6 and 7. In the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof will be simplified or omitted. The method for manufacturing a semiconductor module 1 according to the second embodiment differs from the first embodiment in that the first chip placement step is performed after the rewiring layer formation step. The method for manufacturing a semiconductor module 1 according to the second embodiment also differs from the first embodiment in that the second chip placement step, pillar formation step, and substrate placement step are performed after the first chip placement step.

[0043] 6, a rewiring layer forming step is performed on the carrier substrate 100. Next, a first chip placement step and a connection terminal forming step are performed on one surface side of the rewiring layer 15. Next, a first molding portion forming step is performed.

[0044] Next, the carrier substrate 100 is removed as shown in Fig. 7. Next, similarly to the first embodiment, a second chip arrangement step, a pillar formation step, a second mold part formation step, and a substrate arrangement step are performed.

[0045] The semiconductor module 1 according to the second embodiment and the manufacturing method thereof have the following advantages. (2) The first chip placement process is performed after the rewiring layer formation process, and the second chip placement process, pillar formation process, and substrate placement process are performed after the first chip placement process. This allows the semiconductor module 1 to be manufactured easily.

[0046] [Third embodiment] Next, a semiconductor module 1 according to a third embodiment of the present invention and a manufacturing method thereof will be described with reference to Figures 8 to 14. In the third embodiment, the same components as those in the first and second embodiments are denoted by the same reference numerals, and the description thereof will be simplified or omitted. The manufacturing method of the semiconductor module 1 according to the third embodiment differs from the first and second embodiments in that the second chip placement step and the pillar formation step are performed after the substrate placement step. The manufacturing method of the semiconductor module 1 according to the third embodiment also differs from the first and second embodiments in that the redistribution layer formation step and the first chip placement step are performed after the second chip placement step and the pillar formation step.

[0047] First, as shown in Fig. 8, a substrate placement step is performed on carrier substrate 100. Substrate 11 may be formed using a rewiring layer. Next, as shown in Fig. 9, a second chip placement step and a pillar formation step are performed on one surface of substrate 11. Next, as shown in Fig. 10, a second molded portion formation step is performed. Next, the molding resin of second molded portion 14 is ground away so that the tip ends of terminal portions 121 of second chip 12 and the tip ends of pillars 13 are exposed.

[0048] Next, as shown in Fig. 11, a redistribution layer forming process is performed on one surface of the substrate 11, in which a redistribution layer 15 is formed on the substrate 11 so as to sandwich the pillars 13 and the second chip 12 between the substrate 11 and the redistribution layer 15. Next, as shown in Fig. 12, a first chip placement process and a connection terminal formation process are performed on the one surface of the redistribution layer 15. Next, as shown in Fig. 13, a first molding portion formation process is performed. Next, as shown in Fig. 14, the carrier substrate 100 is removed, and solder balls 112 are placed on the other surface of the substrate 11. In this way, the semiconductor module 1 is manufactured.

[0049] The semiconductor module 1 according to the third embodiment and the manufacturing method thereof have the following advantages. (3) The second chip placement process and the pillar formation process are performed after the substrate placement process, and the rewiring layer formation process and the first chip placement process are performed after the second chip placement process and the pillar formation process. This makes it possible to easily manufacture the semiconductor module 1.

[0050] [Fourth embodiment] Next, a semiconductor module 1 according to a fourth embodiment of the present invention and a manufacturing method thereof will be described with reference to Figures 15 to 18. In the fourth embodiment, the same components as those in the first to third embodiments are denoted by the same reference numerals, and the description thereof will be simplified or omitted. The semiconductor module 1 and its manufacturing method according to the fourth embodiment differ from the first to third embodiments in that the second chip placement step and the pillar formation step are performed after the rewiring layer formation step. Also, the semiconductor module 1 and its manufacturing method according to the fourth embodiment differ from the first to third embodiments in that the first chip 16 formation and substrate placement step are performed after the second chip placement step and the pillar formation step.

[0051] First, as shown in FIG. 15 , a rewiring layer forming process is performed on the carrier substrate 100. Next, a second chip arrangement process and a pillar formation process are performed on the rewiring layer 15. Next, as shown in FIG. 16 , a second molding section forming process is performed. Next, the molding resin of the second molding section 14 is ground so that the tip ends of the terminal sections 121 of the second chip 12 and the tip ends of the pillars 13 are exposed. Next, the carrier substrate 100 is removed. Next, as shown in FIG. 17 , one surface of the rewiring layer 15 is turned face up, and a first chip arrangement process and a connection terminal formation process are performed on the rewiring layer 15. Next, as shown in FIG. 18 , a first molding section forming process is performed. Next, the other surface of the second chip 12 is turned face up, and a substrate arrangement process is performed. This completes the manufacture of the semiconductor module 1.

[0052] The semiconductor module 1 according to the fourth embodiment and the manufacturing method thereof have the following advantages. (4) The second chip placement process and the pillar formation process are performed after the rewiring layer formation process, and the first chip 16 formation and substrate placement process are performed after the second chip placement process and the pillar formation process. This allows the semiconductor module 1 to be manufactured easily.

[0053] Although the preferred embodiments of the semiconductor module and the manufacturing method thereof according to the present invention have been described above, the present invention is not limited to the above-described embodiments and can be modified as appropriate. For example, in the above embodiment, the method for manufacturing the semiconductor module 1 may include a singulation step for singulating a plurality of semiconductor modules 1. The method for manufacturing the semiconductor module 1 may include forming a plurality of semiconductor modules 1 at a wafer level and then singulating them. The method for manufacturing the semiconductor module 1 may include forming a plurality of semiconductor modules 1 at a panel level and then singulating them. This allows a plurality of semiconductor modules 1 to be manufactured efficiently.

[0054] In the above embodiment, the first chip 16 is a memory unit, but this is not limiting. The second chip 12 is a logic chip, but this is not limiting. The first chip 16 may be a logic chip, and the second chip 12 may be a memory unit. The multiple stacked memories 161 may be electrically connected by TSVs (Through-Silicon Vias). In this case, the multiple stacked memories 161 may be electrically connected to the substrate 11 or the redistribution layer 15 using microbumps. [Explanation of symbols]

[0055] 1. Semiconductor module 11 Circuit Board 12 Second Chip 13 Pillar 14 Second mold section 15 Redistribution layer 16 First Chip 17 Connection terminal 18 First mold section 112 solder balls

Claims

1. A method for manufacturing a semiconductor module including a plurality of chips, comprising: a first chip placement step of placing a first chip; a rewiring layer forming step of forming a rewiring layer disposed on one surface side of the first chip; a second chip placement step of placing a second chip on the other surface of the rewiring layer opposite to the surface facing the first chip, at a position overlapping the first chip in a direction facing the first chip; a pillar forming step of forming a pillar extending from the other surface of the redistribution layer; a substrate placement step of placing a substrate electrically connected to the pillar and the second chip; Equipped with the first chip placement step is performed after the rewiring layer formation step, the second chip placement step, the pillar formation step, and the substrate placement step are performed after the first chip placement step; A method for manufacturing a semiconductor module.

2. A method for manufacturing a semiconductor module including a plurality of chips, comprising: a first chip placement step of placing a first chip; a rewiring layer forming step of forming a rewiring layer disposed on one surface side of the first chip; a second chip placement step of placing a second chip on the other surface of the rewiring layer opposite to the surface facing the first chip, at a position overlapping the first chip in a direction facing the first chip; a pillar forming step of forming a pillar extending from the other surface of the redistribution layer; a substrate placement step of placing a substrate electrically connected to the pillar and the second chip; Equipped with the second chip placement step and the pillar formation step are performed after the substrate placement step, the redistribution layer forming step and the first chip arranging step are performed after the second chip arranging step and the pillar forming step; A method for manufacturing a semiconductor module.

3. A method for manufacturing a semiconductor module including a plurality of chips, comprising: a first chip placement step of placing a first chip; a rewiring layer forming step of forming a rewiring layer disposed on one surface side of the first chip; a second chip placement step of placing a second chip on the other surface of the rewiring layer opposite to the surface facing the first chip, at a position overlapping the first chip in a direction facing the first chip; a pillar forming step of forming a pillar extending from the other surface of the redistribution layer; a substrate placement step of placing a substrate electrically connected to the pillar and the second chip; Equipped with the second chip arrangement step and the pillar formation step are performed after the rewiring layer formation step, the first chip placement step and the substrate placement step are performed after the second chip placement step and the pillar formation step; A method for manufacturing a semiconductor module.

4. 4. The method for manufacturing a semiconductor module according to claim 1, further comprising, following the first chip placement step, a connection step of electrically connecting the first chip and the rewiring layer.

5. 5. The method for manufacturing a semiconductor module according to claim 4, wherein the connecting step is a wire bonding step.

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