Hybrid bonding contact structure for 3D memory devices

Abstract

To provide a through array contact structure of a 3D memory device and a manufacturing method thereof.SOLUTION: A memory device includes an alternate layer stack arranged on a first substrate. The alternate layer stack is constituted of a first region including an alternate dielectric stack and a second region including an alternate conductor / dielectric stack. The memory device further includes: a barrier structure extended vertically through the alternate layer stack so as to horizontally separate the first region from the second region; a plurality of through array contacts in the first region in which the through array contacts are respectively vertically extended through the alternate dielectric stack; an array interconnection layer brought into contact with the through array contact; a peripheral circuit formed on a second substrate; and a peripheral interconnection layer on the peripheral circuit. The array interconnection layer is combined on the peripheral interconnection layer so that the peripheral circuit is electrically connected to at least one through array contact.SELECTED DRAWING: Figure 3A

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to Chinese Patent Application No. 201710135655.3, filed on March 8, 2017, which is incorporated herein by reference in its entirety.

[0002] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate to three-dimensional (3D) memory devices and methods for fabricating the same. [Background technology]

[0003] Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as memory cell feature sizes approach lower limits, planar processes and manufacturing techniques become more difficult and expensive. As a result, memory densities for planar memory cells approach upper limits.

[0004] A 3D memory architecture can address the density limitations of planar memory cells and includes a memory array and peripheral devices that control signals to and from the memory array. Summary of the Invention [Means for solving the problem]

[0005] Disclosed herein are embodiments of a Through Array Contact (TAC) structure for a 3D memory device, and methods for fabricating the same.

[0006] A three-dimensional (3D) NAND memory device is disclosed that includes an alternating layer stack disposed on a first substrate. The alternating layer stack includes a first region including an alternating dielectric stack with multiple dielectric layer pairs and a second region including an alternating conductor / dielectric stack with multiple conductor / dielectric layer pairs. The 3D NAND memory device further includes a barrier structure extending vertically through the alternating layer stack to laterally separate the first region from the second region, a plurality of through array contacts in the first region, each through array contact extending vertically through the alternating dielectric stack, an array interconnect layer in contact with the plurality of through array contacts, a peripheral circuit formed on the second substrate, and a peripheral interconnect layer on the peripheral circuit. The array interconnect layer is coupled onto the peripheral interconnect layer such that the peripheral circuit is electrically connected to at least one of the plurality of through array contacts.

[0007] In some embodiments, the array interconnect layer is disposed on the alternating layer stack at an end of the alternating layer stack opposite the first substrate, hi some other embodiments, the array interconnect layer is disposed on a surface of the first substrate opposite the alternating layer stack.

[0008] The array interconnect layer includes at least one first interconnect structure embedded in a first dielectric layer, the peripheral interconnect layer includes at least one second interconnect structure embedded in a second dielectric layer, and the peripheral circuit is electrically connected to at least one of the plurality of through array contacts via the at least one first interconnect structure and the at least one second interconnect structure.

[0009] The barrier structure is composed of silicon oxide and silicon nitride. Each of the plurality of dielectric layer pairs is composed of a silicon oxide layer and a silicon nitride layer, and each of the plurality of conductor / dielectric layer pairs is composed of a metal layer and a silicon oxide layer. The number of the plurality of dielectric layer pairs is at least 32, and the number of the plurality of conductor / dielectric layer pairs is at least 32.

[0010] The 3D NAND memory device further includes a plurality of slit structures extending vertically and laterally along the word line direction through the alternating conductor / dielectric stack, respectively, to divide the alternating conductor / dielectric stack into a plurality of memory fingers.

[0011] In some embodiments, the barrier structure extends laterally along the word line direction, and the first region is separated from the second region by the barrier structure and sandwiched between two adjacent slit structures.

[0012] In some embodiments, the barrier structure extends laterally along a bit line direction that is different from the word line direction and may be orthogonal to the word line direction to laterally separate the first region from the second region.

[0013] In some embodiments, the width of the first region surrounded by the barrier structure in the bit line direction is greater than the distance between two adjacent slit structures.

[0014] In some embodiments, a first region surrounded by a barrier structure is sandwiched between two top selective gate staircase regions in the word line direction. At least two top layers of the alternating conductor / dielectric stack away from the first substrate in each top select gate staircase region have a staircase structure. At least one conductive layer on the staircase structure in the top select gate staircase region is configured to interconnect top select gates above the alternating conductor / dielectric stack in the second region and on both sides of the first region surrounded by the barrier structure in the word line direction. The at least two first regions are surrounded by corresponding barrier structures, and each first region extends parallel along the bit line direction.

[0015] The 3D NAND memory device further includes a plurality of barrier structures surrounding the plurality of first regions from the second region such that the plurality of first regions are aligned in the bit line direction, each of the plurality of first regions being sandwiched between two adjacent slit structures in the bit line direction, and the plurality of first regions being aligned to form at least two columns in the bit line direction.

[0016] In some embodiments, at least one slit structure sandwiched between two adjacent barrier structures in the bit line direction includes a gap, and the at least one slit structure is configured to interconnect word lines of adjacent memory fingers of the plurality of memory fingers.

[0017] In some embodiments, the first region is separated from the staircase structure on the edge of the alternating conductor / dielectric layer stack along the bit line direction by a barrier structure. The opening in the barrier structure is at the edge of the alternating layer stack along the bit line direction. The width of the first region in the bit line direction is greater than the distance between two adjacent slit structures. Alternatively, the width of the first region in the bit line direction is less than the maximum distance between two adjacent slit structures in the staircase structure on the edge of the alternating layer stack along the bit line direction.

[0018] The 3D NAND memory device further includes a plurality of dummy channel structures adjacent to the barrier structure, each dummy channel structure extending vertically through the alternating conductor / dielectric stack.

[0019] Another aspect of the present disclosure provides a method of forming a three-dimensional (3D) NAND memory device, the method including: forming, on a first substrate, an alternating dielectric stack comprising a plurality of dielectric layer pairs, each of the plurality of dielectric layer pairs including a first dielectric layer and a second dielectric layer different from the first dielectric layer; and forming at least one barrier structure each extending vertically through the alternating dielectric stack, the at least one barrier structure separating the alternating dielectric stack into at least one first region and a second region laterally surrounded by at least the barrier structure. The method further includes forming a plurality of slits and replacing a first dielectric layer in a second portion of the alternating dielectric stack with a conductor layer through the slits to form an alternating conductor / dielectric stack comprising a plurality of conductor / dielectric layer pairs; depositing a conductive material into the slits to form a plurality of slit structures; forming a plurality of through array contacts in the first region, each through array contact extending vertically through the alternating dielectric stack; forming an array interconnect layer in contact with the plurality of through array contacts; and bonding the array interconnect layer to a peripheral interconnect layer on the second substrate such that at least one of the plurality of through array contacts is electrically connected to peripheral circuitry on the second substrate.

[0020] In some embodiments, forming the array interconnect layer includes forming at least one first interconnect structure in a first dielectric layer located on the alternating layer stack at an end of the alternating layer stack opposite the first substrate, hi some other embodiments, forming the array interconnect layer includes forming at least one first interconnect structure in a first dielectric layer located on a surface of the first substrate opposite the alternating layer stack.

[0021] The method further includes forming a peripheral circuit on the second substrate before bonding the array interconnect layer to the peripheral interconnect layer; forming the peripheral interconnect layer on the peripheral circuit such that at least one second interconnect structure in the peripheral interconnect layer is electrically connected to the peripheral circuit; and arranging the array interconnect layer and the peripheral interconnect layer such that at least one first interconnect structure corresponds to at least one second interconnect structure, respectively.

[0022] The method further includes, before the step of forming the slits, forming a plurality of doped regions in the first substrate such that each slit structure contacts a corresponding doped region.

[0023] The method further includes laterally forming a plurality of slit structures extending along the word line direction to divide the alternating conductor / dielectric stack into a plurality of memory fingers.

[0024] The method further includes forming two parallel barrier structures laterally to extend along the word line direction such that the first region is separated from the second region by the two parallel barrier structures and sandwiched between two adjacent slit structures.

[0025] The method further includes forming a barrier structure extending laterally along a bitline direction different from the wordline direction to laterally separate the first region from the second region.

[0026] The method further includes forming a barrier structure to extend laterally along a bit line direction that is orthogonal to the word line direction.

[0027] The method further includes forming the barrier structure such that a width in the bit line direction of the first region surrounded by the barrier structure is greater than a distance between two adjacent slit structures.

[0028] The method further includes forming a stair structure in the alternating dielectric stack adjacent to the barrier structure.

[0029] The method further includes forming at least one conductive layer on the staircase structure adjacent to the barrier structure to interconnect upper select gates on either side of the first region above the alternating conductor / dielectric stack in the second region and both surrounded by the barrier structure in the word line direction.

[0030] The method further includes forming at least two barrier structures surrounding at least two first regions extending parallel along the bit line direction.

[0031] The method further includes forming a plurality of barrier structures surrounding the plurality of first regions aligned in the bit line direction from the second region such that each of the plurality of first regions is sandwiched between two adjacent slit structures in the bit line direction.

[0032] The method further includes forming the plurality of barrier structures such that the plurality of first regions surrounded by the plurality of barrier structures are arranged in at least two columns in a bit line direction.

[0033] The method further includes forming a gap in at least one slit structure sandwiched by two adjacent barrier structures in the bit line direction to interconnect word lines of adjacent memory fingers.

[0034] The method further includes forming a barrier structure to separate a first region in the staircase structure at an edge of the alternating stack, the opening in the barrier structure being at the edge of the alternating layer stack along a bitline direction different from the wordline direction.

[0035] The method further includes forming the barrier structure such that a width of the first region in the bit line direction is greater than a distance between two adjacent slit structures.

[0036] The method further includes forming the barrier structure such that a width of the first region in the bit line direction is smaller than a maximum distance between two adjacent slit structures in the staircase structure.

[0037] The method further includes forming a plurality of dummy channel structures adjacent to the barrier structure, each dummy channel structure extending vertically through the alternating conductor / dielectric stack.

[0038] Other aspects of the present disclosure will be apparent to those skilled in the art in view of the specification, claims, and drawings of the present disclosure.

[0039] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the present disclosure and, together with the detailed description, serve to further explain the principles of the disclosure and to enable those skilled in the art to make and use the disclosure. [Brief explanation of the drawings]

[0040] [Figure 1] 1 is a schematic diagram in plan view of an exemplary 3D memory device according to some embodiments of the present disclosure. FIG. [Figure 2] 1 is a schematic enlarged plan view of a region of a 3D memory device including an exemplary bitline through array contact region according to some embodiments of the present disclosure. [Figure 3A] 1A-1C show schematic enlarged plan views of areas of a 3D memory device including various exemplary word line through array contact areas according to some embodiments of the present disclosure. [Figure 3B] 1A-1C show schematic enlarged plan views of areas of a 3D memory device including various exemplary word line through array contact areas according to some embodiments of the present disclosure. [Figure 3C] 1A-1C show schematic enlarged plan views of areas of a 3D memory device including various exemplary word line through array contact areas according to some embodiments of the present disclosure. [Figure 3D]1A-1C show schematic enlarged plan views of areas of a 3D memory device including various exemplary word line through array contact areas according to some embodiments of the present disclosure. [Figure 4A] 1A-1C are schematic enlarged plan views of areas of a 3D memory device including various exemplary stepped through-array contact regions according to some embodiments of the present disclosure. [Figure 4B] 1A-1C are schematic enlarged plan views of areas of a 3D memory device including various exemplary stepped through-array contact regions according to some embodiments of the present disclosure. [Figure 5A] 1A-1D illustrate schematic cross-sectional views of an exemplary 3D memory device at several stages of fabrication according to some embodiments of the present disclosure. [Figure 5B] 1A-1D illustrate schematic cross-sectional views of an exemplary 3D memory device at several stages of fabrication according to some embodiments of the present disclosure. [Figure 6A] 1 is a flow diagram of an exemplary method for forming a 3D memory device according to some embodiments of the present disclosure. [Figure 6B] 1 is a flow diagram of an exemplary method for forming a 3D memory device according to some embodiments of the present disclosure. [Figure 7A] 6A-6B are schematic cross-sectional views of an exemplary 3D memory device at several stages of fabrication in the method illustrated in FIGS. 6A-6B according to some embodiments of the present disclosure. [Figure 7B] 6A-6B are schematic cross-sectional views of an exemplary 3D memory device at several stages of fabrication in the method illustrated in FIGS. 6A-6B according to some embodiments of the present disclosure. [Figure 7C] 6A-6B are schematic cross-sectional views of an exemplary 3D memory device at several stages of fabrication in the method illustrated in FIGS. 6A-6B according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0041] Embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0042] While specific configurations and arrangements are described, it should be understood that this is done for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the present disclosure. It will also be apparent to those skilled in the art that the present disclosure can be used in a variety of other applications.

[0043] It should be noted that references herein to "one embodiment," "embodiment," "exemplary embodiment," "some embodiments," and the like indicate that the described embodiment may include a particular feature, structure, or characteristic, but not all embodiments necessarily include this particular feature, structure, or characteristic. Also, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is within the knowledge of one of ordinary skill in the art to also provide such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly stated.

[0044] Generally, terminology can be understood, at least in part, from how it is used in context. For example, as used herein, the term "one or more" can be used in a singular sense to describe any feature, structure, or characteristic, or in a plural sense to describe any combination of features, structures, or characteristics, depending, at least in part, on the context. Similarly, terms such as "a," "an," or "the" can be understood to convey singular or plural usage, again, depending, at least in part, on the context.

[0045] It should be readily understood that the meanings of "on," "above," and "over" in this disclosure are to be interpreted in their broadest terms, whereby "on" not only means "directly on" something, but can also mean "on" something with an intermediate feature or layer therebetween, and "above" or "above" not only means "above" or "above" something, but can also mean "on" or "above" something without an intermediate feature or layer therebetween (i.e., directly on top of something).

[0046] Additionally, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to facilitate describing the relative relationship of one element or feature to another as shown in the figures. This spatially relative terminology is intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may otherwise be oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0047] As used herein, the term "substrate" refers to a material onto which subsequent layers of material are applied. The substrate itself may be patterned. The material applied on top of the substrate may be patterned or may remain unpatterned. Additionally, substrates can be composed of a wide array of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made from a non-conductive material such as glass, plastic, or a sapphire wafer.

[0048] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer can extend across the entire underlying or superimposed structure, or it can have an extent that is smaller than the extent of the underlying or superimposed structure. Furthermore, a layer can be a uniform continuous structure or a region of a non-uniform continuous structure having a thickness that is less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal planes, between continuous structures, or at upper and lower surfaces. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a single layer and can include one or more layers within it and / or have one or more layers on, above, and / or below it. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (in which contacts, interconnect lines, and / or vias are formed) and one or more dielectric layers.

[0049] As used herein, the term "nominal" refers to a desired or target value of a characteristic or parameter for a component or process operation established during the design phase of a product or process, along with a range of values ​​above and / or below the desired value. The range of values ​​may be due to slight variations or tolerances in the manufacturing process. As used herein, the term "about" indicates a value of a given quantity that may vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "about" can indicate, for example, a value of a given quantity that varies within a range of 10% to 30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0050] As used herein, the term "3D memory device" refers to a semiconductor device having vertically oriented strings of memory cell transistors (i.e., regions herein such as "memory strings," such as NAND strings) on a substrate that is laterally oriented so that the memory strings extend perpendicular to the substrate. As used herein, the term "vertical" nominally means perpendicular to the sides of the substrate.

[0051] Various embodiments according to the present disclosure provide 3D memory devices having a through array contact (TAC) structure for memory arrays (also referred to herein as "array devices"). The TAC structure allows contacts between memory and various peripheral circuits and / or devices (e.g., page buffers, latches, decoders, etc.) to be fabricated in a limited number of steps (e.g., in a single step or two steps), thereby reducing process complexity and manufacturing costs. The disclosed TAC is formed through a stack of alternating dielectric layers, which may make etching to form through holes therein easier compared to a stack of alternating conductor and dielectric layers.

[0052] The TAC can provide vertical interconnections between stacked array devices and peripheral devices (e.g., for power buses and metal routing), thereby reducing metal levels and shrinking die sizes. In some embodiments, the TAC can interconnect with various lines in upper and / or lower conductive layers, which is suitable for 3D memory architectures in which array devices and peripheral devices formed on different substrates are formed sequentially or joined in a face-to-face manner by hybrid bonding. In some embodiments, the TAC in the through array contact structures disclosed herein is formed through a stack of alternating dielectric layers, which may make etching to form through holes therein easier compared to a stack of alternating conductor and dielectric layers, thereby reducing process complexity and manufacturing costs.

[0053] 1 illustrates a schematic diagram in a plan view of an exemplary 3D memory device 100 according to some embodiments of the present disclosure. The 3D memory device 100 can include multiple channel structure regions (e.g., memory planes, memory blocks, memory fingers, etc., which will be described in detail in connection with various figures below), while one or more TAC structures can be formed between two adjacent channel structure regions (e.g., two channel structure regions next to each other).

[0054] 1, the 3D memory device 100 may include four or more memory planes 110, and each memory plane 110 may include multiple memory blocks 115. It should be noted that the arrangement of the memory planes 110 in the 3D memory device 100 and the arrangement of the memory blocks 115 in each memory plane 100 shown in FIG. 1 is used as an example only and is not intended to limit the scope of the present disclosure.

[0055] The TAC structure may include one or more bit line (BL) TAC regions 160 sandwiched between two adjacent memory blocks 115 in the bit line direction of the 3D memory device (labeled "BL" in the figures) and extending along the word line direction of the 3D memory device (labeled "WL" in the figures), one or more word line (WL) TAC regions 170 sandwiched between two adjacent memory blocks 115 in the word line direction (WL) and extending along the bit line direction (BL), and one or more staircase structure (SS) TAC regions 180 located at the edge of each memory plane 110.

[0056] In some embodiments, the 3D memory device 100 may include a plurality of contact pads 120 arranged in a row on the edge of the 3D memory device 100. The interconnect contacts may be used to electrically interconnect the 3D memory device 100 to any suitable device and / or interface to provide driving power, receive control signals, transmit response signals, etc.

[0057] Figure 2 shows an expanded plan view of region 130 shown in Figure 1 including exemplary bit line (BL) TAC regions 160 of a 3D memory device. Figures 3A-3D show expanded plan views of region 140 shown in Figure 1 including various exemplary word line (WL) TAC regions 170 of a 3D memory device. Figures 4A and 4B show expanded plan views of region 150 shown in Figure 1 including various exemplary staircase structure (SS) TAC regions 180 of a 3D memory device.

[0058] 2, an expanded plan view of region 130 shown in FIG. 1 is shown, including an exemplary bit line (BL) TAC region of a 3D memory device according to some embodiments of the present disclosure. Region 200 of the 3D memory device (i.e., region 130 as shown in FIG. 1) can include two channel structure regions 210 (e.g., adjacent memory blocks 115 in the BL direction) and a bit line (BL) TAC region 233 (e.g., BL TAC region 160 as shown in FIG. 1).

[0059] The channel structure region 210 can include an array of channel structures 212, each part of a NAND string including multiple stacked memory cells. The channel structures 212 extend through multiple conductive and dielectric layer pairs arranged along a direction perpendicular to the plan view, also referred to as a direction perpendicular to the surface of the substrate of the 3D memory device, and / or along a "vertical direction" (shown in cross section in connection with FIG. 5, described in detail below).

[0060] A plurality of conductor / dielectric layer pairs is also referred to herein as an "alternating conductor / dielectric stack." The number of conductor / dielectric layer pairs in the alternating conductor / dielectric stack (e.g., 32, 64, or 96) can set the number of memory cells in the 3D memory device 100. The conductive and dielectric layers in the alternating conductor / dielectric stack alternate in the vertical direction. In other words, except for those at the top or bottom of the alternating conductor / dielectric stack, each conductive layer can be flanked by two dielectric layers on either side, and each dielectric layer can be flanked by two conductive layers on either side.

[0061] The conductive layer may be composed of a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon (polysilicon), doped silicon, silicide, or any combination thereof. The dielectric layer may be composed of a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the conductive layer is composed of a metal layer such as W, and the dielectric layer is composed of silicon oxide.

[0062] In some embodiments, the BL TAC region 233 may be sandwiched by two adjacent channel structure regions 210 in the BL direction and may extend in the WL direction. The TAC region 233 may be defined by a barrier structure 224 in association with an edge of the BL TAC region 233 of a 3D memory device. A plurality of TACs 226 may be formed in the BL TAC region 233, and the BL TAC region 233 is laterally surrounded by the barrier structure 224 and the edge of the BL TAC region 233. In some embodiments, the plurality of TACs 226 in the BL TAC region 233 may penetrate an alternating dielectric stack for switching routing and reducing bit line capacitance.

[0063] The alternating dielectric stack can include multiple dielectric layer pairs arranged along a vertical direction perpendicular to the surface of the substrate of the 3D memory device (shown in cross section in connection with FIG. 5 , described in detail below). Each dielectric layer pair includes a first dielectric layer and a second dielectric layer different from the first dielectric layer. In some embodiments, the first dielectric layer and the second dielectric layer include silicon nitride and silicon oxide, respectively. The first dielectric layer in the alternating dielectric stack can be the same as the dielectric layer in the alternating conductor / dielectric stack described above. In some embodiments, the number of dielectric layer pairs in the alternating dielectric stack is the same as the number of conductor / dielectric layer pairs in the alternating conductor / dielectric stack.

[0064] 2, each channel structure region 210 may include one or more slit structures 214 each extending in the WL direction. At least some of the slit structures 214 may function as a common source contact for the array of channel structures 212 in the channel structure region 210. The slit structures 214 may also divide the 3D memory device into multiple memory fingers 242 and / or dummy memory fingers 246. A top select gate cut 255 may be disposed in the center of each memory finger 242 to divide a top select gate (TSG) of the memory finger into two parts. The top select gate cut 255 may be composed of a dielectric material, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0065] In some embodiments, dummy channel structures 222 are formed in portions of channel structure region 210, for example, in dummy memory fingers 246 adjacent to BL TAC region 233 in the BL direction. Dummy channel structures 222 can provide mechanical support for the memory array structure. Dummy memory fingers 246 have no memory functionality, and therefore bit lines and associated interconnect lines are not formed in dummy memory fingers 246.

[0066] 3A, an expanded plan view of region 140 shown in FIG. 1 is shown, including an exemplary word line (WL) TAC region of a 3D memory device according to some embodiments of the present disclosure. Region 300A of the 3D memory device (i.e., region 140 as shown in FIG. 1) can include a channel structure region 320, a word line (WL) TAC region 372 (e.g., WL TAC region 170 as shown in FIG. 1), and a top select gate (TSG) staircase region 330.

[0067] 3A , the channel structure region 320 can include an array of channel structures 312, each including multiple stacked memory cells. TSG staircase regions 330 can be disposed on either side of the channel structure region 320 and adjacent to a WL TAC region 372 in a plan view. That is, the WL TAC region 372 is sandwiched between two TSG staircase regions 330 in the WL direction. The WL TAC region 372 can be defined by a barrier structure 324. A plurality of TACs 326 used for switching routing and reducing word line capacitance can be formed within the WL TAC region 372, which is laterally surrounded by the barrier structure 324.

[0068] In some embodiments, dummy channel structures 322 are formed outside of WL TAC regions 372 to provide mechanical support for the memory array structure. It is understood that dummy channel structures 322 may be formed in any region outside of WL TAC regions 372, for example, within TSG staircase regions 330 and along the edges of channel structure regions 320 adjacent to TSG staircase regions 330. Note that channel structures 312 and dummy channel structures 322 penetrate alternating conductor / dielectric stacks, while TAC 326 penetrates alternating dielectric stacks.

[0069] In some embodiments, a plurality of slit structures 314 each extending in the W-L direction can divide the 3D memory device into a plurality of memory fingers 342, 344. At least some of the slit structures 314 can function as a common source contact for the array of channel structures 312 in the channel structure region 320. The sidewalls of the slit structures 314 can contain a dielectric material, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The fill material of the slit structures 314 can include a conductive material, including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon (polysilicon), doped silicon, silicide, or any combination thereof.

[0070] An upper select gate cut 355 may be disposed in the center of each memory finger 342, 344 to divide the upper select gate (TSG) of the memory finger into two portions. The upper select gate cut 355 may be composed of a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0071] It should be noted that the width of the WL TAC region 372 in the BL direction can be greater than the width of each memory finger 342 or 344. That is, the barrier structure 324 in the BL direction can span at least two adjacent slit structures 314. Therefore, the conductive layer in the channel structure region 320 in the memory finger 344 can be completely blocked by the barrier structure 324. Therefore, the upper select gates of the channel structures 312 between the two channel structure regions 320 in the memory fingers 344 on either side of the WL TAC region 372 are not interconnected by the upper conductive layer in the alternating conductor / dielectric stack.

[0072] To interconnect the upper select gates of the channel structures 312 between the two channel structure regions 320 in the memory fingers 344 on either side of the WL TAC region 372, the TSG staircase region 330 may include one or more conductive lines (not shown in FIG. 3A ) formed in a staircase structure (e.g., in the top 2-4 levels) to electrically interconnect the upper select gates of the channel structures 312 between the two channel structure regions 320 in the memory fingers 344 separated by the WL TAC region 372.

[0073] For example, the slit structure 314 cut by the WL TAC region 372 can extend into the TSG staircase region 330. The top two conductive layers in the alternating conductor / dielectric stack can have a one-sided staircase structure. One or more interconnect layers having contacts can be formed on the one-sided staircase structure to provide electrical interconnection between the upper select gates of the channel structures 312 in the channel structure region 320 separated by the WL TAC region 372 and the upper select gates of the channel structures 312 of the memory fingers 344.

[0074] Therefore, by introducing TSG staircase regions 330 that interconnect the upper select gates on both sides of the WL TAC region 372, the WL TAC region 372 can extend along the BL direction to provide a size sufficient to encompass a desired number of TACs 326. Furthermore, each memory plane 110 can include multiple WL TAC regions 372 arranged in the WL direction, as shown in FIG. 1 . That is, multiple memory blocks 115 may be arranged in the WL direction within each memory plane 110.

[0075] 3B, an expanded plan view of region 140 shown in FIG. 1 is shown, including another exemplary word line (WL) TAC region of a 3D memory device according to some alternative embodiments of the present disclosure. Region 300B of the 3D memory device (i.e., region 140 as shown in FIG. 1) can include a channel structure region 320 and a dummy channel region 350 surrounding word line (WL) TAC region 372 (e.g., WL TAC region 170 as shown in FIG. 1).

[0076] 3B, the channel structure region 320 can include an array of channel structures 312, each including multiple stacked memory cells. A dummy channel region 350 is sandwiched between two channel structure regions 320 in the WL direction. A WL TAC region 372 is surrounded by the dummy channel region 350. The WL TAC region 372 can be defined by a barrier structure 324. Multiple TACs 326 can be formed within the WL TAC region 372, which is laterally surrounded by the barrier structure 324.

[0077] In some embodiments, dummy channel structures 322 are formed outside of WL TAC regions 372 to provide mechanical support to the memory array structure. It is understood that dummy channel structures 322 may be formed in any region outside of WL TAC regions 372, for example, within dummy channel regions 350 and along the edges of channel structure regions 320 adjacent to dummy channel regions 350. Note that channel structures 312 and dummy channel structures 322 penetrate alternating conductor / dielectric stacks, while TAC 326 penetrates alternating dielectric stacks.

[0078] In some embodiments, a plurality of slit structures 314 each extending in the WL direction can divide the 3D memory device into a plurality of memory fingers 342, 344. A top select gate cut 355 can be disposed in the center of each memory finger 342, 344 to divide a top select gate (TSG) of the memory finger into two parts.

[0079] It should be noted that the width of the WL TAC region 372 in the BL direction can be greater than the width of each memory finger 342 or 344. That is, the barrier structure 324 in the BL direction can span at least two adjacent slit structures 314. Therefore, the conductive layer in the channel structure region 320 in the memory finger 344 can be completely blocked by the barrier structure 324. Therefore, the upper select gates of the channel structures 312 between the two channel structure regions 320 in the memory fingers 344 on either side of the WL TAC region 372 are not interconnected by the upper conductive layer in the alternating conductor / dielectric stack.

[0080] Therefore, in some embodiments related to such a design of the WL TAC region 372, one memory plane 110 may include only two memory blocks 115 in the WL direction. The WL TAC region 372 is sandwiched between two memory blocks (i.e., the channel structure region 320 as shown in FIG. 3B ), while the outer side of the channel structure region 320 in the WL direction may have a staircase structure (not shown in FIG. 3B ). Therefore, the upper select gates of the channel structures 312 between the two channel structure regions 320 in the memory fingers 344 on either side of the WL TAC region 372 may be interconnected by using a staircase structure on the edge of the memory plane 110 of the 3D NAND device. Such a design may be suitable for zigzag word line decoder (X-DEC) routing.

[0081] 3C, an expanded plan view of region 140 shown in FIG. 1 is shown, including another exemplary word line (WL) TAC region of a 3D memory device according to some alternative embodiments of the present disclosure. Region 300C of the 3D memory device (i.e., region 140 as shown in FIG. 1) can include a channel structure region 320 and a dummy channel region 350 surrounding a plurality of word line (WL) TAC regions 376.

[0082] 3C , in some embodiments, a plurality of slit structures 314 each extending in the WL direction can divide the 3D memory device into a plurality of memory fingers 342. A top select gate cut 355 can be disposed in the center of each memory finger 342 to divide a top select gate (TSG) of the memory finger into two parts.

[0083] The channel structure region 320 can include an array of channel structures 312, each including a plurality of stacked memory cells. A dummy channel region 350 is sandwiched between two channel structure regions 320 in the WL direction. A plurality of WL TAC regions 376 arranged in a row along the BL direction are surrounded by the dummy channel regions 350. Each WL TAC region 376 can be defined by a barrier structure 324. A plurality of TACs 326 can be formed within each WL TAC region 376, and the WL TAC region 376 is laterally surrounded by the barrier structure 324.

[0084] In some embodiments, the width of each WL TAC region 376 in the BL direction can be smaller than the width of each memory finger 342. That is, the barrier structure 324 of each WL TAC region 376 can be located between two adjacent slit structures 314. Because the barrier structure 324 of each WL TAC region 376 does not completely block the conductive layer in the dummy channel region 350, the upper select gates of the channel structures 312 between the two channel structure regions 320 in each memory finger 342 on either side of the WL TAC region 376 can be interconnected by the upper conductive layer in the alternating conductor / dielectric stack in the dummy channel region 350.

[0085] In some embodiments, dummy channel structures 322 are formed outside of WL TAC regions 376 to provide mechanical support for the memory array structure. It is understood that dummy channel structures 322 may be formed in any region outside of WL TAC regions 376, for example, within dummy channel regions 350 and along the edges of channel structure regions 320 adjacent to dummy channel regions 350. Note that channel structures 312 and dummy channel structures 322 penetrate alternating conductor / dielectric stacks, while TAC 326 penetrates alternating dielectric stacks.

[0086] Therefore, by disposing one WL TAC region 376 in each memory finger 342, the upper conductive layer in the alternating conductor / dielectric stack does not need to be blocked by the WL TAC region 376. Thus, no additional structure is required to further interconnect the upper select gates of the channel structures 312 between the two channel structure regions 320 in each memory finger 342 on either side of the WL TAC region 376. Therefore, multiple WL TAC regions 376 can be disposed in each memory finger 342 along the WL direction. That is, the memory 110 can include multiple memory blocks 115 in the WL direction.

[0087] 3D , an expanded plan view of region 140 shown in FIG. 1 is shown, including another exemplary word line (WL) TAC region of a 3D memory device according to some alternative embodiments of the present disclosure. Region 300D of the 3D memory device (i.e., region 140 as shown in FIG. 1) can include a channel structure region 320 and a dummy channel region 350 surrounding a plurality of word line (WL) TAC regions 376.

[0088] 3D , in some embodiments, a plurality of slit structures 314, 316 each extending in the WL direction can divide the 3D memory device into a plurality of memory fingers 342. In some embodiments, the slit structure 314 can extend all the way in the WL direction through two or more channel structure regions 320 and one or more dummy channel regions 350. As shown in FIG. 3D , at least one slit structure 316 can include a gap 318 in the dummy channel region 350. An upper select gate cut 355 can be disposed in the center of each memory finger 342 to divide an upper select gate (TSG) of the memory finger into two portions.

[0089] The channel structure region 320 can include an array of channel structures 312, each including a plurality of stacked memory cells. A dummy channel region 350 is sandwiched between two channel structure regions 320 in the WL direction. A plurality of WL TAC regions 376 arranged in a row along the BL direction are surrounded by the dummy channel regions 350. Each WL TAC region 376 can be defined by a barrier structure 324. A plurality of TACs 326 can be formed within each WL TAC region 376, and the WL TAC region 376 is laterally surrounded by the barrier structure 324.

[0090] In some embodiments, the width of each WL TAC region 376 in the BL direction can be smaller than the width of each memory finger 342. That is, the barrier structure 324 of each WL TAC region 376 can be located between two adjacent slit structures 314. Because the barrier structure 324 of each WL TAC region 376 does not completely block the conductive layer in the dummy channel region 350, the upper select gates of the channel structures 312 between the two channel structure regions 320 in each memory finger 342 on either side of the WL TAC region 376 can be interconnected by the upper conductive layer in the alternating conductor / dielectric stack in the dummy channel region 350.

[0091] In some embodiments, dummy channel structures 322 are formed outside of WL TAC regions 376 to provide mechanical support for the memory array structure. It is understood that dummy channel structures 322 may be formed in any region outside of WL TAC regions 376, for example, within dummy channel regions 350 and along the edges of channel structure regions 320 adjacent to dummy channel regions 350. Note that channel structures 312 and dummy channel structures 322 penetrate alternating conductor / dielectric stacks, while TAC 326 penetrates alternating dielectric stacks.

[0092] In some embodiments, one or more slit structures 316 may include gaps 318 in the dummy channel regions 350. Word lines in adjacent memory fingers 342 may be interconnected by using conductive lines passing through the gaps 318. For example, as shown in FIG. 3D , slit structures 314 at the edge of a memory block 115 may extend all the way in the WL direction through two or more channel structure regions 320 and one or more dummy channel regions 350, while slit structures 316 inside each memory block 115 may include one or more gaps 318 in their corresponding dummy channel regions 350. Thus, all upper select gates and / or word lines in the same memory block 115 may be interconnected without additional structures.

[0093] Therefore, by disposing the WL TAC regions 376 in the memory fingers 342 and providing the gaps 318 in the slit structures 316, the upper conductive layers in the alternating conductor / dielectric stacks may not be blocked by the WL TAC regions 376, and the word lines in adjacent memory fingers 342 may be interconnected. Therefore, multiple WL TAC regions 376 may be disposed in each memory finger 342 along the WL direction. That is, the memory 110 may include multiple memory blocks 115 in the WL direction. Such a structure may have a high integration level and a simple layout that may be easily manufactured.

[0094] 4A, an enlarged plan view of region 150 shown in FIG. 1 is shown, including an exemplary staircase structure (SS) TAC region of a 3D memory device according to some embodiments of the present disclosure. Region 400A of the 3D memory device (i.e., region 150 as shown in FIG. 1) can include a channel structure region 420, a staircase region 410, and a staircase structure (SS) TAC region 482.

[0095] The channel structure region 420 can include an array of channel structures 412, each including a plurality of stacked memory cells. The staircase region 410 can include a staircase structure and an array of wordline contacts 432 formed on the staircase structure. In some embodiments, an SS TAC region 482 is within the staircase region 410. The SS TAC region 482 can be defined by a barrier structure 424, alone or in conjunction with an edge of the staircase region 410 of a 3D memory device. A plurality of TACs 426 can be formed within the SS TAC region 482, which is laterally surrounded by at least the barrier structure 424.

[0096] 4A , in some embodiments, a plurality of slit structures 414, 416 each extending in the WL direction can divide the 3D memory device into a plurality of memory fingers 442, 444. In some embodiments, the slit structures 414 can extend in the WL direction into at least a portion of the staircase region 410. At least some of the slit structures 416 can include one or more gaps 418 within the staircase region 410. A top select gate cut 455 can be disposed in the center of each memory finger 442, 444 to divide the top select gate (TSG) of the memory finger into two portions.

[0097] In some embodiments, one or more slit structures 416 may include a gap 418 in the staircase region 410. The word line contacts 432 in adjacent memory fingers 442 may be interconnected by using a conductive line passing through the gap 418. For example, as shown in FIG. 4A , the slit structures 414 at the edge of the memory block 115 may extend all the way in the WL direction through the channel structure region 420 and the staircase region 410, while the slit structures 416 inside each memory block 115 may include one or more gaps 418 in the staircase region 410. Thus, all word line contacts 432 in the same memory block 115 may be interconnected without additional structures.

[0098] Note that the width of the SS TAC region 482 in the BL direction can be greater than the width of each memory finger 442, 444. That is, the barrier structure 424 in the BL direction can span at least two adjacent slit structures 414. Because the SS TAC region 482 occupies a portion of the area of ​​the staircase region 410 corresponding to the memory finger 444 that is completely blocked by the barrier structure 424, the staircase structure in the SS TAC region 482 is used to form the TAC 426 rather than forming the word line contact 432 for the memory finger 444. Therefore, the staircase structure corresponding to the memory finger 444 on the other side of the memory plane 110 (not shown in FIG. 4B ) may be used to form the word line contact 432 rather than the SS TAC region 482.

[0099] Thus, in some embodiments related to such a design of SS TAC regions 482, the SS TAC regions 482 on either side of memory plane 110 do not extend in the WL direction. That is, one memory finger corresponds to at most one SS TAC region 482. Such a design may be suitable for zigzag word line decoder (X-DEC) routing. Furthermore, in some embodiments related to the design of SS TAC regions 482, and for the same reasons related to the design of WL TAC regions 372 described above in connection with FIG. 3B , the SS TAC regions 482 and the WL TAC regions 372 do not extend in the WL direction. That is, one memory finger corresponds to at most either one SS TAC region 482 or one WL TAC region 372.

[0100] 4B, an enlarged plan view of region 150 shown in FIG. 1 is shown, including another exemplary staircase structure (SS) TAC region of a 3D memory device according to some alternative embodiments of the present disclosure. Region 400B of the 3D memory device (i.e., region 150 as shown in FIG. 1) can include a channel structure region 420, a staircase region 410, and multiple staircase structure (SS) TAC regions 484.

[0101] The channel structure region 420 can include an array of channel structures 412, each including a plurality of stacked memory cells. The staircase region 410 can include a staircase structure and an array of wordline contacts 432 formed on the staircase structure. In some embodiments, SS TAC regions 484 are formed within the staircase region 410. Each SS TAC region 484 can be defined by a barrier structure 424, either alone or in conjunction with an edge of the staircase region 410 of the 3D memory device. A plurality of TACs 426 can be formed within the SS TAC region 482, which is laterally surrounded by at least the barrier structure 424.

[0102] As shown in FIG. 4B , in some embodiments, a plurality of slit structures 414 each extending in the WL direction in the channel structure region 420 can divide the 3D memory device into a plurality of memory fingers 442. An upper select gate cut 455 can be disposed in the center of each memory finger 442 to divide the upper select gate (TSG) of the memory finger into two parts. In some embodiments, the slit structures 414 can extend in the WL direction within at least a portion of the staircase region 410. In some embodiments, the staircase region 410 may further include a plurality of slit structures 416 that are not aligned with the slit structures 414 in the WL direction. That is, the distance between adjacent slit structures in the staircase region 410 can be non-uniform. Some adjacent slit structure pairs can have a first distance that is greater than a second distance between other adjacent slit structure pairs.

[0103] In some embodiments, each SS TAC region 484 may be located between adjacent slit structure pairs having a first distance. That is, the width of the SS TAC region 484 in the BL direction may be smaller than the first distance. Therefore, in addition to the space occupied by the SS TAC region 484, the staircase region 410 between such adjacent slit structure pairs having the first distance may have extra space to form word line contacts 432.

[0104] 5A-5B, schematic cross-sectional views of an exemplary 3D memory device at several stages of fabrication according to some embodiments of the present disclosure are shown. FIG. 5A shows two separated chips 500A and 500B before bonding, while FIG. 5B shows a 3D memory device 500C formed by bonding a first chip 500A and a second chip 500B together. Note that the 3D memory device 500C shown in FIG. 5B may be part of a non-monolithic 3D memory device in which components (e.g., peripheral devices and array devices) may be formed separately on different substrates. For example, the 3D memory device 500C may be region 130, region 140, or region 150 described above in connection with FIG. 1.

[0105] 5A, the first chip 500A may include a first substrate 570 and an array device above the first substrate 570. Note that X and Y axes have been added to FIGS. 5A and 5B to further illustrate the spatial relationships of components in the chips 500A and 500B and the 3D memory device 500C. The first substrate 570 includes a first bonding interface 534, which may be a lateral bottom surface extending laterally in the X direction (e.g., a WL direction or a BL direction).

[0106] As used herein, whether one component (e.g., a layer or device) is "on," "above," or "below" another component (e.g., a layer or device) of a semiconductor device (e.g., an array device) is determined relative to the substrate of the semiconductor device (e.g., first substrate 570) in the Y direction (vertical direction) when the substrate is placed (or otherwise disposed) in the lowest plane of the semiconductor device in the Y direction. The cross-sectional views of the 3D memory device shown in Figures 5A and 5B are along the plane of the BL direction and the Y direction. The same concepts for describing spatial relationships apply throughout this disclosure.

[0107] The first substrate 570 can be used to support the array device and can include an array interconnect layer 530 and a base substrate 540. The array interconnect layer 530 can be a back-end-of-line (BEOL) interconnect layer including one or more interconnect structures 532 embedded in a dielectric layer. The interconnect structures 532 can include, but are not limited to, contacts, single-layer / multi-layer vias, conductive lines, plugs, pads, and / or any other suitable conductive structures made of conductive materials including, but not limited to, W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The dielectric layer can be composed of a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. One or more portions of the interconnect structures 532 can be exposed on a first bonding surface 534 of the first substrate 570.

[0108] The base substrate 540 may be composed of any suitable semiconductor material, which may include silicon (e.g., single crystal silicon, polycrystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any suitable combination thereof. In some embodiments, the base substrate 540 is a thinned substrate (e.g., a semiconductor layer), which has been thinned by grinding, wet / dry etching, chemical mechanical polishing (CMP), or any combination thereof. In some embodiments, the base substrate 540 may be a single-layer substrate or a multi-layer substrate, such as a single crystal single-layer substrate, a polycrystalline silicon (polysilicon) single-layer substrate, a polysilicon and metal multi-layer substrate, etc.

[0109] Additionally, one or more openings 542 may be formed in an area of ​​the base substrate 540 corresponding to one or more through array contact (TAC) structures of the array device. In some embodiments, the TACs 526 may pass through the one or more openings 542 to electrically connect with one or more interconnect structures 532 in the array interconnect layer 530. In some other embodiments, conductive plugs (not shown) passing through the one or more openings 542 may be used to electrically connect the TACs to the one or more interconnect structures 532 in the array interconnect layer 530. Note that the one or more openings 542 may be filled with a dielectric material to insulate the TACs 526 and / or the conductive plugs.

[0110] In some embodiments, the array device may be a NAND flash memory device in which the memory cells are provided in an array of channel structures (not shown in FIGS. 5A and 5B ) extending in the Y-direction above a substrate 570. The array device may include a plurality of channel structures extending through an alternating conductor / dielectric stack 580 that includes a plurality of pairs of conductive layers 580A and dielectric layers 580B. The number of conductor / dielectric layer pairs in the alternating conductor / dielectric stack 580 (e.g., 32, 64, or 96) can set the number of memory cells in the 3D memory device.

[0111] The conductive layers 580A and dielectric layers 580B in the alternating conductor / dielectric stack 580 alternate in the Y direction. In other words, except at the top or bottom of the alternating conductor / dielectric stack 580, each conductive layer 580A may be adjacent to two dielectric layers 580B on either side, and each dielectric layer 580B may be adjacent to two conductive layers 580A on either side. The conductive layers 580A may each have the same thickness or different thicknesses. Similarly, the dielectric layers 580B may each have the same thickness or different thicknesses. The conductive layers 580A may be composed of a conductive material, including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon (polysilicon), doped silicon, silicide, or any combination thereof. Dielectric layer 580B can be composed of a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, conductive layer 580A is composed of a metal layer, such as W, and dielectric layer 580B is composed of silicon oxide.

[0112] In some embodiments, the array device further includes slit structures 514. Each slit structure 514 extends in the Y direction through the alternating conductor / dielectric stack 580. The slit structures 514 may also extend laterally (i.e., approximately parallel to the substrate) to separate the alternating conductor / dielectric stack 580 into multiple blocks. The slit structures 514 may include slits filled with a conductive material, including, but not limited to, W, Co, Cu, Al, a silicide, or any combination thereof. The slit structures 514 may further include a dielectric layer having any suitable dielectric material between the filled conductive material and the alternating conductor / dielectric stack 580 to electrically insulate the filled conductive material from the surrounding conductive layer 580A within the alternating conductor / dielectric stack 580. As a result, the slit structures 514 can separate the 3D memory device 500 into multiple memory fingers (e.g., as shown in FIGS. 2, 3A-3D, and 4A-4B in plan views).

[0113] In some embodiments, the slit structure 514 functions as a source contact for channel structures in the same memory finger that share the same array common source. Thus, the slit structure 514 may be referred to as a "common source contact" for multiple channel structures. In some embodiments, the base substrate 540 includes a doped region 544 (comprising a p-type dopant or an n-type dopant at a desired doping level), and the bottom end of the slit structure 514 is in contact with the doped region 544 of the base substrate 540.

[0114] In some embodiments, the alternating dielectric stack 560 may be located within a region laterally surrounded by the barrier structure 516 on the base substrate 540. The alternating dielectric stack 560 may include multiple dielectric layer pairs. For example, the alternating dielectric stack 560 may be formed by an alternating stack of a first dielectric layer 560A and a second dielectric layer 560B that is different from the first dielectric layer 560A. In some embodiments, the first dielectric layer 560A is composed of silicon nitride, and the second dielectric layer 560B is composed of silicon oxide. The second dielectric layer 560B in the alternating dielectric stack 560 may be the same as the dielectric layer 580B in the alternating conductor / dielectric stack 580. In some embodiments, the number of dielectric layer pairs in the alternating dielectric stack 560 is the same as the number of conductor / dielectric layer pairs in the alternating conductor / dielectric stack 580.

[0115] In some embodiments, the barrier structures 516 extend in the Y direction to laterally separate the alternating conductor / dielectric stacks 580 and the alternating dielectric stacks 560. That is, the barrier structures 516 can be a boundary between the alternating conductor / dielectric stacks 580 and the alternating dielectric stacks 560. The alternating dielectric stacks 560 can be at least laterally surrounded by the barrier structures 516. In some embodiments, the barrier structures 516 are closed shapes (e.g., rectangular, square, circular, etc.) in plan view to completely surround the alternating dielectric stacks 560. For example, as shown in FIGS. 3A-3D , the barrier structures 324 are rectangular in plan view to completely surround the alternating dielectric stacks in the WL TAC regions 372, 376. In some embodiments, the barrier structures 516 are not closed shapes in plan view but can surround the alternating dielectric stacks 560 along with one or more edges of the array device. For example, as shown in Figures 4A and 4B, a barrier structure 424 surrounds the alternating dielectric stacks in the SS TAC regions 482, 484 as well as the edges of the 3D memory device.

[0116] As shown in FIG. 5A , the first chip 500A further includes multiple TACs 526, each extending in the Y direction through the alternating dielectric stack 560. The TACs 526 may be formed only within an area laterally surrounded by at least the barrier structure 516, which includes multiple dielectric layer pairs. That is, the TACs 526 may extend vertically through the dielectric layers (e.g., the first dielectric layer 560A and the second dielectric layer 560B), but not through any of the conductive layers (e.g., the conductive layer 580A). Each TAC 526 may extend through the entire thickness of the alternating dielectric stack 560 (e.g., all of the dielectric layer pairs in the Y direction). In some embodiments, the TACs 526 further penetrate the base substrate 540 through openings 542 to electrically contact the interconnect structure 532.

[0117] The TACs 526 can carry electrical signals to and from array devices, such as portions of a power bus, using shortened interconnect routing. In some embodiments, the TACs 526 can provide electrical connections (not shown in FIGS. 5A and 5B ) between the array devices and peripheral devices through one or more interconnect structures 532. The TACs 526 can also provide mechanical support for the alternating dielectric stacks 560. Each TAC 526 can include a vertical opening that is filled with a conductive material, including but not limited to W, Co, Cu, Al, doped silicon, silicide, or any combination thereof, through the alternating dielectric stacks 560. In some embodiments, when the TACs 526 are formed by the alternating dielectric stacks 560 (surrounded by a dielectric layer), no additional dielectric layer between the TACs 526 and the alternating dielectric stacks 560 is required for isolation.

[0118] The second chip 500B may include a second substrate 510 and a peripheral interconnect layer 520 on the second substrate 510. The second substrate 510 may be composed of any suitable semiconductor material, which may include silicon (e.g., single crystal silicon, polycrystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any suitable combination thereof. The second substrate 510 may be a single-layer substrate or a multi-layer substrate, such as a single-crystal single-layer substrate, a polycrystalline silicon (polysilicon) single-layer substrate, a polysilicon and metal multi-layer substrate, etc. In some embodiments, the second substrate 510 is a thinned substrate (e.g., a semiconductor layer), which has been thinned by grinding, wet / dry etching, chemical-mechanical polishing (CMP), or any combination thereof.

[0119] One or more peripheral circuits (not shown in FIGS. 5A and 5B ) can be formed on the second substrate 510. The one or more peripheral circuits can include any suitable digital, analog, and / or mixed-signal peripheral circuitry used to facilitate operation of the 3D memory device. For example, the one or more peripheral circuits can include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder), a latch, a sense amplifier, a driver, a charge pump, a current or voltage reference, or any active or passive components of a circuit (e.g., a transistor, a diode, a resistor, or a capacitor). In some embodiments, the one or more peripheral circuits can be formed on the second substrate 510 using complementary metal-oxide-semiconductor (CMOS) technology (also known as a “CMOS chip”).

[0120] In some embodiments, the peripheral interconnect layer 520 may include one or more interconnect structures 522 embedded in a dielectric layer to electrically connect one or more peripheral circuits to array devices above the first substrate 570. The one or more interconnect structures 522 may include any suitable conductive structures, including but not limited to, contacts, single / multi-layer vias, conductive layers, plugs, pads, and / or any other suitable conductive structures, made of conductive materials including, but not limited to, W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The dielectric layer of the peripheral interconnect layer 520 may have a single or multi-layer structure and includes dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, or any combination thereof.

[0121] The second chip 500B can include a second bonding interface 524, which can be a lateral top surface extending laterally in the X direction (a horizontal direction, e.g., the WL direction or the BL direction). In some embodiments, the first bonding surface 534 of the first chip 500A is bonded to the second bonding surface 524 of the second chip 500B. That is, the peripheral interconnect layer 520 and the array interconnect 530 can be bonded in a face-to-face manner. Thus, as shown in FIG. 5B , the first chip 500A and the second chip 500B can be bonded at a bonding interface 555 to form a 3D memory device 500C.

[0122] A bonding interface 555 is between the peripheral interconnect layer 520 and the array interconnect 530. That is, the bonding interface 555 can be between two dielectric layers, such as between a silicon nitride layer and a silicon oxide layer. The bonding interface 555 can also be between two conductive layers, such as between two metal (e.g., Cu) layers. In some embodiments, the bonding interface includes both an interface between dielectric layers and an interface between conductive layers. In some embodiments, one or more interconnect structures 532 in the first chip 500A and one or more interconnect structures 522 in the second chip 500B can contact each other at the bonding interface 555 to electrically interconnect one or more TACs 526 in the first chip 500A with peripheral circuitry in the second chip 500B.

[0123] 5A, the bonding interface 555 may be formed by chemical bonding between, for example, the dielectric and / or conductive layers on either side of the bonding interface, the first bonding surface 534 and the second surface 524. The bonding interface 555 may be formed by physical interaction (e.g., interdiffusion) between the dielectric and / or conductive layers on either side of the bonding interface. In some embodiments, the bonding interface is formed after plasma or heat treatment of the surfaces on either side of the bonding interface prior to the bonding process.

[0124] By using the bonding through contact holes on the back side of the first substrate, a pad layer of the interconnect structure can be formed on the back side of the first substrate corresponding to the array device. Because the pad layer is formed on the back side of the first substrate instead of the peripheral region of the first substrate, the size of the 3D memory device can be reduced and the integration degree of the 3D memory device can be improved.

[0125] 6A-6B, a schematic flow diagram of an exemplary method for forming a 3D memory device according to some embodiments of the present disclosure is shown. It should be understood that the operations shown in FIGS. 6A-6B are not exhaustive, and that other operations may be performed before, after, or between any of the operations shown. FIGS. 7A-7C show schematic cross-sectional views of another exemplary 3D memory device at several fabrication stages of the method shown in FIGS. 6A-6B according to some other embodiments of the present disclosure.

[0126] 6A, a flow diagram of an exemplary method 600A for forming an array device and array interconnect layer according to some embodiments is shown. As shown in FIG. 6A, method 600A begins at operation 604, where an alternating dielectric stack is formed on a first substrate. In some embodiments, the first substrate may be any suitable semiconductor substrate having any suitable structure, such as a single crystal single layer substrate, a polycrystalline silicon (polysilicon) single layer substrate, a polysilicon and metal multilayer substrate, etc.

[0127] A plurality of dielectric layer pairs (also referred to herein as "alternating dielectric stacks") can be formed on a first substrate. The alternating dielectric stack can include an alternating stack of a first dielectric layer and a second dielectric layer different from the first dielectric layer. In some embodiments, each dielectric layer pair includes a layer of silicon nitride and a layer of silicon oxide. In some embodiments, there are more layers in the alternating dielectric stack than dielectric layer pairs made of different materials and having different thicknesses. The alternating dielectric stack can be formed by one or more thin film deposition processes, including, but not limited to, CVD, PVD, ALD, or any combination thereof.

[0128] The method 600A proceeds to operation 606, where a staircase structure is formed on one or more edges of the alternating dielectric stack. In some embodiments, a trim etch process can be performed on at least one side of the alternating dielectric stack (laterally) to form the staircase structure on multiple levels. Each level can include one or more dielectric layer pairs having alternating first and second dielectric layers.

[0129] The method 600A proceeds to operation 608 of forming a plurality of channel structures and one or more barrier structures. Each channel structure and each barrier structure can extend vertically through the alternating dielectric stack.

[0130] In some embodiments, the fabrication process for forming the channel structure includes forming a channel hole extending vertically through the alternating dielectric stack, for example, by wet etching and / or dry etching. In some embodiments, the fabrication process for forming the channel structure further includes forming a semiconductor channel and a memory film between the semiconductor channel and the dielectric layer pair in the alternating dielectric stack. The semiconductor channel may be composed of a semiconductor material such as polysilicon. The memory film may be a composite dielectric layer, such as a combination of a tunneling layer, a recording layer, and a blocking layer.

[0131] The tunneling layer can be composed of a dielectric material, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. Electrons or holes from the semiconductor channel can tunnel through the tunneling layer to the recording layer. The recording layer can include a material that stores charge for memory operation. Recording layer materials include, but are not limited to, silicon nitride, silicon oxynitride, a combination of silicon oxide and silicon nitride, or any combination thereof. The blocking layer can be composed of a dielectric material, including, but not limited to, silicon oxide, or a combination of silicon oxide / silicon nitride / silicon oxide (ONO). The blocking layer can further include a high-k dielectric layer, such as an aluminum oxide (Al2O3) layer. The semiconductor channel and memory film can be formed by one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof.

[0132] In some embodiments, the manufacturing process that forms the barrier structures is similar to and simultaneous with the manufacturing process that forms the channel structures, thereby reducing manufacturing complexity and cost, hi some other embodiments, the channel structures and barrier structures are formed in different manufacturing steps, whereby the barrier structures can be filled with a material that is different from the material that fills the channel structures.

[0133] In some embodiments, the fabrication process for forming the barrier structure includes forming vertically extending trenches through the alternating dielectric stack, for example, by wet etching and / or dry etching. After the trenches are formed through the alternating dielectric stack, one or more thin film deposition processes may be performed to fill the trenches with a dielectric material, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, silicon oxide / silicon nitride / silicon oxide (ONO), aluminum oxide (Al2O3), or the like, or any combination thereof.

[0134] By forming one or more barrier structures, the alternating dielectric stack can be separated into two types of regions: one or more inner regions, each laterally surrounded by at least a barrier structure (along with the edges of the alternating dielectric stack in some embodiments), and outer regions in which channel structures and / or word line contacts can be formed. Note that each inner region corresponds to an opening in the first substrate.

[0135] In some embodiments, at least one inner region can be used to form a BL TAC structure as described above in connection with Figure 2. Accordingly, the barrier structure surrounding such an inner region can include two parallel barrier walls extending along the WL direction.

[0136] In some embodiments, at least one inner region can be used to form a BL TAC structure as described above in connection with Figure 3A or 3B. Accordingly, the barrier structure surrounding such an inner region can have a rectangular shape. The width of the barrier structure in the BL direction can be greater than the distance between two adjacent slit structures formed in a subsequent process.

[0137] In some embodiments, at least one inner region can be used to form a BL TAC structure as described above with reference to Figure 3C or 3D. Accordingly, the barrier structure surrounding such an inner region can have a rectangular shape. The width of the barrier structure in the BL direction can be smaller than the distance between two adjacent slit structures formed in a subsequent process.

[0138] In some embodiments, at least one inner region can be used to form an SS TAC structure as described above in connection with FIG. 4A. Accordingly, the barrier structure separating such inner regions can have a rectangular shape with one open edge facing the edge of the staircase structure. The width of the barrier structure in the BL direction can be greater than the distance between two adjacent slit structures formed in subsequent processes.

[0139] In some embodiments, at least one inner region can be used to form an SS TAC structure, as described above in connection with FIG. 4B. Accordingly, the barrier structure separating such inner regions can have a rectangular shape with one open edge facing the edge of the staircase structure. The width of the barrier structure in the BL direction can be smaller than the maximum distance between two adjacent slit structures formed in the staircase region in subsequent processes.

[0140] In some embodiments, the dummy channel structure can be formed simultaneously with the channel structure. The dummy channel structure can extend vertically through the alternating layer stack and can be filled with the same material as the channel structure. Unlike the channel structure, contacts are not formed on the dummy channel structure to provide electrical connection with other components of the 3D memory device. Therefore, the dummy channel structure cannot be used to form memory cells in the 3D memory device.

[0141] The method 600A proceeds to operation 610, which involves forming a plurality of slits and replacing a first dielectric layer in a portion of the alternating dielectric stack with a conductive layer through the plurality of slits. For example, first, a plurality of parallel slits extending in the WL direction can be formed by wet and / or dry etching of a dielectric (e.g., silicon oxide and silicon nitride) through the alternating dielectric stack in the outer areas. In some embodiments, a doped region is then formed in the first substrate below each slit, for example, by ion implantation and / or thermal diffusion through the slits. It will be appreciated that, according to some embodiments, the doped region can be formed at an earlier manufacturing stage, for example, before the formation of the slits.

[0142] In some embodiments, the formed slits are used in a gate replacement process (also known as a "word line replacement" process) to replace a first dielectric layer (e.g., silicon nitride) with a conductive layer (e.g., W) in the outer areas of the alternating dielectric stack. Note that gate replacement occurs only in the outer areas of the alternating dielectric stack, but not in the inner areas, due to the formation of a barrier structure. This barrier structure can prevent etching of the first dielectric layer (e.g., silicon nitride) in the inner areas of the alternating dielectric stack, because the barrier structure is a filler material that cannot be etched by the etching step of the gate replacement process.

[0143] As a result, modifying the alternating dielectric stack outside of the region after the gate replacement process will modify the alternating conductor / dielectric stack. Replacement of the first dielectric layer with a conductive layer can be performed by wet etching the first dielectric layer (e.g., silicon nitride) selectively to the second dielectric layer (e.g., silicon oxide) and filling the structure with a conductive layer (e.g., W). The conductive layer can be filled by PVD, CVD, ALD, any other suitable process, or any combination thereof. The conductive layer can be composed of a conductive material, including, but not limited to, W, Co, Cu, Al, polysilicon, silicide, or any combination thereof. The formed alternating conductor / dielectric stack and the remaining alternating dielectric stack can constitute an alternating stack.

[0144] The method 600A proceeds to operation 612, which forms a slit structure by filling (e.g., depositing) a conductive material into the slit by PVD, CVD, ALD, any other suitable process, or any combination thereof. The slit structure may be composed of a conductive material including, but not limited to, W, Co, Cu, Al, polysilicon, silicide, or any combination thereof. In some embodiments, for insulation purposes, a dielectric layer (e.g., a silicon oxide layer) is first formed between the conductive material of the slit structure and a conductive layer surrounding the slit structure in the alternating conductor / dielectric stack. The bottom end of the slit structure may contact the doped region.

[0145] The method 600A proceeds to operation 614, where multiple TACs are formed through the alternating dielectric stack. The TACs may be formed in one or more interior regions by first etching vertical openings (e.g., by wet etching and / or dry etching) and then filling the openings with a conductive material using ALD, CVD, PVD, any other suitable process, or any combination thereof. The conductive material used to fill the localized contacts may include, but is not limited to, W, Co, Cu, Al, polysilicon, silicide, or any combination thereof. In some embodiments, other conductive materials may also be used to fill the openings, which function as barrier layers, adhesion layers, and / or seed layers.

[0146] The TAC can be formed by etching through the entire thickness of the alternating dielectric stack. Because the alternating dielectric stack includes alternating layers of dielectrics, such as silicon oxide and silicon nitride, the openings in the TAC can be formed by deep etching of the dielectric material (e.g., by a deep reactive-ion etching (DRIE) process or any other suitable anisotropic etching process). In some embodiments, the TAC is formed after gate replacement, but by preserving areas of the alternating dielectric stack that are unaffected (not turned into an alternating conductor / dielectric stack) by the gate replacement process, the TAC is formed further through the dielectric layers (without passing through any conductive layers), thereby simplifying the manufacturing process and reducing costs.

[0147] The method 600A proceeds to operation 616, where an array interconnect layer is formed on the alternating stack. The array interconnect layer may be used to transmit electrical signals between the TAC and other portions of the 3D memory device, such as peripheral circuitry. In some embodiments, the fabrication process for forming the array interconnect layer includes forming a dielectric layer, followed by forming a plurality of interconnect structures. One or more of the interconnect structures may each contact the TAC.

[0148] The dielectric layer may include one or more layers of dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The interconnect structures may be composed of, but are not limited to, contacts, single / multi-layer vias, conductive lines, plugs, pads, and / or any other suitable conductive structures made from conductive materials including, but not limited to, W, Co, Cu, Al, doped silicon, silicide, or any combination thereof.

[0149] In some embodiments, a fabrication process for forming an interconnect structure includes forming an opening in a dielectric layer and subsequently filling the opening with a conductive material. The opening in the dielectric layer may be filled with the conductive material by ALD, CVD, PVD, any other suitable process, or any combination thereof. In some embodiments, the fabrication process for forming an interconnect structure further includes forming one or more conductive layers and one or more contact layers in the dielectric layer. The conductive layers and conductor contact layers may be formed by any suitable known BEOL method.

[0150] 6B, a flowchart of an exemplary method 600B of forming peripheral circuitry and a peripheral interconnect layer according to some embodiments is shown. As shown in FIG. 6B, method 600B begins with operation 622 of forming peripheral circuitry on a second substrate. In some embodiments, the second substrate can be any suitable semiconductor substrate having any suitable structure, such as a single-crystal single-layer substrate, a polycrystalline silicon (polysilicon) single-layer substrate, a polysilicon and metal multi-layer substrate, etc.

[0151] The peripheral circuitry may include any suitable peripheral devices formed on the second substrate and any suitable interconnect circuitry between the peripheral devices. One or more peripheral devices and / or interconnect circuitry may be formed by multiple process steps, including, but not limited to, photolithography, dry / wet etch, thin film deposition, thermal growth, implantation, CMP, or any combination thereof.

[0152] The method 600B proceeds to operation 624 with forming a peripheral interconnect layer over the peripheral circuitry. The peripheral interconnect layer may include a dielectric layer above the peripheral circuitry and one or more interconnect structures formed within the dielectric layer. The dielectric layer may include one or more layers of a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The interconnect structures may include, but are not limited to, contacts, single / multi-layer vias, conductive lines, plugs, pads, and / or any other suitable conductive structures made from conductive materials including, but not limited to, W, Co, Cu, Al, doped silicon, silicide, or any combination thereof.

[0153] In some embodiments, the interconnect structure can be formed by using any suitable known middle-end-of-line (MEOL) method. For example, a fabrication process for forming the interconnect structure can include forming an opening in a dielectric layer and subsequently filling the opening with a conductive material. The opening in the dielectric layer can be filled with the conductive material by ALD, CVD, PVD, any other suitable process, or any combination thereof. Additionally, a fabrication process for forming the interconnect structure can include forming one or more conductive layers and one or more contact layers in the dielectric layer. The conductive layers and conductive contact layers can be composed of conductive materials deposited by one or more thin film deposition processes, including, but not limited to, CVD, PVD, ALD, electrolytic plating, electroless plating, or any combination thereof. The fabrication process for forming the conductive layers and contact layers can also include photolithography, CMP, wet / dry etch, or any combination thereof.

[0154] As shown in Figure 7A, a dielectric layer 740 is formed on a second substrate 750, while a plurality of interconnect structures 742 are formed within the dielectric layer 740. Note that peripheral circuitry is not shown in Figure 7A. The plurality of interconnect structures 742 are in electrical contact with the peripheral circuitry.

[0155] Method 600B proceeds to operation 626, which involves placing (or otherwise disposing) the array device (and array interconnect layer) below the first substrate (e.g., by flipping the first substrate upside down), with the array interconnect layer aligned with the peripheral interconnect layer. As shown in FIG. 7A , array interconnect layer 730 may be placed below second silicon substrate 710. TAC 726 may penetrate alternating stack 720. In some embodiments, aligning array interconnect layer 730 with peripheral interconnect layer 740 is performed by aligning interconnect structures 733 in array interconnect layer 730 with interconnect structures 742 in peripheral interconnect layer 740. As a result, interconnect structures 733 can be in electrical contact with interconnect structures 742 when the array device is bonded to peripheral circuitry in a subsequent operation.

[0156] The method 600B proceeds to operation 628, which bonds the array interconnect layer to the peripheral interconnect layer, as shown in FIG. 6B. The array interconnect layer can be bonded to the peripheral interconnect layer by flip-chip bonding the first and second substrates. In some embodiments, the array interconnect layer and the peripheral interconnect layer are bonded by hybrid bonding of the first and second substrates in a face-to-face manner, whereby the array interconnect layer is above and in contact with the peripheral interconnect layer in the resulting 3D memory device.

[0157] Hybrid bonding (also known as "metal / dielectric hybrid bonding") can be a direct bonding technique that simultaneously achieves metal-metal bonding and dielectric-dielectric bonding (e.g., forming a bond between surfaces without the use of an intermediate layer such as solder or adhesive). As shown in Figure 7B, the array interconnect layer 730 can be joined with the periphery interconnect layer 740, thereby forming a bonding interface 734.

[0158] In some embodiments, a treatment process may be used to enhance the bonding strength between the array interconnect layer 730 and the peripheral interconnect layer 740 before or during the bonding process of the two interconnect layers. In some embodiments, each dielectric layer in the array interconnect layer 730 and the peripheral interconnect layer 740 is composed of silicon oxide or silicon nitride. For example, a plasma treatment may be used to treat each surface of the array interconnect layer 730 and the peripheral interconnect layer 740 so that the surfaces of the two interconnect layers form a chemical bond between the two dielectric layers. As another example, a wet process may be used to treat each surface of the array interconnect layer 730 and the peripheral interconnect layer 740 so that the surfaces of the two interconnect layers form a preferred chemical bond to enhance the bonding strength between the two dielectric layers. As yet another example, a thermal process may be performed at a temperature of about 250°C to about 600°C (e.g., 250°C to 600°C). The thermal process may cause interdiffusion between the interconnect structures 733 and 742. As a result, the corresponding interconnect structures 733 and 742 may intermix after the bonding process. In some embodiments, interconnect structures 733 and 742 may each contain Cu.

[0159] The method 600B proceeds to operation 630, where the thinned first substrate is thinned so that the thinned first substrate serves as an upper semiconductor layer of array devices (e.g., NAND strings), as shown in FIG. 6B. As shown in FIG. 7C, the thinned first substrate 710 can be a monocrystalline silicon layer. In some embodiments, after the thinning process, the monocrystalline silicon layer 710 has a thickness of between about 5 nm and about 50 μm (e.g., 5 nm, 50 nm, 500 nm, 5 μm, 50 μm, any range bounded at the lower end by any of these values, or any range defined by any two of these values). The first substrate 710 can be thinned by processes including, but not limited to, wafer grinding, dry etching, wet etching, CMP, any other suitable process, or any combination thereof.

[0160] The method 600B proceeds to operation 632 where a BEOL interconnect layer may be formed above the semiconductor layer, as shown in Figure 6B. As shown in Figure 7C, the BEOL interconnect layer is formed above a first substrate 710. The BEOL interconnect layer may include a dielectric layer 760 overlying the first substrate 710 and a plurality of interconnect structures 762 within the dielectric layer 760.

[0161] In some embodiments, the fabrication process for the interconnect structure 762 may include separate process steps for forming one or more contact layers, conductive layers, and / or pad layers in the dielectric layer. The dielectric layer 760 may be a combination of multiple dielectric layers formed in separate process steps. The interconnect structure 762 may be composed of a conductive material, including, but not limited to, W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. In some embodiments, the fabrication process for the interconnect structure 762 further includes forming one or more openings in the first substrate 710. The one or more openings may correspond to one or more through-array contact TAC structures (e.g., word line (WL) TAC structures as shown in FIG. 2, bit line (BL) TAC structures as shown in FIGS. 3A-3D, and staircase structure (SS) TAC structures as shown in FIGS. 4A-4B). Thus, the one or more interconnect structures 762 penetrate the dielectric layer 760 and the first substrate 710 and are electrically connected to the TAC 726, respectively. Thus, TAC 726 can be used to electrically interconnect external circuits or devices to transmit electrical signals between the bonded array and / or peripheral circuitry and the external circuit or device.

[0162] Various embodiments according to the present disclosure provide 3D memory devices with smaller die sizes, higher device densities, and improved performance compared to other 3D memory devices. By vertically stacking array devices and BEOL interconnects above peripheral circuitry, the density of 3D memory devices can be increased. By providing a memory array with a through array contact (TAC) structure, vertical interconnects between stacked array devices and peripheral devices (e.g., for power buses and metal routing) can be realized to reduce metal levels and shrink die sizes. In some embodiments, the through array contact structures disclosed herein are formed through a stack of alternating dielectric layers, which can be more easily etched to form through holes therein compared to a stack of alternating conductor and dielectric layers, thereby reducing process complexity and manufacturing costs.

[0163] Accordingly, one aspect of the present invention discloses a three-dimensional (3D) NAND memory device including an alternating layer stack disposed on a first substrate. The alternating layer stack can include a first region including an alternating dielectric stack comprising a plurality of dielectric layer pairs and a second region including an alternating conductor / dielectric stack comprising a plurality of conductor / dielectric layer pairs. The 3D NAND memory device further includes a barrier structure extending vertically through the alternating layer stack to laterally separate the first region from the second region, and a plurality of through array contacts in the first region. Each through array contact extends vertically through the alternating dielectric stack. The 3D NAND memory device further includes an array interconnect layer disposed on the alternating layer stack at an end of the alternating layer stack opposite the first substrate. The array interconnect layer includes at least one first interconnect structure electrically connected to at least one through array contact. The 3D NAND memory device further includes a peripheral circuit formed on the second substrate and a peripheral interconnect layer on the at least one peripheral circuit, the peripheral circuit including at least one second interconnect structure electrically connected to the peripheral circuit, and the array interconnect layer is coupled on the peripheral interconnect layer such that the peripheral circuit is electrically connected to at least one of the plurality of array interconnect structures through the at least one first interconnect structure and the at least one second interconnect structure.

[0164] The barrier structure is composed of silicon oxide and silicon nitride. Each of the plurality of dielectric layer pairs is composed of a silicon oxide layer and a silicon nitride layer, and each of the plurality of conductor / dielectric layer pairs is composed of a metal layer and a silicon oxide layer. The number of the plurality of dielectric layer pairs is at least 32, and the number of the plurality of conductor / dielectric layer pairs is at least 32.

[0165] The 3D NAND memory device further includes a plurality of slit structures extending vertically and laterally along the word line direction through the alternating conductor / dielectric stack, respectively, to divide the alternating conductor / dielectric stack into a plurality of memory fingers.

[0166] In some embodiments, the barrier structure extends laterally along the word line direction, and the first region is separated from the second region by the barrier structure and sandwiched between two adjacent slit structures.

[0167] In some embodiments, the barrier structure extends laterally along a bit line direction that is different from the word line direction and may be orthogonal to the word line direction to laterally separate the first region from the second region.

[0168] In some embodiments, the width of the first region surrounded by the barrier structure in the bit line direction may be greater than the distance between two adjacent slit structures.

[0169] In some embodiments, the first region surrounded by the barrier structure may be sandwiched between two upper select gate staircase regions in the word line direction. At least the top two layers of the alternating conductor / dielectric stack away from the first substrate in each upper select gate staircase region may have a staircase structure. At least one conductive layer on the staircase structure in the upper select gate staircase region is configured to interconnect upper select gates above the alternating conductor / dielectric stack in the second region and on either side of the first region surrounded by the barrier structure in the word line direction.

[0170] The 3D NAND memory device further includes at least two first regions surrounded by corresponding barrier structures, each first region extending parallel along the bit line direction.

[0171] The 3D NAND memory device further includes a plurality of barrier structures surrounding the plurality of first regions from the second region such that the plurality of first regions are aligned in the bit line direction. Each of the plurality of first regions is sandwiched between two adjacent slit structures in the bit line direction. In some embodiments, the plurality of first regions are aligned to form at least two columns in the bit line direction.

[0172] In some embodiments, at least one slit structure sandwiched between two adjacent barrier structures in the bit line direction includes a gap, and the at least one slit structure is configured to interconnect word lines of adjacent memory fingers of the plurality of memory fingers.

[0173] In some embodiments, the first region is separated from the staircase structure on an edge of the alternating conductor / dielectric layer stack along the bitline direction by a barrier structure, the opening in the barrier structure being at the edge of the alternating layer stack along the bitline direction.

[0174] In some embodiments, the width of the first region in the bit line direction is greater than the distance between two adjacent slit structures.

[0175] In some embodiments, the width of the first region in the bit line direction is smaller than the maximum distance between two adjacent slit structures in the staircase structure on the edge of the alternating layer stack along the bit line direction.

[0176] The 3D memory device may further include a plurality of dummy channel structures adjacent to the barrier structure, each dummy channel structure extending vertically through the alternating conductor / dielectric stack.

[0177] Another aspect of the present disclosure provides a method for forming a three-dimensional (3D) NAND memory device, the method including the steps of: forming an alternating dielectric stack on a first substrate, the alternating dielectric stack comprising a plurality of dielectric layer pairs, each of the plurality of dielectric layer pairs including a first dielectric layer and a second dielectric layer different from the first dielectric layer; forming at least one barrier structure each extending vertically through the alternating dielectric stack, the at least one barrier structure separating the alternating dielectric stack into at least one first region and a second region laterally surrounded by at least the barrier structure; forming a plurality of slits, and replacing the first dielectric layer in a second portion of the alternating dielectric stack with a conductor layer through the slits, to form an alternating conductor / dielectric stack comprising a plurality of conductor / dielectric layer pairs; and forming a plurality of slit structures. The method may include depositing a conductive material into the slits; forming a plurality of through array contacts in the first region, each through array contact extending vertically through the alternating dielectric stack; forming an array interconnect layer on the alternating layer stack and including at least one first interconnect structure electrically connected to at least one through array contact; and coupling the array interconnect layer to a peripheral interconnect layer on the second substrate, the peripheral circuitry being formed on the second substrate and including at least one second interconnect structure electrically connected to at least one of the plurality of peripheral circuits through the at least one first interconnect structure and the at least one second interconnect structure.

[0178] The method may further include, before bonding the array interconnect layer to the peripheral interconnect layer, forming a peripheral circuit on the second substrate; forming a peripheral interconnect layer on the peripheral circuit such that at least one second interconnect structure in the peripheral interconnect layer is electrically connected to the peripheral circuit; and arranging the array interconnect layer and the peripheral interconnect layer such that at least one first interconnect structure corresponds to at least one second interconnect structure, respectively.

[0179] The method may further include, before the step of forming the slits, forming a plurality of doped regions in the first substrate such that each slit structure contacts a corresponding doped region.

[0180] The method may further include laterally forming a plurality of slit structures extending along the word line direction to divide the alternating conductor / dielectric stack into a plurality of memory fingers.

[0181] The method may further include forming two parallel barrier structures laterally to extend along the word line direction such that the first region is separated from the second region by the two parallel barrier structures and is sandwiched between two adjacent slit structures.

[0182] The method may further include forming a barrier structure extending laterally along a bitline direction different from the wordline direction to laterally separate the first region from the second region.

[0183] The method may further include forming a barrier structure to extend laterally along a bit line direction that is orthogonal to the word line direction.

[0184] The method may further include forming the barrier structure such that a width in the bit line direction of the first region surrounded by the barrier structure is greater than a distance between two adjacent slit structures.

[0185] The method may further include forming a staircase structure in the alternating dielectric stack adjacent to the barrier structure.

[0186] The method may further include forming at least one conductive layer on the staircase structure adjacent to the barrier structure to interconnect upper select gates on either side of the first region above the alternating conductor / dielectric stack in the second region and both surrounded by the barrier structure in the word line direction.

[0187] The method may further include forming at least two barrier structures surrounding at least two first regions extending parallel along the bit line direction.

[0188] The method may further include forming a plurality of barrier structures surrounding the plurality of first regions aligned in the bit line direction from the second region such that each of the plurality of first regions is sandwiched between two adjacent slit structures in the bit line direction.

[0189] The method may further include forming the plurality of barrier structures such that the plurality of first regions surrounded by the plurality of barrier structures are arranged in at least two in the bit line direction.

[0190] The method may further include forming a gap in at least one slit structure sandwiched by two adjacent barrier structures in the bit line direction to interconnect word lines of adjacent memory fingers.

[0191] The method can further include forming a barrier structure to separate the first region in the staircase structure at an edge of the alternating stack, and the opening in the barrier structure can be at the edge of the alternating layer stack along a bitline direction that is different from the wordline direction.

[0192] The method may further include forming the barrier structure such that a width of the first region in the bit line direction is greater than a distance between two adjacent slit structures.

[0193] The method may further include forming the barrier structure such that a width of the first region in the bit line direction is smaller than a maximum distance between two adjacent slit structures in the staircase structure.

[0194] The method may further include forming a plurality of dummy channel structures adjacent to the barrier structure, each dummy channel structure extending vertically through the alternating conductor / dielectric stack.

[0195] The foregoing description of specific embodiments sufficiently reveals the general nature of the present disclosure so that others, by applying knowledge within the art, can readily modify and / or adapt such specific embodiments to various uses without undue experimentation without departing from the general concepts of the present disclosure. Therefore, such adaptations and modifications, based on the teaching and guidance provided herein, are intended to be within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the terminology or terminology used herein is for purposes of description and not limitation, as would be interpreted by one of ordinary skill in the art in light of the teaching and guidance.

[0196] The embodiments of the present disclosure are described above using functional building blocks that illustrate the implementation of specific functions and relationships thereof. The boundaries of these functional building blocks are arbitrarily defined herein for ease of explanation. Alternative boundaries may be defined as long as the specific functions and relationships thereof are appropriately performed.

[0197] The Summary and Abstract sections may describe one or more, but not necessarily all, exemplary embodiments of the present disclosure contemplated by the inventors, and are therefore not intended to limit the scope of the disclosure and appended claims in any way.

[0198] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents. [Explanation of symbols]

[0199] 100 3D memory devices, memory 110 Memory Plane 115 memory blocks 120 contact pads 130 areas 140 areas 150 areas 160 bit line (BL) TAC area, BL TAC area 170 Word Line (WL) TAC Area 172 WL TAC area 180 Staircase structure (SS) TAC area 200 areas 210 Channel structure region 212 Channel Structure 214 Slit Structure 222 Dummy Channel Structure 224 Barrier Structure 226 Multiple TACs 233 bit line (BL) TAC area, BL TAC area, TAC area 242 Memory Finger 246 Dummy Memory Finger 255 Upper Select Gate Cut 300A area 300B area 300C area 312 Channel Structure, Channel Structure 314 Slit structure 316 Slit structure 318 Gap 320 Channel Structure Region 322 Dummy Channel Structure 324 Barrier Structure 326 TAC 330 Upper Select Gate (TSG) Staircase Area, TSG Staircase Area 342 Memory Finger 344 Memory Finger 350 Dummy Channel Region 355 Upper Select Gate Cut 372 Word Line (WL) TAC Area, WL TAC Area 376 Word Line (WL) TAC Area, WL TAC Area 400A area 400B area 410 Stairs area 412 Channel Structure 414 Slit Structure 416 Slit structure 418 Gap 420 Channel Structure Region 424 Barrier Structure 426 Multiple TACs, TACs 432 word line contact 442 Memory Finger 444 Memory Finger 482 Staircase structure (SS) TAC area, SS TAC area 484 Staircase structure (SS) TAC area, SS TAC area 455 Upper Select Gate Cut 500 3D memory devices 500A chip, first chip 500B chip, second chip 500C 3D memory device 510 Second substrate 514 Slit structure 516 Barrier Structure 520 Peripheral Interconnect Layer 522 Interconnection Structure 524 Second bonding interface, second bonding surface 526 TAC 530 Array Interconnect Layer 532 Interconnection Structure 534 first bonding interface, first bonding surface 540 base board 542 Opening 555 Bonding Interface 560 Alternating Dielectric Stack 560A First Dielectric Layer 560B Second Dielectric Layer 570 substrate, first substrate 580 Alternating Conductor / Dielectric Stack 580A Conductive Layer 580B dielectric layer 710 second silicon substrate, thinned first substrate, single crystal silicon layer, first substrate 720 Alternating Stacks 726 TAC 730 Array Interconnect Layer 733 Interconnection Structure 740 Dielectric layer, Peripheral interconnect layer 742 Interconnection Structure 750 Second Board 760 Dielectric Layer 762 Interconnection Structure

Claims

1. A substrate, A staircase region including a plurality of first stacks and a plurality of second stacks, each of the plurality of first stacks is disposed on the substrate and includes first and second dielectric layers that are vertically alternating; each of the plurality of second stacks is disposed on the substrate and includes a conductor layer and a third dielectric layer alternately disposed in the vertical direction; The staircase area; a plurality of barrier structures arranged along the bit line direction and laterally separating the first stack from the second stack, a plurality of barrier structures, each of the barrier structures extending vertically through a corresponding one of the plurality of first stacks and including an opening, the openings of the plurality of barrier structures being arranged in the bit line direction; a through array contact extending through one of the first stacks to the substrate; a plurality of dummy channel structures, each extending vertically through one of the second stacks; Equipped with the dummy channel structures include a plurality of columns arranged in the bit line direction, each column including a plurality of dummy channel structures spaced apart in the vertical direction and a word line direction perpendicular to the bit line direction; a three-dimensional (3D) NAND memory device, wherein one of the barrier structures overlaps only two of the plurality of columns of the dummy channel structures in the word line direction;

2. The memory device of claim 1 , wherein the through array contacts are connected to peripheral circuitry.

3. each of the first dielectric layers comprises silicon oxide; each of the second dielectric layers comprises silicon nitride; each of the third dielectric layers comprises silicon oxide; The memory device of claim 1 , wherein each of the conductive layers comprises a metal.

4. the number of layers of the first dielectric layer is at least 32; the number of layers of the second dielectric layer is at least 32; the number of layers of the third dielectric layer is at least 32; The memory device of claim 1 , wherein the number of said conductor layers is at least 32.

5. The memory device of claim 1 , wherein each of the barrier structures comprises silicon oxide and silicon nitride.

6. The memory device of claim 1 , wherein the staircase region includes a staircase structure and an array of wordline contacts formed on the staircase structure.

7. The memory device of claim 6 , wherein the barrier structure separates the first stack and the staircase structure, the staircase structure being on an edge of the second stack.

8. The memory device of claim 1 , further comprising a channel structure region, said channel structure region located on one side of said staircase region.

9. 10. The memory device of claim 8, further comprising a slit structure extending vertically through the second stack, the slit structure extending from the staircase region to the channel structure region and dividing the second stack into a plurality of memory fingers.

10. A memory device as described in claim 9, wherein the opening of each of the barrier structures is at the edge of the corresponding one of the first stacks in the word line direction.

11. 2. The memory device of claim 1, wherein the barrier structure comprises two parallel first sub-barrier structures and a second sub-barrier structure, and ends of the two parallel first sub-barrier structures are connected to the second sub-barrier structure.

12. 1. A method of forming a three-dimensional (3D) NAND memory device, comprising: - forming a substrate; forming an alternating dielectric stack on the substrate, the alternating dielectric stack comprising a dielectric layer pair, the dielectric layer pair comprising a first dielectric layer and a second dielectric layer different from the first dielectric layer; forming a plurality of barrier structures arranged along a bit line direction and laterally separating the alternating dielectric stack into a plurality of first portions and a plurality of second portions, each of the plurality of barrier structures extending vertically through a corresponding one of the plurality of first portions and including an opening, the openings of the plurality of barrier structures being arranged in the bit line direction; replacing the first dielectric layer of the second portion of the alternating dielectric stack with a conductor layer to form an alternating conductor / dielectric stack including the conductor layer and a third dielectric layer; forming a through array contact extending perpendicular to the substrate through one of the first portions of the alternating dielectric stack; forming a plurality of dummy channel structures extending through the alternating conductor / dielectric stack; Including, the dummy channel structures include a plurality of columns arranged in the bit line direction, each column including a plurality of dummy channel structures spaced apart in the vertical direction and a word line direction perpendicular to the bit line direction; The method, wherein one of the barrier structures overlaps only two of the plurality of columns of the dummy channel structures in the word line direction.

13. The method of claim 12 , wherein forming the alternating dielectric stack comprises forming at least 32 dielectric layer pairs in the alternating dielectric stack.

14. prior to the step of replacing the first dielectric layer of the second portion of the alternating dielectric stack with the conductor layer; forming a slit extending vertically through the second portion of the alternating dielectric stack; depositing a conductive material into the slit to form a slit structure; The method of claim 12 further comprising:

15. prior to the step of replacing the first dielectric layer of the second portion of the alternating dielectric stack with the conductor layer; The method of claim 12 , further comprising forming a channel structure extending vertically through the second portion of the alternating dielectric stack.

16. 13. The method of claim 12, wherein the barrier structure comprises two parallel first sub-barrier structures and a second sub-barrier structure, and ends of the two parallel first sub-barrier structures are connected to the second sub-barrier structure.

17. A substrate; A staircase region including a plurality of first stacks and a plurality of second stacks, each of the plurality of first stacks is disposed on the substrate and includes first and second dielectric layers that are vertically alternating; a step region, wherein each of the plurality of second stacks is disposed on the substrate and includes a conductor layer and a third dielectric layer alternately disposed in the vertical direction; a barrier structure aligned along the bit line direction and laterally separating the first stack from the second stack, a plurality of barrier structures, each of the barrier structures extending vertically through a corresponding one of the plurality of first stacks and including an opening, the openings of the plurality of barrier structures being arranged in the bit line direction; a through array contact extending vertically through a corresponding one of the plurality of first stacks, the through array contact being connected to peripheral circuitry; a plurality of dummy channel structures extending vertically through the second stack; Equipped with the dummy channel structures include a plurality of columns arranged in the bit line direction, each column including a plurality of dummy channel structures spaced apart in the vertical direction and a word line direction perpendicular to the bit line direction; a three-dimensional (3D) NAND memory device, wherein one of the barrier structures overlaps only two of the plurality of columns of the dummy channel structures in the word line direction;

18. each of the first dielectric layers comprises silicon oxide; each of the second dielectric layers comprises silicon nitride; each of the third dielectric layers comprises silicon oxide; 20. The memory device of claim 17, wherein each of the conductor layers comprises a metal.

19. the number of layers of the first dielectric layer is at least 32; the number of layers of the second dielectric layer is at least 32; the number of layers of the third dielectric layer is at least 32; 18. The memory device of claim 17, wherein the number of conductor layers is at least 32.

20. 20. The memory device of claim 17, wherein the barrier structure comprises silicon oxide and silicon nitride.

21. 20. The memory device of claim 17, wherein the staircase region includes a staircase structure and an array of wordline contacts formed on the staircase structure.

22. 22. The memory device of claim 21, wherein the barrier structure separates the first stack and the staircase structure, the staircase structure being on an edge of the second stack.

23. 20. The memory device of claim 17, wherein the barrier structure comprises two parallel first sub-barrier structures and a second sub-barrier structure, ends of the two parallel first sub-barrier structures being connected to the second sub-barrier structure.

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