Semiconductor Devices

Abstract

To provide a semiconductor device capable of improving the humidity resistance while suppressing deformation of a substrate and a case caused by expansion and contraction of an encapsulation material due to hardening in a manufacturing process.SOLUTION: A semiconductor device comprises: an insulation substrate; a first circuit pattern formed on one surface of the insulation substrate; a second circuit pattern formed on one surface of the insulation substrate; a first terminal electrode electrically connected with the first circuit pattern; a first semiconductor element placed on the first circuit pattern; a second semiconductor element placed on the first circuit pattern, being different from the first semiconductor element; a second terminal electrode electrically connected with the first semiconductor element and the second semiconductor element via the second circuit pattern; a first encapsulation material that covers the first semiconductor element; a second encapsulation material that covers the second semiconductor element, being formed of a material different from that of the first encapsulation material; and a case that surrounds the first semiconductor element and the second semiconductor element, being bonded with the insulation substrate so as to be separated from the first encapsulation material and the second encapsulation material.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art Conventionally, in semiconductor devices, a case of the semiconductor device is filled with resin to seal the semiconductor element, in order to protect the semiconductor element and ensure moisture resistance. For this reason, when a semiconductor device is operated, the heat generated by the semiconductor element may cause the encapsulating resin to deform, resulting in warping of the semiconductor device. Patent Document 1 discloses a technique for suppressing warping of a semiconductor device due to heat generation from the semiconductor element by continuously increasing the linear expansion coefficient of the encapsulating resin from the semiconductor element toward the upper surface of the encapsulating resin. Patent Document 2 also discloses a technique for locally covering each semiconductor element or a group of adjacent semiconductor elements with an epoxy resin, and then filling the upper part with urethane resin to seal the entire module. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-107666 [Patent Document 2] Japanese Patent Application Laid-Open No. 2006-351737 Summary of the Invention [Problem to be solved by the invention]

[0004] However, the above method does not take into consideration the expansion and contraction of the encapsulating resin during the manufacturing process of the semiconductor device, and therefore there is a problem that the expansion and contraction that accompanies the hardening of the encapsulating resin during the manufacturing process can cause deformation of the substrate and case. If the substrate and case deform, there is a concern that sufficient contact between the semiconductor device and the heat sink will be insufficient, resulting in a decrease in heat dissipation performance, and that the substrate and case will crack when the semiconductor device and the heat sink are fastened together. In Patent Document 2, the semiconductor element is locally sealed with epoxy resin, and the surrounding area is sealed with urethane resin, thereby sealing the entire case, which can cause deformation of the substrate and case due to expansion and contraction caused by hardening of the sealing resin. If the sealing with urethane resin were eliminated, the thickness of the sealing resin would be thinner than before, making it difficult to protect the semiconductor element and ensure moisture resistance.

[0005] The present disclosure has been made to solve the above-mentioned problems, and aims to provide a semiconductor device with improved moisture resistance while suppressing deformation of the substrate and case caused by expansion and contraction of the sealing material as it hardens during the manufacturing process. [Means for solving the problem]

[0006] A semiconductor device according to one aspect of the present disclosure includes an insulating substrate, a first circuit pattern formed on one surface of the insulating substrate, a second circuit pattern formed on one surface of the insulating substrate, a first terminal electrode electrically connected to the first circuit pattern, a first semiconductor element placed on the first circuit pattern, a second semiconductor element placed on the first circuit pattern and separate from the first semiconductor element, a second terminal electrode electrically connected to the first semiconductor element and the second semiconductor element via the second circuit pattern, and a first semiconductor element. whole a first sealing material that covers the second semiconductor element; whole a second sealing material made of a material different from that of the first sealing material and covering the first semiconductor element and the second semiconductor element; and a case that surrounds the first semiconductor element and the second semiconductor element and is bonded to an insulating substrate at a distance from the first sealing material and the second sealing material, A gap is provided between the case and the first sealing material, thereby exposing the insulating substrate, and a gap is provided between the case and the second sealing material, thereby exposing the insulating substrate. It is something. [Effects of the Invention]

[0007] According to the present disclosure, it is possible to obtain a semiconductor device with improved moisture resistance while suppressing deformation of the substrate and case caused by expansion and contraction of the sealing material as it hardens. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 10 is a cross-sectional view illustrating a semiconductor device according to a second embodiment. [Figure 3] 1 is a schematic top view of a semiconductor device before a first sealing material 9 and a second sealing material 10 are formed in the first and second embodiments. FIG. [Figure 4] FIG. 10 is a schematic top view of the semiconductor device in a state where a first jig 12 is set in the second embodiment. [Figure 5] 10 is a schematic top view of the semiconductor device in a state where a first sealing material 9 is poured into a first jig 12 in the second embodiment. FIG. [Figure 6] FIG. 10 is a schematic top view of the semiconductor device in a state where a second jig 13 is set in the second embodiment. [Figure 7] FIG. 10 is a schematic top view of the semiconductor device in a state where second sealing material 10 is poured into second jig 13 in the second embodiment. [Figure 8] FIG. 10 is a schematic top view of the semiconductor device after a first sealing material 9 and a second sealing material 10 have been formed in the second embodiment. [Figure 9] FIG. 10 is a cross-sectional view illustrating a semiconductor device according to a third embodiment. [Figure 10] FIG. 10 is a cross-sectional view illustrating a semiconductor device according to a fourth embodiment. [Figure 11] FIG. 11 is a cross-sectional view illustrating a semiconductor device according to a fifth embodiment. [Figure 12] FIG. 13 is a cross-sectional view illustrating a semiconductor device according to a sixth embodiment. [Figure 13] FIG. 13 is a cross-sectional view illustrating a semiconductor device according to a seventh embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Below, an example of a semiconductor device according to the present disclosure is shown, but it is not limited to the embodiment shown below, and can be implemented by any modification within the scope that does not deviate from the gist of the present disclosure.

[0010] Embodiment 1 Fig. 1 is a schematic cross-sectional view of a semiconductor device according to embodiment 1. Fig. 3 is a schematic top view of a semiconductor device according to embodiments 1 and 2 before a first sealing material 9 and a second sealing material 10 are formed. As shown in FIGS. 1 and 3 , the semiconductor device according to the first embodiment has a first circuit pattern 2a and a second circuit pattern 2b formed on one surface of an insulating substrate 1, and a base plate 3 formed as a heat spreader on the other surface of the insulating substrate 1. A first semiconductor element 4 and a second semiconductor element 5 separate from the first semiconductor element 4 are mounted on the first circuit pattern 2a. The first semiconductor element 4 is electrically connected to the second circuit pattern 2b via a lead wire 6a, and the second semiconductor element 5 is electrically connected to the second circuit pattern 2b via a lead wire 6b. The first circuit pattern 2a is electrically connected to a terminal electrode 8a via a control wiring 7a. The second circuit pattern 2b is electrically connected to a terminal electrode 8b via a control wiring 7b. The first semiconductor element 4 is covered with a first sealing material 9, and the second semiconductor element 5 is covered with a second sealing material 10 made of a different material from the first sealing material 9. Furthermore, a case 11 is provided which surrounds the first semiconductor element 4 and the second semiconductor element 5, is spaced apart from the first sealing material 9 and the second sealing material 10, and is joined to the insulating substrate 1.

[0011] Note that the mounting of a first semiconductor element 4 and a second semiconductor element 5 separate from the first semiconductor element 4 means that two semiconductor elements are mounted, regardless of the type, structure, drive voltage, etc. of the semiconductor elements. For example, regardless of whether the types of semiconductor elements are the same or different, this includes cases where both the first semiconductor element 4 and the second semiconductor element 5 are diodes, or where one is a diode and the other is a transistor. Furthermore, while discrete semiconductors are given as an example, this also includes cases where integrated semiconductors are applied, and the combination of the first semiconductor element 4 and the second semiconductor element 5 is not limited in terms of the type, structure, drive voltage, etc. of the semiconductor elements.

[0012] Furthermore, the encapsulant material can be selected appropriately for each semiconductor element to be covered, with the aim of protecting the semiconductor element and improving its moisture resistance. In other words, a material that can protect the semiconductor element and ensure moisture resistance can be selected for each semiconductor element, eliminating the need to resin-encapsulate the entire case 11. For example, if the encapsulant for the first semiconductor element 4 requires stronger adhesion and the encapsulant for the second semiconductor element 5 requires stronger heat resistance, an epoxy resin can be used as the first encapsulant 9 and a silicone resin can be used as the second encapsulant 10. However, the combinations shown here are merely examples, and the encapsulant material can be selected for each semiconductor element to be covered depending on the specifications required for the semiconductor element and the semiconductor device. As an example of materials for the other components, a copper alloy can be used for the base plate 3 and an engineering plastic can be used for the case 11. However, the materials for the components are not limited to those mentioned above, and any combination can be used depending on the specifications and required performance of the semiconductor device.

[0013] Furthermore, a polymer compound layer (not shown) made of a material different from the first encapsulant 9 and the second encapsulant 10 may be formed on the surface of either the first semiconductor element 4 or the second semiconductor element 5. For example, when the first encapsulant 9 is an epoxy resin, by applying polyimide as a polymer compound layer to the surface of the first semiconductor element 4, it is possible to further improve moisture resistance compared to when no polymer compound layer is applied.

[0014] By applying a semiconductor device configured in this manner, it is possible to use different sealing material for each semiconductor element without filling the entire case with sealing material, thereby providing a semiconductor device with improved moisture resistance while suppressing deformation of the substrate and case caused by expansion and contraction of the sealing material as it hardens.

[0015] Therefore, by applying the semiconductor device shown in embodiment 1, it is possible to use different sealing material for each semiconductor element without filling the entire inside of the case with sealing material, and it is possible to obtain a semiconductor device with improved moisture resistance while suppressing deformation of the substrate and case caused by expansion and contraction of the sealing material as it hardens.

[0016] Embodiment 2 FIG. 2 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. The semiconductor device according to the second embodiment differs from the first embodiment in that the first sealing material 9 and the second sealing material 10 are spaced apart from each other, as shown in FIG. 2. The other configurations are the same as those of the first embodiment, and therefore detailed description thereof will be omitted. By spaced apart the first sealing material 9 and the second sealing material 10, even if one of the sealing materials expands or contracts as it hardens during the manufacturing process, it is possible to prevent the other sealing material from interfering with and applying stress to it. In other words, it is possible to prevent deformation of the shapes of the substrate and case due to expansion or contraction of the sealing material as it hardens.

[0017] By applying a semiconductor device configured in this manner, it is possible to use different sealing material for each semiconductor element without filling the entire case with sealing material, and it is also possible to prevent the sealing materials for each semiconductor element from interfering with each other, thereby obtaining a semiconductor device with improved moisture resistance while further suppressing deformation of the substrate and case caused by expansion and contraction of the sealing material as it hardens.

[0018] Here, the steps of forming the first sealing material 9 and the second sealing material 10 for the semiconductor device shown in the second embodiment will be schematically shown as an example. FIG. 3 is a schematic top view of a semiconductor device according to the second embodiment before the first encapsulant 9 and the second encapsulant 10 are formed. FIG. 4 is a schematic top view of a semiconductor device according to the second embodiment in a state where a first jig 12 is set. FIG. 5 is a schematic top view of a semiconductor device according to the second embodiment in a state where the first encapsulant 9 has been injected into the first jig 12. FIG. 6 is a schematic top view of a semiconductor device according to the second embodiment in a state where a second jig 13 has been set. FIG. 7 is a schematic top view of a semiconductor device according to the second embodiment in a state where the second encapsulant 10 has been injected into the second jig 13. FIG. 8 is a schematic top view of a semiconductor device according to the second embodiment after the first encapsulant 9 and the second encapsulant 10 have been formed.

[0019] For simplicity, the process is shown in order, starting from the state immediately before the first encapsulant 9 and the second encapsulant 10 are formed. As shown in FIG. 3, the first semiconductor element 4 and the second semiconductor element 5 are placed on the first circuit pattern 2a in an exposed state. First, to resin-encapsulate the first semiconductor element 4, a first jig 12 having a sectioned area for forming the first encapsulant 9 is set as shown in FIG. 4. Next, as shown in FIG. 5, the first encapsulant 9 is poured into the area enclosed by the first jig 12. After the first encapsulant 9 is cured, the first jig 12 is removed. Note that the curing method for the first encapsulant 9 is not particularly limited, and curing methods such as ultraviolet irradiation and heat treatment can be applied depending on the encapsulant used. Next, to resin-encapsulate the second semiconductor element 5, a second jig 13 having a sectioned area for forming the second encapsulant 10 is set as shown in FIG. 6. 7, second sealing material 10 is injected into the area surrounded by second jig 13. After the second sealing material 10 is cured, second jig 13 is removed, whereby the semiconductor device of the second embodiment is obtained, in which first sealing material 9 and second sealing material 10 are formed spaced apart from each other, as shown in FIG.

[0020] Therefore, by applying the semiconductor device shown in embodiment 2, in addition to the same effects as embodiment 1, it is possible to prevent the sealing materials for each semiconductor element from interfering with each other, thereby obtaining the effect of further suppressing deformation of the substrate and case.

[0021] Embodiment 3 FIG. 9 is a schematic cross-sectional view of a semiconductor device according to the third embodiment. The semiconductor device according to the third embodiment differs from the first embodiment in that, as shown in FIG. 9, the first circuit pattern has a first semiconductor mount circuit 14 and a second semiconductor mount circuit 15, the first semiconductor element 4 is mounted on the first semiconductor mount circuit 14, and the second semiconductor element 5 is mounted on the second semiconductor mount circuit 15, the first semiconductor element 4 and the second semiconductor element 5 are electrically connected by lead wires 6a, and terminal electrodes 16 are provided between the first semiconductor element 4 and the second semiconductor element 5. The second semiconductor element 5 and the second circuit pattern 2b are electrically connected by lead wires 6b. Since the other configurations are the same as those of the first embodiment, detailed description thereof will be omitted.

[0022] By applying a semiconductor device configured in this manner, even in a semiconductor device designed for three-pole operation, it is possible to use different sealing material for each semiconductor element without filling the entire case with sealing material, thereby obtaining a semiconductor device with improved moisture resistance while suppressing deformation of the substrate and case caused by expansion and contraction of the sealing material as it hardens. For example, in the case of a power semiconductor device in which the first semiconductor element 4 shown in FIG. 9 is the P-side and the second semiconductor element 5 is the N-side, the type, operation, characteristics, etc. of the semiconductor elements on the P-side and N-side may differ, so being able to use an appropriate sealing material for each will greatly contribute to improving moisture resistance.

[0023] Therefore, by applying the semiconductor device shown in embodiment 3, in addition to the same effects as embodiment 1, it is possible to obtain a semiconductor device with further improved moisture resistance, since it is possible to use appropriate sealing materials to accommodate differences in circuit configuration.

[0024] Embodiment 4 FIG. 10 is a schematic cross-sectional view of a semiconductor device according to the fourth embodiment. 10, the semiconductor device according to the fourth embodiment differs from the first embodiment in that it has a third circuit pattern 17 on which no semiconductor element is mounted, and that the terminal electrode 8a and the first circuit pattern 2a are electrically connected via the control wiring 7a and the third circuit pattern 17. Since the other configurations are the same as those of the first embodiment, detailed description thereof will be omitted.

[0025] By applying a semiconductor device configured in this manner, it is possible to improve the design freedom of the semiconductor element placement and circuit pattern, while also being able to use different sealing material for each semiconductor element without filling the entire case with sealing material, thereby suppressing deformation of the substrate and case caused by expansion and contraction of the sealing material as it hardens, and obtaining a semiconductor device with improved moisture resistance. For example, if there is a circuit pattern that should not be sealed with a sealing material, by configuring it as the third circuit pattern 17 shown in Figure 10, it is possible to obtain a semiconductor device having a circuit pattern that is not sealed with a sealing material.

[0026] Therefore, by applying the semiconductor device shown in embodiment 4, in addition to the same effects as embodiment 1, it is possible to improve the design freedom of the semiconductor element arrangement and circuit pattern, thereby obtaining a semiconductor device with further improved moisture resistance.

[0027] Embodiment 5 FIG. 11 is a schematic cross-sectional view of a semiconductor device according to the fifth embodiment. The semiconductor device according to the fifth embodiment differs from the first embodiment in that, as shown in Fig. 11, the control wiring 7a and the control wiring 7b are sealed with a third sealing material 18. The other configurations are the same as those of the first embodiment, and therefore detailed description thereof will be omitted. The material of the third sealing material 18 may be the same as that of the first sealing material 9 or the second sealing material 10, but it is also possible to use a material different from that of the first sealing material 9 and the second sealing material 10, and any material can be used depending on the purpose of covering the control wiring 7a and the control wiring 7b.

[0028] By applying a semiconductor device configured in this manner, it is possible to seal the control wiring with a sealing material while using different sealing material materials for each semiconductor element without filling the entire case with sealing material, thereby obtaining a semiconductor device with improved moisture resistance while suppressing deformation of the substrate and case caused by expansion and contraction of the sealing material as it hardens.

[0029] Therefore, by applying the semiconductor device shown in embodiment 5, in addition to the same effects as embodiment 1, the control wiring can also be covered with the sealing material, making it possible to obtain a semiconductor device with further improved moisture resistance.

[0030] Embodiment 6 FIG. 12 is a schematic cross-sectional view of a semiconductor device according to the sixth embodiment. The semiconductor device according to the sixth embodiment differs from the first embodiment in that the terminal electrode 8a is directly bonded to the first circuit pattern 2a, and the terminal electrode 8b is directly bonded to the second circuit pattern 2b, as shown in Fig. 12. The other configurations are the same as those of the first embodiment, and therefore detailed description thereof will be omitted. Any method such as thermocompression bonding, ultrasonic bonding, pulse heater bonding, or laser heating can be used as the direct bonding method. For example, ultrasonic bonding is suitable when it is desired to reduce contact resistance and obtain strong direct bonding while avoiding bonding methods that involve heating.

[0031] By applying a semiconductor device configured in this manner, it is possible to reduce the contact resistance of the terminal electrodes and improve bonding stability, while suppressing deformation of the substrate and case caused by expansion and contraction of the sealing material as it hardens, thereby obtaining a semiconductor device with improved moisture resistance.

[0032] Therefore, by applying the semiconductor device shown in embodiment 6, in addition to the same effects as embodiment 1, it is possible to reduce the contact resistance of the terminal electrodes and improve the bonding stability, thereby obtaining a semiconductor device with even improved reliability.

[0033] Embodiment 7 FIG. 13 is a schematic cross-sectional view of a semiconductor device according to the seventh embodiment. The semiconductor device according to the seventh embodiment differs from the first embodiment in that the case 11 is provided with a lid 19, as shown in Fig. 13. The other configurations are the same as those of the first embodiment, and therefore detailed description thereof will be omitted.

[0034] By applying the semiconductor device configured in this manner, the protection and moisture resistance of the inside of the case can be improved by having a lid, and different encapsulant materials can be used for each semiconductor element without filling the entire inside of the case with encapsulant, so it is possible to obtain a semiconductor device with improved moisture resistance while suppressing deformation of the substrate and case caused by expansion and contraction of the encapsulant as it hardens.In addition, having a lid also widens the range of design options for the semiconductor device.

[0035] Therefore, by applying the semiconductor device shown in embodiment 7, in addition to the same effects as embodiment 1, a semiconductor device can be obtained that has improved protection and moisture resistance inside the case due to the lid, and has a wider range of design options.

[0036] Various aspects of the present disclosure are summarized below as appendices.

[0037] (Appendix 1) an insulating substrate; a first circuit pattern formed on one surface of the insulating substrate; a second circuit pattern formed on one surface of the insulating substrate; a first terminal electrode electrically connected to the first circuit pattern; a first semiconductor element placed on the first circuit pattern; a second semiconductor element placed on the first circuit pattern and separate from the first semiconductor element; a second terminal electrode electrically connected to the first semiconductor element and the second semiconductor element via the second circuit pattern; a first sealing material that covers the first semiconductor element; a second sealing material that covers the second semiconductor element and is made of a different material from the first sealing material; a case that encloses the first semiconductor element and the second semiconductor element and is bonded to the insulating substrate while being spaced apart from the first sealing material and the second sealing material; A semiconductor device comprising: (Appendix 2) a polymer compound layer made of a material different from that of the first sealing material and the second sealing material is formed on a surface of either the first semiconductor element or the second semiconductor element; 2. The semiconductor device according to claim 1, (Appendix 3) the first sealing material and the second sealing material are spaced apart from each other; 3. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer and a second insulating layer. (Appendix 4) the first circuit pattern has a first semiconductor mount circuit and a second semiconductor mount circuit, the first semiconductor element is mounted on the first semiconductor mount circuit, and the second semiconductor element is mounted on the second semiconductor mount circuit; 4. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer and a second insulating layer. (Appendix 5) The semiconductor device is a power semiconductor device, the first semiconductor mounted circuit is a P-side, and the second semiconductor mounted circuit is an N-side; 5. The semiconductor device according to claim 4, (Appendix 6) the first circuit pattern and the first terminal electrode are electrically connected via a third circuit pattern on which no semiconductor element is mounted; 6. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer and a second insulating layer. (Appendix 7) the third circuit pattern is not covered with a sealing material; 7. The semiconductor device according to claim 6, (Appendix 8) the first terminal electrode and the first circuit pattern are electrically connected by a first control wiring, and the second terminal electrode and the second circuit pattern are electrically connected by a second control wiring; the first control wiring and the second control wiring are covered with a third sealing material; 8. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer and a second insulating layer. (Appendix 9) the material of the third sealing material is different from the material of the first sealing material and the material of the second sealing material; 9. The semiconductor device according to claim 8, (Appendix 10) at least one of the electrical connection between the first terminal electrode and the first circuit pattern and the electrical connection between the second terminal electrode and the second circuit pattern is made by direct bonding; 10. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer and a second insulating layer. (Appendix 11) at least one of the electrical connection between the first terminal electrode and the first circuit pattern and the electrical connection between the second terminal electrode and the second circuit pattern is directly bonded by ultrasonic bonding; 11. The semiconductor device according to claim 10, (Appendix 12) the case has a lid; 12. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer and a second insulating layer. [Explanation of symbols]

[0038] 1. Insulating substrate 2a First circuit pattern 2b Second circuit pattern 3 Base plate 4. First semiconductor element 5. Second semiconductor element 6a lead wire 6b lead wire 7a Control wiring 7b Control wiring 8a terminal electrode 8b terminal electrode 9 First sealing material 10 Second sealing material 11 cases 12 First jig 13 Second jig 14 First semiconductor mounted circuit 15 Second semiconductor mounted circuit 16 terminal electrode 17 Third Circuit Pattern 18 Third Encapsulation Material 19 Lid

Claims

1. an insulating substrate; a first circuit pattern formed on one surface of the insulating substrate; a second circuit pattern formed on one surface of the insulating substrate; a first terminal electrode electrically connected to the first circuit pattern; a first semiconductor element placed on the first circuit pattern; a second semiconductor element placed on the first circuit pattern and separate from the first semiconductor element; a second terminal electrode electrically connected to the first semiconductor element and the second semiconductor element via the second circuit pattern; a first sealing material that covers the entire first semiconductor element; a second sealing material that covers the entire second semiconductor element and is made of a different material from the first sealing material; a case that encloses the first semiconductor element and the second semiconductor element and is bonded to the insulating substrate while being spaced apart from the first sealing material and the second sealing material; Equipped with a gap is provided between the case and the first sealing material, thereby exposing the insulating substrate; The semiconductor device has a gap between the case and the second sealing material, thereby exposing the insulating substrate.

2. a polymer compound layer made of a material different from that of the first sealing material and the second sealing material is formed on a surface of either the first semiconductor element or the second semiconductor element; 2. The semiconductor device according to claim 1, wherein:

3. the first sealing material and the second sealing material are spaced apart from each other; 2. The semiconductor device according to claim 1, wherein:

4. the first circuit pattern has a first semiconductor mount circuit and a second semiconductor mount circuit, the first semiconductor element is mounted on the first semiconductor mount circuit, and the second semiconductor element is mounted on the second semiconductor mount circuit; 2. The semiconductor device according to claim 1, wherein:

5. The semiconductor device is a power semiconductor device, the first semiconductor mounted circuit is a P-side, and the second semiconductor mounted circuit is an N-side; 5. The semiconductor device according to claim 4, wherein:

6. the first circuit pattern and the first terminal electrode are electrically connected via a third circuit pattern on which no semiconductor element is mounted; 2. The semiconductor device according to claim 1, wherein:

7. the third circuit pattern is not covered with a sealing material; 7. The semiconductor device according to claim 6, wherein:

8. the first terminal electrode and the first circuit pattern are electrically connected by a first control wiring, and the second terminal electrode and the second circuit pattern are electrically connected by a second control wiring; the first control wiring and the second control wiring are covered with a third sealing material; 2. The semiconductor device according to claim 1, wherein:

9. the material of the third sealing material is different from the material of the first sealing material and the material of the second sealing material; 9. The semiconductor device according to claim 8,

10. at least one of the electrical connection between the first terminal electrode and the first circuit pattern and the electrical connection between the second terminal electrode and the second circuit pattern is made by direct bonding; 2. The semiconductor device according to claim 1, wherein:

11. at least one of the electrical connection between the first terminal electrode and the first circuit pattern and the electrical connection between the second terminal electrode and the second circuit pattern is directly bonded by ultrasonic bonding; 11. The semiconductor device according to claim 10,

12. the case has a lid; 2. The semiconductor device according to claim 1, wherein:

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