Semiconductor unit and semiconductor device

Abstract

To prevent short-circuiting and to suppress a ceramic plate from expanding.SOLUTION: A ceramic plate 21 is in a rectangular shape encircled with first, second sides 21a, 21b opposed to each other, and third, fourth sides 21c, 21d orthogonally opposed to the first, second sides 21a, 21b. A circuit pattern 23b is formed on a top surface of the ceramic plate 21. A circuit pattern 23a is formed on the top surface of the ceramic plate 21, and a reverse surface of a semiconductor chip 30 is joined. Further, the circuit pattern 23b and circuit pattern 23a are formed over from the third side 21c to the fourth side 21d, respectively, and further formed side by side in a main current direction D1 from the first side 21a to the second side 21b.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor unit and a semiconductor device. [Background technology]

[0002] The semiconductor device includes a power device. The power device is, for example, a semiconductor chip including an IGBT (Insulated Gate Bipolar Transistor) or a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Such a semiconductor device includes a ceramic circuit substrate on which the above-mentioned semiconductor chip is disposed. The ceramic circuit substrate includes a ceramic plate and a plurality of circuit patterns formed on the front surface of the ceramic plate. Circuit patterns are formed on one ceramic circuit substrate so as to correspond to the upper arm and the lower arm, respectively. The semiconductor chip is appropriately mounted on the plurality of circuit patterns. Control electrodes of the semiconductor chip, main electrodes of the semiconductor chip, and the circuit patterns of the ceramic circuit substrate are electrically connected by appropriate bonding wires. This allows the semiconductor device to achieve the desired function (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2016 / 084622 Summary of the Invention [Problem to be solved by the invention]

[0004] In the semiconductor device described above, it is necessary to form the circuit patterns corresponding to the upper arm and the lower arm on the ceramic plate with a predetermined distance between them. This prevents short circuits between the circuit patterns corresponding to the upper arm and the lower arm. However, because a predetermined distance must be provided between the circuit patterns, the mounting area of ​​the circuit patterns on the ceramic plate is narrowed, making it difficult to miniaturize the ceramic plate. This makes it difficult to miniaturize the semiconductor device.

[0005] The present invention has been made in consideration of the above points, and aims to provide a semiconductor unit that can prevent short circuits and suppress expansion of the ceramic plate, and a semiconductor device that includes the semiconductor unit. [Means for solving the problem]

[0006] According to one aspect of the present invention, there is provided a semiconductor device including a semiconductor chip, an input circuit metal, and an output circuit metal electrically connected to the semiconductor chip. The output circuit metal includes an output terminal area and is adjacent to the input circuit metal, the input circuit metal includes an input terminal area on the opposite side of the output circuit metal with respect to the semiconductor chip disposed thereon, and a main current flows in a main current direction from the input circuit metal to the output circuit metal. A semiconductor device including a semiconductor unit, the semiconductor unit being connected to a positive electrode and a load. The input terminal region of the input circuit metal and the output terminal region of the output circuit metal are respectively a first semiconductor unit that configures an upper arm portion connected to the load and the negative electrode; The input terminal region of the input circuit metal and the output terminal region of the output circuit metal are respectively and a second semiconductor unit that configures a lower arm portion to be connected to the first semiconductor unit, wherein the first semiconductor unit and the second semiconductor unit are The aforementioned The semiconductor device is provided in which a plurality of semiconductor devices are arranged side by side, alternately in a left-right direction perpendicular to the main current direction, so that the main current directions are opposite to each other.

[0007] According to another aspect of the present invention, there is provided a semiconductor device including a semiconductor chip, an input circuit metal, and an output circuit metal electrically connected to the semiconductor chip. The output circuit metal includes an output terminal area and is adjacent to the input circuit metal, the input circuit metal includes an input terminal area on the opposite side of the output circuit metal with respect to the semiconductor chip disposed thereon, and a main current flows in a main current direction from the input circuit metal to the output circuit metal. A semiconductor device including a semiconductor unit, the semiconductor unit being connected to a positive electrode and a load. The input terminal region of the input circuit metal and the output terminal region of the output circuit metal are respectively a first semiconductor unit that configures an upper arm portion connected to the load and the negative electrode; The input terminal region of the input circuit metal and the output terminal region of the output circuit metal are respectively a second semiconductor unit that configures a lower arm portion connected to the first semiconductor unit, The aforementioned A plurality of second semiconductor units are arranged in the left-right direction perpendicular to the main current direction, The aforementioned A semiconductor device is provided in which a plurality of the first semiconductor units are arranged side by side in the left-right direction with their main current direction opposite to that of the first semiconductor unit. [Effects of the Invention]

[0008] According to the disclosed technology, it is possible to prevent short circuits, suppress the expansion of the ceramic plate, and achieve miniaturization of the semiconductor unit and the semiconductor device.

[0009] The above and other objects, features and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings illustrating preferred embodiments of the present invention. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 2 is a plan view of a semiconductor unit included in the semiconductor device of the first embodiment. [Figure 2] 1 is a cross-sectional view of a semiconductor unit included in the semiconductor device of the first embodiment. [Figure 3] 4 is another plan view of the semiconductor unit included in the semiconductor device of the first embodiment. FIG. [Figure 4] 1 is a plan view (part 1) of a semiconductor device according to a first embodiment; [Figure 5] FIG. 2 is a plan view (part 2) of the semiconductor device according to the first embodiment; [Figure 6] FIG. 2 is a diagram illustrating an equivalent circuit of the semiconductor device according to the first embodiment. [Figure 7] FIG. 10 is a plan view of a semiconductor unit according to a reference example. [Figure 8] FIG. 1 is a plan view of a semiconductor device according to a first modification of the first embodiment. [Figure 9] FIG. 10 is a plan view of a semiconductor device according to a second modification of the first embodiment. [Figure 10] 10 is a plan view (part 1) of a semiconductor device according to a third modification of the first embodiment; FIG. [Figure 11]10 is a plan view (part 2) of the semiconductor device according to the third modification of the first embodiment; FIG. [Figure 12] 10 is a plan view (part 1) of a semiconductor device according to a fourth modified example of the first embodiment; FIG. [Figure 13] FIG. 10 is a plan view (part 2) of the semiconductor device according to the fourth modification of the first embodiment. [Figure 14] 13 is a plan view (part 1) of a semiconductor device according to a fifth modified example of the first embodiment. FIG. [Figure 15] 13 is a plan view (part 2) of the semiconductor device according to the fifth modification of the first embodiment. FIG. [Figure 16] FIG. 10 is a plan view of a semiconductor unit included in a semiconductor device according to a second embodiment. [Figure 17] FIG. 10 is a plan view of a semiconductor unit included in a semiconductor device according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, the embodiments will be described with reference to the drawings. In the following description, the terms "front surface" and "upper surface" refer to the surfaces of the semiconductor unit 10 in FIG. 1 facing toward the viewer (+Z direction). Similarly, "up" refers to the direction toward the viewer (+Z direction) of the semiconductor unit 10 in FIG. 1. The terms "rear surface" and "lower surface" refer to the surfaces of the semiconductor unit 10 in FIG. 1 facing toward the depth of the viewer (-Z direction) of the page (the rear surface is not shown in FIG. 1). Similarly, the term "lower" refers to the direction toward the depth of the viewer (-Z direction) of the page of the semiconductor unit 10 in FIG. 1. The term "side surface" refers to the surface connecting the "front surface" or "upper surface" with the "rear surface" or "lower surface" of the semiconductor unit 10. For example, the term "side surface" refers to the surfaces of the semiconductor unit 10 in FIG. 1 facing up and down (±X directions) and left and right (±Y directions) of the page. Similar directions will be used in other drawings as necessary. The terms "front surface," "upper surface," "top," "back surface," "bottom surface," "bottom," and "side surface" are merely convenient expressions for specifying relative positional relationships and do not limit the technical concept of the present invention. For example, "top" and "bottom" do not necessarily refer to the vertical direction relative to the ground. In other words, the directions of "top" and "bottom" are not limited to the direction of gravity. In addition, in the following description, "main component" refers to a component containing 80 vol% or more.

[0012] [First embodiment] Hereinafter, a semiconductor device according to a first embodiment will be described with reference to the drawings using Figs. 1 to 3. Fig. 1 is a plan view of a semiconductor unit included in the semiconductor device according to the first embodiment, and Fig. 2 is a cross-sectional view of the semiconductor unit included in the semiconductor device according to the first embodiment. Fig. 3 is another plan view of the semiconductor unit included in the semiconductor device according to the first embodiment. Fig. 2 is a cross-sectional view taken along the dashed dotted line XX in Fig. 1.

[0013] As will be described later, the semiconductor device includes two semiconductor units 10 shown in Figures 1 and 2. The semiconductor unit 10 includes a ceramic circuit board 20 (insulating circuit board) and a semiconductor chip 30 provided on the front surface of the ceramic circuit board 20.

[0014] The semiconductor chip 30 is primarily composed of silicon or silicon carbide. The semiconductor chip 30 includes a switching element of an RC (Reverse Conducting)-IGBT. The RC-IGBT is configured by connecting an IGBT and an FWD (Free Wheeling Diode) in anti-parallel within a single chip. The semiconductor chip 30 has a control electrode 31 (gate electrode) and an output electrode 32 (an emitter electrode of the IGBT section and a cathode electrode of the FWD section) on its front surface. The semiconductor chip 30 has a rectangular shape in plan view. The control electrode 31 is provided at the center of one side of the front surface of the semiconductor chip 30. The output electrode 32 is provided on the front surface of the semiconductor chip 30 in an area excluding the control electrode 31. The semiconductor chip 30 also has input electrodes (a collector electrode of the IGBT section and an anode electrode of the FWD section) (not shown) on its back surface. In the semiconductor unit 10, four semiconductor chips 30 are arranged with their back surfaces on the circuit pattern 23a with their control electrodes 31 facing inward. The number and arrangement positions of the semiconductor chips 30 are not limited to this case.

[0015] The ceramic circuit board 20 has a rectangular shape in a plan view. The ceramic circuit board 20 has a ceramic plate 21 and a metal plate 22 formed on the back surface of the ceramic plate 21. Furthermore, the ceramic circuit board 20 has circuit patterns 23a to 23f formed on the front surface of the ceramic plate 21. The ceramic plate 21 and the metal plate 22 have a rectangular shape in a plan view. The corners of the ceramic plate 21 and the metal plate 22 may be R-chamfered or C-chamfered. The size of the metal plate 22 is smaller than the size of the ceramic plate 21 in a plan view, and is formed inside the ceramic plate 21.

[0016] In a plan view, the ceramic plate 21 has a rectangular shape surrounded by first and second sides 21a and 21b that face each other (in the ±X directions) and third and fourth sides 21c and 21d that face each other (in the ±Y directions) and are perpendicular to the first and second sides 21a and 21b. In a plan view, the ceramic plate 21 may have a rectangular shape with the first and second sides 21a and 21b as long sides and the third and fourth sides 21c and 21d as short sides. Note that the direction (+X direction) from the first side 21a on the side of the input terminal region 23a2 (described later) to the second side 21b on the side of the output terminal region 23b2 (described later) is defined as the main current direction D1. The ceramic plate 21 is primarily composed of ceramics with good thermal conductivity. The ceramics constituting the ceramic plate 21 may be, for example, a composite material mainly composed of aluminum oxide and zirconium oxide added to the aluminum oxide, or a material mainly composed of silicon nitride. The thickness of the ceramic plate 21 is 0.2 mm or more and 2.5 mm or less.

[0017] The metal plate 22 is mainly composed of a metal with excellent thermal conductivity. Such metals include, for example, aluminum, iron, silver, copper, or an alloy containing at least one of these. The thickness of the metal plate 22 is 0.1 mm or more and 5.0 mm or less. The surface of the metal plate 22 may be plated to improve corrosion resistance. Examples of plating materials include nickel, nickel-phosphorus alloys, and nickel-boron alloys.

[0018] The circuit patterns 23a-23f are primarily composed of a metal with excellent conductivity. Examples of such metals include silver, copper, nickel, and alloys containing at least one of these. The circuit patterns 23a-23f have a thickness of 0.1 mm or more and 5.0 mm or less. The surfaces of the circuit patterns 23a-23f may be plated to improve corrosion resistance. Examples of the plating material include nickel, nickel-phosphorus alloy, and nickel-boron alloy. The circuit patterns 23a-23f are obtained by etching or other processes on a metal layer formed on the front surface of the ceramic plate 21. Alternatively, the circuit patterns 23a-23f may be cut out from a metal layer and then pressure-bonded to the front surface of the ceramic plate 21. The circuit patterns 23a-23f shown in FIGS. 1 and 2 are merely examples. Details of the circuit patterns 23a-23f will be described below. The surfaces of the circuit patterns 23a-23f may also be plated to improve corrosion resistance. Examples of the plating material include nickel, nickel-phosphorus alloy, and nickel-boron alloy.

[0019] A DCB (Direct Copper Bonding) substrate or an AMB (Active Metal Brazed) substrate may be used as the ceramic circuit substrate 20 having such a configuration. The ceramic circuit substrate 20 can conduct heat generated in the semiconductor chip 30 to the outside via the circuit pattern 23a, the ceramic plate 21, and the metal plate 22.

[0020] Here, each of the circuit patterns 23a to 23f will be described in detail. The circuit pattern 23a (input circuit pattern) is mechanically and electrically connected via solder to an input electrode formed on the back surface of the semiconductor chip 30. The circuit pattern 23a has a substantially rectangular shape and includes a recessed portion 23a1 on the lower side in FIG. 1. A contact region 23c1 of the circuit pattern 23c, which will be described later, fits into this recessed portion 23a1. The circuit pattern 23a further includes two input terminal regions 23a2 on the circuit pattern 23c side, sandwiching the recessed portion 23a1.

[0021] The circuit pattern 23a is provided in an area including a center line (dotted dash line XX) perpendicular to the main current direction D1. The semiconductor chips 30 are arranged in an area including the center line (dotted dash line XX). In FIG. 1, four semiconductor chips 30 are arranged two by two, one above the other (in the ±X directions) around the center line (dotted dash line XX). The semiconductor chips 30 are arranged two by two, symmetrically about the center line (dotted dash line YY) between the third side 21c and the fourth side 21d of the ceramic plate 21. The control electrodes 31 of the respective semiconductor chips 30 are arranged on the side of the center line (dotted dash line YY) and are arranged opposite each other with the center line (dotted dash line YY) as the center.

[0022] The circuit pattern 23b (output circuit pattern) is mechanically and electrically connected to the output electrode 32 of the semiconductor chip 30 by a main current wire 41 that is wired in the main current direction D1. The circuit pattern 23b includes two output terminal areas 23b2 on the circuit pattern 23f side.

[0023] These circuit patterns 23a, 23b are formed from the third side 21c to the fourth side 21d of the ceramic plate 21. Furthermore, the circuit patterns 23a, 23b are formed side by side in this order in the main current direction D1. That is, the circuit patterns 23a, 23b are formed adjacent to each other in the ±X directions, with no other circuit patterns formed between them. Furthermore, the ends (on the -Y direction side) of the circuit patterns 23a, 23b are formed adjacent to the third side 21c of the ceramic plate 21, with no other circuit patterns formed between them. The ends (on the +Y direction side) of the circuit patterns 23a, 23b are formed adjacent to and facing the fourth side 21d of the ceramic plate 21, with no other circuit patterns formed between them. Therefore, in the ceramic circuit substrate 20, the main current input to the input terminal region 23a2 flows in the main current direction D1 and is output from the output terminal region 23b2.

[0024] The interval between the circuit patterns 23a and 23b, the interval between the ends of the circuit patterns 23a and 23b on the -Y direction side and the third side 21c of the ceramic plate 21, and the interval between the ends of the circuit patterns 23a and 23b on the +Y direction side and the fourth side 21d of the ceramic plate 21 may be formed according to a predetermined insulation distance. For example, the interval formed according to the predetermined insulation distance may be 0.5 mm or more and 4.0 mm or less.

[0025] Furthermore, for example, all of the ±Y direction ends of circuit pattern 23b (output circuit pattern) may be formed adjacent to third and fourth sides 21c and 21d. Circuit pattern 23a (input circuit pattern) may be formed such that its ±Y direction ends are adjacent to third and fourth sides 21c and 21d in the region where semiconductor chip 30 is disposed. Meanwhile, in the region where input terminal region 23a2 is disposed, circuit patterns 23c and 23d, which are control circuits, sense circuits, etc., described below, may be formed between its ±Y direction ends and third and fourth sides 21c and 21d.

[0026] In addition, in the ceramic circuit substrate 20, the input terminal region 23a2 is arranged on the first side 21a side, and the output terminal region 23b2 is arranged on the second side 21b side. In other words, the main current direction D1 is the direction from the input terminal region 23a2 to the output terminal region 23b2. The input terminal region 23a2 and the output terminal region 23b2 are provided at equal distances from the center line (dashed dotted line XX) of the ceramic circuit substrate 20 that is perpendicular to the main current direction D1. Furthermore, the input terminal region 23a2 and the output terminal region 23b2 are provided at approximately equal distances from the first and second sides 21a and 21b.

[0027] The circuit pattern 23c (first control circuit pattern) is electrically connected to the control electrode 31 of the semiconductor chip 30. The circuit pattern 23c is formed adjacent to the outer side of the circuit pattern 23a (opposite the main current direction D1). The ends (on the ±Y direction sides) of the circuit pattern 23c are formed to correspond to the width of the area where the input terminal area 23a2 of the circuit pattern 23a is provided. That is, there is a gap between the ends (on the ±Y direction sides) of the circuit pattern 23c and the third and fourth sides 21c, 21d of the ceramic plate 21. The circuit pattern 23c also includes a contact area 23c1 at a location corresponding to the middle of the third and fourth sides 21c, 21d of the ceramic plate 21. This contact area 23c1 is embedded in the recessed portion 23a1 of the circuit pattern 23a. The circuit pattern 23c (contact region 23c1) is mechanically and electrically connected to the control electrode 31 facing inward of the semiconductor chip 30 by a control wire 42 (control wiring member) wired in the main current direction D1.

[0028] The circuit pattern 23f (second control circuit pattern) may be electrically connected to the control electrode 31 of the semiconductor chip 30. The circuit pattern 23f is linear and formed adjacent to the outer side (main current direction D1) of the circuit pattern 23b. The ends (on the ±Y direction sides) of the circuit pattern 23f are formed to correspond to the ends (on the ±Y direction sides) of the circuit pattern 23b.

[0029] Moreover, such circuit patterns 23c and 23f are formed at positions that are symmetrical with respect to the center line (dotted chain line XX) that is perpendicular to the main current direction D1 of the ceramic circuit board 20. Moreover, the circuit patterns 23c and 23f are formed at equal distances from the first and second sides 21a and 21b of the ceramic plate 21.

[0030] The circuit pattern 23d (first sense circuit pattern) is electrically connected to the output electrode 32 of the semiconductor chip 30. The circuit pattern 23d is formed in the opposite direction of the main current direction D1 with respect to the circuit pattern 23a. The circuit pattern 23d is formed adjacent to the outer side (negative X-direction side) of the circuit pattern 23c. That is, in the first embodiment, the circuit pattern 23d has a U-shape in a plan view. Specifically, the circuit pattern 23d is formed along each region where the input terminal region 23a2 of the circuit pattern 23a is set, along each end of the circuit pattern 23c (on the ±Y-direction side), and along the opposite side of the circuit pattern 23c in the main current direction D1. The circuit pattern 23d is mechanically and electrically connected to the output electrode 32 of the semiconductor chip 30 by a sense wire 46 wired in the main current direction D1.

[0031] The circuit pattern 23e (second sense circuit pattern) may be electrically connected to the output electrode 32 of the semiconductor chip 30. The circuit pattern 23e is linear and formed adjacent to the outer side (main current direction D1) of the circuit pattern 23f. The ends (on the ±Y direction sides) of the circuit pattern 23e are formed to correspond to the ends (on the ±Y direction sides) of the circuit pattern 23f.

[0032] Moreover, such circuit patterns 23d and 23e are formed at equal distances from the center line (dash-dotted line XX) perpendicular to the main current direction D1 of the ceramic circuit board 20. Moreover, the circuit patterns 23d and 23e are formed at equal distances from the first and second sides 21a and 21b of the ceramic plate 21, respectively.

[0033] The main current wire 41, the control wire 42, and the sense wire 46 are primarily composed of a metal with excellent conductivity. Examples of such metals include gold, silver, copper, aluminum, and alloys containing at least one of these. The diameters of the control wire 42 and the sense wire 46 may be smaller than that of the main current wire 41. This reduces the bonding area and facilitates wiring to small areas. The diameters of the control wire 42 and the sense wire 46 are, for example, 50 μm or more and 400 μm or less, and the diameter of the main current wire 41 is 300 μm or more and 600 μm or less. Note that the control connection wires 44a, 44b and the sense connection wires 45a, 45b, which will be described later, are also made of the same material as the control wire 42 and the sense wire 46. The diameters of the control connection wires 44a, 44b and the sense connection wires 45a, 45b may be the same as those of the control wire 42 and the sense wire 46, but may be smaller than that of the main current wire 41.

[0034] The control wire 42 and the sense wire 46 are not limited to the case of FIG. 1 , and may be wired as shown in FIG. 3 . The control wire 42 is wired parallel to the main current direction D1 between the contact region 23c1 of the circuit pattern 23c and the control electrode 31 of the semiconductor chip 30, and connects them. The sense wire 46 is wired parallel to the main current direction D1 between the circuit patterns 23b and 23d, and connects them on the third and fourth sides 21c and 21d of the ceramic plate 21. Furthermore, the main current wire 41 is wired parallel to the main current direction D1 between the control wire 42 and the sense wire 46. In this way, the main current wire 41, the control wire 42, and the sense wire 46 are all wired parallel to the main current direction D1, and therefore can be easily bonded.

[0035] In this way, the semiconductor chip 30 and the circuit patterns 23a, 23b, 23c, and 23d are connected by the main current wire 41, the control wire 42, and the sense wire 46. In the semiconductor unit 10, an arm portion is formed by such connections. The arm portion functions as an upper arm or a lower arm depending on the arrangement direction (the orientation in which the main current direction D1 is arranged). Details of these will be described later.

[0036] Next, a semiconductor device including such a semiconductor unit 10 will be described with reference to FIGS. 4 to 6. FIGS. 4 and 5 are plan views of the semiconductor device of the first embodiment. FIG. 6 is a diagram showing an equivalent circuit included in the semiconductor device of the first embodiment. In these figures, reference numerals are used to denote components necessary for explanation. For components where reference numerals are omitted, reference can be made to FIGS. 1 and 2. The semiconductor device may also employ the semiconductor unit of FIG. 3.

[0037] The semiconductor device 1 includes two semiconductor units 10a and 10b. The semiconductor unit 10a has the semiconductor unit 10 oriented in a main current direction D1 and functions as an upper arm. The semiconductor unit 10b has the semiconductor unit 10 oriented in a main current direction D1 opposite to that of the semiconductor unit 10a and functions as a lower arm. Therefore, the semiconductor units 10a and 10b each have the same components as the semiconductor unit 10, and only the arrangement direction is different.

[0038] In such a semiconductor device 1, the circuit pattern 23b of the semiconductor unit 10a and the circuit pattern 23a of the semiconductor unit 10b may be mechanically and electrically connected by a main circuit connecting wire (not shown).

[0039] In the semiconductor device 1, the circuit pattern 23c of the semiconductor unit 10a and the circuit pattern 23f of the semiconductor unit 10b are mechanically and electrically connected by a control connecting wire 44a. The circuit pattern 23f of the semiconductor unit 10a and the circuit pattern 23c of the semiconductor unit 10b are mechanically and electrically connected by a control connecting wire 44b.

[0040] In the semiconductor device 1, the circuit pattern 23d of the semiconductor unit 10a and the circuit pattern 23e of the semiconductor unit 10b are mechanically and electrically connected by a sense coupling wire 45a. The circuit pattern 23e of the semiconductor unit 10a and the circuit pattern 23d of the semiconductor unit 10b are mechanically and electrically connected by a sense coupling wire 45b.

[0041] The semiconductor device 1 further includes bus bars 50a and 50b. The bus bars 50a and 50b are mainly composed of a metal with excellent electrical conductivity. Examples of such metals include silver, copper, nickel, and alloys containing at least one of these. The surfaces of the bus bars 50a and 50b may also be plated to improve corrosion resistance. Examples of plating materials used in this case include nickel, a nickel-phosphorus alloy, and a nickel-boron alloy.

[0042] The bus bar 50a includes a leg portion 51a and a wiring portion 52a. The leg portion 51a is joined to the input terminal region 23a2 of the circuit pattern 23a of the semiconductor unit 10a. The leg portion 51a is joined by, for example, soldering or ultrasonic bonding. The wiring portion 52a is mechanically connected to the leg portion 51a. The wiring portion 52a and the leg portion 51a may be integral with each other or may be joined by, for example, welding. The wiring portion 52a extends in the ±Y direction in FIG. 5, orthogonal to the main current direction D1. Note that FIG. 5 shows only a portion of the wiring portion 52a. The wiring portion 52a can extend in a desired direction depending on the design and specifications of the semiconductor device 1.

[0043] The bus bar 50b also includes a leg portion 51b and a wiring portion 52b. The leg portion 51b is joined to the output terminal region 23b2 of the circuit pattern 23b of the semiconductor unit 10b. The leg portion 51b is also joined by, for example, soldering or ultrasonic bonding. The wiring portion 52b is mechanically connected to the leg portion 51b. The wiring portion 52b and the leg portion 51b may also be integral with each other or may be joined by, for example, welding. The wiring portion 52b extends in the ±Y direction in FIG. 5, orthogonal to the main current direction D1. Note that FIG. 5 shows only a portion of the wiring portion 52b. The wiring portion 52b can extend in a direction required depending on the design and specifications of the semiconductor device 1.

[0044] The bus bar 50c also includes a leg portion 51c and a wiring portion 52c. The leg portion 51c is joined to the output terminal region 23b2 of the circuit pattern 23b of the semiconductor unit 10a and the input terminal region 23a2 of the circuit pattern 23a of the semiconductor unit 10b. The leg portion 51c is also joined by, for example, soldering or ultrasonic bonding. The wiring portion 52c is mechanically connected to the leg portion 51c. The wiring portion 52c and the leg portion 51c may also be integral with each other or may be joined by, for example, welding. The wiring portion 52c extends in the ±Y direction in FIG. 5, orthogonal to the main current direction D1. Note that FIG. 5 shows only a portion of the wiring portion 52c. The wiring portion 52c can extend in a desired direction depending on the design and specifications of the semiconductor device 1.

[0045] The semiconductor device 1 forms a half-bridge circuit shown in FIG. 6 and includes an upper arm A and a lower arm B. By connecting the semiconductor units 10a and 10b, the semiconductor device 1 can have the semiconductor unit 10a function as the upper arm A and the semiconductor unit 10b function as the lower arm B. In this case, in the semiconductor device 1, a connection point C1 connected to a positive terminal P of an external power supply (not shown) corresponds to the input terminal area 23a2 of the semiconductor unit 10a. A connection point E1C2 connected to a terminal O of a load (not shown) corresponds to the output terminal area 23b2 of the semiconductor unit 10a and the input terminal area 23a2 of the semiconductor unit 10b. A connection point E2 connected to a negative terminal N of the external power supply corresponds to the output terminal area 23b2 of the semiconductor unit 10b.

[0046] From connection point C1, a line is wired to the outside of semiconductor device 1 via bus bar 50a and connected to the high potential terminal (P) of the external power supply. From connection point E2, a line is wired to the outside of semiconductor device 1 via bus bar 50b and connected to the low potential terminal (N) of the external power supply. Then, from connection point E1C2, a line is wired to the outside of semiconductor device 1 via bus bar 50c and connected to the terminal (O) of the load. This allows the semiconductor unit 10 to function as an inverter.

[0047] The semiconductor device 1 with the semiconductor units 10a and 10b connected in this manner is disposed on a heat dissipation substrate, for example, via solder or silver solder. The heat dissipation substrate may be a rectangular flat plate in plan view. The heat dissipation substrate is primarily composed of a metal with excellent thermal conductivity. Examples of such metals include aluminum, iron, silver, copper, and alloys containing at least one of these. Furthermore, to improve corrosion resistance, nickel may be formed on the surface of the heat dissipation substrate by plating or the like. Specifically, nickel-phosphorus alloys and nickel-boron alloys are available in addition to nickel. Mounting holes and the like are appropriately formed in such a heat dissipation substrate to be used when mounting the semiconductor device 1 to an external device.

[0048] A cooling unit may be attached to the back surface of the heat dissipation substrate of such a semiconductor device 1 via thermal grease. The thermal grease may be, for example, silicone mixed with a metal oxide filler. This cooling unit is also primarily composed of a material with excellent thermal conductivity, and its surface may be plated as needed. The cooling unit may be, for example, a heat sink composed of multiple fins and a water-cooled cooling device. The heat dissipation substrate may also be configured integrally with such a cooling unit.

[0049] The semiconductor device 1 may also be sealed with a sealing member. The sealing member may seal the front surface of the ceramic circuit board 20, the semiconductor chip 30, and wires such as the main current wire 41, the control wire 42, and the sense wire 46. The back surface of the heat dissipation substrate may be exposed from the sealing member. The sealing member is a thermosetting resin such as an epoxy resin, or a silicone gel. It may also contain a filling material such as a filler.

[0050] Alternatively, the device may be housed in a case (not shown) and then sealed with a sealing member. The case may be provided with wiring members, if necessary. The wiring members may be, for example, a lead frame or bus bars 50a, 50b, and 50c. In this case, the case exposes control terminals and sense terminals included in the lead frame, as well as external terminals included in the bus bars 50a, 50b, and 50c. Control signals are input through the control terminals, and measurement signals are output through the sense terminals. A predetermined current is input / output to / from the external terminals. Such a case is primarily composed of a thermoplastic resin. Examples of such resins include polyphenylene sulfide resin, polybutylene terephthalate resin, polybutylene succinate resin, polyamide resin, and acrylonitrile butadiene styrene resin.

[0051] Next, a semiconductor unit of a reference example compared to the semiconductor unit 10 will be described with reference to FIG. 7. FIG. 7 is a plan view of the semiconductor unit of the reference example. In the semiconductor unit 100 shown in FIG. 7, the same components as those in the semiconductor unit 10 are denoted by the same reference numerals, and their description will be omitted. The semiconductor unit 100 includes a ceramic plate 21, circuit patterns 230a to 230g, and semiconductor chips 130 and 131. The circuit patterns 230a to 230g are formed in the shapes and positions shown in FIG. 7.

[0052] The semiconductor chips 130 and 131 include a switching element and a diode element, respectively. The semiconductor chip 130, which is a switching element, has an input electrode on its back surface and a control electrode and an output electrode on its front surface. The semiconductor chip 131, which is a diode element, has an output electrode on its back surface and an input electrode on its front surface.

[0053] The circuit pattern 230a forms a pattern including the connection point E1C2 in FIG. 6. The circuit pattern 230a is connected to a bonding wire 140 connected to an input electrode of the semiconductor chip 131 arranged on the circuit pattern 230b. The circuit pattern 230a is also connected to the rear surfaces of the semiconductor chips 130 and 131 via solder. The circuit pattern 230a has a substantially rectangular shape, and a portion including the contact region 230a1 protrudes upward in FIG. 7. The circuit pattern 230a is arranged alongside the circuit pattern 230b.

[0054] The circuit pattern 230b forms a pattern that includes the connection point C1 of the upper arm A in Fig. 6. The circuit pattern 230b is joined to the rear surfaces of the semiconductor chips 130 and 131 via solder. A portion of the circuit pattern 230b that includes the contact region 230b1 protrudes downward in Fig. 7.

[0055] 6. The circuit pattern 230c is connected to a bonding wire 140 which is connected to an input electrode of the semiconductor chip 131. The circuit pattern 230c is provided with a contact region 230c1 on the second side 21b of the ceramic plate 21.

[0056] The circuit pattern 230d constitutes the control pattern of the upper arm A. The circuit pattern 230d is connected to the control electrode of the semiconductor chip 130 by a control wire 42. The circuit pattern 230d is formed on the second side 21b of the ceramic plate 21 in FIG.

[0057] The circuit pattern 230g constitutes the control pattern of the lower arm B. The circuit pattern 230g is connected to the control electrode of the semiconductor chip 130 of the circuit pattern 230a by a control wire 42. In FIG. 7, the circuit pattern 230g is formed on the first side 21a of the ceramic plate 21, opposite to the circuit pattern 230d.

[0058] Furthermore, the circuit patterns 230e and 230f constitute a sense pattern. The circuit pattern 230f is arranged on the first side 21a of the ceramic plate 21, and the circuit pattern 230e is arranged on the second side 21b opposite to the circuit pattern 230f. The circuit patterns 230e and 230f are mechanically and electrically connected to the output electrodes of the semiconductor chip 130 by the sense wires 46.

[0059] In such a semiconductor unit 100, a gap G must be provided between the circuit pattern 230b of the upper arm A and the circuit pattern 230a of the lower arm B. This prevents a short circuit between the circuit pattern 230b and the circuit pattern 230a. That is, in the semiconductor unit 100, the area of ​​the ceramic plate 21 increases in order to ensure the gap G. This makes it difficult to reduce the size of the ceramic plate 21, and therefore makes it difficult to reduce the size of the semiconductor unit 100, and therefore of a semiconductor device including the semiconductor unit 100.

[0060] On the other hand, the semiconductor unit 10 has a semiconductor chip 30 and a ceramic circuit substrate 20. The semiconductor chip 30 has an output electrode 32 and a control electrode 31 on its front surface and an input electrode on its back surface. The ceramic circuit substrate 20 includes a ceramic plate 21 and circuit patterns 23b and 23a. In a plan view, the ceramic plate 21 has a rectangular shape surrounded by opposing first and second sides 21a and 21b and third and fourth sides 21c and 21d that are perpendicular to and opposed to the first and second sides 21a and 21b. The circuit pattern 23b is formed on the front surface of the ceramic plate 21. The circuit pattern 23a is formed on the front surface of the ceramic plate 21, and the back surface of the semiconductor chip 30 is joined to the circuit pattern 23a. Furthermore, the circuit pattern 23b and the circuit pattern 23a are each formed from the third side 21c to the fourth side 21d, and further formed side by side in the main current direction D1 from the first side 21a to the second side 21b.

[0061] Two semiconductor units 10a and 10b using the semiconductor unit 10 are arranged side by side so that the main current direction D1 is opposite to each other, and are connected by wiring to obtain a semiconductor device 1. In this way, the semiconductor device 1 can be easily configured by simply changing the orientation of the semiconductor units 10. In addition to this, the semiconductor device 1 can be configured by various combinations of the semiconductor units 10.

[0062] Furthermore, in the semiconductor device 1, the semiconductor units 10a and 10b are formed on different ceramic circuit substrates 20, so that insulation between the semiconductor units 10a and 10b is maintained, and short-circuiting between the semiconductor units 10a and 10b can be prevented. This prevents the area of ​​the ceramic plate 21 from increasing, and also prevents the semiconductor unit 10 (semiconductor units 10a and 10b) from increasing in size. Furthermore, the semiconductor unit 10 can be made smaller, and the semiconductor device 1 can be made smaller as well.

[0063] In the following, modifications of the semiconductor device based on various combinations of such semiconductor units 10 will be described.

[0064] [Variation 1] In Modification 1, a case where another pair of semiconductor units 10a, 10b shown in FIGS. 4 and 5 are connected will be described with reference to FIG. 8. FIG. 8 is a plan view of a semiconductor device according to Modification 1 of the first embodiment. Note that the semiconductor units 10a, 10b included in the semiconductor device 1a in FIG. 8 are the same as those described in FIGS. 1 to 5, and therefore the reference numerals and detailed description thereof will be omitted. For convenience, Y1 to Y4 are assigned to the semiconductor units 10a, 10b of the semiconductor device 1a along the +Y direction.

[0065] As shown in Fig. 8, the semiconductor device 1a includes two pairs of semiconductor units 10a, 10b. That is, in the semiconductor device 1a, the semiconductor units 10a, 10b (Y3, Y4) are further connected in the +Y direction to the semiconductor units 10a, 10b (Y1, Y2) included in the semiconductor device 1. In other words, the semiconductor units 10 are arranged so that the main current direction D1 alternates. Note that the semiconductor units 10b, 10a (Y2, Y3) are mechanically and electrically connected to each other by control coupling wires 44a, 44b and sense coupling wires 45a, 45b, similar to the semiconductor units 10a, 10b shown in Fig. 4.

[0066] In the semiconductor device 1a, the semiconductor units 10a, 10a (Y1, Y3) are connected by a bus bar 50a, and the semiconductor units 10b, 10b (Y2, Y4) are connected by a bus bar 50b. Furthermore, the semiconductor units 10a, 10b, 10a, 10b (Y1, Y2, Y3, Y4) are connected by a bus bar 50c. Note that the connections of the bus bars 50a, 50b, 50c to the semiconductor units 10a, 10b are the same as in FIG. 5.

[0067] In the bus bar 50a, the leg portion 51a is joined to the input terminal region 23a2 of the circuit pattern 23a of the semiconductor units 10a, 10a (Y1, Y3). The wiring portion 52a is mechanically connected to the leg portion 51a. The wiring portion 52a extends in the ±Y direction in FIG. 8, perpendicular to the main current direction D1. Note that FIG. 8 shows only a portion of the wiring portion 52a. The wiring portion 52a can extend in a desired direction depending on the design and specifications of the semiconductor device 1a.

[0068] In the bus bar 50b, the leg portion 51b is also joined to the output terminal region 23b2 of the circuit pattern 23b of the semiconductor units 10b, 10b (Y2, Y4). The wiring portion 52b is mechanically connected to the leg portion 51b. The wiring portion 52b extends in the ±Y direction in FIG. 8, perpendicular to the main current direction D1. Note that FIG. 8 shows only a portion of the wiring portion 52b. The wiring portion 52b can extend in a desired direction depending on the design and specifications of the semiconductor device 1a.

[0069] In the bus bar 50c, the leg portion 51c is also joined to the output terminal region 23b2 of the circuit pattern 23b of the semiconductor unit 10a (Y1, Y3) and the input terminal region 23a2 of the circuit pattern 23a of the semiconductor unit 10b (Y2, Y4). The leg portion 51c is also joined by, for example, soldering or ultrasonic bonding. The wiring portion 52c extends in the ±Y directions in FIG. 8, orthogonal to the main current direction D1. Note that FIG. 8 shows only a portion of the wiring portion 52c. The wiring portion 52c can be extended in a desired direction depending on the design and specifications of the semiconductor device 1a.

[0070] The semiconductor device 1a of Modification 1 merely shows a case where two pairs of semiconductor units 10a and 10b are connected together. If necessary, a plurality of pairs of semiconductor units 10a and 10b may be connected together along the Y direction in FIG.

[0071] [Variation 2] In Modification 2, a case in which semiconductor units 10a and 10b are connected to the outer sides of the semiconductor units 10a and 10b shown in FIGS. 4 and 5 will be described with reference to FIG. 9. FIG. 9 is a plan view of a semiconductor device according to Modification 2 of the first embodiment. Note that the semiconductor units 10a and 10b included in the semiconductor device 1b in FIG. 9 are the same as those described in FIGS. 1 to 5, and therefore the reference numerals and detailed description thereof will be omitted. For convenience, Y1 to Y4 are assigned to the semiconductor units 10a and 10b of the semiconductor device 1b along the +Y direction.

[0072] As shown in FIG. 9, the semiconductor device 1b further includes a semiconductor unit 10a (Y1) on the −Y direction side and a semiconductor unit 10b (Y4) on the +Y direction side of the semiconductor units 10a, 10b (Y2, Y3) shown in FIGS. 1 to 5. That is, in the semiconductor device 1b, two semiconductor units 10a, 10a (Y1, Y2) and two semiconductor units 10b, 10b (Y3, Y4) are connected in a row. The semiconductor units 10a, 10a (Y1, Y2) are mechanically and electrically connected to each other by wires via their respective circuit patterns 23c, 23d, 23e, and 23f. The semiconductor units 10b, 10b (Y3, Y4) are similarly mechanically and electrically connected to each other by wires.

[0073] In the semiconductor device 1b, the semiconductor units 10a, 10a (Y1, Y2) are connected by a bus bar 50a, and the semiconductor units 10b, 10b (Y3, Y4) are connected by a bus bar 50b. Furthermore, the semiconductor units 10a, 10a, 10b, 10b (Y1, Y2, Y3, Y4) are connected by a bus bar 50c.

[0074] In the bus bar 50a, the leg portion 51a is joined to the input terminal region 23a2 of the circuit pattern 23a of the semiconductor units 10a, 10a (Y1, Y2). The wiring portion 52a is mechanically connected to the leg portion 51a. The wiring portion 52a extends in the ±Y direction in FIG. 9, perpendicular to the main current direction D1. Note that FIG. 9 shows only a portion of the wiring portion 52a. The wiring portion 52a can extend in a desired direction depending on the design and specifications of the semiconductor device 1b.

[0075] In the bus bar 50b, the leg portion 51b is also joined to the output terminal region 23b2 of the circuit pattern 23b of the semiconductor units 10b, 10b (Y3, Y4). The wiring portion 52b is mechanically connected to the leg portion 51b. The wiring portion 52b extends in the ±Y direction in FIG. 9, perpendicular to the main current direction D1. Note that FIG. 9 shows only a portion of the wiring portion 52b. The wiring portion 52b can extend in a desired direction depending on the design and specifications of the semiconductor device 1b.

[0076] In the bus bar 50c, the leg portion 51c is also joined to the output terminal region 23b2 of the circuit pattern 23b of the semiconductor unit 10a (Y1, Y2) and the input terminal region 23a2 of the circuit pattern 23a of the semiconductor unit 10b (Y3, Y4). The leg portion 51c is also joined by, for example, soldering or ultrasonic bonding. The wiring portion 52c extends in the ±Y directions in FIG. 9, orthogonal to the main current direction D1. Note that FIG. 9 shows only a portion of the wiring portion 52c. The wiring portion 52c can be extended in a desired direction depending on the design and specifications of the semiconductor device 1b.

[0077] The semiconductor device 1b of Modification 2 merely shows a case where a pair of semiconductor units 10a, 10b are connected in the ±Y direction of Fig. 9. If necessary, a plurality of semiconductor units 10a may be connected in the -Y direction of a pair of semiconductor units 10a, 10b, and a plurality of semiconductor units 10b may be connected in the +Y direction.

[0078] [Variation 3] In Modification 3, a case where the semiconductor units 10a and 10b shown in FIGS. 4 and 5 are arranged in the vertical direction (X direction) will be described with reference to FIGS. 10 and 11. FIGS. 10 and 11 are plan views of a semiconductor device according to Modification 3 of the first embodiment. The semiconductor units 10a and 10b included in the semiconductor device 1c in FIG. 10 are the same as those described in FIGS. 1 to 5, and therefore the reference numerals and detailed description thereof will be omitted. FIG. 11 also shows a case where a plurality of semiconductor devices 1c in FIG. 10 are arranged in the Y direction. For convenience, X1 and X2 are assigned to the semiconductor units 10a and 10b of the semiconductor device 1c in FIG. 10 along the −X direction. For convenience, X11, X12, X21, and X22 are assigned to the semiconductor units 10a and 10b of the semiconductor device 1d in FIG. 11 along the −X direction and +Y direction.

[0079] 10, the semiconductor device 1c includes a pair of semiconductor units 10a and 10b. That is, the semiconductor device 1c has the semiconductor units 10a and 10b (X1 and X2) arranged in a line parallel to the main current direction D1 and mechanically and electrically connected to each other. The main current directions D1 of the semiconductor unit 10a (X1) and the semiconductor unit 10b (X2) are the same (+X direction).

[0080] The semiconductor units 10a and 10b (X1 and X2) can be mechanically and electrically connected to each other by control coupling wires 44a and 44b and sense coupling wires 45a and 45b, similar to the semiconductor units 10a and 10b shown in Fig. 4. Furthermore, in the semiconductor device 1c, bus bars 50a, 50b, and 50c can be connected to the semiconductor units 10a and 10b, respectively, as appropriate (see, for example, Fig. 11).

[0081] In the semiconductor device 1c, the semiconductor units 10a and 10b may not have the sense coupling circuit pattern 23e and the gate coupling circuit pattern 23f. In this case, the control coupling wires 44a and 44b and the sense coupling wires 45a and 45b are also not required. This further reduces the substrate area, resulting in a compact semiconductor device 1c.

[0082] In the semiconductor device 1c, for example, the input terminal region 23a2 of the semiconductor unit 10a corresponds to the connection point C1 in FIG. 6. The output terminal region 23b2 of the semiconductor unit 10a corresponds to the connection point E1C2 in FIG. 6. The input terminal region 23a2 of the semiconductor unit 10b corresponds to the connection point E1C2 in FIG. 6. The output terminal region 23b2 of the semiconductor unit 10b corresponds to the connection point E2 in FIG. 6. This allows a half-bridge circuit to be formed in the semiconductor device 1c. Also, for example, the input terminal region 23a2 of the semiconductor unit 10b corresponds to the connection point C1 in FIG. 6. The output terminal region 23b2 of the semiconductor unit 10b corresponds to the connection point E1C2 in FIG. 6. The input terminal region 23a2 of the semiconductor unit 10a corresponds to the connection point E1C2 in FIG. 6. The output terminal region 23b2 of the semiconductor unit 10a corresponds to the connection point E2 in FIG. 6. This allows a half-bridge circuit to be formed.

[0083] Also, for example, the input terminal region 23a2 of the semiconductor units 10a and 10b corresponds to the connection point C1 in FIG. 6. The output terminal region 23b2 of the semiconductor units 10a and 10b corresponds to the connection point E1C2 in FIG. 6. This allows for the formation of a parallel upper arm A. Also, for example, the input terminal region 23a2 of the semiconductor units 10a and 10b corresponds to the connection point E1C2 in FIG. 6. The output terminal region 23b2 of the semiconductor units 10a and 10b corresponds to the connection point E2 in FIG. 6. This allows for the formation of a parallel lower arm B.

[0084] The semiconductor device 1c merely shows a pair of semiconductor units 10a and 10b connected in the vertical direction. If necessary, a plurality of pairs of semiconductor units 10a and 10b may be connected along the Y direction in FIG.

[0085] For example, a semiconductor device 1d shown in FIG. 11 is a semiconductor device in which another pair of semiconductor devices 1c is provided in addition to the semiconductor device 1c. In the semiconductor device 1d, another pair of semiconductor units 10a, 10b is arranged in the +Y direction of the pair of semiconductor units 10a, 10b shown in FIG. 10. That is, in the semiconductor device 1d, the semiconductor units 10a, 10b (X11, X12) are arranged vertically in the first row, and the semiconductor units 10a, 10b (X21, X22) are arranged vertically in the second row. That is, in the semiconductor device 1d, a plurality of semiconductor units 10a are arranged in the direction orthogonal to the main current direction D1 (+Y direction), and the semiconductor units 10b are arranged opposite the semiconductor units 10a in the direction orthogonal to the main current direction D1 (+Y direction). In the semiconductor device 1d, the semiconductor units 10a and 10b (X21, X22) are mechanically and electrically connected to each other by a control coupling wire 44b and a sense coupling wire 45b, similar to the semiconductor units 10a and 10b shown in FIG. 10. The semiconductor units 10a and 10b (X11, X12) can be mechanically and electrically connected to each other by a control coupling wire 44a and a sense coupling wire 45a, similar to the semiconductor units 10a and 10b shown in FIG. 10. Furthermore, the circuit patterns 23e and 23f of the semiconductor units 10a and 10a (X11, X21) are mechanically and electrically connected to each other by wires. The circuit patterns 23c and 23d of the semiconductor units 10b and 10b (X12, X22) are mechanically and electrically connected to each other by wires.

[0086] In the semiconductor device 1d, the semiconductor units 10a, 10a (X11, X21) are connected by bus bars 50a, 50c1, and the semiconductor units 10b, 10b (X12, X22) are connected by bus bars 50b, 50c2.

[0087] In the bus bar 50a, the leg portion 51a is joined to the input terminal region 23a2 of the circuit pattern 23a of the semiconductor unit 10a (X11, X21). The wiring portion 52a is mechanically connected to the leg portion 51a. The wiring portion 52a extends in the ±Y direction in FIG. 11, perpendicular to the main current direction D1. The wiring portion 52a can be extended in any direction required depending on the design and specifications of the semiconductor device 1d.

[0088] In the bus bar 50b, the leg portion 51b is also joined to the output terminal region 23b2 of the circuit pattern 23b of the semiconductor unit 10b (X12, X22). The wiring portion 52b is mechanically connected to the leg portion 51b. The wiring portion 52b extends in the ±Y direction in FIG. 11, perpendicular to the main current direction D1. The wiring portion 52b can be extended in any direction required depending on the design and specifications of the semiconductor device 1d.

[0089] The bus bar 50c1 includes a leg portion 51c1 and a wiring portion 52c1. The leg portion 51c1 is joined to the output terminal region 23b2 of the circuit pattern 23b of the semiconductor unit 10a (X11, X21). The leg portion 51c is also joined by, for example, soldering or ultrasonic bonding. The wiring portion 52c1 extends in the ±Y direction in FIG. 11, perpendicular to the main current direction D1. Note that FIG. 11 shows only a portion of the wiring portion 52c1. The wiring portion 52c1 can be extended in a desired direction depending on the design and specifications of the semiconductor device 1d.

[0090] The bus bar 50c2 includes a leg portion 51c2 and a wiring portion 52c2. The leg portion 51c2 is joined to the input terminal region 23a2 of the circuit pattern 23a of the semiconductor unit 10b (X12, X22). The leg portion 51c2 is also joined by, for example, soldering or ultrasonic bonding. The wiring portion 52c2 extends in the ±Y direction in FIG. 11, perpendicular to the main current direction D1. Note that FIG. 11 shows only a portion of the wiring portion 52c2. The wiring portion 52c2 can be extended in a desired direction depending on the design and specifications of the semiconductor device 1d.

[0091] 11 shows an example in which the semiconductor units 10a, 10b (X11, X12) and the semiconductor units 10a, 10b (X21, X22) are arranged so that the main current direction D1 is the same direction (+X direction). This is not limited to this example, and the semiconductor units 10a, 10b may be arranged at (X11, X12) and the semiconductor units 10a, 10b may be arranged at (X21, X22) so that the main current direction D1 is opposite. In other words, the semiconductor unit 10a whose main current direction D1 is the +X direction may be arranged at (X11, X21), and the semiconductor unit 10b whose main current direction D1 is the −X direction may be arranged at (X21, X22).

[0092] [Variation 4] In Modification 4, a case where the arrangement direction of the semiconductor units 10 in the semiconductor device 1c shown in FIG. 10 is changed will be described with reference to FIGS. 12 and 13. FIGS. 12 and 13 are plan views of a semiconductor device according to Modification 4 of the first embodiment. The semiconductor units 10a and 10b included in the semiconductor devices 1e1 and 1e2 in FIG. 12 are the same as those described in FIGS. 1 to 5, and therefore the reference numerals and detailed description will be omitted. Also, bus bars are omitted in FIG. 12. Also, FIG. 12(A) shows the semiconductor units 10a and 10b, and FIG. 12(B) shows the semiconductor units 10b and 10a, respectively, arranged along the −X direction. Also, X1 and X2 correspond to the respective units along the −X direction. For convenience, X11, X12, X21, and X22 correspond to the semiconductor units 10a and 10b of the semiconductor device 1e in FIG. 13 along the −X direction and +Y direction.

[0093] As shown in FIG. 12A, the semiconductor device 1e1 includes a pair of semiconductor units 10a and 10b. That is, the semiconductor device 1e1 has the semiconductor units 10a and 10b (X1 and X2) arranged in a line and mechanically and electrically connected. The main current directions D1 of the semiconductor unit 10a (X1) and the semiconductor unit 10b (X2) are opposite to each other. That is, the main current direction D1 of the semiconductor unit 10a is in the +X direction, and the main current direction D1 of the semiconductor unit 10b is in the -X direction.

[0094] The semiconductor units 10a and 10b (X1 and X2) can be mechanically and electrically connected to each other by control coupling wires 44a and 44b and sense coupling wires 45a and 45b, similar to the semiconductor units 10a and 10b shown in Fig. 10. Furthermore, in the semiconductor device 1e1, bus bars can be connected to the semiconductor units 10a and 10b, respectively (see Fig. 11, for example).

[0095] As shown in FIG. 12B, the semiconductor device 1e2 includes a pair of semiconductor units 10a and 10b. That is, the semiconductor device 1e2 has the semiconductor units 10b and 10a (X1 and X2) arranged in a line and mechanically and electrically connected. The main current directions D1 of the semiconductor units 10b (X1) and 10a (X2) are opposite to each other. That is, the main current direction D1 of the semiconductor unit 10b is in the −X direction, and the main current direction D1 of the semiconductor unit 10a is in the +X direction.

[0096] The semiconductor units 10b and 10a (X1 and X2) can be mechanically and electrically connected to each other by control coupling wires 44a and 44b and sense coupling wires 45a and 45b, similar to the semiconductor units 10b and 10a shown in Fig. 10. Furthermore, in the semiconductor device 1e2, bus bars can be connected to the semiconductor units 10b and 10a, respectively (see Fig. 11, for example).

[0097] In semiconductor devices 1e1 and 1e2, sense coupling circuit pattern 23e and gate coupling circuit pattern 23f may be omitted in semiconductor units 10a and 10b. In this case, control coupling wires 44a and 44b and sense coupling wires 45a and 45b are also unnecessary. This further reduces the substrate area, resulting in compact semiconductor devices 1e1 and 1e2.

[0098] Furthermore, in the semiconductor devices 1e1 and 1e2, for example, the input terminal region 23a2 of the semiconductor unit 10a corresponds to the connection point C1 in FIG. 6. The output terminal region 23b2 of the semiconductor unit 10a corresponds to the connection point E1C2 in FIG. 6. The input terminal region 23a2 of the semiconductor unit 10b corresponds to the connection point E1C2 in FIG. 6. The output terminal region 23b2 of the semiconductor unit 10b corresponds to the connection point E2 in FIG. 6. This allows a half-bridge circuit to be formed. Furthermore, for example, the input terminal region 23a2 of the semiconductor unit 10b corresponds to the connection point C1 in FIG. 6. The output terminal region 23b2 of the semiconductor unit 10b corresponds to the connection point E1C2 in FIG. 6. The input terminal region 23a2 of the semiconductor unit 10a corresponds to the connection point E1C2 in FIG. 6. The output terminal region 23b2 of the semiconductor unit 10a corresponds to the connection point E2 in FIG. 6. This allows a half-bridge circuit to be formed.

[0099] Also, for example, the input terminal region 23a2 of the semiconductor units 10a and 10b corresponds to the connection point C1 in FIG. 6. The output terminal region 23b2 of the semiconductor units 10a and 10b corresponds to the connection point E1C2 in FIG. 6. This allows for the formation of a parallel upper arm A. Also, for example, the input terminal region 23a2 of the semiconductor units 10a and 10b corresponds to the connection point E1C2 in FIG. 6. The output terminal region 23b2 of the semiconductor units 10a and 10b corresponds to the connection point E2 in FIG. 6. This allows for the formation of a parallel lower arm B.

[0100] Note that a plurality of semiconductor devices 1e1 and 1e2 may be connected along the Y direction in FIG. 12. In an example of this case, the semiconductor device 1e shown in FIG. 13 has the semiconductor devices 1e1 and 1e2 shown in FIG. 12 arranged side by side in the +Y direction. That is, in the semiconductor device 1e, the semiconductor units 10a and 10b (X11, X12) are arranged vertically in the first row, and the semiconductor units 10b and 10a (X21, X22) are arranged vertically in the second row. Note that in the semiconductor device 1e, the semiconductor units 10b and 10a (X21, X22) are mechanically and electrically connected to each other by the control coupling wire 44b and the sense coupling wire 45b, similar to the semiconductor units 10a and 10b shown in FIG. 12(B). Furthermore, the semiconductor units 10a and 10b (X11, X12) can be mechanically and electrically connected to each other by the control coupling wire 44a and the sense coupling wire 45a, similar to the semiconductor units 10a and 10b shown in FIG. 12(A). Furthermore, the semiconductor units 10a and 10b (X11, X21) are mechanically and electrically connected to each other by coupling wires 44b and 44a and sense coupling wires 45b and 45a, similar to the semiconductor chips 10a and 10b shown in Fig. 4. The semiconductor units 10b and 10a (X12, X22) are also mechanically and electrically connected to each other by wires.

[0101] 13, in the semiconductor device 1e, a bus bar 50a is connected to the semiconductor units 10a and 10b (X11, X12) on the −Y direction side. Furthermore, a bus bar 50b is connected to the semiconductor units 10a and 10b (X22, X21) on the +Y direction side. Furthermore, the semiconductor units 10a and 10b (X11, X21) on the +X direction side are connected by a bus bar 50c1. Furthermore, the semiconductor units 10b and 10a (X12, X22) on the −X direction side are connected by a bus bar 50c2.

[0102] In the bus bar 50a, the leg portion 51a is joined to the input terminal region 23a2 of each circuit pattern 23a of the semiconductor units 10a and 10b (X11 and X12) on the -Y direction side. The wiring portion 52a is mechanically connected to the leg portion 51a. However, the wiring portion 52a is U-shaped according to the arrangement positions of the semiconductor units 10a and 10b.

[0103] In the bus bar 50b, the leg 51b is also joined to the output terminal region 23b2 of the circuit pattern 23b of the semiconductor units 10b and 10a (X21 and X22) on the +Y direction side. The wiring portion 52b is mechanically connected to the leg 51b. In this case, the wiring portion 52b is also U-shaped according to the arrangement positions of the semiconductor units 10b and 10a.

[0104] In the bus bar 50c1, the leg 51c1 is also joined to the output terminal region 23b2 of the circuit pattern 23b and the input terminal region 23a2 of the circuit pattern 23a of the semiconductor units 10a, 10b (X11, X21) on the +X direction side. The leg 51c is also joined by, for example, soldering or ultrasonic bonding. The wiring portion 52c1 extends in the ±Y directions in FIG. 13, perpendicular to the main current direction D1. Note that FIG. 13 shows only a portion of the wiring portion 52c1. The wiring portion 52c1 can be extended in a desired direction depending on the design and specifications of the semiconductor device 1e.

[0105] In the bus bar 50c2, the leg portion 51c2 is also joined to the output terminal region 23b2 of the circuit pattern 23b and the input terminal region 23a2 of the circuit pattern 23a of the semiconductor units 10b, 10a (X12, X22) on the -X direction side. The leg portion 51c2 is also joined by, for example, soldering or ultrasonic bonding. The wiring portion 52c2 extends in the ±Y directions in FIG. 13, perpendicular to the main current direction D1. Note that FIG. 13 shows only a portion of the wiring portion 52c2. The wiring portion 52c2 can be extended in any direction required depending on the design and specifications of the semiconductor device 1e.

[0106] [Variation 5] In Modification 5, a case where a plurality of semiconductor units 10 shown in FIG. 1 are arranged in the Y direction with the same orientation will be described with reference to FIGS. 14 and 15. FIGS. 14 and 15 are plan views of a semiconductor device according to Modification 5 of the first embodiment. The semiconductor units 10a and 10b included in the semiconductor devices 1f and 1g in FIGS. 14 and 15 are the same as those described in FIGS. 1 to 5, and therefore the reference numerals and detailed description will be omitted. FIG. 14 illustrates a case where two sets of semiconductor units 10a, each of which has the same main current direction D1 facing the +X direction, are arranged in the Y direction. FIG. 15 illustrates a case where two sets of semiconductor units 10b, each of which has the same main current direction D1 facing the -X direction, are arranged in the Y direction. For convenience, the semiconductor units 10a and 10b included in the semiconductor devices 1f and 1g are assigned Y1 and Y2 along the +Y direction.

[0107] The semiconductor device 1f includes two pairs of semiconductor units 10a, 10a whose main current direction D1 faces the same +X direction. That is, the semiconductor device 1f has the semiconductor units 10a, 10a (Y1, Y2) arranged in a line in the Y direction and mechanically and electrically connected. That is, the semiconductor unit 10a (Y2) is arranged adjacent to the semiconductor unit 10a (Y1) in the direction perpendicular to the main current direction D1 (+Y direction).

[0108] The semiconductor units 10a, 10a (Y1, Y2) can be mechanically and electrically connected to each other by control coupling wires 44a, 44b and sense coupling wires 45a, 45b, similar to the semiconductor units 10a, 10a (Y1, Y2) shown in Fig. 9. In addition, in the semiconductor device 1f, a bus bar 50a is connected to the semiconductor units 10a, 10b (Y1, Y2), similar to Fig. 9.

[0109] Such a semiconductor device 1f has a configuration obtained by including semiconductor units 10a all facing the main current direction D1. The semiconductor device 1f is not limited to including two sets of semiconductor units 10a, and may include one set, or three or more sets of semiconductor units 10a.

[0110] On the other hand, as shown in FIG. 15, the semiconductor device 1g is configured such that the main current direction D1 of the semiconductor device 1f faces the -X direction, which is the same direction. That is, the semiconductor device 1g has semiconductor units 10b, 10b (Y1, Y2) arranged in a line in the Y direction and mechanically and electrically connected. The semiconductor units 10b, 10b (Y1, Y2) can be mechanically and electrically connected to each other by control coupling wires 44a, 44b and sense coupling wires 45a, 45b, similar to the semiconductor units 10b, 10b (Y3, Y4) shown in FIG. 9. In addition, in the semiconductor device 1g, a bus bar 50b is connected to the semiconductor units 10b, 10b (Y1, Y2), similar to FIG. 9.

[0111] Such a semiconductor device 1g has a single configuration with semiconductor units 10b in which all of the main current directions D1 are oriented in the same direction. Furthermore, the inputs and outputs of the semiconductor device 1g are interchangeable with those of the semiconductor device 1f. The semiconductor device 1g is also not limited to two sets of semiconductor units 10b, and may include one set, or three or more sets. In the semiconductor devices 1f and 1g, the sense coupling circuit pattern 23e and the gate coupling circuit pattern 23f may be omitted in the semiconductor units 10a and 10b. In this case, the control coupling wires 44a and 44b and the sense coupling wires 45a and 45b are also unnecessary. This further reduces the substrate area, resulting in compact semiconductor devices 1f and 1g.

[0112] [Second embodiment] In the second embodiment, a case where two types of semiconductor chips, a switching element and a diode element, are used instead of the RC-IGBT used in the first embodiment will be described with reference to FIG. 16. FIG. 16 is a plan view of a semiconductor unit included in a semiconductor device according to the second embodiment. A semiconductor unit 11 according to the second embodiment has the same configuration as the semiconductor unit 10, except for the semiconductor chips 30a and 30b. Therefore, components of the semiconductor unit 11 that are similar to those of the semiconductor unit 10 are given the same reference numerals, and their description will be simplified or omitted. The semiconductor unit 11 may not have the sense coupling circuit pattern 23e and the gate coupling circuit pattern 23f. This can further reduce the substrate area.

[0113] Semiconductor chips 30a and 30b are arranged in two rows along the −X direction on the circuit pattern 23a of the semiconductor unit 11. The semiconductor chips 30a and 30b are also made mainly of silicon or silicon carbide.

[0114] The semiconductor chip 30a is a switching element. Examples of switching elements include an IGBT or a power MOSFET. If the semiconductor chip 30a is an IGBT, it has an input electrode (collector electrode) on its back surface and a control electrode 31 (gate electrode) and an output electrode 32 (emitter electrode) on its front surface. If the semiconductor chip 30a is a power MOSFET, it has an input electrode (drain electrode) on its back surface and a control electrode 31 (gate electrode) and an output electrode 32 (source electrode) on its front surface. The back surface of the semiconductor chip 30a is mechanically and electrically bonded to the circuit pattern 23a by solder. The semiconductor chip 30a is bonded to the circuit pattern 23a with the control electrode 31 facing the -X side. The semiconductor chips 30a may be arranged so that their control electrodes 31 face each other, as in the semiconductor chip 30 of FIG. 1.

[0115] The semiconductor chip 30b is a diode element. Examples of the diode element include FWDs such as SBD (Schottky Barrier Diode) and PiN (P-intrinsic-N) diodes. Such a semiconductor chip 30b has an output electrode (cathode electrode) on its back surface and an input electrode (anode electrode) on its front surface. The back surface of the semiconductor chip 30b is mechanically and electrically joined to the circuit pattern 23a by soldering.

[0116] Furthermore, a main current wire 41 connects an output electrode on the front surface of semiconductor chip 30a to an input electrode on the front surface of semiconductor chip 30b by stitch bonding, and is further connected to circuit pattern 23b. A control wire 42 mechanically and electrically connects a central contact region 23c1 of circuit pattern 23c to control electrode 31 of semiconductor chip 30a.

[0117] 4 and 5, a semiconductor device including a half-bridge circuit can be obtained by arranging such semiconductor units 11 in a row in the Y direction so that the main current directions D1 of two semiconductor units 11 are opposite to each other, and connecting the semiconductor units to each other. Also, by appropriately combining the arrangement of multiple semiconductor units 11 and the orientation of the main current directions D1, semiconductor devices such as those of the first embodiment and its modifications can be easily obtained.

[0118] Furthermore, since the two semiconductor units 11 used in the semiconductor device are made of different ceramic circuit substrates 20, insulation between the semiconductor units is maintained, and short circuits between the semiconductor units can be prevented. This prevents the area of ​​the ceramic plate 21 from increasing, and also prevents the semiconductor unit 11 from increasing in size. Furthermore, the semiconductor unit 11 can be made smaller, and the semiconductor device can be made smaller as well.

[0119] [Third embodiment] The third embodiment will be described with reference to FIG. 17, in which a circuit pattern different from that of the semiconductor unit 10 of the first embodiment is used. FIG. 17 is a plan view of a semiconductor unit included in a semiconductor device of the third embodiment. Note that, in a semiconductor unit 12 of the third embodiment, the shapes of circuit patterns 23a and 23c are changed, the positions of circuit patterns 23c and 23d are swapped, and the positions of circuit patterns 23e and 23f are swapped, compared to the semiconductor unit 10. Furthermore, components of the semiconductor unit 12 that are similar to those of the semiconductor unit 10 are assigned the same reference numerals, and their description will be omitted. Only components that are different from those of the semiconductor unit 10 will be described.

[0120] In the semiconductor unit 12, first, the semiconductor chip 30 is bonded to the circuit pattern 23a with the control electrodes 31 facing outward (towards the third and fourth sides 21c and 21d).

[0121] The circuit pattern 23a is generally rectangular and includes a protruding region 23a3 that protrudes downward in FIG. 17. The circuit pattern 23a is formed from the third side 21c to the fourth side 21d of the ceramic plate 21. That is, the end (on the -Y direction side) of the circuit pattern 23a is formed adjacent to the third side 21c of the ceramic plate 21, with no other circuit patterns formed therebetween. The end (on the +Y direction side) of the circuit pattern 23a is formed adjacent to and facing the fourth side 21d of the ceramic plate 21, with no other circuit patterns formed therebetween. The width of the protruding region 23a3 in the ±Y directions is narrower than the width of the circuit pattern 23a in the ±Y directions. Therefore, there is a gap between the ±Y side end of the protruding region 23a3 and the third and fourth sides 21c and 21d of the ceramic plate 21. The protruding region 23a3 of the circuit pattern 23a includes one input terminal region 23a2.

[0122] In such a circuit pattern 23a, the semiconductor chips 30 are arranged in an area including the center line (dotted dash line XX). In Fig. 17, four semiconductor chips 30 are arranged two by two, vertically arranged (in the ±X direction) around the center line (dotted dash line XX). Furthermore, two by two, arranged symmetrically about the center line (dotted dash line YY) between the third side 21c and the fourth side 21d of the ceramic plate 21. The control electrodes 31 of each semiconductor chip 30 are arranged on the third side 21c and the fourth side 21d side, and are arranged opposite each other with the center line (dotted dash line YY) as the center.

[0123] The circuit pattern 23d is formed adjacent to the outside of the circuit pattern 23a (on the opposite side of the main current direction D1). The circuit pattern 23d is U-shaped in plan view along the protruding region 23a3 of the circuit pattern 23a. Both ends of the circuit pattern 23d are mechanically and electrically connected to the output electrodes 32 of the semiconductor chip 30 by sense wires 46. The circuit pattern 23c is formed adjacent to the outside of the circuit pattern 23d. That is, the circuit pattern 23c is also U-shaped in plan view and formed along the circuit pattern 23d. Both ends of the circuit pattern 23c are mechanically and electrically connected to the control electrodes 31 of the semiconductor chip 30 by control wires 42.

[0124] Furthermore, in the semiconductor unit 12, the positions of the circuit patterns 23e and 23f in the semiconductor unit 10 are swapped. That is, the circuit pattern 23e (second sense circuit pattern) may be electrically connected to the output electrode 32 of the semiconductor chip 30. The circuit pattern 23e is linear and formed adjacent to the outside (main current direction D1) of the circuit pattern 23b. An end (on the ±Y direction side) of the circuit pattern 23e is formed corresponding to an end (on the ±Y direction side) of the circuit pattern 23f. The circuit pattern 23f (second control circuit pattern) may be electrically connected to the control electrode 31 of the semiconductor chip 30. The circuit pattern 23f is linear and formed adjacent to the outside (main current direction D1) of the circuit pattern 23e. An end (on the ±Y direction side) of the circuit pattern 23f is formed corresponding to an end (on the ±Y direction side) of the circuit pattern 23b.

[0125] Furthermore, these circuit patterns 23d, 23e are formed at positions that are symmetrical with respect to the center line (dash-dotted line XX) that is perpendicular to the main current direction D1 of the ceramic circuit substrate 20. Furthermore, the circuit patterns 23d, 23e are formed at equal distances from the first and second sides 21a, 21b of the ceramic plate 21. Note that the semiconductor unit 12 does not necessarily need to have the sense-coupling circuit pattern 23e and the gate-coupling circuit pattern 23f. This allows for further reduction in the substrate area.

[0126] 4 and 5, a semiconductor device including a half-bridge circuit can be obtained by arranging such semiconductor units 12 in a row in the Y direction so that the main current directions D1 of two semiconductor units 12 are opposite to each other, and connecting the semiconductor units to each other. In this way, by combining the arrangement of the semiconductor units 12 and the orientation of the main current direction D1, semiconductor devices such as those of the first embodiment and its modifications can be easily obtained.

[0127] Furthermore, since the two semiconductor units 12 used in the semiconductor device are made of different ceramic circuit substrates 20, insulation between the semiconductor units 12 is maintained, and short circuits between the semiconductor units 12 can be suppressed. This prevents the area of ​​the ceramic plate 21 from increasing, and also prevents the semiconductor units 12 from increasing in size. Furthermore, the semiconductor units 12 can be made smaller, and the semiconductor device as a whole can be made smaller.

[0128] The foregoing merely illustrates the principles of the present invention. Further, since numerous modifications and changes will be apparent to those skilled in the art, the present invention is not limited to the exact construction and application shown and described above, and all corresponding modifications and equivalents are deemed to be within the scope of the present invention as defined by the appended claims and their equivalents. [Explanation of symbols]

[0129] 1, 1a, 1b, 1c, 1d, 1e, 1f, 1g, 1e1, 1e2 semiconductor device 10, 10a, 10b, 11, 12 Semiconductor unit 20 Ceramic circuit board 21 Ceramic plate 21a Side 1 21b Side 2 21c Third side 21d Side 4 22 Metal plate 23a, 23b, 23c, 23d, 23e, 23f Circuit patterns 23a1 recess 23a2 Input terminal area 23a3 Protruding area 23b2 Output terminal area 23c1 Contact area 30, 30a, 30b Semiconductor chip 31 Control electrode 32 Output electrode 41 Main current wire 42 control wire 44a, 44b Control connection wire 45a, 45b Sense connecting wire 46 Sense wire 50a, 50b, 50c, 50c1, 50c2 busbars 51a,51b,51c,51c1,51c2 Legs 52a,52b,52c,52c1,52c2 Wiring section

Claims

1. A semiconductor device comprising a semiconductor unit having a semiconductor chip, and an input circuit metal and an output circuit metal electrically connected to the semiconductor chip, the output circuit metal including an output terminal area and adjacent to the input circuit metal, the input circuit metal including an input terminal area on the opposite side of the output circuit metal with respect to the semiconductor chip where the semiconductor chip is disposed, and a main current flows in a main current direction from the input circuit metal to the output circuit metal, The semiconductor unit comprises: a first semiconductor unit constituting an upper arm portion in which the input terminal region of the input circuit metal and the output terminal region of the output circuit metal are connected to a positive electrode and a load, respectively; a second semiconductor unit constituting a lower arm portion in which the input terminal region of the input circuit metal and the output terminal region of the output circuit metal are connected to the load and the negative electrode, respectively; Including, the first semiconductor units and the second semiconductor units are arranged alternately in a left-right direction perpendicular to the main current direction so that the main current directions are opposite to each other; Semiconductor device.

2. A semiconductor device comprising a semiconductor unit having a semiconductor chip, and an input circuit metal and an output circuit metal electrically connected to the semiconductor chip, the output circuit metal including an output terminal area and adjacent to the input circuit metal, the input circuit metal including an input terminal area on the opposite side of the output circuit metal with respect to the semiconductor chip where the semiconductor chip is disposed, and a main current flows in a main current direction from the input circuit metal to the output circuit metal, The semiconductor unit comprises: a first semiconductor unit constituting an upper arm portion in which the input terminal region of the input circuit metal and the output terminal region of the output circuit metal are connected to a positive electrode and a load, respectively; a second semiconductor unit constituting a lower arm portion in which the input terminal region of the input circuit metal and the output terminal region of the output circuit metal are connected to the load and the negative electrode, respectively; Including, a plurality of the first semiconductor units are arranged in a left-right direction perpendicular to the main current direction, and a plurality of the second semiconductor units are arranged in a left-right direction with the main current direction opposite to that of the first semiconductor units; Semiconductor device.

3. The first semiconductor unit and the second semiconductor unit each have two short sides and two long sides.

3. The semiconductor device according to claim 1.

4. a longitudinal direction of the first semiconductor unit and the second semiconductor unit is the main current direction; The semiconductor device according to claim 3 .

5. the input terminal region of the first semiconductor unit and the output terminal region of the second semiconductor unit are provided on the same side in the longitudinal direction; The semiconductor device according to claim 4 .

6. a first wiring member extending in the left-right direction and joined to the input terminal area of ​​the first semiconductor unit; a second wiring member extending in the left-right direction and joined to the output terminal region of the second semiconductor unit; The semiconductor device according to claim 5 , comprising:

7. a third wiring member provided on the opposite side of the first wiring member and the second wiring member in the longitudinal direction, extending in the left-right direction, and joined to the output terminal region of the first semiconductor unit and the input terminal region of the second semiconductor unit; The semiconductor device according to claim 6.

8. the first semiconductor unit and the second semiconductor unit each include a plurality of the semiconductor chips; The semiconductor device according to claim 1 .

9. The semiconductor chip is an RC-IGBT. The semiconductor device according to claim 1 .

10. the first semiconductor unit and the second semiconductor unit each have a control circuit metal and a sense circuit metal electrically connected to the semiconductor chip; The semiconductor device according to claim 1 .

11. the input circuit metal, the output circuit metal, the control circuit metal, and the sense circuit metal are circuit patterns provided on an insulating plate; The semiconductor device according to claim 10.

12. a heat dissipation substrate on which the first semiconductor unit and the second semiconductor unit are mounted, The semiconductor device according to claim 1 .

13. The first semiconductor unit and the second semiconductor unit each have the semiconductor chip, the input circuit metal, and the output circuit metal provided on an upper surface of a ceramic circuit substrate. The semiconductor device according to claim 1 .

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