Directed self-assembly structures and techniques

Abstract

Disclosed herein are structures and techniques that utilize directed self-assembly for microelectronic device fabrication. For example, a microelectronic structure may include a patterned region including a first conductive line and a second conductive line, the second conductive line being adjacent to the first conductive line, and a disordered region having a disordered layered pattern, the disordered region being coplanar with the patterned region.

Description

[Technical Field]

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] This application claims priority to U.S. Provisional Patent Application No. 63 / 033,721, entitled "Chemical Compositions and Methods for Patterning Microelectronic Device Structures," filed June 2, 2020, and U.S. Nonprovisional Patent Application No. 17 / 032,517, entitled "Directed Self-Assembly Structures and Techniques," filed September 25, 2020. These priority applications are hereby incorporated herein in their entireties. [Background technology]

[0002] Conventional microelectronic fabrication techniques may not be able to reliably pattern particularly small features, resulting in limited size and performance of microelectronic devices. [Brief explanation of the drawings]

[0003] Embodiments will be readily understood by the following detailed description taken in conjunction with the accompanying drawings, in which: To facilitate this description, like reference numerals refer to like structural elements, and in which embodiments are shown by way of example, and not by way of limitation.

[0004] [Figure 1A] 1A-1D are various views of microelectronic structures including lines with low line edge roughness (LER) according to various embodiments. [Figure 1B] 1A-1D are various views of microelectronic structures including lines with low line edge roughness (LER) according to various embodiments. [Figure 1C] 1A-1D are various views of microelectronic structures including lines with low line edge roughness (LER) according to various embodiments.

[0005] [Figure 2A] 2A-2D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 1 according to various embodiments. [Figure 2B] 2A-2D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 1 according to various embodiments. [Figure 2C] 2A-2D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 1 according to various embodiments. [Figure 2D] 2A-2D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 1 according to various embodiments. [Figure 2E] 2A-2D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 1 according to various embodiments. [Figure 2F] 2A-2D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 1 according to various embodiments. [Figure 2G] 2A-2D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 1 according to various embodiments. [Figure 2H] 2A-2D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 1 according to various embodiments. [Figure 2I] 2A-2D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 1 according to various embodiments. [Figure 2J] 2A-2D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 1 according to various embodiments. [Figure 2K] 2A-2D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 1 according to various embodiments. [Figure 2L] 2A-2D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 1 according to various embodiments.

[0006] [Figure 3] 2A-2D illustrate stages in another exemplary process for fabricating the microelectronic structure of FIG. 1 according to various embodiments.

[0007] [Figure 4A] 1A-1C are various views of another microelectronic structure including lines with low line edge roughness (LER) according to various embodiments. [Figure 4B]1A-1C are various views of another microelectronic structure including lines with low line edge roughness (LER) according to various embodiments.

[0008] [Figure 5A] 5A-5C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 4 according to various embodiments. [Figure 5B] 5A-5C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 4 according to various embodiments. [Figure 5C] 5A-5C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 4 according to various embodiments. [Figure 5D] 5A-5C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 4 according to various embodiments.

[0009] [Figure 6A] 1A-1D are various views of another microelectronic structure including lines with low LER according to various embodiments. [Figure 6B] 1A-1D are various views of another microelectronic structure including lines with low LER according to various embodiments.

[0010] [Figure 7A] 7A-7D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 6 according to various embodiments. [Figure 7B] 7A-7D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 6 according to various embodiments. [Figure 7C] 7A-7D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 6 according to various embodiments. [Figure 7D] 7A-7D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 6 according to various embodiments. [Figure 7E] 7A-7D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 6 according to various embodiments. [Figure 7F] 7A-7D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 6 according to various embodiments. [Figure 7G] 7A-7D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 6 according to various embodiments. [Figure 7H] 7A-7D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 6 according to various embodiments.

[0011] [Figure 8A] 1A-1D are various views of a microelectronic structure including lines with low LER and lines with high LER, according to various embodiments. [Figure 8B] 1A-1D are various views of a microelectronic structure including lines with low LER and lines with high LER, according to various embodiments.

[0012] [Figure 9A] 9A-9C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 8 according to various embodiments. [Figure 9B] 9A-9C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 8 according to various embodiments. [Figure 9C] 9A-9C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 8 according to various embodiments. [Figure 9D] 9A-9C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 8 according to various embodiments. [Figure 9E] 9A-9C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 8 according to various embodiments. [Figure 9F] 9A-9C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 8 according to various embodiments. [Figure 9G] 9A-9C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 8 according to various embodiments. [Figure 9H] 9A-9C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 8 according to various embodiments. [Figure 9I] 9A-9C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 8 according to various embodiments. [Figure 9J]9A-9C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 8 according to various embodiments. [Figure 9K] 9A-9C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 8 according to various embodiments. [Figure 9L] 9A-9C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 8 according to various embodiments. [Figure 9M] 9A-9C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 8 according to various embodiments.

[0013] [Figure 10A] 1A-1D are various views of another microelectronic structure including lines with low LER according to various embodiments. [Figure 10B] 1A-1D are various views of another microelectronic structure including lines with low LER according to various embodiments.

[0014] [Figure 11A] 11A-11D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 10 according to various embodiments. [Figure 11B] 11A-11D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 10 according to various embodiments. [Figure 11C] 11A-11D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 10 according to various embodiments. [Figure 11D] 11A-11D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 10 according to various embodiments. [Figure 11E] 11A-11D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 10 according to various embodiments. [Figure 11F] 11A-11D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 10 according to various embodiments. [Figure 11G] 11A-11D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 10 according to various embodiments. [Figure 11H]11A-11D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 10 according to various embodiments.

[0015] [Figure 12A] 1A-1C are various views of another microelectronic structure including lines with low LER and lines with high LER, according to various embodiments. [Figure 12B] 1A-1C are various views of another microelectronic structure including lines with low LER and lines with high LER, according to various embodiments.

[0016] [Figure 13A] 13A-13C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 12 according to various embodiments. [Figure 13B] 13A-13C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 12 according to various embodiments. [Figure 13C] 13A-13C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 12 according to various embodiments. [Figure 13D] 13A-13C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 12 according to various embodiments. [Figure 13E] 13A-13C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 12 according to various embodiments. [Figure 13F] 13A-13C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 12 according to various embodiments. [Figure 13G] 13A-13C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 12 according to various embodiments. [Figure 13H] 13A-13C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 12 according to various embodiments. [Figure 13I] 13A-13C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 12 according to various embodiments. [Figure 13J] 13A-13C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 12 according to various embodiments. [Figure 13K]13A-13C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 12 according to various embodiments. [Figure 13L] 13A-13C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 12 according to various embodiments. [Figure 13M] 13A-13C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 12 according to various embodiments. [Figure 13N] 13A-13C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 12 according to various embodiments. [Figure 13O] 13A-13C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 12 according to various embodiments. [Figure 13P] 13A-13C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 12 according to various embodiments.

[0017] [Figure 14A] 1A-1D are various views of another microelectronic structure including lines with low LER according to various embodiments. [Figure 14B] 1A-1D are various views of another microelectronic structure including lines with low LER according to various embodiments.

[0018] [Figure 15A] 15A-15C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 14 according to various embodiments. [Figure 15B] 15A-15C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 14 according to various embodiments. [Figure 15C] 15A-15C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 14 according to various embodiments. [Figure 15D] 15A-15C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 14 according to various embodiments. [Figure 15E] 15A-15C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 14 according to various embodiments. [Figure 15F]15A-15C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 14 according to various embodiments. [Figure 15G] 15A-15C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 14 according to various embodiments.

[0019] [Figure 16A] 1A-1D are various views of another microelectronic structure including lines with low LER according to various embodiments. [Figure 16B] 1A-1D are various views of another microelectronic structure including lines with low LER according to various embodiments.

[0020] [Figure 17A] 17A-17D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 16 according to various embodiments. [Figure 17B] 17A-17D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 16 according to various embodiments. [Figure 17C] 17A-17D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 16 according to various embodiments. [Figure 17D] 17A-17D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 16 according to various embodiments. [Figure 17E] 17A-17D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 16 according to various embodiments. [Figure 17F] 17A-17D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 16 according to various embodiments. [Figure 17G] 17A-17D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 16 according to various embodiments.

[0021] [Figure 18] 1A-1C are top views of microelectronic structures including lines with low LER at multiple pitches according to various embodiments.

[0022] [Figure 19A]20A-20C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 18 according to various embodiments. [Figure 19B] 20A-20C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 18 according to various embodiments. [Figure 19C] 20A-20C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 18 according to various embodiments. [Figure 19D] 20A-20C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 18 according to various embodiments. [Figure 19E] 20A-20C illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 18 according to various embodiments.

[0023] [Figure 20] 20 illustrates stages in another exemplary process for fabricating the microelectronic structure of FIG. 18, according to various embodiments.

[0024] [Figure 21] 1A-1C are cross-sectional side views of microelectronic structures including vias in conductive contact with lines having low LER according to various embodiments.

[0025] [Figure 22A] 22A-22D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 21 according to various embodiments. [Figure 22B] 22A-22D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 21 according to various embodiments. [Figure 22C] 22A-22D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 21 according to various embodiments. [Figure 22D] 22A-22D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 21 according to various embodiments. [Figure 22E] 22A-22D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 21 according to various embodiments. [Figure 22F] 22A-22D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 21 according to various embodiments.

[0026] [Figure 23] 1 is a cross-sectional side view of another microelectronic structure including a via in conductive contact with a line having a low LER in accordance with various embodiments.

[0027] [Figure 24A] 24A-24D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 23 according to various embodiments. [Figure 24B] 24A-24D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 23 according to various embodiments. [Figure 24C] 24A-24D illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 23 according to various embodiments.

[0028] [Figure 25] 1A-1C are top views of microelectronic structures including pitch division artifacts in accordance with various embodiments. [Figure 26] 1A-1C are top views of microelectronic structures including pitch division artifacts in accordance with various embodiments. [Figure 27] 1A-1C are top views of microelectronic structures including pitch division artifacts in accordance with various embodiments.

[0029] [Figure 28] FIG. 1 is a top view of a wafer and die that may include any of the microelectronic structures disclosed herein.

[0030] [Figure 29] 1 is a cross-sectional side view of a microelectronic device that may include any of the microelectronic structures disclosed herein.

[0031] [Figure 30] 1 is a cross-sectional side view of a microelectronic package that may include any of the microelectronic structures disclosed herein.

[0032] [Figure 31] FIG. 1 is a cross-sectional side view of a microelectronic device assembly that may include any of the microelectronic structures disclosed herein.

[0033] [Figure 32] FIG. 1 is a block diagram of an exemplary computing device that may include any of the microelectronic structures disclosed herein. DETAILED DESCRIPTION OF THE INVENTION

[0034] Disclosed herein are structures and techniques that utilize directed self-assembly (DSA) for microelectronic device fabrication. The structures and techniques disclosed herein can achieve fine feature sizes with low roughness and defect densities, and may be particularly suitable for accompanying and enhancing extreme ultraviolet (EUV) lithography techniques.

[0035] Existing conventional lithography techniques, such as existing conventional EUV techniques, may not be able to pattern features that are both small enough and low enough in defects to be used in commercial microelectronic devices. For example, conventional EUV lithography can suffer from high roughness and excessive bridging defects at tight pitches (e.g., pitches smaller than 32 nanometers), which can limit or significantly hinder the deployment of EUV patterning techniques (e.g., spacer-based pitch division techniques with a resist “backbone” defined by EUV lithography). Conventional EUV lithography techniques also suffer from a trade-off between EUV dose and resist thickness. While higher EUV doses have the potential to pattern lines with lower roughness, such higher EUV doses typically require thinner resist layers to achieve the desired depth of focus and avoid pattern collapse. However, these thinner resist layers typically cannot withstand etch transfer (i.e., transferring the resist pattern to one or more underlying layers) as well as thicker resists. These limitations pose significant obstacles to the adoption of EUV technology in commercial microelectronic manufacturing processes.

[0036] Various embodiments disclosed herein may use DSA operations to overcome the shortcomings of conventional EUV lithography techniques. DSA-based techniques may take advantage of the property of some materials to self-assemble into specific patterns under specific conditions, and these patterns may be used in various ways to fabricate small, precise features in microelectronic devices. For example, various embodiments disclosed herein may include lines with low line edge roughness (LER) at different pitches that can be reliably fabricated using DSA-based techniques.

[0037] In the following detailed description, reference is made to the accompanying drawings, which form a part of this specification. In the accompanying drawings, where like reference numerals refer to like parts throughout, there are shown by way of illustration embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.

[0038] Various operations may be described sequentially as multiple separate actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order presented. The described operations may also be performed in a different order than in the described embodiment. Various additional operations may be performed and / or described operations may be omitted in further embodiments.

[0039] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C). The phrase "A, B, or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C). The drawings are not necessarily to scale. While many of the drawings show rectilinear structures with flat walls and square corners, this is for ease of illustration only; actual devices made using these techniques will exhibit rounded corners, surface roughness, and other features.

[0040] The description uses the phrases "in an embodiment" or "in embodiments," each of which may refer to one or more of the same or different embodiments. Furthermore, terms such as "comprising," "including," and "having," when used with respect to embodiments of the present disclosure, are synonymous. As used herein, a "conductive" material refers to a material that is electrically conductive, unless otherwise specified. When used to describe a range of dimensions, the phrase "between X and Y" refers to the range inclusive of X and Y. For convenience, the phrase "Figure 1" may be used to refer to the set of drawings named Figures 1A to 1C, the phrase "Figure 2" may be used to refer to the set of drawings named Figures 2A to 2L, and so on. The mask material is referred to by various reference numbers that are repeated among different ones of the drawings (e.g., mask material 126, mask material 128, mask material 148, etc.), but this is merely for ease of illustration; the mask material referred to by a particular reference number in one of the drawings (e.g., mask material 128 in the drawing of FIG. 7) is not necessarily the same mask material as the mask material referred to by the same reference number in another drawing (e.g., mask material 128 in the drawing of FIG. 9).

[0041] 1A-1C show various views of an exemplary microelectronic structure 100 including a line 140 having a low LER. Such a line 140 may be referred to herein as a low-LER line 140. FIG. 1A is a side cross-sectional view of the microelectronic structure 100 through section AA in FIG. 1B, FIG. 1B is a top view of the microelectronic structure 100, and FIG. 1C is a detailed top view of the disordered layered structure 138 of the microelectronic structure 100 (discussed further below). The low-LER line 140 in FIG. 1 may have an edge 130, as shown. The term "low," when used in reference to the low-LER line 140, is relative, indicating that the LER of the low-LER line 140 is less than the LER of other "high-LER" lines (e.g., the high-LER line 170, described below). LER may measure the local deviation of a line edge from its center of mass. In some embodiments, LER may be quantified as the mean-square deviation of the line edge from a best-fit straight line. In some embodiments, the low LER lines 140 may be patterned using various of the DSA-based techniques disclosed herein, and the high LER lines may be patterned using conventional techniques (e.g., EUV lithography). In some embodiments, the LER of the low LER lines 140 may be less than 1.2 nanometers, and the LER of the high LER lines may be greater than 1.2 nanometers. In other embodiments, the LER of the low LER lines 140 may be less than 1.5 nanometers, and the LER of the high LER lines may be greater than 1.5 nanometers, although these are merely examples and other LER thresholds may apply (e.g., depending on the pitch and process). In some embodiments, the microelectronic structure 100 of FIG. 1 may be part of an interconnect layer in a microelectronic device (e.g., as described below with reference to FIG. 29).

[0042] The microelectronic structure 100 of FIG. 1 includes a plurality of low LER lines 140 formed from a juxtaposition of line materials 120 with a dielectric material 102. The line materials 120 may include one or more layers of various materials, such as one or more layers of a liner material and a filler material. In some embodiments, the liner material may include tantalum, tantalum nitride, titanium, titanium nitride, cobalt, or ruthenium (e.g., combinations thereof), and the filler material may include tungsten, cobalt (e.g., as cobalt silicide), ruthenium, molybdenum, copper, silver, nickel (e.g., as nickel silicide), gold, aluminum, other metals or alloys, or other combinations of materials. The dielectric material 102 may include any suitable dielectric material. For example, in some embodiments, the dielectric material 102 may include inorganic dielectric materials such as silicon oxide, carbon-doped oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide, or insulating metal oxides such as hafnium oxide and zirconium oxide. In some embodiments, the dielectric material 102 may have a porosity and / or voids of less than 50% (e.g., less than 30%). In some embodiments, the pitch 172 of the low LER lines 140 may be less than 30 nanometers (e.g., less than 24 nanometers), the linewidth 174 of the low LER lines 140 may be less than 15 nanometers (e.g., less than 12 nanometers), and / or the spacing between adjacent low LER lines 140 may be less than 15 nanometers (e.g., less than 12 nanometers).

[0043] The low LER lines 140 may be part of a patterned region 142, and the microelectronic structure 100 may include one or more unpatterned regions 144. In some embodiments, when a DSA-based technique is used to fabricate the microelectronic structure 100 (e.g., as described below with reference to FIG. 2), the unpatterned regions 144 may include a disordered layered structure 138, similar to that shown in FIG. 1C. The disordered layered structure 138 may include line material 120 and dielectric material 102 that are patterned according to the disordered layered structure of the DSA material, which was not ordered during a prior patterning operation (e.g., due to the absence of brush material patterned for the unpatterned regions 144, as described below with reference to FIG. 2). The presence of a disordered layered structure 138 in the unpatterned regions 144 of the microelectronic structure 100, similar to that shown in FIG. 1C, may indicate the use of a DSA-based technique during the fabrication of the patterned regions 142. In some embodiments, the non-patterned region 144 may be part of a transition region of the die containing the microelectronic structure 100, may be under a guard ring of the die containing the microelectronic structure 100, or may be within the frame of the die containing the microelectronic structure 100 (e.g., may be any of the dies 1502 described below with reference to FIG. 28).

[0044] 2A-2L illustrate stages in an exemplary process for fabricating the microelectronic structure 100 of FIG. 1 according to various embodiments. While the operations of the method of FIG. 2 (and other methods disclosed herein) may be illustrated with reference to a specific embodiment of the microelectronic structure 100 disclosed herein, the method of FIG. 2 (and other methods disclosed herein) may be used to form any suitable microelectronic structure 100. Although the operations are shown each once and in a particular order in FIG. 2 (and other figures describing the methods disclosed herein), the operations may be reordered and / or repeated as appropriate (e.g., different operations performed in parallel when simultaneously fabricating multiple microelectronic structures 100).

[0045] 2A is a cross-sectional side view of an assembly including dielectric material 102, mask material 104, mask material 106, and mask material 108. In some embodiments, mask material 104 may include titanium nitride. In some embodiments, mask material 106 may include silicon nitride, silicon oxide, or a silicon anti-reflective coating. In some embodiments, mask material 108 may be a carbon-based hard mask or may include amorphous silicon. The specific number and arrangement of mask materials shown in the assembly of FIG. 2A (and other of the accompanying figures) are merely exemplary; more or fewer mask materials may be arranged in any desired manner in accordance with the techniques disclosed herein.

[0046] FIG. 2B is a cross-sectional side view of the assembly of FIG. 2A after forming an initial brush 110 on the mask material 108. The initial brush 110 may comprise a material that serves as a template for DSA of a block copolymer (BCP), as described below, and in some embodiments, may comprise one or more of the components of the BCP. For ease of explanation, the DSA-based techniques disclosed herein may refer to a BCP (e.g., BCP 114, described below) having two components, namely, a first component 116 and a second component 118; however, this is merely exemplary, and BCPs having more than two components may be utilized in any of the techniques disclosed herein. One example of a BCP that may function as the BCP 114 in the operations disclosed herein is polystyrene-co-poly(methyl methacrylate) (PS-PMMA). When the BCP 114 is PS-PMMA, the first component 116 may be polystyrene (PS) and the second component 118 may be polymethyl methacrylate (PMMA). As mentioned above, the DSA-based techniques disclosed herein may utilize brush 110 including one or more of first component 116 and second component 118 of BCP 114, but this is also merely exemplary and any suitable material or materials (e.g., materials that are not components of the BCP that undergo DSA on brush 110) may be included in brush 110. FIG. 2B (and other accompanying figures) may show brush 110 including first component 116. Although brush 110 is shown as including first component 116, brush 110 may include other materials, as appropriate. (For example, brush 110 may include second component 118 instead of or in addition to first component 116, or brush 110 may include one or more materials different from first component 116 and second component 118.) As used herein, "brush" may refer to any material that promotes self-assembly of DSA materials on itself, and may include large polymers, small polymers, self-assembled monolayers (SAMs), and other suitable materials.

[0047] FIG. 2C is a cross-sectional side view of the initial brush 110 of the assembly of FIG. 2B after patterning the brush 110 to form openings 178 in the assembly. The locations of the openings 178 may correspond to desired locations of low-LER lines 140 in the microelectronic structure 100, although the roughness of the edges 130 of the openings 178 in the assembly of FIG. 2C need not be "low," as described below. In some embodiments, the brush 110 itself may be photolithographically patterned. (For example, the brush 110 may be selectively treated to change the properties of the brush 110 according to a desired pattern, and then portions of the brush 110 may be removed by appropriate etching or rinsing to achieve the desired pattern.) In some such embodiments, the brush 110 may include components capable of undergoing chain scission reactions upon photon or electron exposure (e.g., PMMA resist). In other such embodiments, the brush 110 may include surface-anchored groups that can be cleaved by photon or electron exposure or subsequent reaction with a photoacid or photobase. In other such embodiments, the brush 110 may undergo a polarity change upon photon or electron exposure, which may produce either a two-tone or three-tone brush contrast, depending on the edge broadening effect. In other embodiments, the brush 110 may be patterned by applying a photoresist material (not shown), patterning the photoresist material, transferring the pattern of the photoresist material to the brush 110, and then removing the photoresist material. FIG. 2D is a top view of the assembly of FIG. 2C , showing the edges 130 of the openings 178 in the brush 110. The view of FIG. 2C is taken through cross-section CC of FIG. 2D . As mentioned above, the openings 178 may have very rough edges 130, and if the pattern of the openings 178 were transferred to the dielectric material 102 and the transferred openings were filled with the line material 120, the resulting line would be similarly rough and therefore a high LER line (e.g., the high LER line 170 described below).

[0048] 2C and 2D after depositing BCP 114 thereon. As noted above, brush 110 and BCP 114 may be selected to achieve desired DSA behavior, as described below with reference to FIG. 2F. In the embodiment of FIG. 2, BCP 114 may include first component 116 and second component 118 (not shown in FIG. 2E), as noted above.

[0049] 2F is a cross-sectional side view of the assembly of FIG. 2E after processing to cause the BCP 114 to self-assemble according to the template provided by the brush 110. In the specific embodiment of FIG. 2F, the self-assembly of the BCP 114 involves the BCP 114 self-segregating its first and second components 116, 118 into bands to form alternating vertically oriented regions of the first and second components 116, 118 in the patterned region 142. The dimensions and spacing of the openings 178 in the brush 110 may be selected to correspond to the size and spacing of the bands of the second component 118 of the BCP 114, as shown, and the dimensions and spacing of the first component 116 in the brush 110 may be selected to correspond to the size and spacing of the bands of the first component 116 of the BCP 114, such that the brush 110 provides a “template” for the self-assembly of the BCP 114 and aligns the self-assembled BCP 114 in a desired manner with respect to the underlying brush 110. The BCP 114 may be able to "stretch" or "contract" around the nominal "natural" spacing of the self-assembled bands of the first component 116 / second component 118, allowing for a range of dimensions for the self-assembled bands of the first component 116 / second component 118, along with some tolerance for deviations in the patterning of the brush 110 from its intended pattern. The specific band-like self-assembly shown in FIG. 2F is one example of a pattern in which the BCP 114 may self-assemble; some BCPs 114 may self-assemble into other patterns, and various BCPs 114 may self-assemble into multiple different patterns under different conditions, as described below. Outside the patterned regions 142, the brush 110 may not provide a surface onto which the BCP 114 can readily self-assemble into alternating vertically oriented regions of the first component 116 and the second component 118; instead, the BCP 114 in the non-patterned regions 144 may self-assemble into a disordered layer 132 of the first component 116 and the second component 118, which may have a structure similar to that shown in FIG. 1C.

[0050] FIG. 2G is a cross-sectional side view of the assembly of FIG. 2F after removing the second component 118. The first component 116 may remain in place, and therefore, the patterned region 142 may include a series of parallel openings 180. In some embodiments, the assembly of FIG. 2F may be treated with an ion implantation technique to harden the first component 116 (e.g., PS) before removing the second component 118 (e.g., PMMA). In some embodiments, a suitable selective etching technique may be used to remove the second component 118 while leaving the first component 116 in place. Removing the second component 118 from the disordered layer 132 in the unpatterned region 144 may result in a partially etched disordered layer 134, retaining a structure similar to that shown in FIG. 1C. FIG. 2H is a top view of the assembly of FIG. 2G, showing the edges 130 of the openings 180 in the first component 116. The view of FIG. 2G is taken through cross-section GG of FIG. 2H. These openings 180 may have low-LER edges 130. If the pattern of openings 180 were transferred into dielectric material 102 (as described below) and the transferred openings were filled with line material 120 (as described below), the resulting lines would similarly be rough, and therefore low-LER lines 140. The process of performing a DSA-based technique on the “rough” openings 178 of the assembly of FIG. 2D may result in the “smooth” openings 180 of the assembly of FIG. 2H; therefore, the technique of FIG. 2 (and other DSA-based techniques disclosed herein) may be said to “tune” the “rough” openings 178. The ability of the DSA-based techniques disclosed herein to tune coarse lithographic features may enable the use of low-dose EUV lithography for manufacturing. The additional roughness associated with low-dose EUV lithography (versus higher-dose EUV lithography) may be remedied by DSA operations, and the benefits of low-dose EUV lithography (e.g., the ability to use thicker resist materials) may be realized without the roughness penalty traditionally associated with it.

[0051] 2G and 2H after transferring the pattern of openings 180 into the underlying mask material 108. Any suitable etching technique may be used. Transferring the pattern of openings 180 into the mask material 108 may also result in transferring the disordered layer pattern of the partially etched disordered layer 134 into the underlying mask material 108 in the unpatterned regions 144, resulting in a disordered layer-patterned mask material 136.

[0052] 2J is a cross-sectional side view of the assembly of FIG. 2I after removal of first component 116. Any suitable selective etching technique may be used. (For example, if first component 116 comprises PS, an ashing technique may be used.)

[0053] 2K is a cross-sectional side view of the assembly after performing a lateral etch on the mask material 108 of FIG. 2J to reduce the lateral size of the portions of the mask material 108, thereby increasing the distance between adjacent portions of the mask material 108. This etch may be controlled to achieve a desired distance between adjacent portions of the mask material. In some embodiments, the width 111 of the portions of the mask material 108 may be between 10 and 12 nanometers.

[0054] 2L is a cross-sectional side view of the assembly after transferring the pattern of the mask material 108 / disordered-layer-patterned mask material 136 to the dielectric material 102 of the assembly of FIG. 2K (through the intermediate mask materials 104 and 106, which are subsequently removed), and then providing line material 120 in the openings in the dielectric material 102 to form low LER lines 140. The pattern of the disordered-layer-patterned mask material 136 may be transferred to the dielectric material 102 to form a disordered layered structure 138. The assembly of FIG. 2L may take the form of the microelectronic structure 100 of FIG. 1.

[0055] As discussed above, in some embodiments, the brush 110 may include multiple different materials arranged in a desired pattern. For example, FIG. 3 shows the assembly of FIG. 2C after depositing the second component 118 into the openings 178 in the brush 110. The operations described above with reference to FIGS. 2E-2L may be performed on the assembly of FIG. 3 to form the microelectronic structure 100 of FIG. 1. Utilizing multiple different materials in the brush 110 may provide a stronger "template" for the BCP 114, thereby improving the resulting self-assembly and achieving a lower LER line 140.

[0056] In some embodiments, spacer-based techniques may be used to further reduce the pitch 172 of the low LER lines 140 in the patterned region 142 . For example, Figures 4A-4B show various views of another microelectronic structure 100 including low LER lines 140 according to various embodiments. Figure 4A is a side cross-sectional view of the microelectronic structure 100 through section AA in Figure 4B, and Figure 4B is a top view of the microelectronic structure 100. The disordered layered structure 138 of the microelectronic structure 100 of Figure 4 may take the form shown in Figure 1C. The embodiment of Figure 4 shares many elements with the embodiment of Figure 1. For ease of explanation, the description of these elements will not be repeated, and these elements may take the form of any of the embodiments of these elements disclosed herein. Relative to the embodiment of Figure 1, the low LER lines 140 of the embodiment of Figure 4 may have a smaller pitch 172, a smaller line width 174, and / or a smaller spacing 176.

[0057] 5A-5D illustrate stages in an exemplary process for fabricating the microelectronic structure 100 of FIG. 4 according to various embodiments. FIG. 5A is a cross-sectional side view of the assembly of FIG. 2K after forming spacers 124 on the sides of the patterned mask material 108 of the assembly. The spacers 124 may comprise a dielectric material and may be fabricated using any suitable spacer technique (e.g., conformal deposition of the dielectric material, such as by atomic layer deposition (ALD), followed by an etch in a "down" direction to remove the dielectric material on the horizontal surfaces and leave the dielectric material in place on the sides).

[0058] 5B is a cross-sectional side view of the assembly of FIG. 5A after depositing and patterning a mask material 182 on the assembly to cover the mask material 108 adjacent the disordered layer-patterned mask material 136, and then removing the remaining mask material 108. Any suitable mask material 182, deposition technique, patterning technique, and etching technique may be used.

[0059] FIG. 5C is a cross-sectional side view of the assembly after transferring the pattern of the mask material 108 / disordered-layer-patterned mask material 136 to the dielectric material 102 of the assembly of FIG. 5B (through the intermediate mask materials 104 and 106, which are subsequently removed) and then providing line material 120 in the openings in the dielectric material 102 to form low LER lines 140. The pattern of the disordered-layer-patterned mask material 136 may be transferred to the dielectric material 102 to form a disordered layered structure 138. FIG. 5D is a top view of the assembly of FIG. 5C, showing the edge 130 of the low LER lines 140. The view of FIG. 5C is taken through cross-section CC of FIG. 5D. The assembly of FIGS. 5C and 5D may take the form of the microelectronic structure 100 of FIG. 4.

[0060] Spacer-based techniques may be used in other ways to reduce the spacing 176 between low-LER lines 140 in a microelectronic structure 100. For example, FIGS. 6A-6B show various views of another microelectronic structure 100 including low-LER lines 140 according to various embodiments. FIG. 6A is a side cross-sectional view of the microelectronic structure 100 through section AA in FIG. 6B, and FIG. 6B is a top view of the microelectronic structure 100. The disordered layered structure 138 of the microelectronic structure 100 of FIG. 6 may take the form shown in FIG. 1C. The embodiment of FIG. 6 shares many elements with the above-described embodiments. For ease of explanation, the description of these elements will not be repeated, and these elements may take the form of any of the embodiments of these elements disclosed herein. Relative to the embodiment of FIG. 1, the low-LER lines 140 of the embodiment of FIG. 6 may have a smaller spacing 176.

[0061] 7A-7H illustrate stages in an exemplary process for fabricating the microelectronic structure 100 of FIG. 6 according to various embodiments. FIG. 7A is a cross-sectional side view of an assembly substantially similar to that of FIG. 2G, except with an additional opening 180 for illustrative purposes between the outermost portion of the first component 116 and the disordered layer 132, after applying and patterning a mask material 128 in the unpatterned region 144 of the assembly. Any suitable mask material 128 may be used.

[0062] Figure 7B is a cross-sectional side view of the assembly of Figure 7A after forming spacers 124 on the sides of first component 116. Spacers 124 may take any of the forms disclosed herein.

[0063] 7C is a cross-sectional side view of the assembly of FIG. 7B after depositing a mask material 126 over the assembly. In some embodiments, the mask material 126 may include amorphous silicon. The mask material 126 may fill the openings in the disordered layer 132, forming a layered material 184.

[0064] Figure 7D is a cross-sectional side view of the assembly after the assembly of Figure 7C, with removal of the overcoat of mask material 126. In some embodiments, chemical mechanical polishing (CMP) techniques may be used.

[0065] 7E is a cross-sectional side view of the assembly of FIG. 7D after removal of first component 116 and spacer 124. Any suitable selective etching technique may be used. (For example, if first component 116 includes PS, an ashing technique may be used.) Removal of first component 116 from layered material 184 results in a partially etched layered material 186, which may have a structure similar to that of FIG. 1C.

[0066] 7F is a cross-sectional side view of the assembly of FIG. 7E after transferring the pattern of the partially etched layered material 186 / mask material 126 to the mask material 108. Transferring the pattern may include transferring the disordered layered pattern of the partially etched layered material 186 to the underlying mask material 108 in the unpatterned regions 144, resulting in a disordered layered patterned mask material 136.

[0067] FIG. 7G is a cross-sectional side view of the assembly of FIG. 7F after transferring the pattern of the mask material 108 / disordered-layer-patterned mask material 136 to the dielectric material 102 (through the intermediate mask materials 104 and 106, which are subsequently removed) and then providing line material 120 in the openings in the dielectric material 102 to form low LER lines 140. The pattern of the disordered-layer-patterned mask material 136 may be transferred to the dielectric material 102 to form a disordered layered structure 138. FIG. 7H is a top view of the assembly of FIG. 7G, showing the edge 130 of the low LER line 140. The view of FIG. 7G is taken through cross-section GG of FIG. 7H. The assembly of FIGS. 7G and 7H may take the form of the microelectronic structure 100 of FIG. 6.

[0068] In some embodiments, the microelectronic structure 100 may include low LER lines 140 and high LER lines 170. For example, FIGS. 8A-8B are various views of another microelectronic structure 100 including a low LER line 140 according to various embodiments. FIG. 8A is a side cross-sectional view of the microelectronic structure 100 through section AA of FIG. 8B, and FIG. 8B is a top view of the microelectronic structure 100. The disordered layered structure 138 of the microelectronic structure 100 of FIG. 8 may take the form shown in FIG. 1C. The embodiment of FIG. 8 shares many elements with the above-described embodiments. For ease of explanation, the description of these elements will not be repeated, and these elements may take the form of any of the embodiments of these elements disclosed herein. In comparison to the embodiment of FIG. 1, the microelectronic structure 100 of FIG. 8 includes a first patterning region 142-1 including a low LER line 140 and a second patterning region 142-2 including one or more high LER lines 170 (as shown).

[0069] As described above, in some embodiments, lines or other features patterned by DSA-based techniques may be distinguished from lines or other features patterned by lithography techniques (e.g., EUV lithography techniques) by their LER. In particular, lines or other features patterned by DSA-based techniques disclosed herein may have a lower LER than lines or other features patterned by lithography techniques. Other markers may distinguish lines or other features patterned by DSA-based techniques disclosed herein from lines or other features patterned by lithography techniques. For example, in some embodiments, lines or other features patterned by conventional lithography techniques (e.g., EUV lithography techniques) may have a line width roughness (LWR) equal to the LER of those lines or other features multiplied by the square root of two. This "lithographic characteristic" may not apply to lines or other features patterned by the DSA-based techniques disclosed herein, and therefore the presence of this lithographic characteristic may indicate whether a feature was patterned using conventional lithographic techniques or the DSA-based techniques disclosed herein.

[0070] 9A-9M illustrate stages in an exemplary process for fabricating the microelectronic structure 100 of FIG. 8 according to various embodiments. FIG. 9A is a cross-sectional side view of an assembly similar to that of FIG. 2C , including a patterned initial brush 110. The assembly of FIG. 9A may be formed according to any of the fabrication techniques described herein with reference to FIG. 2C . As with the assembly of FIG. 2C , the opening 178 may be patterned in the first patterning region 142-1 of the first component 116 using lithographic techniques and may therefore have very rough edges.

[0071] Figure 9B is a cross-sectional side view of the assembly of Figure 9A after depositing BCP 114 thereon. The brush 110 and BCP 114 may be selected to achieve desired behavior when BCP 114 self-assembles on brush 110. In the embodiment of Figure 9, BCP 114 may include a first component 116 and a second component 118.

[0072] 9B after processing the assembly to allow the BCP 114 to self-assemble according to the template provided by the brush 110. As described above with reference to FIG. 2, the resulting assembly may include alternating vertically oriented regions of the first component 116 and the second component 118 in the first patterned region 142-1. Outside of the first patterned region 142-1, the brush 110 may not provide a surface onto which the BCP 114 can readily self-assemble into the alternating vertically oriented regions of the first component 116 and the second component 118; instead, the BCP 114 in the non-patterned region 144 and the second patterned region 142-2 may self-assemble into a disordered layer 132 of the first component 116 and the second component 118, which may have a structure similar to that shown in FIG. 1C.

[0073] 9D is a cross-sectional side view of the assembly of FIG. 9C after removing the second component 118. The first component 116 may remain in place, and therefore the first patterning region 142-1 may include a series of parallel openings 180. In some embodiments, the assembly of FIG. 9C may be treated with an ion implantation technique to harden the first component 116 (e.g., PS) before removing the second component 118 (e.g., PMMA). In some embodiments, a suitable selective etching technique may be used to remove the second component 118. Removing the second component 118 from the disordered layer 132 may result in a partially etched disordered layer 134, retaining a structure similar to that shown in FIG. 1C. As described above with reference to Figures 2G and 2H, the process of performing a DSA operation on the "coarse" opening 178 of the assembly of Figure 9A may result in the "smooth" opening 180 of the assembly of Figure 9D, and therefore the technique of Figure 9 (and other DSA-based techniques disclosed herein) may be said to "tune" the "coarse" opening 178.

[0074] 9E is a cross-sectional side view of the assembly of FIG. 9D after depositing and patterning a mask material 148 on the assembly to cover the partially etched disordered layer 134 in the second patterning region 142-2. Any suitable mask material 148 and any suitable patterning technique may be used.

[0075] 9F is a cross-sectional side view of the assembly of FIG. 9E after transferring the pattern of openings 180 of the assembly to the underlying mask material 108. Any suitable etching technique may be used. The result of transferring the pattern of openings 180 to the mask material 108 may also be to transfer the disordered layer pattern of the exposed and partially etched disordered layer 134 to the underlying mask material 108 in the unpatterned regions 144, resulting in a disordered layer-patterned mask material 136.

[0076] 9G is a cross-sectional side view of the assembly of FIG. 9F after removing mask material 148 and then first component 116. Any suitable selective etching technique may be used. (For example, if first component 116 comprises PS, an ashing technique may be used.)

[0077] Figure 9H is a cross-sectional side view of the assembly of Figure 9G after depositing a mask material 128 over the assembly. Any suitable mask material 128 may be used.

[0078] Figure 91 is a cross-sectional side view of the assembly after patterning mask material 128 in second patterning region 142-2 to form openings 188 corresponding to high LER lines 170 in Figure 8. In some embodiments, openings 188 may be formed using lithographic techniques and therefore may have rough edges.

[0079] Figure 9J is a cross-sectional side view of the assembly of Figure 9I after the pattern of mask material 128 has been transferred to mask material 108 and mask material 106. Any suitable etching technique may be used.

[0080] Figure 9K is a cross-sectional side view of the assembly of Figure 9J after removal of mask material 128. Any suitable etching technique may be used.

[0081] FIG. 9L is a cross-sectional side view of the assembly after transferring the pattern of the mask material 108 / disordered-layer-patterned mask material 136 to the dielectric material 102 (through the intermediate mask materials 104 and 106, which are subsequently removed) and then providing line material 120 in the openings in the dielectric material 102 to form low LER lines 140 and high LER lines 170. The pattern of the disordered-layer-patterned mask material 136 may be transferred to the dielectric material 102 to form the disordered layered structure 138. FIG. 9M is a top view of the assembly of FIG. 9L, showing the edges 130 of the low LER lines 140 and high LER lines 170. The view of FIG. 9L is taken through cross-section LL of FIG. 9M. The assembly of FIGS. 9L and 9M may take the form of the microelectronic structure 100 of FIG. 8.

[0082] In some embodiments, the spacing 176 between adjacent low LER lines 140 may be increased by selective depopulation using DSA-based techniques. For example, FIGS. 10A-10B show various views of another microelectronic structure 100 including low LER lines 140 according to various embodiments. FIG. 10A is a side cross-sectional view of the microelectronic structure 100 through section AA in FIG. 10B, and FIG. 10B is a top view of the microelectronic structure 100. The disordered layered structure 138 of the microelectronic structure 100 of FIG. 10 may take the form shown in FIG. 1C. The embodiment of FIG. 10 shares many elements with the above-described embodiments. For ease of explanation, the description of these elements will not be repeated, and these elements may take the form of any of the embodiments of these elements disclosed herein. Relative to the embodiment of FIG. 1, the microelectronic structure 100 of FIG. 10 includes a smaller inter-line space 150-1 and a larger inter-line space 150-2 between adjacent low LER lines 140. The particular arrangement of smaller inter-line spaces 150-1 and larger inter-line spaces 150-2 is merely exemplary, and any desired arrangement may be included in microelectronic structure 100 in accordance with the techniques disclosed herein.

[0083] 11A-11H illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 10 according to various embodiments. FIG. 11A is a cross-sectional side view of an assembly similar to that of FIGS. 2C and 9A, including a patterned initial brush 110. The assembly of FIG. 11A may be formed according to any of the fabrication techniques described herein with reference to FIG. 2C. As with the assembly of FIG. 2C, the opening 178 may be patterned in the first component 116 using lithographic techniques and may therefore have very rough edges.

[0084] 11B is a cross-sectional side view of the assembly of FIG. 11A after depositing a BCP (e.g., the BCP 114 described above, not shown) onto the assembly and then processing the resulting assembly to cause the BCP to self-assemble according to a template provided by the brush 110. The resulting assembly includes alternating vertically oriented regions of the first component 116 and the second component 118 in the patterned region 142. Outside the patterned region 142, the brush 110 may not provide a surface onto which the BCP can readily self-assemble into the alternating vertically oriented regions of the first component 116 and the second component 118; instead, the BCP 114 in the non-patterned region 144 may self-assemble into a disordered layer 132 of the first component 116 and the second component 118, which may have a structure similar to that shown in FIG. 1C.

[0085] 11C is a cross-sectional side view of the assembly of FIG. 11B after removing the second component 118. The first component 116 may remain in place, and thus the patterned region 142 may include a series of parallel openings 180. In some embodiments, the assembly of FIG. 11B may be treated with an ion implantation technique to harden the first component 116 (e.g., PS) before removing the second component 118 (e.g., PMMA). In some embodiments, a suitable selective etching technique may be used to remove the second component 118. Removing the second component 118 from the disordered layer 132 may result in a partially etched disordered layer 134, retaining a structure similar to that shown in FIG. 1C. As described above with reference to Figures 2G and 2H, the process of performing a DSA operation on the "coarse" opening 178 of the assembly of Figure 11A may result in the "smooth" opening 180 of the assembly of Figure 11C, and therefore the technique of Figure 11 (and other DSA-based techniques disclosed herein) may be said to "tune" the "coarse" opening 178.

[0086] Figure 11D is a cross-sectional side view of the assembly of Figure 11C after a mask material 128 has been deposited over the assembly. Any suitable mask material 128 may be used.

[0087] 11E is a cross-sectional side view of the assembly of FIG. 11D after patterning mask material 128 to cover openings 180 in areas corresponding to larger inter-line spaces 150-2 between adjacent low-LER lines 140. Any suitable patterning technique may be used.

[0088] 11F is a cross-sectional side view of the assembly of FIG. 11E after transferring the pattern of exposed openings 180 of the assembly to the underlying mask material 108. Any suitable etching technique may be used. The result of transferring the pattern of openings 180 to the mask material 108 may also be to transfer the disordered layer pattern of the exposed and partially etched disordered layer 134 to the underlying mask material 108 in the unpatterned regions 144, resulting in a disordered layer-patterned mask material 136.

[0089] FIG. 11G is a cross-sectional side view of the assembly of FIG. 11F after removing the mask material 128, transferring the pattern of the mask material 108 / disordered-layer-patterned mask material 136 to the dielectric material 102 (through the subsequently removed intermediate mask materials 104 and 106), and then providing line material 120 in the openings in the dielectric material 102 to form low LER lines 140. The pattern of the disordered-layer-patterned mask material 136 may be transferred to the dielectric material 102 to form the disordered layered structure 138. FIG. 11H is a top view of the assembly of FIG. 11G, showing the edges 130 of the low LER lines 140, the smaller inter-line spacing 150-1, and the larger inter-line spacing 150-2. The view of FIG. 11G is taken through cross-section G-G of FIG. 11H. The assembly of FIGS. 11G and 11H may take the form of the microelectronic structure 100 of FIG. 10.

[0090] 1-24 illustrate exemplary microelectronic structures 100 and examples of methods for fabricating such microelectronic structures 100. Any of the features described herein with reference to any of FIGS. 1-24 may be combined with any other feature to form the microelectronic structure 100. For example, FIGS. 3 and 4 illustrate embodiments in which spacer-based techniques are used to reduce the pitch of low LER lines 140, FIGS. 8 and 9 illustrate embodiments including both low LER lines 140 and high LER lines 170, and FIGS. 10 and 11 illustrate embodiments in which the spacing between various pairs of adjacent low LER lines 140 is increased by selective depopulation. These features of FIGS. 3, 4, 8, 9, 10, and 11 may be combined such that the microelectronic structure 100 includes reduced-pitch low LER lines 140, both low LER lines 140 and high LER lines 170, and increased spacing between various pairs of low LER lines 140. Such an embodiment of the microelectronic structure 100 is shown in Figure 12, and a method for manufacturing the microelectronic structure 100 of Figure 12 is shown in Figure 13. However, this particular combination is merely an example, and any combination may be used.

[0091] As mentioned above, FIGS. 12A-12B are various views of another microelectronic structure 100 including low LER lines 140 and high LER lines 170 according to various embodiments. FIG. 12A is a side cross-sectional view of the microelectronic structure 100 through section AA of FIG. 12B, and FIG. 12B is a top view of the microelectronic structure 100. The disordered layered structure 138 of the microelectronic structure 100 of FIG. 12 may take the form shown in FIG. 1C. The embodiment of FIG. 12 shares many elements with the above-described embodiments. For ease of explanation, the description of these elements will not be repeated, and these elements may take the form of any of the embodiments of these elements disclosed herein. Relative to the embodiment of FIG. 1, the microelectronic structure 100 includes reduced pitch low LER lines 140, both low LER lines 140 and high LER lines 170, and increased spacing 176 between various pairs of low LER lines 140.

[0092] 13A-13P illustrate stages in an exemplary process for fabricating the microelectronic structure of FIG. 12 according to various embodiments. FIG. 13A is a cross-sectional side view of an assembly similar to those of FIGS. 2C, 9A, and 11A, including a patterned initial brush 110. The assembly of FIG. 13A may be formed according to any of the fabrication techniques described herein with reference to FIG. 2C. As with the assembly of FIG. 2C, the opening 178 may be patterned in the first component 116 using lithographic techniques and may therefore have very rough edges.

[0093] 13B is a cross-sectional side view of the assembly of FIG. 13A after depositing a BCP (e.g., the BCP 114 described above, not shown) onto the assembly and then processing the resulting assembly to cause the BCP to self-assemble according to a template provided by the brush 110. The resulting assembly includes alternating vertically oriented regions of the first component 116 and the second component 118 in the patterned region 142. Outside the patterned region 142, the brush 110 may not provide a surface onto which the BCP can readily self-assemble into the alternating vertically oriented regions of the first component 116 and the second component 118; instead, the BCP 114 in the non-patterned region 144 may self-assemble into a disordered layer 132 of the first component 116 and the second component 118, which may have a structure similar to that shown in FIG. 1C.

[0094] 13C is a cross-sectional side view of the assembly of FIG. 13B after removing the second component 118. The first component 116 may remain in place, and thus the patterned region 142 may include a series of parallel openings 180. In some embodiments, the assembly of FIG. 13B may be treated with an ion implantation technique to harden the first component 116 (e.g., PS) before removing the second component 118 (e.g., PMMA). In some embodiments, a suitable selective etching technique may be used to remove the second component 118. Removing the second component 118 from the disordered layer 132 may result in a partially etched disordered layer 134, retaining a structure similar to that of FIG. 1C. As described above with reference to Figures 2G and 2H, the process of performing a DSA operation on the "coarse" opening 178 of the assembly of Figure 13A may result in the "smooth" opening 180 of the assembly of Figure 13C, and therefore the technique of Figure 13 (and other DSA-based techniques disclosed herein) may be said to "tune" the "coarse" opening 178.

[0095] 13D is a cross-sectional side view of the assembly of FIG. 13C after transferring the pattern of openings 180 of the assembly to the underlying mask material 108. Any suitable etching technique may be used. Transferring the pattern of openings 180 to the mask material 108 may also result in transferring the disordered layer pattern of the partially etched disordered layer 134 to the underlying mask material 108 in the unpatterned regions 144, resulting in a disordered layer-patterned mask material 136.

[0096] Figure 13E is a cross-sectional side view of the assembly of Figure 13D after removal of the first component 116 (and therefore the partially etched disordered layer 134). Any suitable etching technique may be used (e.g., an ashing technique if the first component 116 comprises PS).

[0097] 13F is a cross-sectional side view of the assembly of FIG. 13E after depositing mask material 128 over the assembly and patterning it to cover mask material 108 (and thus, along with disordered, layer-patterned mask material 136) in unpatterned areas 144 and first patterned areas 142-1 while exposing mask material 108 in second patterned areas 142-2. Any suitable mask material 128 may be used.

[0098] Figure 13G is a cross-sectional side view of the assembly of Figure 13F after removal of exposed mask material 108 (in second patterning region 142-2). Any suitable etching technique may be used.

[0099] 13H is a cross-sectional side view of the assembly of FIG. 13G after removing mask material 128 from the assembly and forming spacers 124 on the sides of the remaining patterned mask material 108. Spacers 124 may comprise a dielectric material and may be fabricated using any known spacer technique (e.g., conformal deposition of a dielectric material, followed by an etch in the "down" direction to remove the dielectric material on the horizontal surfaces and leave the dielectric material in place on the sides).

[0100] 13I is a cross-sectional side view of the assembly of FIG. 13H after depositing and patterning a mask material 148 over the assembly to selectively cover desired portions of the mask material 108, spaces between the mask material 108, and portions of the mask material 106 in the second patterning region 142-2, as shown. Any suitable mask material 148 and selective etching technique may be used. The openings 188 in the mask material 128 in the second patterning region 142-2 correspond to the high LER lines 170 in FIG. 12. In some embodiments, the openings 188 may be formed using lithographic techniques and may therefore have rough edges.

[0101] 13J is a cross-sectional side view of the assembly of FIG. 13I after the pattern of the mask material 108 / spacer material 124 / mask material 148 of the assembly has been transferred to the underlying mask material 106. Any suitable selective etching technique may be used. The pattern of the disordered layer-patterned mask material 136 may be transferred to the mask material 106 in the unpatterned regions 144, resulting in the disordered layer-patterned mask material 146.

[0102] Figure 13K is a cross-sectional side view of the assembly of Figure 13J after mask material 182 has been deposited on it and then recessed to expose the top surfaces of mask material 108 (and thus mask material 136 patterned in a disordered layer) and spacers 124. Any suitable mask material 182 and recess-forming technique may be used.

[0103] Figure 13L is a cross-sectional side view of the assembly of Figure 13K after removing the exposed mask material 108 (and thus the disordered layer-patterned mask material 136) from the assembly and selectively exposing the underlying mask material 106. Any suitable selective etching technique may be used.

[0104] Figure 13M is a cross-sectional side view of the assembly of Figure 13L after removal of exposed mask material 106. Any suitable selective etching technique may be used.

[0105] Figure 13N is a cross-sectional side view of the assembly of Figure 13M after removing spacers 124 and mask material 182. Any suitable selective etching technique may be used.

[0106] FIG. 13O is a cross-sectional side view of the assembly of FIG. 13N after transferring the pattern of the mask material 106 / disordered-layer-patterned mask material 146 to the dielectric material 102 (through the intermediate mask material 104, which is subsequently removed) and then providing line material 120 in the openings in the dielectric material 102 to form the low LER lines 140 and the high LER lines 170. The pattern of the disordered-layer-patterned mask material 146 may be transferred to the dielectric material 102 to form the disordered layered structure 138. FIG. 13P is a top view of the assembly of FIG. 13O, showing the edges 130 of the low LER lines 140 and the high LER lines 170 with selectively variable line spacing. The view of FIG. 13O is taken through cross-section OO of FIG. 13P. The assembly of FIGS. 13O and 13P may take the form of the microelectronic structure 100 of FIG. 12.

[0107] As discussed above, BCPs may be capable of self-assembling into a number of different configurations. For example, BCPs may be capable of forming both vertically repeating and horizontally repeating structures as shown in various of the figures above. Whether such BCPs form vertically repeating, horizontally repeating, or disordered structures may vary depending on the pattern of the underlying brushes 110, the composition of the BCP, and the conditions for DSA of the BCP; these variables may be adjusted to achieve desired results. The opportunity to form horizontally repeating structures may be utilized to fabricate low LER lines 140 with different linewidths 174. For example, FIGS. 14A-14B show various views of another microelectronic structure 100 including low LER lines 140 with different linewidths 174, according to various embodiments. FIG. 14A is a side cross-sectional view of the microelectronic structure 100 through section AA of FIG. 14B, and FIG. 14B is a top view of the microelectronic structure 100. The disordered layered structure 138 of the microelectronic structure 100 of Figure 14 may take the form shown in Figure 1C. The embodiment of Figure 14 shares many elements with the above-described embodiments. For ease of explanation, the description of these elements will not be repeated, and these elements may take the form of any of the embodiments of these elements disclosed herein. In contrast to the embodiment of Figure 1, the microelectronic structure 100 of Figure 14 includes low LER lines 140 having different linewidths 174 (i.e., has an intermediate low LER line 140 having a linewidth 174 that is larger than an adjacent low LER line 140).

[0108] 15A-15G illustrate stages in an exemplary process for fabricating the microelectronic structure 100 of FIG. 14 according to various embodiments. FIG. 15A is a cross-sectional side view of an assembly similar to that of FIG. 2C including a patterned initial brush 110, which may include a second component 118 instead of the first component 116. The assembly of FIG. 15A may be formed according to any of the fabrication techniques described herein with reference to FIG. 2C. As with the assembly of FIG. 2C, the opening 178 in the brush 110 may be patterned using lithographic techniques and may therefore have very rough edges. Note that the center of the second component 118 of the brush 110 is wider than other portions of the second component 118 in the patterned region 142.

[0109] Figure 15B is a cross-sectional side view of the assembly after the opening 178 of the brush 110 of Figure 15A has been "filled" with the first component 116 and the brush 110 has been "finished" as described above with reference to Figure 3. In other embodiments, this operation is not performed before proceeding to subsequent operations.

[0110] 15C is a cross-sectional side view of the assembly of FIG. 15B after depositing a BCP 114 thereon. As discussed above, the brush 110 and BCP 114 may be selected to achieve a desired DSA behavior. In the embodiment of FIG. 15, the BCP 114 may include a first component 116 and a second component 118.

[0111] 15D is a cross-sectional side view of the assembly of FIG. 15C after processing to allow the BCP 114 to self-assemble according to the template provided by the brush 110. The resulting assembly includes regions where the first component 116 and the second component 118 are alternately oriented vertically, along with regions where the first component 116 (formed above the "wider" portion of the second component 118 in the patterned region 142) is oriented horizontally. Outside the patterned regions 142, the brush 110 may not provide a surface onto which the BCP 114 readily self-assembles into alternating vertically oriented regions of the first component 116 and the second component 118 (or into alternating horizontally oriented regions of the first component 116 and the second component 118), so instead, the BCP 114 in the non-patterned regions 144 may self-assemble into a disordered layer 132 of the first component 116 and the second component 118, which may have a structure similar to that shown in FIG. 1C.

[0112] FIG. 15E is a cross-sectional side view of the assembly of FIG. 15D after planarization and removal of first component 116, second component 118, and the top portions of disordered layer 132 (eg, using CMP techniques).

[0113] FIG. 15F is a cross-sectional side view of the assembly of FIG. 15E after removing the second component 118 (e.g., using a suitable selective etching technique), forming a "smooth" opening in the first component 116 rather than the rough opening 178, transferring the pattern of the first component 116 (through the subsequently removed intermediate mask materials 108, 106, and 104), and then providing line material 120 in the opening in the dielectric material 102 to form the low LER line 140. The pattern of the disordered layer 132 may be transferred to the dielectric material 102 to form the disordered layered structure 138. FIG. 15G is a top view of the assembly of FIG. 15F, showing the edge 130 of the low LER line 140. The view of FIG. 15F is taken through cross-section FF of FIG. 15G. The assembly of FIGS. 15F and 15G may take the form of the microelectronic structure 100 of FIG. 14.

[0114] The opportunity to form horizontally repeating structures may be utilized to fabricate low LER lines 140 with different spacings 176 (instead of, or in addition to, different line widths 174, as described above with reference to FIGS. 14 and 15 ). For example, FIGS. 16A-16B show various views of another microelectronic structure 100 including low LER lines 140 with different spacings 176 therebetween, according to various embodiments. FIG. 16A is a cross-sectional side view of the microelectronic structure 100 through section AA of FIG. 16B, and FIG. 16B is a top view of the microelectronic structure 100. The disordered layered structure 138 of the microelectronic structure 100 of FIG. 16 may take the form shown in FIG. 1C. The embodiment of FIG. 16 shares many elements with the above-described embodiments. For ease of explanation, the description of these elements will not be repeated, and these elements may take the form of any of the embodiments of these elements disclosed herein. 1, the microelectronic structure 100 of FIG. 16 includes low LER lines 140 having different spacings 176 (ie, intermediate spacings 176 that are larger than adjacent spacings 176).

[0115] 17A-17G illustrate stages in an exemplary process for fabricating the microelectronic structure 100 of FIG. 16 according to various embodiments. FIG. 17A is a cross-sectional side view of an assembly similar to that of FIG. 2C , including a patterned initial brush 110 of the first component 116. The assembly of FIG. 17A may be formed according to any of the fabrication techniques described herein with reference to FIG. 2C . As with the assembly of FIG. 2C , the opening 178 of the brush 110 may be patterned using lithographic techniques and may therefore have very rough edges. Note that the center of the first component 116 of the brush 110 is wider than other portions of the first component 116 in the patterned region 142.

[0116] Figure 17B is a cross-sectional side view of the assembly after the opening 178 of the brush 110 of Figure 17A has been "filled" with the second component 118 to "finish" the brush 110 as described above with reference to Figure 3. In other embodiments, this operation is not performed before proceeding to subsequent operations.

[0117] 17C is a cross-sectional side view of the assembly of FIG. 17B after depositing a BCP 114 thereon. As discussed above, the brush 110 and BCP 114 may be selected to achieve a desired DSA behavior. In the embodiment of FIG. 17, the BCP 114 may include a first component 116 and a second component 118.

[0118] 17D is a cross-sectional side view of the assembly of FIG. 17C after processing the assembly to cause the BCP 114 to self-assemble according to the template provided by the brush 110. The resulting assembly includes regions where the first component 116 and the second component 118 are alternately oriented vertically, along with regions where the second component 118 is oriented horizontally (formed above the "wider" portions of the first component 116 in the patterned region 142). Outside the patterned region 142, the brush 110 may not provide a surface onto which the BCP 114 readily self-assembles into the alternating vertically (or horizontally) oriented regions of the first component 116 and the second component 118; instead, the BCP 114 in the non-patterned region 144 may self-assemble into a disordered layer 132 of the first component 116 and the second component 118, which may have a structure similar to that of FIG. 1C.

[0119] FIG. 17E is a cross-sectional side view of the assembly of FIG. 17D after planarization to remove first component 116, second component 118, and the top portions of disordered layer 132 (eg, using CMP techniques).

[0120] FIG. 17F is a cross-sectional side view of the assembly of FIG. 17E after removing second component 118 (e.g., using a suitable selective etching technique), forming a "smooth" opening in first component 116 rather than rough opening 178, transferring the pattern of first component 116 (through intermediate mask materials 108, 106, and 104, which are subsequently removed), and then providing line material 120 in the opening in dielectric material 102 to form low LER line 140. The pattern of disordered layer 132 may be transferred to dielectric material 102 to form disordered layered structure 138. FIG. 17G is a top view of the assembly of FIG. 17F, showing edge 130 of low LER line 140. The view of FIG. 17F is taken through cross section FF of FIG. 17G. The assembly of FIGS. 17F and 17G may take the form of microelectronic structure 100 of FIG. 16.

[0121] In some embodiments, the BCP used in DSA-based techniques may be "stretchable" in that it can self-assemble into repeating patterns with variable sizes (e.g., approximately nominal size) depending on the dimensions and structure of the underlying brush. For example, FIG. 18 is a top view of a microelectronic structure 100 including low-LER lines 140 of multiple pitches (including variable line widths and spacings) according to various embodiments. The microelectronic structure 100 of FIG. 18 includes a first set of low-LER lines 140-1, a second set of low-LER lines 140-2, and corresponding inter-line spaces 150-1 and 150-2, respectively. The widths of the low-LER lines 140 are shown superimposed on the low-LER lines 140 (e.g., 1x, 1.5x, 2x), and the widths of the inter-line spaces 150 are shown adjacent to the inter-line spaces 150 (e.g., 1x, 1.2x, 3x). The use of stretchable BCP in DSA-based techniques for forming microelectronic structures 100, such as those described below with reference to Figures 19 and 20, results in features with roughness that increases with the size of the feature. Furthermore, these features may not have lithographic characteristics, as discussed above, and therefore the use of stretchable BCP in microelectronic structure 100 fabrication may be detected in the microelectronic structure 100.

[0122] 19A-19E illustrate stages in an exemplary process for fabricating the microelectronic structure 100 of FIG. 18 according to various embodiments. FIG. 19A is a top view of an assembly including a metal 152 patterned on a mask material 108. Additional mask materials (e.g., mask materials 104 and 106, not shown) may be below the mask material 108, and a dielectric material 102 (not shown) may be below the additional mask material. In some embodiments, the metal 152 may include titanium nitride or a metal oxide. The metal 152 may be patterned using lithographic techniques (and therefore may have rough edges).

[0123] 19B is a top view of the assembly of FIG. 19A after providing brushes 110 on metal 152. In some embodiments, brushes 110 can be a material that selectively deposits and adheres to metal 152 to replicate the pattern of metal 152.

[0124] 19C is a top view of the assembly after depositing BCPs (e.g., BCP 114, not shown), processing the resulting assembly to allow the BCPs to self-assemble according to the template provided by brush 110, and then removing some of the assembled BCPs to leave BCP component 154. BCP component 154 may be a "stretchable" component such that it can assemble into vertically oriented bands of different widths (e.g., 1x and 1.2x) depending on the dimensions of the underlying brush 110. In some embodiments, the "stretchable" BCP may comprise a triblock copolymer such as PMMA-b-PS-b-PMMA, PS-b-PMMA-b-PS, PS-b-poly(ethylene oxide) (PEO), PS-b-PEO-b-PS, PEO-b-PS-b-PEO, poly(styrene-b-2-vinylpyridine) (PS-b-P2VP), PS-b-P2VP-b-PS, P2VP-b-PS-b-P2VP, PS-b-P4VP, PS-b-P4VP-b-PS, P4VP-b-PS-b-P4VP, polystyrene-block-polydimethylsiloxane (PS-b-PDMS), PDMS-b-PS-b-PDMS, or PS-b-PDMS-b-PS.

[0125] 19C after removing the exposed mask material 108 from the assembly (e.g., by a suitable selective etch), patterning the dielectric material 102 underlying the resulting assembly according to the pattern of the BCP components 154 and brushes 110, and then removing the BCP components 154 and brushes 110 (e.g., by a suitable selective etch). The openings 190 in the dielectric material 102 may have "smooth" edges.

[0126] 19E is a top view of the assembly of FIG. 19D after filling the openings 190 with line material (e.g., line material 120) to form low LER lines 140 and inter-line spaces 150. The assembly of FIG. 19E may take the form of the microelectronic structure 100 of FIG. 18. Note that the drawings of FIGS. 18 and 19 are merely examples, and these components may take any suitable form. For example, the dielectric material 102 may be a multi-layer dielectric, and / or the inter-line spaces 150 may be provided by dielectric spacers (e.g., comprising silicon oxynitride, silicon oxycarbide, aluminum oxide, silicon nitride, or silicon oxide) on an intervening dielectric material (e.g., a carbon-doped oxide).

[0127] In some embodiments, the "stretchable" BCP may be utilized in a DSA-based technique that does not utilize an underlying metal 152 upon which the brushes 110 may be replicated. Instead, the brushes 110 may be patterned using other techniques (e.g., lithography). For example, FIG. 20 is a top view of an assembly including patterned brushes 110 on a mask material 108. An assembly similar to that of FIG. 20 may be utilized as described above with reference to FIGS. 19C-19E to form the microelectronic structure 100 of FIG. 18.

[0128] In some embodiments, the low LER line 140 may be included in a metallization stack, as described below with reference to FIG. 29 . For example, the low LER line 140 according to any of the embodiments disclosed herein may be part of the M0, M1, M2, or other interconnect layer of a metallization stack. In some embodiments, the low LER line 140 may be contacted by a via in the metallization stack. In some such embodiments, the via may be formed using conventional techniques, such as using lithographic techniques to form openings that land on the low LER line 140 and filling these openings with a conductive material. In other embodiments, such vias may be formed using self-aligned techniques to reduce misalignment that may occur when conventional approaches are used. For example, FIG. 21 is a cross-sectional side view of a microelectronic structure 100 including a via 166 in conductive contact with the low LER line 140, according to various embodiments. While FIG. 21 (and other accompanying figures) shows the via 166 as including line material 120, the via 166 may include any suitable fill and / or liner material.

[0129] In the microelectronic structure 100 of Figure 21, the via 166 includes a lower portion that extends through the second replicated brush component 158 ​​(described further below) and an upper portion that extends through the photoresist 162. The photoresist 162 may be a dielectric material that includes cross-linking elements that can be selectively activated by EUV exposure, as described further below. The unpatterned regions 144 of the microelectronic structure 100 of Figure 21 may include the disordered layered structure 138 and the disordered dielectric material 160 over the disordered layered structure 138, as described above.

[0130] Figures 22A-22F illustrate stages in an exemplary process for fabricating the microelectronic structure 100 of Figure 21 according to various embodiments. Figure 22A is a cross-sectional side view of an assembly including a patterned region 142 having one or more low LER lines 140 in a dielectric material 102 and an unpatterned region 144 having a disordered layered structure 138. The assembly of Figure 22A may take the form of any of the microelectronic structures 100 described above with reference to Figures 1-20.

[0131] 22B is a cross-sectional side view of the assembly of FIG. 22A after forming a replicate brush 192 on the assembly. The replicate brush 192 may include a first replicate brush component 156 and a second replicate brush component 158. The first replicate brush component 156 may preferentially adhere to the line material 120 of the low LER line 140, and the second replicate brush component 158 ​​may preferentially adhere to the dielectric material 102 to form a self-assembled replicate brush 192. The replicate brush 192 may include a disordered dielectric material 160, which may not have a self-assembled structure or may have a disordered layered structure similar to that of FIG. 1C. In some embodiments, the first replicate brush component 156 (metal-selective brush material) may have surface anchoring groups including phosphines, thiols, thiolic acids, thioacetic acids, disulfides, alkyl azides, aryl azides, nitriles, phosphates, silyl, alkyl and other phosphonate esters, phosphonamides, sulfonamides, sulfenic acids, sulfinic acids, sulfonic acids, boronic acids, phosphonic acids, carboxylic acids, phosphorus dichloride, alkenes, or alkyne materials. In some embodiments, the second replicate brush component 158 ​​(dielectric-selective brush material) may have surface anchoring groups of hydroxy, amine, or carboxylic acid groups.

[0132] FIG. 22C is a cross-sectional side view of the assembly of FIG. 22B after depositing photoresist 162 on it. Photoresist 162 may include cross-linking elements that, upon activation by EUV exposure, cross-link in the presence of first replicate brush component 156 but not otherwise. In some embodiments, photoresist 162 and / or first replicate brush component 156 may include photoacid generator (PAG) molecules that, upon ultraviolet (UV) exposure (e.g., EUV exposure), generate acid, causing cross-linking of photoresist 162. The cross-linked photoresist 164, described below, may then be selectively removed. In some embodiments, photoresist 162 and / or second replicate brush component 158 ​​may include quencher molecules that, upon UV exposure, quench the acid generated by photoresist 162 in the region above second replicate brush component 158, preventing cross-linking of photoresist 162 in the region above second replicate brush component 158. The cross-linked photoresist 164, described below, may then be selectively removed. More generally, the first replica brush component 156, the second replica brush component 158, and / or the photoresist 162 may include a catalyst capable of selectively localizing cross-linking of the photoresist 162 upon exposure to UV radiation.

[0133] Figure 22D is a cross-sectional side view of the assembly of Figure 22C after the photoresist 162 of the assembly has been exposed to EUV radiation (e.g., EUV "flooding") to form cross-linked photoresist 164 in the volume of photoresist 162 adjacent to the first replica brush component 156.

[0134] FIG. 22E is a cross-sectional side view of the assembly of FIG. 22D after cross-linked photoresist 164 has been removed from the assembly (eg, using a suitable selective etching technique).

[0135] Figure 22F is a cross-sectional side view of the assembly of Figure 22E after removing the first replica brush component 156 from the assembly (e.g., using a suitable selective etching technique) and then filling the opening with line material 120 to form a via 166. The assembly of Figure 22F may take the form of the microelectronic structure 100 of Figure 21.

[0136] 21 and 22 illustrate a microelectronic structure 100 that may include a via 166 patterned by techniques including EUV flooding. In other embodiments, the via 166 may be patterned using selective application of UV radiation. For example, FIG. 23 is a cross-sectional side view of another microelectronic structure 100 including a via 166 in conductive contact with a low LER line 140, according to various embodiments. The microelectronic structure 100 of FIG. 23 shares many elements in common with the microelectronic structure 100 of FIG. 21. For ease of explanation, the description of these elements will not be repeated, and these elements may take the form of any of the embodiments of these elements disclosed herein. However, in the embodiment of FIG. 23, the via 166 may not be located at the center of the low LER line 140, but instead may be formed at the intersection between the volume above the low LER line 140 and a region to which EUV radiation is selectively applied, as described below.

[0137] 24A-24C illustrate stages in an exemplary process for fabricating the microelectronic structure 100 of FIG. 23 according to various embodiments. FIG. 24A is a cross-sectional side view of the assembly of FIG. 22C after exposing the photoresist 162 of the assembly to patterned EUV radiation (with the EUV-irradiated area shown in dotted lines) to form cross-linked photoresist 164 at the intersection between the EUV-irradiated volume and the volume of photoresist 162 proximate the first replicated brush component 156.

[0138] FIG. 24B is a cross-sectional side view of the assembly of FIG. 24A after cross-linked photoresist 164 has been removed from the assembly (eg, using a suitable selective etching technique).

[0139] Figure 24C is a cross-sectional side view of the assembly of Figure 24B after removing the first replica brush component 156 from the assembly (e.g., using a suitable selective etching technique) and then filling the opening with line material 122 to form a via 166. The assembly of Figure 24C may take the form of the microelectronic structure 100 of Figure 23.

[0140] The fabrication process described above with reference to FIGS. 4-5, 6-7, and 12-13 includes a spacer-based pitch division technique. While the specific pitch division technique in FIGS. 5, 7, and 13 is a two-part pitch division technique (utilizing one round of spacer formation), in other embodiments, a four-part pitch division technique (using two rounds of spacer formation) may be used instead to obtain smaller feature sizes. The use of such pitch division techniques in the process of forming low-LER lines 140 in patterning region 142 may be evidenced in microelectronic structure 100 by the presence of pitch division artifacts in microelectronic structure 100. For example, due to the manner in which the widths of various elements expand into line widths 174 and line spacings 176 through the pitch division technique, line widths 174 and line spacings 176 may exhibit periodicity across several of the low-LER lines 140. Such periodicity may serve as a pitch division artifact in microelectronic structure 100, providing evidence of the use of pitch division techniques during fabrication. Another example of a pitch division artifact that may appear in the microelectronic structure 100 is a nested and / or rounded semi-circular pattern in the dielectric material 102 corresponding to the ends of the spacers 124. FIGS. 25, 26, and 27 are top views of the microelectronic structure 100 of FIGS. 4, 6, and 12, respectively, showing such a nested, rounded pattern 168 near the periphery of the patterned area 142. In embodiments in which a quarter-pitch division technique is used instead of a half-pitch division technique, more “half-circles” may be part of the pattern 168. The presence of such nested and / or rounded patterns may serve as a pitch division artifact in the microelectronic structure 100, providing evidence of the use of a pitch division technique during fabrication. Other pitch division artifacts may be present in place of or in addition to one or more of these artifacts. For example, as described above, spacer-based pitch division may have a single-sized feature (either line width or line-space width) defined by ALD spacer deposition. The thickness of the ALD spacer deposition may determine this size.

[0141] The microelectronic structures 100 disclosed herein may be included in any suitable electronic component. Figures 28-32 show various examples of devices that may include any of the microelectronic structures 100 disclosed herein.

[0142] FIG. 28 is a top view of a wafer 1500 and die 1502 that may include one or more microelectronic structures 100 according to any of the embodiments disclosed herein. The wafer 1500 may be constructed from a semiconductor material and may include one or more die 1502 having microelectronic structures formed on the surface of the wafer 1500. Each of the die 1502 may be a repeating unit of a semiconductor product including any suitable microelectronic structure. After fabrication of the semiconductor product is complete, the wafer 1500 may undergo a singulation process in which the die 1502 are separated from one another to provide individual "chips" of the semiconductor product. The die 1502 may include one or more microelectronic structures 100 (e.g., as described below with reference to FIG. 29), one or more transistors (e.g., some of the transistors 1640 in FIG. 29 described below), and / or support circuitry that routes electrical signals to the transistors, along with any other circuit components. In some embodiments, wafer 1500 or die 1502 may include memory devices (e.g., random access memory (RAM) devices such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive bridge RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. Multiple of these devices may be combined on a single die 1502. For example, a memory array formed by multiple memory devices may be formed on the same die 1502 as a processing device (e.g., processing device 1802 of FIG. 32) or other logic configured to store information in the memory devices or execute instructions stored in the memory array.

[0143] FIG. 29 is a cross-sectional side view of a microelectronic device 1600 that may include one or more microelectronic structures 100 according to any of the embodiments disclosed herein. One or more of the microelectronic devices 1600 may be included in one or more dies 1502 (FIG. 28). The microelectronic devices 1600 may be formed on a substrate 1602 (e.g., wafer 1500 of FIG. 28) and may be included in a die (e.g., die 1502 of FIG. 28). The substrate 1602 may be a semiconductor substrate comprised of a semiconductor material system, including, for example, an n-type or p-type material system (or a combination of both). The substrate 1602 may include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the substrate 1602 may be formed using alternative materials. Such materials may or may not be combined with silicon, including, but not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Additionally, materials classified as II-VI, III-V, or IV may also be used to form substrate 1602. Some examples of materials from which substrate 1602 may be formed are described here, although any material capable of serving as the foundation for microelectronic device 1600 may be used. Substrate 1602 may be part of a singulated die (e.g., die 1502 of FIG. 28) or wafer (e.g., wafer 1500 of FIG. 28).

[0144] The microelectronic device 1600 may include one or more device layers 1604 disposed on a substrate 1602. The device layer 1604 may include features of one or more transistors 1640 (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) formed on the substrate 1602. The device layer 1604 may include, for example, one or more source and / or drain (S / D) regions 1620, a gate 1622 for controlling the flow of current in the transistor 1640 between the S / D regions 1620, and one or more S / D contacts 1624 for routing electrical signals to and from the S / D regions 1620. The transistor 1640 may include additional features such as device isolation regions, gate contacts, etc., not shown for clarity. The transistor 1640 is not limited to the type and configuration shown in FIG. 29 and may include a variety of other types and configurations, such as, for example, planar transistors, non-planar transistors, or a combination of both. Planar transistors may include bipolar junction transistors (BJTs), heterojunction bipolar transistors (HBTs), or high electron mobility transistors (HEMTs). Non-planar transistors may include FinFET transistors, such as double-gate or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbon and nanowire transistors.

[0145] Each transistor 1640 may include a gate 1622 formed of at least two layers, a gate dielectric, and a gate electrode. The gate dielectric may include one layer or a stack of layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be performed on the gate dielectric to improve the quality of the gate dielectric when high-k materials are used.

[0146] A gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether transistor 1640 is to be a p-type metal oxide semiconductor (PMOS) or n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may be composed of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Additionally, metal layers may be included for other purposes, such as barrier layers, etc. For PMOS transistors, metals that may be used in the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals described below with reference to NMOS transistors (e.g., for work function tuning). For NMOS transistors, metals that may be used in the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals mentioned above with reference to PMOS transistors (e.g., for work function tuning).

[0147] In some embodiments, when viewed as a cross-section of transistor 1640 along the source-channel-drain direction, the gate electrode may be comprised of a U-shaped structure including a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions that are substantially perpendicular to the top surface of the substrate. In other embodiments, the gate electrode may be comprised of a combination of U-shaped and planar non-U-shaped structures. For example, the gate electrode may be comprised of one or more U-shaped metal layers formed on one or more planar non-U-shaped layers.

[0148] In some embodiments, pairs of sidewall spacers may be formed on opposing sides of the gate stack to sandwich the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming sidewall spacers are known in the art and generally include deposition and etching process steps. In some embodiments, multiple pairs of spacers may be used. For example, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

[0149] The S / D regions 1620 may be formed in the substrate 1602 adjacent to the gate 1622 of each transistor 1640. The S / D regions 1620 may be formed using, for example, an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion-implanted into the substrate 1602 to form the S / D regions 1620. The ion-implantation process may be followed by an annealing process to activate the dopants and diffuse them deeper into the substrate 1602. In the latter process, the substrate 1602 may first be etched to form recesses at the locations of the S / D regions 1620. An epitaxial deposition process may then be performed to fill the recesses with the material used to fabricate the S / D regions 1620. In some implementations, the S / D regions 1620 may be fabricated using silicon germanium or a silicon alloy such as silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with a dopant, such as boron, arsenic, or phosphorus. In some embodiments, the S / D regions 1620 may be formed using one or more alternative semiconductor materials, such as germanium or a III-V material or alloy. In further embodiments, one or more layers of metal and / or metal alloy may be used to form the S / D regions 1620.

[0150] Electrical signals, such as power and / or input / output (I / O) signals, may be routed to and / or from devices (e.g., transistor 1640) in device layer 1604 through one or more interconnect layers (such as interconnect layers 1606-1610 shown in FIG. 29 ) disposed in device layer 1604. For example, conductive features (e.g., gate 1622 and S / D contacts 1624) in device layer 1604 may be electrically coupled to interconnect structures 1628 in interconnect layers 1606-1610. One or more interconnect layers 1606-1610 may form a metallization stack (also referred to as an “ILD” stack) 1619 of microelectronic device 1600. Any of the microelectronic structures 100 disclosed herein may be included in any of the interconnect layers of metallization stack 1619.

[0151] The interconnect structures 1628 may be arranged within the interconnect layers 1606-1610 to route electrical signals according to a variety of designs (notably, such arrangements are not limited to the particular configuration of the interconnect structures 1628 shown in Figure 29). Although a specific number of interconnect layers 1606-1610 are shown in Figure 29, embodiments of the present disclosure include microelectronic devices having more or fewer interconnect layers than those shown.

[0152] In some embodiments, the interconnect structure 1628 may include lines 1628a and / or vias 1628b filled with a conductive material such as a metal. The lines 1628a may be arranged to route electrical signals in a planar direction that is substantially parallel to the surface of the substrate 1602 on which the device layer 1604 is formed. For example, the lines 1628a may route electrical signals in directions into and out of the plane of the paper from the perspective of FIG. 29 . Any of the lines 1628a in the metallization stack 1619 may take the form of a low LER line 140 disclosed herein. For example, one or more of the lines 1628a in the interconnect layer in the metallization stack 1619 may be a low LER line 140. The vias 1628b may be arranged to route electrical signals in a planar direction that is substantially perpendicular to the surface of the substrate 1602 on which the device layer 1604 is formed. In some embodiments, the vias 1628b may electrically couple together the lines 1628a of different interconnect layers 1606-1610. Any of the vias 1628b in the metallization stack 1619 may take the form of the vias 166 disclosed herein.

[0153] 29, the interconnect layers 1606-1610 may include a dielectric material 1626 disposed between interconnect structures 1628. In some embodiments, the dielectric material 1626 disposed between the interconnect structures 1628 in different ones of the interconnect layers 1606-1610 may have different compositions. In other embodiments, the composition of the dielectric material 1626 between different interconnect layers 1606-1610 may be the same.

[0154] A first interconnect layer 1606 may be formed over the device layer 1604. As shown, in some embodiments, the first interconnect layer 1606 may include lines 1628a and / or vias 1628b. The lines 1628a of the first interconnect layer 1606 may be coupled to contacts (e.g., S / D contacts 1624) of the device layer 1604. The first interconnect layer 1606 may be referred to as an "M0" interconnect layer, and in some embodiments, the M0 interconnect layer may include any of the low LER lines 140 disclosed herein. In some embodiments, the M0 interconnect layer may include any suitable portion of any of the microelectronic structures 100 disclosed herein.

[0155] A second interconnect layer 1608 may be formed over the first interconnect layer 1606. In some embodiments, the second interconnect layer 1608 may include vias 1628b for coupling the lines 1628a of the second interconnect layer 1608 to the lines 1628a of the first interconnect layer 1606. Although the lines 1628a and the vias 1628b are structurally delineated within each interconnect layer (e.g., within the second interconnect layer 1608) for clarity, in some embodiments the lines 1628a and the vias 1628b may be structurally and / or materially adjacent (e.g., may be filled simultaneously during a dual damascene process). The second interconnect layer 1608 may be referred to as an “M1” interconnect layer, and in some embodiments the M1 interconnect layer may include any of the low LER lines 140 disclosed herein. In some embodiments, the M1 interconnect layer may include any suitable portion of any of the microelectronic structures 100 disclosed herein.

[0156] The third interconnect layer 1610 (and additional interconnect layers, if desired) may be successively formed on the second interconnect layer 1608 according to techniques and configurations similar to those described in connection with the second interconnect layer 1608 or the first interconnect layer 1606. The third interconnect layer 1610 may be referred to as the "M2" interconnect layer, and in some embodiments, the M2 interconnect layer may include any of the low LER lines 140 disclosed herein. In some embodiments, the M2 interconnect layer may include any appropriate portion of any of the microelectronic structures 100 disclosed herein. In some embodiments, interconnect layers "higher" in the metallization stack 1619 in the microelectronic device 1600 (i.e., farther away from the device layer 1604) may be thicker.

[0157] The microelectronic device 1600 may include a solder resist material 1634 (e.g., polyimide or a similar material) and one or more conductive contacts 1636 formed on the interconnect layers 1606-1610. In FIG. 29 , the conductive contacts 1636 are shown as taking the form of bond pads. The conductive contacts 1636 may be electrically coupled to the interconnect structure 1628 and may be configured to route electrical signals from the transistor 1640 to other external devices. For example, solder bonds may be formed on the one or more conductive contacts 1636 to mechanically and / or electrically couple a chip including the microelectronic device 1600 to another component (e.g., a circuit board). The microelectronic device 1600 may include additional or alternative structures for routing electrical signals from the interconnect layers 1606-1610. For example, the conductive contacts 1636 may include other similar features (e.g., posts) that route electrical signals to external components.

[0158] 30 is a cross-sectional side view of an exemplary microelectronic package 1650 that may include one or more microelectronic structures 100 according to any of the embodiments disclosed herein. In some embodiments, the microelectronic package 1650 may be a system-in-package (SiP).

[0159] The package substrate 1652 may be formed of a dielectric material (e.g., ceramic, build-up film, epoxy film with filler particles therein, glass, organic, inorganic, a combination of organic and inorganic, embedded portions formed of different materials, etc.) and may have conductive paths extending through the dielectric material between the face 1672 and the face 1674, or between different locations on the face 1672 and / or between different locations on the face 1674. These conductive paths may take the form of any of the interconnects 1628 described above with reference to FIG. 29 .

[0160] The package substrate 1652 may include conductive contacts 1663 that are coupled to conductive paths (not shown) through the package substrate 1652, thereby enabling circuitry within the die 1656 and / or interposer 1657 to be electrically coupled to various of the conductive contacts 1664 (or to other devices (not shown) included in the package substrate 1652).

[0161] The microelectronic package 1650 may include an interposer 1657 coupled to a package substrate 1652 via conductive contacts 1661 of the interposer 1657, first-level interconnects 1665, and conductive contacts 1663 of the package substrate 1652. The first-level interconnects 1665 shown in FIG. 30 are solder bumps, although any suitable first-level interconnects 1665 may be used. In some embodiments, the interposer 1657 may not be included in the microelectronic package 1650; instead, the die 1656 may be directly coupled to the conductive contacts 1663 at the surface 1672 by the first-level interconnects 1665. More generally, one or more die 1656 may be coupled to the package substrate 1652 via any suitable structure (e.g., a silicon bridge, an organic bridge, one or more waveguides, one or more interposers, wire bonds, etc.).

[0162] The microelectronic package 1650 may include one or more dies 1656 coupled to an interposer 1657 via conductive contacts 1654 of the die 1656, first-level interconnects 1658, and conductive contacts 1660 of the interposer 1657. The conductive contacts 1660 may be coupled to conductive paths (not shown) through the interposer 1657, allowing circuitry within the die 1656 to be electrically coupled to various of the conductive contacts 1661 (or to other devices (not shown) included in the interposer 1657). The first-level interconnects 1658 shown in FIG. 30 are solder bumps, although any suitable first-level interconnects 1658 may be used. As used herein, "conductive contacts" may refer to portions of a conductive material (e.g., a metal) that serve as an interface between different components. The conductive contacts may be recesses formed in the surface of the component, may be flush with the surface, or may extend away from the surface, and may take any suitable form (e.g., conductive pads or sockets).

[0163] In some embodiments, an underfill material 1666 may be disposed between the package substrate 1652 and the interposer 1657 around the first-level interconnect 1665, and a molding compound 1668 may be disposed around the die 1656 and the interposer 1657 and in contact with the package substrate 1652. In some embodiments, the underfill material 1666 may be the same as the molding compound 1668. An exemplary material that may be used for the underfill material 1666 and the molding compound 1668 is an epoxy molding material, if desired. The second-level interconnect 1670 may be coupled to the conductive contacts 1664. The second-level interconnect 1670 shown in FIG. 30 is a solder ball (e.g., for a ball grid array arrangement), although any suitable second-level interconnect 1670 (e.g., a pin in a pin grid array arrangement or a land in a land grid array arrangement) may be used. The second level interconnect 1670 may be used to couple the microelectronic package 1650 to another component, such as a circuit board (e.g., a motherboard), an interposer, or another microelectronic package as known in the art and described below with reference to FIG. 31.

[0164] The die 1656 may take the form of any of the embodiments of die 1502 described herein (e.g., may include any of the embodiments of microelectronic device 1600). In embodiments in which the microelectronic package 1650 includes multiple die 1656, the microelectronic package 1650 may be referred to as a multi-chip package (MCP). The die 1656 may include circuitry for performing any desired function. For example, one or more of the die 1656 may be logic die (e.g., silicon-based die) and one or more of the die 1656 may be memory die (e.g., high-bandwidth memory).

[0165] Although the microelectronic package 1650 shown in FIG. 30 is a flip-chip package, other package architectures may be used. For example, the microelectronic package 1650 may be a ball grid array (BGA) package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, the microelectronic package 1650 may be a wafer-level chip-scale package (WLCSP) or a panel fan-out (FO) package. Although two dies 1656 are shown in the microelectronic package 1650 of FIG. 30, the microelectronic package 1650 may include any desired number of dies 1656. The microelectronic package 1650 may include additional passive components, such as surface-mount resistors, capacitors, and inductors, disposed on either the first side 1672 or the second side 1674 of the package substrate 1652 or on the interposer 1657. More generally, the microelectronic package 1650 may include any other active or passive components known in the art.

[0166] 31 is a cross-sectional side view of a microelectronic device assembly 1700 that may include one or more microelectronic packages or other electronic components (e.g., dies) that include one or more microelectronic structures 100 according to any of the embodiments disclosed herein. The microelectronic device assembly 1700 includes multiple components disposed on a circuit board 1702 (which may be, for example, a motherboard). The microelectronic device assembly 1700 includes components disposed on a first side 1740 of the circuit board 1702 and on an opposing second side 1742 of the circuit board 1702; typically, components may be disposed on one or both of the sides 1740 and 1742. Any of the microelectronic packages described below with reference to the microelectronic device assembly 1700 may take the form of any of the embodiments of the microelectronic package 1650 described above with reference to FIG. 30 (e.g., may include one or more microelectronic structures 100 in a die).

[0167] In some embodiments, the circuit board 1702 may be a printed circuit board (PCB) that includes multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. Any one or more of the metal layers may be formed (optionally in conjunction with other metal layers) to route electrical signals between components coupled to the circuit board 1702 in a desired circuit pattern. In other embodiments, the circuit board 1702 may be a non-PCB substrate.

[0168] The microelectronic device assembly 1700 shown in Figure 31 includes a package-on-interposer structure 1736 coupled to a first surface 1740 of a circuit board 1702 by coupling components 1716. The coupling components 1716 may electrically and mechanically couple the package-on-interposer structure 1736 to the circuit board 1702 and may include solder balls (shown in Figure 31), male and female portions of a socket, adhesive, underfill material, and / or any other suitable electrical and / or mechanical coupling structure.

[0169] The package-on-interposer structure 1736 may include a microelectronic package 1720 coupled to a package interposer 1704 by a bonding component 1718. The bonding component 1718 may take any suitable form for the application, such as those described above with reference to the bonding component 1716. While a single microelectronic package 1720 is shown in FIG. 31 , multiple microelectronic packages may be coupled to the package interposer 1704, and in fact, additional interposers may be coupled to the package interposer 1704. The package interposer 1704 may provide an intervening substrate used to bridge the circuit board 1702 and the microelectronic package 1720. The microelectronic package 1720 may be or include, for example, a die (such as the die 1502 in FIG. 28 ), a microelectronic device (such as the microelectronic device 1600 in FIG. 29 ), or any other suitable component. In general, the package interposer 1704 may spread connections to a wider pitch or reroute connections to different connections. For example, the package interposer 1704 may couple a microelectronic package 1720 (e.g., a die) to a set of BGA conductive contacts of the mating component 1716 for coupling to the circuit board 1702. In the embodiment shown in FIG. 31 , the microelectronic package 1720 and the circuit board 1702 are attached to opposite sides of the package interposer 1704. In other embodiments, the microelectronic package 1720 and the circuit board 1702 may be attached to the same side of the package interposer 1704. In some embodiments, three or more components may be interconnected by the package interposer 1704.

[0170] In some embodiments, the package interposer 1704 may be formed as a PCB including multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. In some embodiments, the package interposer 1704 may be formed of a polymeric material such as epoxy, glass-reinforced epoxy, epoxy with inorganic filler, ceramic material, or polyimide. In some embodiments, the package interposer 1704 may be formed of alternative rigid or flexible materials. Such materials may include the same materials described above for semiconductor substrates, such as silicon, germanium, and other III-V and IV materials. The package interposer 1704 may include metal lines 1710 and vias 1708, including, but not limited to, through-silicon vias (TSVs) 1706. The package interposer 1704 may further include embedded devices 1714, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the package interposer 1704. The package-on-interposer structure 1736 may take the form of any of the package-on-interposer structures known in the art.

[0171] Microelectronic device assembly 1700 may include a microelectronic package 1724 coupled to a first surface 1740 of circuit board 1702 by a coupling component 1722. Coupling component 1722 may take the form of any of the embodiments described above with reference to coupling component 1716, and microelectronic package 1724 may take the form of any of the embodiments described above with reference to microelectronic package 1720.

[0172] 31 includes a package-on-package structure 1734 coupled to a second surface 1742 of a circuit board 1702 by a bonding component 1728. The package-on-package structure 1734 may include a microelectronic package 1726 and a microelectronic package 1732 coupled together by a bonding component 1730 such that the microelectronic package 1726 is disposed between the circuit board 1702 and the microelectronic package 1732. The bonding components 1728 and 1730 may take the form of any of the embodiments of the bonding component 1716 described above, and the microelectronic packages 1726 and 1732 may take the form of any of the embodiments of the microelectronic package 1720 described above. The package-on-package structure 1734 may be configured according to any of the package-on-package structures known in the art.

[0173] FIG. 32 is a block diagram of an example computing device 1800 that may include one or more microelectronic structures 100 according to any of the embodiments disclosed herein. For example, any suitable number of components of the computing device 1800 may include one or more of the microelectronic devices, microelectronic device assemblies 1700, microelectronic packages 1650, microelectronic devices 1600, or die 1502 disclosed herein. While numerous components are shown in FIG. 32 as being included in the computing device 1800, any one or more of these components may be omitted or duplicated, as appropriate, depending on the application. In some embodiments, some or all of the components included in the computing device 1800 may be mounted on one or more motherboards. In some embodiments, some or all of these components are fabricated on a single system-on-chip (SoC) die.

[0174] 32 , but the computing device 1800 may include interface circuitry for coupling one or more components. For example, the computing device 1800 may not include a display device 1806, but may include display device interface circuitry (e.g., connectors and driver circuits) to which the display device 1806 may be coupled. In another set of examples, the computing device 1800 may not include an audio input device 1824 or an audio output device 1808, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuits) to which the audio input device 1824 or the audio output device 1808 may be coupled.

[0175] Computing device 1800 may include processing device 1802 (e.g., one or more processing devices). As used herein, the terms “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and / or memory and converts the electronic data into other electronic data that can be stored in registers and / or memory. Processing device 1802 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (specialized processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing devices. Computing device 1800 may include memory 1804, which may itself include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard drive. In some embodiments, memory 1804 may include memory that shares a die with processing device 1802. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0176] In some embodiments, computing device 1800 may include a communications chip 1812 (e.g., one or more communications chips). For example, communications chip 1812 may be configured to manage wireless communications for the transfer of data to and from computing device 1800. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc. that may communicate data using modulated electromagnetic radiation through a non-solid medium. Although the associated devices may not include wires in some embodiments, the term does not imply that the associated devices do not include any wires.

[0177] The communications chip 1812 may implement any of a number of wireless standards or protocols, including, but not limited to, Institute of Electrical and Electronics Engineers (IEEE) standards including Wi-Fi® (IEEE 802.11 family), the IEEE 802.16 standard (e.g., the IEEE 802.16-2005 amendment), the Long Term Evolution (LTE) project with any amendments, updates, and / or revisions (e.g., the Advanced LTE project, the Ultra Mobile Broadband (UMB) project (also referred to as "3GPP®2"), etc.). Broadband wireless access (BWA) networks compatible with IEEE 802.16 are commonly referred to as WiMAX® networks. The acronym stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed IEEE 802.16 standard compliance and interoperability testing. The communications chip 1812 may operate according to Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA or LTE network). The communications chip 1812 may operate according to Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Next Generation UTRAN (E-UTRAN). The communications chip 1812 may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO), and their derivatives, as well as any other wireless protocols designated as 3G, 4G, 5G, and beyond. In other embodiments, the communications chip 1812 may operate according to other wireless protocols. Computing device 1800 may include an antenna 1822 for facilitating wireless communication and / or receiving other wireless communications (such as AM or FM radio transmissions).

[0178] In some embodiments, the communications chip 1812 may manage wired communications, such as electrical, optical, or any other suitable communications protocol (e.g., Ethernet). As described above, the communications chip 1812 may include multiple communications chips. For example, a first communications chip 1812 may be dedicated to short-range wireless communications, such as Wi-Fi or Bluetooth, and a second communications chip 1812 may be dedicated to long-range wireless communications, such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communications chip 1812 may be dedicated to wireless communications, and the second communications chip 1812 may be dedicated to wired communications.

[0179] Computing device 1800 may include battery / power circuitry 1814. Battery / power circuitry 1814 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of computing device 1800 to an energy source (e.g., AC line power) separate from computing device 1800.

[0180] Computing device 1800 may include a display device 1806 (or corresponding interface circuitry as described above). Display device 1806 may include any visual indicator, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

[0181] The computing device 1800 may include an audio output device 1808 (or corresponding interface circuitry as described above). The audio output device 1808 may include any device that generates an audible indicator, such as a speaker, a headset, or earphones.

[0182] The computing device 1800 may include an audio input device 1824 (or corresponding interface circuitry as described above). The audio input device 1824 may include any device that generates a signal representing sound, such as a microphone, a microphone array, or a digital device (e.g., a device with a Musical Instrument Digital Interface (MIDI) output).

[0183] Computing device 1800 may include a GPS device 1818 (or corresponding interface circuitry as described above), which may communicate with a satellite-based system and receive the location of computing device 1800 in a manner known in the art.

[0184] The computing device 1800 may include other output devices 1810 (or corresponding interface circuitry, as described above). Examples of other output devices 1810 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or additional storage devices.

[0185] The computing device 1800 may include other input devices 1820 (or corresponding interface circuitry, as described above). Examples of other input devices 1820 may include an accelerometer, a gyroscope, a compass, an imaging device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0186] Computing device 1800 may have any desirable form factor, such as a handheld or mobile computing device (e.g., a mobile phone, smartphone, mobile internet device, music player, tablet computer, laptop computer, netbook computer, ultrabook computer, personal digital assistant (PDA), ultramobile personal computer, etc.), desktop computing device, server computing device or other network computing component, vehicle computing device (e.g., a vehicle control unit), laptop computing device, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, digital video recorder, or wearable computing device. In some embodiments, computing device 1800 may be any other electronic device that processes data.

[0187] The following paragraphs provide various examples of the embodiments disclosed herein. Example 1 is a microelectronic structure including a patterned region including a first conductive line and a second conductive line, the second conductive line adjacent to the first conductive line, the first conductive line and the second conductive line having a pitch of less than 30 nanometers, the first conductive line having a line edge roughness of less than 1.2 nanometers, and the second conductive line having a line edge roughness of less than 1.2 nanometers.

[0188] Example 2 includes the subject matter of Example 1, further providing that the microelectronic structure further includes a disordered region having a disordered layered pattern, the disordered region being coplanar with the patterned region.

[0189] Example 3 includes the subject matter of Example 2, further specifying that the microelectronic structure is part of a die, and the disordered region is part of a transition region of the die, under a guard ring of the die, or in a frame of the die.

[0190] Example 4 includes the subject matter of any of Examples 2-3, further specifying that the first conductive line includes a conductive material and the disordered region includes a material having the same material composition as the conductive material.

[0191] Example 5 includes the subject matter of any of Examples 2-4, further providing that the patterned regions include a dielectric material and the disordered regions include a material having the same material composition as the dielectric material.

[0192] Example 6 includes the subject matter of any of Examples 1-5, further specifying that the spacing between the first conductive line and the second conductive line is less than 15 nanometers.

[0193] Example 7 includes the subject matter of any of Examples 1-6, further specifying that the spacing between the first conductive line and the second conductive line is less than 12 nanometers.

[0194] Example 8 includes the subject matter of any of Examples 1-6, further providing that the first conductive line has a width less than 15 nanometers.

[0195] Example 9 includes the subject matter of any of Examples 1-8, further specifying that the first conductive line has a width less than 12 nanometers.

[0196] Example 10 includes the subject matter of any of Examples 1-9, further providing that the second conductive line has a width less than 15 nanometers.

[0197] Example 11 includes the subject matter of any of Examples 1-10, further providing that the second conductive line has a width less than 12 nanometers.

[0198] Example 12 includes the subject matter of any of Examples 1-11, further providing that the first conductive line and the second conductive line are part of a conductive line set, the conductive line set including more than two conductive lines, and the pitch of the first conductive line and the second conductive line is the same as the pitch between adjacent conductive lines in the conductive line set.

[0199] Example 13 includes the subject matter of any of Examples 1-12, further providing that the microelectronic structure further includes a pitch division artifact proximate the patterned region.

[0200] Example 14 includes the subject matter of example 13, further specifying that the pitch division artifacts include one or more semi-circular patterns in a dielectric material.

[0201] Example 15 includes the subject matter of any of Examples 1-14, further providing that widths of at least some of the conductive lines in the patterned region are periodic across the conductive lines.

[0202] Example 16 includes the subject matter of any of Examples 1-15, further providing that the second conductive line has a width greater than a width of the first conductive line.

[0203] Example 17 includes the subject matter of example 16, further specifying that the line edge roughness of the second conductive line is greater than the line edge roughness of the first conductive line.

[0204] Example 18 includes the subject matter of Example 17, further specifying that the patterning region includes another conductive line, a width of the other conductive line being greater than a width of the second conductive line, and a line edge roughness of the other conductive line being greater than a line edge roughness of the second conductive line.

[0205] Example 19 includes the subject matter of any of Examples 16-18, further providing that the width of the second conductive line is at least three times greater than the width of the first conductive line.

[0206] Example 20 includes the subject matter of any of Examples 1-15, further providing that the first conductive line has a width greater than a width of the second conductive line.

[0207] Example 21 includes the subject matter of example 20, further specifying that the line edge roughness of the first conductive line is greater than the line edge roughness of the second conductive line.

[0208] Example 22 includes the subject matter of Example 21, further specifying that the patterning region includes another conductive line, a width of the other conductive line being greater than a width of the first conductive line, and a line edge roughness of the other conductive line being greater than a line edge roughness of the first conductive line.

[0209] Example 23 includes the subject matter of Example 22, further specifying that the width of the first conductive line is at least three times greater than the width of the second conductive line.

[0210] Example 24 includes the subject matter of any of Examples 1-23, further specifying that a spacing between the first conductive line and the second conductive line is greater than a spacing between the second conductive line and a conductive line adjacent to the second conductive line.

[0211] Example 25 includes the subject matter of any of Examples 1-23, further specifying that a spacing between the first conductive line and the second conductive line is less than a spacing between the second conductive line and a conductive line adjacent to the second conductive line.

[0212] Example 26 includes the subject matter of any of Examples 1-25, further providing that the patterning region is a first patterning region, the microelectronic structure further includes a second patterning region including a first conductive line and a second conductive line, the second conductive line of the second patterning region adjacent to the first conductive line of the second patterning region, and the first conductive line of the second patterning region and the second conductive line of the second patterning region have a pitch greater than 24 nanometers.

[0213] Example 27 includes the subject matter of example 26, further specifying that the first conductive line in the second patterned region and the second conductive line in the second patterned region have a pitch greater than 30 nanometers.

[0214] Example 28 includes the subject matter of any of Examples 26-27, further specifying that the first conductive lines in the second patterning region have a line edge roughness greater than 1.2 nanometers and the second conductive lines have a line edge roughness greater than 1.2 nanometers.

[0215] Example 29 includes the subject matter of any of Examples 26-28, further specifying that the first conductive line in the second patterning region has a line width roughness and a line edge roughness, and the line width roughness is equal to the line edge roughness multiplied by the square root of two.

[0216] Example 30 includes the subject matter of any of Examples 26-29, further providing that the second conductive line in the second patterning region has a line width roughness and a line edge roughness, and the line width roughness is equal to the line edge roughness multiplied by the square root of two.

[0217] Example 31 includes the subject matter of any of Examples 26-30, further providing that the second patterning region is coplanar with the first patterning region.

[0218] Example 32 includes the subject matter of any of Examples 26-31, further providing that the second patterned region is in the same layer of the metallization stack as the first patterned region.

[0219] Example 33 includes the subject matter of any of Examples 1-32, further specifying that the first conductive line has a line width roughness, and the line width roughness of the first conductive line is not equal to the line edge roughness of the first conductive line multiplied by the square root of two.

[0220] Example 34 includes the subject matter of any of Examples 1-33, further specifying that the second conductive line has a line width roughness, and the line width roughness of the second conductive line is not equal to the line edge roughness of the second conductive line multiplied by the square root of two.

[0221] Example 35 includes the subject matter of any of Examples 1-34, further specifying that the patterning region includes a third conductive line and a fourth conductive line, the third conductive line being between the second conductive line and the fourth conductive line, the third conductive line having a line edge roughness greater than 1.2 nanometers, and the fourth conductive line having a line edge roughness less than 1.2 nanometers.

[0222] Example 36 includes the subject matter of any of Examples 1-35, further providing that the microelectronic structure further includes a via in conductive contact with the first conductive line.

[0223] Example 37 includes the subject matter of Example 36, further specifying that the via is in a dielectric material, and the dielectric material includes a photoacid generator.

[0224] Example 38 includes the subject matter of any of Examples 36-37, further providing that the dielectric material includes a quencher.

[0225] Example 39 includes the subject matter of any of Examples 36-38, further specifying that the via has a side that is self-aligned with a side of the first conductive line.

[0226] Example 40 includes the subject matter of any of Examples 36-38, further providing that the via does not contact dielectric material adjacent the first conductive line in the patterned region.

[0227] Example 41 includes the subject matter of any of Examples 1-40, further providing that the microelectronic structure further includes a via in conductive contact with the second conductive line.

[0228] Example 42 includes the subject matter of Example 41, further specifying that the via is in a dielectric material, and the dielectric material includes a photoacid generator.

[0229] Example 43 includes the subject matter of any of Examples 41-42, further providing that the dielectric material includes a quencher.

[0230] Example 44 includes the subject matter of any of Examples 41-43, further specifying that the via has a side that is self-aligned with a side of the first conductive line.

[0231] Example 45 includes the subject matter of any of Examples 41-43, further providing that the via does not contact dielectric material adjacent the second conductive line in the patterned region.

[0232] Example 46 includes the subject matter of any of Examples 1-45, and further provides that the microelectronic structure further includes a device layer, and the patterning region is included in an interconnect layer above or below the device layer.

[0233] Example 47 includes the subject matter of Example 46, and further provides that the microelectronic structure further includes a conductive contact, and the patterned region is between the conductive contact and the device layer.

[0234] Example 48 includes the subject matter of any of Examples 1-47, and further provides that the patterned region is included in an M0 interconnect layer.

[0235] Example 49 includes the subject matter of any of Examples 1-47, and further provides that the patterned region is included in an M1 interconnect layer.

[0236] Example 50 includes the subject matter of any of Examples 1-47, and further provides that the patterned region is included in an M2 interconnect layer.

[0237] Example 51 includes the subject matter of any of Examples 1-50, further providing that the first conductive lines are parallel to the second conductive lines.

[0238] Example 52 is a microelectronic structure including a patterned region including a first conductive line and a second conductive line, the second conductive line adjacent to the first conductive line, and a disordered region having a disordered layered pattern, the disordered region being coplanar with the patterned region.

[0239] Example 53 includes the subject matter of Example 52, further providing that the first conductive line comprises a conductive material and the disordered region comprises a material having the same material composition as the conductive material.

[0240] Example 54 includes the subject matter of any of Examples 52-53, further providing that the patterned regions include a dielectric material and the disordered regions include a material having the same material composition as the dielectric material.

[0241] Example 55 includes the subject matter of any of Examples 52-54, further providing that the spacing between the first conductive line and the second conductive line is less than 15 nanometers.

[0242] Example 56 includes the subject matter of any of Examples 52-55, further specifying that the spacing between the first conductive line and the second conductive line is less than 12 nanometers.

[0243] Example 57 includes the subject matter of any of Examples 52-55, further providing that the first conductive line has a width less than 15 nanometers.

[0244] Example 58 includes the subject matter of any of Examples 52-57, further providing that the first conductive line has a width less than 12 nanometers.

[0245] Example 59 includes the subject matter of any of Examples 52-58, further providing that the second conductive line has a width less than 15 nanometers.

[0246] Example 60 includes the subject matter of any of Examples 52-59, further providing that the second conductive line has a width less than 12 nanometers.

[0247] Example 61 includes the subject matter of any of Examples 52-60, further specifying that the first conductive line and the second conductive line are part of a conductive line set, the conductive line set including more than two conductive lines, and the pitch of the first conductive line and the second conductive line is the same as the pitch between adjacent conductive lines in the conductive line set.

[0248] Example 62 includes the subject matter of any of Examples 52-61, and further provides that the microelectronic structure further includes a pitch division artifact proximate the patterned region.

[0249] Example 63 includes the subject matter of Example 62, further specifying that the pitch division artifacts include one or more semi-circular patterns in a dielectric material.

[0250] Example 64 includes the subject matter of any of Examples 52-63, further providing that widths of at least some of the conductive lines in the patterned region are periodic across the conductive lines.

[0251] Example 65 includes the subject matter of any of Examples 52-64, further providing that the second conductive line has a width greater than a width of the first conductive line.

[0252] Example 66 includes the subject matter of example 65, further providing that the line edge roughness of the second conductive line is greater than the line edge roughness of the first conductive line.

[0253] Example 67 includes the subject matter of Example 66, further specifying that the patterning region includes another conductive line, a width of the other conductive line being greater than a width of the second conductive line, and a line edge roughness of the other conductive line being greater than a line edge roughness of the second conductive line.

[0254] Example 68 includes the subject matter of any of Examples 65-67, further providing that the width of the second conductive line is at least three times greater than the width of the first conductive line.

[0255] Example 69 includes the subject matter of any of Examples 52-64, further providing that the first conductive line has a width greater than a width of the second conductive line.

[0256] Example 70 includes the subject matter of example 69, further providing that a line edge roughness of the first conductive line is greater than a line edge roughness of the second conductive line.

[0257] Example 71 includes the subject matter of Example 70, and further specifies that the patterning region includes another conductive line, a width of the other conductive line being greater than a width of the first conductive line, and a line edge roughness of the other conductive line being greater than a line edge roughness of the first conductive line.

[0258] Example 72 includes the subject matter of Example 71, further providing that the width of the first conductive line is at least three times greater than the width of the second conductive line.

[0259] Example 73 includes the subject matter of any of Examples 52-72, further specifying that the spacing between the first conductive line and the second conductive line is greater than the spacing between the second conductive line and a conductive line adjacent to the second conductive line.

[0260] Example 74 includes the subject matter of any of Examples 52-72, further specifying that the spacing between the first conductive line and the second conductive line is smaller than the spacing between the second conductive line and a conductive line adjacent to the second conductive line.

[0261] Example 75 includes the subject matter of any of Examples 52-74, further specifying that the patterning area is a first patterning area, the microelectronic structure further includes a second patterning area including a first conductive line and a second conductive line, the second conductive line of the second patterning area adjacent to the first conductive line of the second patterning area, and the first conductive line of the second patterning area and the second conductive line of the second patterning area have a pitch greater than 24 nanometers.

[0262] Example 76 includes the subject matter of Example 75, further specifying that the first conductive line in the second patterned region and the second conductive line in the second patterned region have a pitch greater than 30 nanometers.

[0263] Example 77 includes the subject matter of any of Examples 75-76, further specifying that the first conductive line in the second patterning region has a line edge roughness greater than 1.2 nanometers and the second conductive line has a line edge roughness greater than 1.2 nanometers.

[0264] Example 78 includes the subject matter of any of Examples 75-77, further specifying that the first conductive line in the second patterning region has a line width roughness and a line edge roughness, and the line width roughness is equal to the line edge roughness multiplied by the square root of 2.

[0265] Example 79 includes the subject matter of any of Examples 75-78, further specifying that the second conductive line in the second patterning region has a line width roughness and a line edge roughness, and the line width roughness is equal to the line edge roughness multiplied by the square root of two.

[0266] Example 80 includes the subject matter of any of Examples 75-79, further providing that the second patterning region is coplanar with the first patterning region.

[0267] Example 81 includes the subject matter of any of Examples 75-80, further providing that the second patterned region is in the same layer of the metallization stack as the first patterned region.

[0268] Example 82 includes the subject matter of any of Examples 52-81, further specifying that the first conductive line has a line width roughness, and the line width roughness of the first conductive line is not equal to the line edge roughness of the first conductive line multiplied by the square root of two.

[0269] Example 83 includes the subject matter of any of Examples 52-82, further specifying that the second conductive line has a line width roughness, and the line width roughness of the second conductive line is not equal to the line edge roughness of the second conductive line multiplied by the square root of two.

[0270] Example 84 includes the subject matter of any of Examples 52-83, further specifying that the patterning region includes a third conductive line and a fourth conductive line, the third conductive line being between the second conductive line and the fourth conductive line, the third conductive line having a line edge roughness greater than 1.2 nanometers, and the fourth conductive line having a line edge roughness less than 1.2 nanometers.

[0271] Example 85 includes the subject matter of any of Examples 52-84, further specifying that the microelectronic structure further includes a via in conductive contact with the first conductive line.

[0272] Example 86 includes the subject matter of Example 85, further specifying that the via is in a dielectric material, and the dielectric material includes a photoacid generator.

[0273] Example 87 includes the subject matter of any of Examples 85-86, and further provides that the dielectric material includes a quencher.

[0274] Example 88 includes the subject matter of any of Examples 85-87, further providing that the via has a side that is self-aligned with a side of the first conductive line.

[0275] Example 89 includes the subject matter of any of Examples 85-87, further providing that the via does not contact dielectric material adjacent the first conductive line in the patterned region.

[0276] Example 90 includes the subject matter of any of Examples 52-89, further providing that the microelectronic structure further includes a via in conductive contact with the second conductive line.

[0277] Example 91 includes the subject matter of Example 90, further specifying that the via is in a dielectric material, and the dielectric material includes a photoacid generator.

[0278] Example 92 includes the subject matter of any of Examples 90-91, and further provides that the dielectric material includes a quencher.

[0279] Example 93 includes the subject matter of any of Examples 90-92, further specifying that the via has a side that is self-aligned with a side of the first conductive line.

[0280] Example 94 includes the subject matter of any of Examples 90-92, further providing that the via does not contact dielectric material adjacent the second conductive line in the patterned region.

[0281] Example 95 includes the subject matter of any of Examples 52-94, and further provides that the microelectronic structure further includes a device layer, and the patterning region is included in an interconnect layer above or below the device layer.

[0282] Example 96 includes the subject matter of Example 95, and further provides that the microelectronic structure further includes a conductive contact, and the patterned region is between the conductive contact and the device layer.

[0283] Example 97 includes the subject matter of any of Examples 52-96, and further provides that the patterned region is included in an M0 interconnect layer.

[0284] Example 98 includes the subject matter of any of Examples 52-96, and further provides that the patterned region is included in an M1 interconnect layer.

[0285] Example 99 includes the subject matter of any of Examples 52-96, and further provides that the patterned region is included in an M2 interconnect layer.

[0286] Example 100 includes the subject matter of any of Examples 52-99, further providing that the first conductive lines are parallel to the second conductive lines.

[0287] Example 101 is a microelectronic structure including a first patterning region including a first conductive line and a second patterning region including a second conductive line, the second patterning region being coplanar with the first patterning region, the first conductive line having a first line width roughness and a first line edge roughness, the first line width roughness not equal to the first line edge roughness multiplied by the square root of two, and the second conductive line having a second line width roughness and a second line edge roughness, the second line width roughness equal to the second line edge roughness multiplied by the square root of two.

[0288] Example 102 includes the subject matter of Example 101, and further provides that the microelectronic structure further includes a disordered region having a disordered layered pattern, the disordered region being coplanar with the first patterned region.

[0289] Example 103 includes the subject matter of Example 102, further specifying that the microelectronic structure is part of a die, and the disordered region is part of a transition region of the die, under a guard ring of the die, or in a frame of the die.

[0290] Example 104 includes the subject matter of any of Examples 102-103, further providing that the first conductive line includes a conductive material and the disordered region includes a material having the same material composition as the conductive material.

[0291] Example 105 includes the subject matter of any of Examples 102-104, further providing that the first patterned region includes a dielectric material and the disordered region includes a material having the same material composition as the dielectric material.

[0292] Example 106 includes the subject matter of any of Examples 101-105, further providing that the pitch of the conductive lines in the first patterned region is less than 30 nanometers.

[0293] Example 107 includes the subject matter of any of Examples 101-106, further specifying that the pitch of the conductive lines in the first patterned region is less than 24 nanometers.

[0294] Example 108 includes the subject matter of any of Examples 101-106, further providing that the first conductive line has a width less than 15 nanometers.

[0295] Example 109 includes the subject matter of any of Examples 101-108, further providing that the first conductive line has a width less than 12 nanometers.

[0296] Example 110 includes the subject matter of any of Examples 101-109, and further provides that the microelectronic structure further includes a pitch division artifact proximate the first patterned region.

[0297] Example 111 includes the subject matter of Example 110, and further provides that the pitch division artifacts include one or more semi-circular patterns in a dielectric material.

[0298] Example 112 includes the subject matter of any of Examples 101-111, further providing that widths of at least some of the conductive lines in the first patterned region are periodic across the at least some of the conductive lines.

[0299] Example 113 includes the subject matter of any of Examples 101-112, further providing that the second conductive line has a width greater than a width of the first conductive line.

[0300] Example 114 includes the subject matter of Example 113, and further provides that the second line edge roughness is greater than the first line edge roughness.

[0301] Example 115 includes the subject matter of Example 114, and further specifies that the second line edge roughness is greater than 1.2 nanometers.

[0302] Example 116 includes the subject matter of any of Examples 113-115, and further specifies that the first line edge roughness is less than 1.2 nanometers.

[0303] Example 117 includes the subject matter of any of Examples 101-112, further providing that the first conductive line has a width greater than a width of the second conductive line.

[0304] Example 118 includes the subject matter of any of Examples 101-117, further providing that the pitch of the conductive lines in the second patterned region is greater than 30 nanometers.

[0305] Example 119 includes the subject matter of any of Examples 101-118, further providing that the second patterning region is coplanar with the first patterning region.

[0306] Example 120 includes the subject matter of any of Examples 101-119, further providing that the second patterned region is in the same layer of the metallization stack as the first patterned region.

[0307] Example 121 includes the subject matter of any of Examples 101-120, and further provides that the microelectronic structure further includes a via in conductive contact with the first conductive line.

[0308] Example 122 includes the subject matter of Example 121, further specifying that the via is in a dielectric material, and the dielectric material includes a photoacid generator.

[0309] Example 123 includes the subject matter of any of Examples 121-122, and further provides that the dielectric material includes a quencher.

[0310] Example 124 includes the subject matter of any of Examples 121-123, further providing that the via has a side that is self-aligned with a side of the first conductive line.

[0311] Example 125 includes the subject matter of any of Examples 121-123, further providing that the via does not contact dielectric material adjacent the first conductive line in the first patterned region.

[0312] Example 126 includes the subject matter of any of Examples 101-125, and further provides that the microelectronic structure further includes a device layer, and the first patterning region is included in an interconnect layer above or below the device layer.

[0313] Example 127 includes the subject matter of Example 126, and further specifies that the microelectronic structure further includes a conductive contact, and the first patterned region is between the conductive contact and the device layer.

[0314] Example 128 includes the subject matter of any of Examples 101-127, and further provides that the first patterned region is included in an M0 interconnect layer.

[0315] Example 129 includes the subject matter of any of Examples 101-127, and further provides that the first patterned region is included in an M1 interconnect layer.

[0316] Example 130 includes the subject matter of any of Examples 101-127, and further provides that the first patterned region is included in an M2 interconnect layer.

[0317] Example 131 includes the subject matter of any of Examples 101-130, and further provides that the first conductive lines are parallel to the second conductive lines.

[0318] Example 132 is a computing device that includes a die that includes any of the microelectronic structures described in any of Examples 1-131 and a circuit board, the die being communicatively coupled to the circuit board.

[0319] Example 133 includes the subject matter of Example 132, further specifying that the die is included in a package, and the package is communicatively coupled to the circuit board.

[0320] Example 134 includes the subject matter of Example 133, and further specifies that the package is communicatively coupled to the circuit board by solder.

[0321] Example 135 includes the subject matter of any of Examples 132-134, and further specifies that the circuit board is a motherboard.

[0322] Example 136 includes the subject matter of any of Examples 132-135, and further specifies that the die is part of a processing device or a memory device.

[0323] Example 137 includes the subject matter of any of Examples 132-136, and further specifies that the computing device is a mobile computing device.

[0324] Example 138 includes the subject matter of any of Examples 132-136, and further specifies that the computing device is a laptop computing device.

[0325] Example 139 includes the subject matter of any of Examples 132-136, and further specifies that the computing device is a desktop computing device.

[0326] Example 140 includes the subject matter of any of Examples 132-136, and further specifies that the computing device is a wearable computing device.

[0327] Example 141 includes the subject matter of any of Examples 132-136, and further specifies that the computing device is a server computing device.

[0328] Example 142 includes the subject matter of any of Examples 132-136, and further specifies that the computing device is a vehicle computing device.

[0329] Example 143 includes the subject matter of any of Examples 132-142, and further specifies that the computing device further includes a display communicatively coupled to the circuit board.

[0330] Example 144 includes the subject matter of any of Examples 132-143, and further specifies that the computing device further includes an antenna communicatively coupled to the circuit board.

[0331] Example 145 includes the subject matter of any of Examples 132-144, and further specifies that the computing device further includes a housing around the die and the circuit board.

[0332] Example 146 includes the subject matter of example 145, and further provides that the housing comprises a plastic material.

[0333] Example 147 includes any of the manufacturing methods disclosed herein. [Other Possible Items] (Item 1) a patterned region including a first conductive line and a second conductive line, the second conductive line adjacent to the first conductive line, the first conductive line and the second conductive line having a pitch of less than 30 nanometers, the first conductive line having a line edge roughness of less than 1.2 nanometers, and the second conductive line having a line edge roughness of less than 1.2 nanometers; A microelectronic structure comprising: (Item 2) Item 10. The microelectronic structure of item 1, further comprising a disordered region having a disordered layered pattern, the disordered region being coplanar with the patterned region. (Item 3) Item 10. The microelectronic structure of item 1, wherein the microelectronic structure further comprises a pitch division artifact proximate the patterned region. (Item 4) 4. The microelectronic structure of any of items 1-3, wherein the patterning region is a first patterning region, and the microelectronic structure further includes a second patterning region including a first conductive line and a second conductive line, the second conductive line of the second patterning region adjacent to the first conductive line of the second patterning region, and the first conductive line of the second patterning region and the second conductive line of the second patterning region have a pitch greater than 24 nanometers. (Item 5) Item 5. The microelectronic structure of item 4, wherein the first conductive lines in the second patterned region have a line edge roughness greater than 1.2 nanometers and the second conductive lines have a line edge roughness greater than 1.2 nanometers. (Item 6) Item 5. The microelectronic structure of item 4, wherein the first conductive lines in the second patterning region have a line-width roughness and a line-edge roughness, the line-width roughness being equal to the line-edge roughness multiplied by the square root of two. (Item 7) Item 5. The microelectronic structure of item 4, wherein the second patterning region is coplanar with the first patterning region. (Item 8) Item 5. The microelectronic structure of item 4, wherein the second patterned region is in the same layer of the metallization stack as the first patterned region. (Item 9) 4. The microelectronic structure of any of items 1-3, wherein the first conductive line has a line width roughness, and the line width roughness of the first conductive line is not equal to the line edge roughness of the first conductive line multiplied by the square root of two. (Item 10) 4. The microelectronic structure of any of items 1-3, wherein the patterning region includes a third conductive line and a fourth conductive line, the third conductive line being between the second conductive line and the fourth conductive line, the third conductive line having a line edge roughness greater than 1.2 nanometers, and the fourth conductive line having a line edge roughness less than 1.2 nanometers. (Item 11) a patterned region including a first conductive line and a second conductive line, the second conductive line being adjacent to the first conductive line; a disordered region having a disordered layered pattern, the disordered region being coplanar with the patterned region; A microelectronic structure comprising: (Item 12) Item 12. The microelectronic structure of item 11, wherein the first conductive line comprises a conductive material and the disordered region comprises a material having the same material composition as the conductive material. (Item 13) Item 12. The microelectronic structure of item 11, wherein the patterned regions comprise a dielectric material and the disordered regions comprise a material having the same material composition as the dielectric material. (Item 14) 14. The microelectronic structure of any of items 11-13, wherein the spacing between the first conductive line and the second conductive line is less than 15 nanometers. (Item 15) 14. The microelectronic structure of any of items 11-13, wherein the microelectronic structure further comprises a device layer, and the patterning region is comprised in an interconnect layer above or below the device layer. (Item 16) a first patterning region including a first conductive line; a second patterning region including a second conductive line; A microelectronic structure comprising: the second patterned region is coplanar with the first patterned region, the first conductive line has a first line width roughness and a first line edge roughness, the first line width roughness not equal to the first line edge roughness multiplied by the square root of two, and the second conductive line has a second line width roughness and a second line edge roughness, the second line width roughness equal to the second line edge roughness multiplied by the square root of two. (Item 17) Item 17. The microelectronic structure of item 16, wherein the microelectronic structure further comprises a via in conductive contact with the first conductive line. (Item 18) Item 18. The microelectronic structure of item 17, wherein the via is in a dielectric material, the dielectric material comprising a photoacid generator. (Item 19) Item 19. The microelectronic structure of item 18, wherein the dielectric material comprises a quencher. (Item 20) 20. The microelectronic structure of any of items 17-19, wherein the via has sides that are self-aligned with sides of the first conductive line.

Claims

1. a patterned region including a first conductive line and a second conductive line, the second conductive line adjacent to the first conductive line, the first conductive line and the second conductive line having a pitch less than 30 nanometers, the first conductive line having a line edge roughness less than 1.2 nanometers, and the second conductive line having a line edge roughness less than 1.2 nanometers; a disordered region having a disordered layered pattern, said disordered region adjacent said patterned region.

2. The microelectronic structure of claim 1 , wherein the microelectronic structure further comprises a pitch division artifact proximate the patterned region.

3. 3. The microelectronic structure of claim 1, wherein the patterned region is a first patterned region, and the microelectronic structure further comprises a second patterned region comprising a first conductive line and a second conductive line, the second conductive line of the second patterned region adjacent to the first conductive line of the second patterned region, and the first conductive line of the second patterned region and the second conductive line of the second patterned region have a pitch greater than 24 nanometers.

4. 4. The microelectronic structure of claim 3, wherein the first conductive lines in the second patterned region have a line edge roughness greater than 1.2 nanometers and the second conductive lines have a line edge roughness greater than 1.2 nanometers.

5. 4. The microelectronic structure of claim 3, wherein the first conductive lines in the second patterned region have a line-width roughness and a line-edge roughness, the line-width roughness being equal to the line-edge roughness multiplied by the square root of two.

6. The microelectronic structure of claim 3 , wherein the second patterned region is coplanar with the first patterned region.

7. The microelectronic structure of claim 3 , wherein the second patterned region is in the same layer of a metallization stack as the first patterned region.

8. 3. The microelectronic structure of claim 1, wherein the first conductive line has a line-width roughness, the line-width roughness of the first conductive line not equal to the line-edge roughness of the first conductive line multiplied by the square root of two.

9. 3. The microelectronic structure of claim 1, wherein the patterned region includes a third conductive line and a fourth conductive line, the third conductive line being between the second and fourth conductive lines, the third conductive line having a line edge roughness greater than 1.2 nanometers, and the fourth conductive line having a line edge roughness less than 1.2 nanometers.

10. a patterned region including a first conductive line and a second conductive line, the second conductive line adjacent to the first conductive line; a disordered region having a disordered layered pattern, the disordered region being coplanar with the patterned region; A microelectronic structure comprising:

11. The microelectronic structure of claim 10 , wherein the first conductive line comprises a conductive material and the disordered region comprises a material having the same material composition as the conductive material.

12. The microelectronic structure of claim 10 , wherein the patterned regions comprise a dielectric material and the disordered regions comprise a material having the same material composition as the dielectric material.

13. 13. The microelectronic structure of claim 10, wherein the spacing between the first and second conductive lines is less than 15 nanometers.

14. 13. The microelectronic structure of claim 10, further comprising a device layer, and wherein the patterning region is included in an interconnect layer above or below the device layer.

15. A microelectronic structure as described in any one of claims 1, 2, and 10 to 12, wherein the disordered region is located under a guard ring of the microelectronic structure.

16. A microelectronic structure as described in claim 15, wherein the first conductive wire and the second conductive wire are not under the guard ring.

17. A microelectronic structure as described in any one of claims 1, 2, and 10 to 12, wherein the disordered region is within a die frame of the microelectronic structure.

18. A microelectronic structure as described in any one of claims 1, 2, and 10 to 12, wherein the first conductive wire and the second conductive wire are outside the frame of the die of the microelectronic structure.

19. A microelectronic structure described in any one of claims 1, 2, and 10 to 12, wherein the disordered region comprises a block copolymer.

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