Circuitry for transferring data from one clock domain to another

Abstract

The present invention relates to a circuit for communicating data from one clock domain to another clock domain, the circuit comprising: a digital circuit configured to generate a data signal whose transitions are synchronized with a source clock signal; a phase comparator configured to determine a phase relationship between the source clock signal and a target clock signal; and a data signal synchronization circuit configured to receive the data signal whose transitions are synchronized with the source clock signal and to provide a synchronized data signal whose transitions are synchronized with the target clock signal, the data signal synchronization circuit configured to switch the provision of the synchronized data signal based on the determined phase relationship between the source clock signal and the target clock signal, the determined phase relationship between the source clock signal and the target clock signal being a predetermined frequency relationship between the source clock signal and the target clock signal.

Description

[Technical Field]

[0001] The present invention relates to a circuit for transferring data from one clock domain to another, a test apparatus for testing a device under test, and a method for transferring data from one clock domain to another clock domain. [Background technology]

[0002] Background of the Invention Modern system-on-chip (SoC) designs continue to face challenges in size and complexity, leading to the adoption of multiple asynchronous clock domains for different I / O interfaces. A clock domain crossing (CDC)-based design is one in which one clock is asynchronous with or has a variable phase relationship to another clock. Propagating signals between asynchronous clock domains can lead to setup and hold time violations. These violations can cause signal metastability. Even if synchronizers can eliminate metastability, improper use, such as synchronous signal convergence and improper synchronization protocols, can still lead to functional CDC failures. Functional verification of such SoC designs is one of the most complex and expensive challenges. Summary of the Invention

[0003] Within one clock domain, proper static timing analysis (STA) ensures that data does not change within the clock setup and hold times. When a signal is passed from one clock domain to another asynchronous domain, data can change at any time, so there is no way to avoid metastability.

[0004] Because CDC errors are not addressed and verified early in the design cycle, many designs only develop functional errors later in the design cycle or during post-silicon verification. Several coverage metrics have been proposed to measure the validity and progress of verification, such as code-based coverage, finite-state machine coverage, and functional coverage. However, these coverage metrics do not directly relate to CDC issues.

[0005] Also, a system testing a device has a signal, the start signal of the test (e.g., TEST_EN), that drives a flip-flop in a source domain (e.g., SYNCCLK). This start signal must be transmitted to a target clock domain (e.g., FIFOCLK) that has the same clock frequency as SYNCCLK but whose phase relationship to SYNCCLK is unknown. During the test, SYNCCLK is turned on and off repeatedly for each individual test run. This means that the phase relationship is different for each test, and static solutions such as STA cannot accommodate the phase changes and resolve clock domain transitions.

[0006] The most common solution to the above problem is the two-flip-flop solution shown in Figure 15. Figure 15 has the drawback that the received signal across a clock domain transition has a time ambiguity of two clock cycles. This occurs whenever the signal changes within the setup / hold time window around the capture clock edge. In this case, it is unclear whether to capture the old or new state of the signal. Metastability is not the only root cause of this randomness; jitter, signal noise, and power supply noise also contribute. Ultimately, however, this means that the test cannot start exactly on the required clock cycle.

[0007] The solution to remove this ambiguity is to use a PLL that shifts one of the two clock domains in phase (but not frequency) to meet the setup and hold time criteria of the receiving clock domain, as shown for example in Figure 15. The drawback is that the settling time of the PLL is very long (several milliseconds) and one PLL is required for each clock domain crossing. For high-speed testing, this is unacceptable.

[0008] To accurately verify clock domain crossing, we must avoid ambiguity when sampling a signal. This ambiguity occurs whenever a signal violates the setup / hold criteria when capturing a flip-flop. In this case, metastability occurs, and it becomes impossible to predict what logic level will be captured. This uncertainty lasts for one clock cycle, resulting in a timely ambiguity of the captured signal of two clock cycles.

[0009] Conventional circuits that transfer data from one clock domain to another, such as the circuits shown diagrammatically in Figure 16 and Figure 17, require resynchronization every time the SYNCCLK phase changes. This means that a PLL settling time of around 1 ms is required to synchronize / resynchronize for each new test run. Because the first input data marks the beginning of the waveform, strict timing is required at the data interface. As shown in Figure 15, FF1 determines the enable transition, and the phase detector PD ensures a known phase alignment. Clock 3 is either a delayed version of Clock 1 (n=1) or a multiple of Clock 1 (n>1).

[0010] The object of the present invention is therefore to avoid these drawbacks and therefore to provide an improved scheme for a circuit for transferring data from one clock domain to another with precise timing.

[0011] This object is solved by a circuit for transmitting data from one clock domain to another clock domain according to claim 1, a testing apparatus for a device under test comprising the circuit according to claim 13 of the present application, and a method for transmitting data from one clock domain to another clock domain according to claim 16.

[0012] Some embodiments of the present invention also provide computer programs for carrying out the steps of the methods of the present invention.

[0013] Summary of the Invention According to a first aspect of the present application, there is provided a circuit for transmitting data from one clock domain to another, the circuit comprising a digital circuit, a phase comparator, and a data signal synchronization circuit. The digital circuit is configured to generate a data signal whose transitions are synchronized with a source clock signal, which is a clock signal indicating when to output data, based on input data values ​​associated with sample times on a time grid that is equally spaced in time, and to receive such data by sampling the data signal synchronously with a target clock signal, which is a clock signal indicating when to receive the provided data. The phase comparator is coupled to the processor, for example, to receive the synchronized clock signal, and to the converter, for example, to receive the converter clock signal. Here, the phase comparator is configured to determine a phase relationship between the source clock signal and the target clock signal. That is, the phase comparator compares the timing of rising or falling edges between the synchronized clock signal and the converter clock signal, thereby performing a phase comparison between the signals. The data signal synchronization circuit may include, for example, a first flip-flop FF, a selector, and a second flip-flop FF, and is configured to receive a data signal provided in synchronization with a synchronous clock signal whose transition is synchronized with a source clock signal, and to provide a synchronous data signal whose transition is synchronized with a target clock signal based thereon. Here, the data signal synchronization circuit is configured to switch between providing the synchronous data signal based on sampling of the data signal in response to a rising edge of the target clock signal and providing the synchronous data signal based on sampling of the data signal in response to a falling edge of the target clock signal, based on the determined phase relationship between the source clock signal and the target clock signal. Here, there is a predetermined frequency relationship between the source clock signal and the target clock signal, for example, locked at a predetermined value.

[0014] According to an embodiment of the present application, a data signal synchronization circuit is configured to select between a first mode and a second mode based on information about a phase relationship between a source clock signal and a target clock signal. In the first mode, a data signal that is time-synchronized with the source clock signal is sampled at an edge of a first edge type (e.g., a falling edge) of the target clock signal to obtain an intermediate signal, and the intermediate signal is sampled at an edge of a second edge type (e.g., a rising edge) of the target clock signal to obtain a synchronized data signal that is time-synchronized with the target clock signal. In the second mode, the data signal that is time-synchronized with the source clock signal is sampled at an edge of a second edge type (e.g., a rising edge) of the target clock signal to obtain a synchronized data signal that is time-synchronized with the target clock signal.

[0015] According to an embodiment of the present application, a data signal synchronization circuit includes a first flip-flop circuit, a signal selector, and a second flip-flop circuit. The first flip-flop circuit is configured to receive a data signal provided by a processor, for example, a test signal on a clock domain different from the converter clock signal, for aligning the output timing of the signal data. The first flip-flop circuit is configured to sample the data signal at a first sampling phase when the phase relationship indicates that the value of the phase difference between the synchronized clock signal and the converter clock signal is within a first predetermined range (e.g., smaller than a predetermined value). If the phase difference poses a potential risk of metastability, the phase for sampling the enable signal is inverted to move the sampling time instance away from the clock edge of the synchronized clock signal to obtain a sampled signal. The signal selector is configured to receive the data signal and is coupled to the first flip-flop circuit to receive the sampled signal. The signal selector is configured to select one of the received signals, for example, based on the phase relationship, to receive a selection signal. The second flip-flop circuit is coupled to the signal selector to receive the selection signal. Here, the second flip-flop circuit is configured to sample the selection signal (e.g., data signal) or the sampled signal at a second sampling phase when the phase relationship is within a second predetermined range. The second predetermined range is different from the first predetermined range and typically does not overlap with the first predetermined range. The second predetermined range may also indicate, for example, that the phase difference between the synchronous clock signal and the converter clock signal is greater than a predetermined value. In this case, the edges of the sampled signal are synchronized with the converter clock signal. That is, the output timing of the signals is aligned, and therefore, there is no need to align the rising edges of the clock signals.

[0016] According to an embodiment of the present application, a source clock signal is provided from or used by a device, e.g., provided from a processor, or a memory, or a loopback interface, etc. Here, the digital circuit is a converter configured to convert data between analog and digital, e.g., between a digital representation and an analog representation, e.g., from a digital representation to an analog representation or from an analog representation to a digital representation. The data signal is an enable signal that triggers the analog-to-digital conversion of the signal, i.e., the enable signal is provided synchronously with the synchronous clock signal.

[0017] According to an embodiment of the present application, the data signal synchronization circuit further includes a first-in-first-out circuit, which is coupled to a data source (e.g., a digital signal processor) for receiving signal data, and is coupled to a second flip-flop circuit for receiving an output signal of the second flip-flop or a delayed version of the output signal of the second flip-flop circuit (e.g., indicating the output timing of the signal data of the converter), the second flip-flop circuit calculating a delay time based on a phase difference between the enable signal and a converter clock signal, wherein the first-in-first-out circuit provides the signal data to the converter according to the output signal of the second flip-flop circuit.

[0018] According to an embodiment of the present application, the first-in-first-out circuit is coupled to the output of the second flip-flop circuit via a delay circuit that delays the output signal of the second flip-flop circuit, for example, according to the converted data clock signal. Further, the selector includes a multiplexer that selects one of the input signals based on the information about the phase relationship.

[0019] According to an embodiment of the present application, the phase comparator includes a phase-to-digital converter configured to measure a phase difference between the source clock signal and the target clock signal to determine the phase relationship, and the circuit further includes an oscillator, the output signal of which is used as the target clock signal or the circuit is configured to derive the target clock signal from the output signal of the oscillator.

[0020] According to an embodiment of the present application, the circuit is configured to derive the source clock signal and the target clock signal from a common reference signal such that the frequencies of the source clock signal and the target clock signal have a predetermined relationship (e.g., are regulated to have a predetermined relationship), and such that there is no phase lock between the phases of the source clock signal and the target clock signal (e.g., the phases of the synchronized clock signal and the converted clock signal are free to float relative to each other). Further, the converter is a digital-to-analog converter or an analog-to-digital converter.

[0021] A second aspect of the present application is a test apparatus for testing a device under test, the test apparatus including a circuit according to the present application. According to an embodiment of the present application, the test apparatus is configured to execute a test flow using a plurality of channel modules that provide signals to the device under test and evaluate signals received from the device under test, for example, in synchronization with a source clock signal, for example, to start a test flow.

[0022] According to embodiments of the present application, the testing apparatus is configured to provide an analog signal obtained using a converter to the device under test based on a signal value provided to the device under test by the apparatus, e.g., thereby stimulating the device under test, and / or the apparatus is configured to obtain digital data, e.g., provided by a data source (i.e., a digital signal processor), based on a digitized device under test signal obtained using fractional delay filtering from the digital circuit, and evaluate the digital data, e.g., to characterize the device under test.

[0023] According to a third aspect of the present application, there is provided a method for communicating data from one clock domain to another clock domain, the method comprising: receiving a source clock signal from or used by an apparatus and a target clock signal used by a digital circuit; determining a phase relationship between the source clock signal and the target clock signal; receiving a data signal from the device and providing a synchronized data signal based thereon; and switching between providing the synchronized data signal based on sampling the data signal in response to a rising edge of the target clock signal and providing the synchronized data signal based on sampling the data signal in response to a falling edge of the target clock signal based on the determined phase relationship between the source clock signal and the target clock signal, wherein the frequency relationship between the source clock signal and the target clock signal is locked to a predetermined value.

[0024] According to a fourth aspect of the present application, there is provided a computer program, which is arranged, when run on a computer or microcontroller, to cause the computer program to carry out the above-mentioned method. [Brief explanation of the drawings]

[0025] Hereinafter, embodiments of the present application will be described in more detail with reference to the drawings. [Figure 1] FIG. 1 shows a schematic block diagram of a circuit for transferring data from one clock domain to another according to a first embodiment of the present application. [Figure 2] FIG. 2 shows a schematic timing diagram of the phase comparator according to the first embodiment of the present application. [Figure 3] FIG. 3 shows a schematic block diagram of a phase comparator according to FIG. 2 according to the concept of the present invention. [Figure 4] FIG. 4 shows a block diagram of a circuit for transferring data from one clock domain to another according to a second embodiment of the present invention. [Figure 5] FIG. 5 shows a schematic block diagram illustrating a test apparatus for testing a device under test according to a third embodiment of the present invention. [Figure 6] FIG. 6 shows a schematic timing diagram to explain the normal resynchronization process when there is no ambiguity. [Figure 7] FIG. 7 shows a schematic timing diagram according to the third embodiment of the present invention. [Figure 8] FIG. 8 shows a schematic diagram illustrating the operation of processing blocks that may be implemented in one embodiment of the present application. [Figure 9] FIG. 9 shows a schematic timing chart of the first operation example shown in the schematic diagram of FIG. [Figure 10] FIG. 10 shows a schematic timing chart of the second operation example shown in the schematic diagram of FIG. [Figure 11] FIG. 11 shows a schematic timing chart of the operation example 3 shown in the schematic diagram of FIG. [Figure 12] FIG. 12 shows a schematic diagram illustrating the operating range for all three cases shown in the schematic diagram of FIG. [Figure 13] FIG. 13 shows a flowchart illustrating steps in a method for communicating data from one clock domain to another according to a fourth embodiment of the present inventive concept. [Figure 14]FIG. 14 shows a schematic block diagram of a circuit for transferring data from one clock domain to another according to an alternative embodiment of the present invention. [Figure 15] FIG. 15 shows a schematic block diagram and a schematic timing chart according to an example of the prior art. [Figure 16] FIG. 16 shows a schematic block diagram according to a prior art example for the avoidance of ambiguity. [Figure 17] FIG. 17 shows a schematic timing diagram according to the prior art. DETAILED DESCRIPTION OF THE INVENTION

[0026] The following description sets forth specific details of particular embodiments, procedures, techniques, etc., for purposes of explanation and not limitation. Those skilled in the art will understand that other embodiments may be employed apart from these specific details. For example, the following description is facilitated by non-limiting, exemplary applications, but the techniques may be employed in any type of converter. In some instances, detailed descriptions of well-known methods, interfaces, circuits, and devices are omitted so as not to obscure the description with unnecessary detail.

[0027] In the following description, identical or similar elements having identical or equivalent functions are designated with identical or equivalent reference numerals.

[0028] 1 is a schematic block diagram of a circuit for transmitting data from one clock domain to another according to a first embodiment of the present invention. The circuit 100 includes a digital circuit 4, a phase comparator (PDC) 6, and a data signal synchronization circuit 8.

[0029] The digital circuit 4, i.e., another clock domain, is coupled to the PDC 6 and provides a target clock signal to the PDC 6. Furthermore, the digital circuit 4 is coupled to a data signal synchronization circuit 8 and receives a synchronous data signal. That is, the digital circuit 4 generates a data signal whose transitions are synchronized with the source clock signal. No.The digital circuit may be a converter, i.e., a digital-to-analog converter or an analog-to-digital converter.

[0030] The PDC 6 is coupled to the digital circuit 4 to receive a target clock signal, e.g., a converter clock signal if the digital circuit 4 is a converter, and a source clock signal, e.g., a synchronized clock signal, which is a clock signal for indicating the output timing of data based on input data values ​​associated with sample times on a time grid equally spaced in time from one clock domain. The PDC 6 is configured to perform a phase comparison between the source clock signal (e.g., the synchronized clock signal) and the target clock signal (e.g., the converter clock signal) by comparing the timing of rising or falling edges between the signals. That is, the circuit 100 is configured to select between a first mode and a second mode based on information regarding the phase relationship between the synchronized clock signal and the converter clock signal. In the first mode, an enable signal that triggers digital-to-analog data conversion, which is time-synchronized with the synchronized clock signal, is sampled at a first edge-type edge, e.g., a falling edge, of the converter clock signal to obtain an intermediate signal, and the intermediate signal is sampled at a second edge-type edge, e.g., a rising edge, of the converter clock signal to obtain an enable signal time-synchronized with the converter clock signal. In a second mode, the enable signal, which triggers the conversion of data between digital and analog, synchronized in time with the synchronous clock signal, is sampled on a second edge type edge of the converter clock signal to obtain an enable signal synchronized in time with the converter clock.

[0031] As described above, the PDC 6 detects, for example, the phase difference between the synchronized clock signal and the converter clock signal, and further includes a phase-to-digital converter configured to measure the phase difference between the synchronized clock signal and the converter clock signal to determine the phase relationship.

[0032] The data signal synchronization circuit 8 is coupled to the PDC 6 to receive information regarding the phase relationship, such as a phase difference between the synchronized clock signal and the target clock signal, and is configured to receive a data signal provided synchronously with a source clock signal whose transitions are synchronized with the source clock signal, and to provide a data signal whose transitions are synchronized with the target clock signal based thereon. Further, the data signal synchronization circuit 8 is configured to switch between providing a synchronized data signal based on sampling the data signal in response to a rising edge of the target clock signal and providing a synchronized data signal based on sampling the data signal in response to a falling edge of the target clock signal, based on the determined phase relationship between the source clock signal and the target clock signal.

[0033] Figure 2 shows a schematic timing diagram of the PDC 6, and Figure 3 shows a schematic block diagram of the PDC 6. As shown in Figures 2 and 3, the PDC 6 is provided with a reference clock signal REFCLK / REF_CLK and a measurement clock signal MEASCLK / MEAS_CLK. The PDC 6 then generates a delay from the rising edge of REF_CLK, i.e., the rising edge of the reference clock signal, to the rising edge of MEAS_CLK, i.e., the rising edge of the measurement clock signal. As mentioned above, the PDC 6 determines the phase difference between MEASCLK and REFCLK. This phase difference can be calculated as phase = delay / period. The delay time is the absolute time difference between the two clock edges. Therefore, if the fractional function of a digital signal processor (DSP) is used, the PDC 6 must be accurate. The PDC's accuracy is not necessarily high enough to simply determine which clock edge to use to capture the data signal.

[0034] According to a first embodiment of the present invention, the phase difference between one clock domain, e.g., a device configured to provide a data signal, i.e., a processor, memory, or loopback interface, and another clock domain, e.g., the digital circuit 4, is measured by the PDC 6. Furthermore, the data signal synchronization circuit 8 can switch between providing a synchronized data signal based on the rising edge of the target signal and based on the falling edge of the target signal based on the determined phase difference. This makes it possible to avoid cycle slips due to phase ambiguity and to transmit the data signal correctly and with accurate timing.

[0035] Furthermore, the PDC6 measurement can be completed in a short time, such as 1 to 10 microseconds. In contrast, the PLL method in the prior art requires a longer wait, such as 1 millisecond, for the PLL to settle. Therefore, the circuit 100 can perform the measurement at a higher speed.

[0036] 4 is a block diagram of a circuit for transmitting data from one clock domain to another according to a second embodiment of the present invention. The difference from the first embodiment is the device 2, i.e., the circuit 200 according to the second embodiment further includes a device 2 configured to provide or use a source clock signal. Accordingly, the device 2 is coupled to the PDC 6 to provide the source clock signal, and to the data signal synchronization circuit 8 to provide the data signal. Other configurations of the circuit 200 are similar to those of the circuit 100, and further description will be omitted to avoid unnecessary duplication.

[0037] The circuits 100, 200 may include an oscillator (e.g., a voltage-controlled surface acoustic wave oscillator) whose output signal is used as the converter clock signal, or the circuit is configured to derive the converter clock signal from the oscillator output signal, and the circuit is configured to derive the synchronized clock signal and the converter clock signal from a common reference signal such that the frequencies of the synchronized clock signal and the converter clock signal have a predetermined relationship.

[0038] FIG. 5 is a schematic block diagram of a third embodiment of the present invention. This diagram illustrates a test setup for testing a device under test 5 connected to the output of a digital circuit (DAC) 4 including a circuit according to the present invention. As shown in FIG. 5, a data signal synchronization circuit 8 includes a first flip-flop circuit (FF) 10, a signal selector (e.g., multiplexer 12), a second flip-flop circuit (FF) 14, and a first-in, first-out circuit (FIFO) 16. The FIFO 16 is coupled to a data source, e.g., a digital signal processor, to receive signal data. The FIFO 16 is coupled to the second FF 14 via an additional delay circuit ("Delay N"), which is used to delay the output signal of the FF 14 by a programmable target number of clock signal cycles. The number of clock cycles is selected so that the FIFO's enable signal READ_EN becomes active at precisely the correct time when there is enough data in the FIFO and the device under test is to receive the data via the DAC. The FIFO 16 then provides the signal data to the converter in response to the delay circuit's output signal READ_EN.

[0039] The first FF 10 is coupled to the device 2, e.g., a processor, memory, or loopback interface, to receive a data signal TEST_EN. The TEST_EN is a test signal, e.g., a target clock signal FIFOCLK on a different source clock domain SYNCCLK, provided by the device to align the output timing of the signal data. The FF 10 is configured to sample the data signal at a first sampling phase when the phase relationship indicates that the value of the phase difference between the source clock signal and the target clock signal is within a first predetermined range, e.g., lower than a predetermined value. For example, if the phase difference poses a potential risk of causing metastability, the phase of the sampling of the data signal is inverted to move the sampling time instance away from the clock edge of the source clock signal to obtain the sampled signal. Information about the phase relationship between the source clock domain SYNCCLK and the target clock domain FIFOCLK is measured by a phase-to-digital converter (PDC) 6.

[0040] A signal selector, i.e., multiplexer 12, is coupled to device 2 to receive the data signal TEST_EN and to first FF 10 to receive the sampled signal, and is configured to select one of the received signals based on, for example, a phase relationship and obtain a selection signal EN_SYNC. Multiplexer 12 selects one of the input signals based on information about the phase relationship.

[0041] The second FF 14 is coupled to the multiplexer 12 to receive the selection signal EN_SYNC. Here, the second FF 14 is configured to sample the data signal TEST_EN at a second sampling phase when the phase relationship is within a second predetermined range. The second predetermined range is different from the first predetermined range and typically does not overlap with the first predetermined range. For example, the second predetermined range may indicate that the value of the phase difference between the synchronous clock signal and the converter clock signal is greater than a predetermined value. In this case, the edges of the sampled signal are synchronized with the converter clock signal, i.e., the output timings of the signals are aligned, so there is no need to align the rising edges of the clock signals.

[0042] FIG. 6 is a schematic timing diagram illustrating a normal resynchronization process when there is no ambiguity. As shown in FIG. 6, when a test is started, the source clock signal (SYNCCLK), the data signal, and TEST_EN are synchronized, and the target clock signal (FIFOCLK) and the synchronized data signal (EN_SYNCED) are synchronized. In this example, the rising edge of the source clock signal and the rising edge of the target clock signal are separated. In this example, the multiplexer 12 is switched to bypass the flip-flop 10 and directly use TEST_EN as the source of the selection signal (EN_SYNC). Because the rising edges of the source clock signal and the target clock signal are separated, there is no ambiguity in the capture of the EN_SYNC signal by the flip-flop 14. The digital circuit (converter) 4 can receive the data signal at the correct timing.

[0043] FIG. 7 shows a schematic timing diagram of a third embodiment of the present invention. The difference from FIG. 6 is that the clock edges of the source clock signal (SYNCCLK) and the target clock signal (FIFOCLK) are very close to each other. As shown in FIG. 7, because the beginning of the waveform is determined by the data signal (TEST_EN), it is possible to align the rising edge of the source clock signal (SYNCCLK) with the rising edge of the data signal (TEST_EN), as indicated by reference numeral 30. In this case, the rising edges of the source clock signal and the data signal are very close. In this case, capturing the TEST_EN signal on the rising edge of the target clock signal would violate the setup / hold criteria of the capture flip-flop, creating ambiguity because it would be unclear in which clock cycle of the target clock signal the TEST_EN signal is captured. To overcome this situation, the signal TEST_EN is captured by a first flip-flop 10, which captures data on the rising edge of N_FIFOCLK, which generates the signal EN_SYNC (the same as capturing on the falling edge of FIFOCLK). The second flip-flop 14 then captures EN_SYNC on the rising edge of FIFOCLK to generate the signal EN_SYNCED. The synchronous data signal (EN_SYNCED) always responds to the rising edge of the target clock signal. By switching to a signal captured with the inverted target clock signal N_FIFOCLK, ambiguity, i.e., when sampling the data signal (TEST_EN), can be avoided. Therefore, it is possible to provide the data signal to the digital circuit at the correct timing.

[0044] As described above, the start of the waveform is determined by the TEST_EN signal, which is a data signal, so the timing requirements for the data interface are relatively relaxed.

[0045] Figure 8 is a decision diagram of the operation of a processing block that may be implemented in the embodiment of the present application shown in Figure 14. This block has the function of taking the measured phase values ​​from a PDC (e.g., PDC6), determining which operating case is relevant, and applying edge_select and delay_select accordingly.

[0046] 9 is a schematic timing chart of operation case 1 shown in the schematic diagram of FIG. 14 and the decision diagram of FIG. 8. Operation case 1 shows a case where the signal en_r indicates ambiguity. Operation case 1 has the following criteria: 0≦phase<0.25, edge_select=fall(1), and delay_select=no(0).

[0047] 10 is a schematic timing chart of operation case 2 shown in the schematic diagram of FIG. 14 and the decision diagram of FIG. 8. Operation case 2 shows a case where the signal en_f indicates ambiguity. Operation case 2 has the following criteria: 0.25≦phase<0.75 edge_select=rise(0) delay_select=no(0)

[0048] 11 is a schematic timing diagram of the operating case 3 shown in the schematic diagram of FIG. 14 and the decision diagram of FIG. 8. Operating case 3 is a case where the signal en_r indicates ambiguity, and an additional delay is applied. Operating case 3 also has the following criteria: 0.75≦phase<1 edge_select=fall(1) delay_select=yes(1)

[0049] FIG. 12 is a schematic diagram showing the operating ranges for all three cases shown in the schematic diagram of FIG. 14 and the decision diagram of FIG. 8. As shown in FIG. 12, the rising edge of the synchronization signal fifo_en occurs one and two click cycles after the rising edge of the source signal fifoen_s. Therefore, ambiguity in each of Cases 1 to 3 is effectively avoided.

[0050] FIG. 13 is a flow chart illustrating the steps of a method for transferring data from one clock domain to another according to a fourth embodiment of the present invention.

[0051] First, a source clock signal and a target clock signal to be used by the digital circuit are received (S10). That is, a phase comparator, for example, the PDC 6 shown in FIG. 1, receives the source clock signal and the target clock signal from the digital circuit, for example, the digital circuit 4 in FIG. 1 or 2. The synchronized clock may be provided from a processor, a memory, or a loopback interface.

[0052] Next, the phase relationship between the source clock signal and the target clock signal is determined (S12), and a data signal is received from the device (S14), i.e., a data signal whose transition is synchronized with the source clock signal is received in a data signal synchronization circuit, for example, the data signal synchronization circuit 8 of FIG.

[0053] Then, based on the determined phase relationship between the source clock signal and the target clock signal, the circuit switches between providing a synchronous data signal (e.g., EN_SYNCED) based on sampling of the data signal (e.g., TEST_EN) in response to the rising edge of the target clock signal (e.g., FIFOCLK) and providing a synchronous data signal (EN_SYNCED) based on sampling of the data signal (TEST_EN) in response to the falling edge of the target clock signal (FIFOCLK) (S16). That is, the data signal synchronization circuit selects a sampling type, for example, whether to sample on the rising edge or the falling edge as shown in FIG. 7. The frequency relationship between the source clock signal and the target clock signal is locked at a predetermined value. Then, a synchronous data signal based on the selected sampling type, for example, a synchronous data signal (e.g., EN_SYNCED) having the selected sampling type, is provided to the digital circuit 4 via the FIFO 16 (S18).

[0054] According to a fourth aspect of the present application, there is provided a computer program configured to perform the above-mentioned methods when the computer program is run on a computer or microcontroller such that the above-mentioned methods are performed by the computer program.

[0055] FIG. 14 is a schematic diagram of a variation of the disclosed embodiment. As described above, embodiments of the present invention solve the ambiguity problem by using a PDC to measure the phase difference between both clock domains and by using a specialized receiver circuit that can capture the TEST_EN signal on either the rising or falling edge of the receive clock. Control logic determines which edge is appropriate. This avoids the two-clock cycle ambiguity for starting the test by accurately determining which clock is capturing the signal, as shown in FIG. 14.

[0056] While some aspects have been described in the context of an apparatus, it will be apparent that these aspects also represent a description of a corresponding method, with a block or apparatus corresponding to a method step or feature of a method step. Similarly, aspects described in the context of a method step also represent a description of a corresponding block or item or feature of a corresponding apparatus. Some or all of the method steps may be performed by (or using) a hardware apparatus, such as, for example, a microprocessor, a programmable computer, or an electronic circuit. In some embodiments, one or more of the most important method steps may be performed by such an apparatus.

[0057] The data stream of the present invention can be stored on a digital storage medium and can be transmitted over a transmission medium, such as the Internet, including wireless and wired transmission media.

[0058] Depending on specific implementation requirements, embodiments of the present application can be implemented in hardware or software. Implementation can be done using a digital storage medium, such as a floppy disk, DVD, Blu-Ray, CD, ROM, PROM, EPROM, EEPROM, or FLASH memory, having electronically readable control signals stored thereon and cooperating (or capable of cooperating) with a programmable computer system to perform the respective methods. Thus, the digital storage medium can be computer-readable.

[0059] Some embodiments of the present invention comprise a data carrier having an electronically readable control signal, the data carrier being capable of cooperating with a programmable computer system such that one of the methods described herein is performed.

[0060] Generally, embodiments of the present application can be implemented as a computer program product having program code operable to perform one of the methods when the computer program product is run on a computer. The program code may for example be stored on a machine-readable carrier.

[0061] Other embodiments comprise the computer program for performing one of the methods described herein, stored on a machine readable carrier.

[0062] In other words, an embodiment of the inventive method is, therefore, a computer program having a program code for performing one of the methods described herein, when the computer program runs on a computer.

[0063] A further embodiment of the inventive method is therefore a data carrier (or digital storage medium, or computer-readable medium) comprising recorded thereon a computer program for performing one of the methods described herein. The data carrier, digital storage medium, or recording medium is typically tangible and / or non-transitory.

[0064] A further embodiment of the inventive method is, therefore, a data stream or a sequence of signals representing the computer program for performing one of the methods described herein, The data stream or sequence of signals may for example be adapted to be transmitted via a data communication connection, for example the Internet.

[0065] A further embodiment comprises a processing means, for example a computer, or a programmable logic device, configured to or adapted to perform one of the methods described herein.

[0066] A further embodiment comprises a computer having installed thereon the computer program for performing one of the methods described herein.

[0067] Further embodiments according to the invention comprise an apparatus or system configured to transfer (e.g. electronically or optically) a computer program for performing one of the methods described herein to a receiver. The receiver may be, for example, a computer, a mobile device, a memory device, etc. The apparatus or system may, for example, comprise a file server for transferring the computer program to the receiver.

[0068] In some embodiments, a programmable logic device (e.g., a field programmable gate array) may be used to perform some or all of the functions of the methods described herein. In some embodiments, a field programmable gate array may cooperate with a microprocessor to perform one of the methods described herein. In general, the methods are preferably performed by any hardware apparatus.

[0069] The apparatus described herein may be implemented using a hardware apparatus, a computer, or a combination of a hardware apparatus and a computer.

[0070] The devices described herein, or any components of the devices described herein, may be implemented at least in part in hardware and / or software.

[0071] The above-described embodiments are merely illustrative of the principles of the present invention. It is understood that modifications and variations of the arrangements and detailed descriptions set forth herein will be apparent to those skilled in the art. It is therefore intended to be limited only by the scope of the claims and not by the specific details presented in the description and explanation of the embodiments herein.

Claims

1. 1. A circuit for transmitting data from one clock domain to another clock domain, comprising: a digital circuit in the other clock domain configured to receive a data signal whose transitions are synchronized with a source clock signal by sampling the data signal in synchronization with a target clock signal, the data signal being based on the data signal whose transitions are synchronized with a source clock signal; a phase comparator configured to determine a phase difference between the source clock signal and the target clock signal; a data signal synchronization circuit configured to receive a data signal from the one clock domain whose transitions are synchronized with the source clock signal, and to provide a synchronized data signal to the digital circuit whose transitions are synchronized with the target clock signal based thereon; the data signal synchronization circuit is configured to switch between providing the synchronized data signal based on sampling the data signal in response to a rising edge of the target clock signal and providing the synchronized data signal based on sampling the data signal in response to a falling edge of the target clock signal based on the determined phase difference between the source clock signal and the target clock signal; the data signal synchronization circuit provides the synchronized data signal based on sampling of the data signal in response to a rising edge of the target clock signal when the determined phase difference is greater than a predetermined value, and provides the synchronized data signal based on sampling of the data signal in response to a falling edge of the target clock signal when the determined phase difference is equal to or less than the predetermined value. circuit.

2. 1. A circuit for transmitting data from one clock domain to another clock domain, comprising: a digital circuit that is the other clock domain; a phase comparator configured to determine a phase difference between a source clock signal and a target clock signal from the digital circuit; a data signal synchronization circuit configured to receive a data signal from the one clock domain whose transitions are synchronized with the source clock signal, receive signal data from the one clock domain, and provide signal data synchronized with the target clock signal to the digital circuit based on the data signal and the signal data from the one clock domain; Equipped with the data signal synchronization circuit is configured to switch between generating a synchronized data signal whose transition is synchronized with the target clock signal based on sampling of the data signal in response to a rising edge of the target clock signal and generating the synchronized data signal based on sampling of the data signal in response to a falling edge of the target clock signal, based on the determined phase difference between the source clock signal and the target clock signal; The data signal synchronization circuit a first flip-flop circuit configured to receive the data signal, the first flip-flop circuit configured to sample the data signal at a first sampling phase to obtain a sampled signal; a signal selector configured to receive the data signal and coupled to the first flip-flop circuit to receive the sampled signal, the signal selector configured to select one of the received data signal and the sampled signal to obtain a selection signal; a second flip-flop circuit coupled to the signal selector to receive the selection signal, the second flip-flop circuit configured to sample the selection signal at a second sampling phase to generate the synchronized data signal; a first-in-first-out circuit that receives signal data from the one clock domain and provides signal data synchronized with the target clock signal to the digital circuit in response to an enable signal that delays the synchronous data signal of the second flip-flop circuit by N cycles (N is an integer equal to or greater than 1); the first sampling phase is the phase of an inverted signal of the target clock signal; the second sampling phase is a phase of the target clock signal; the signal selector selects the data signal if the determined phase difference is greater than a predetermined value, and selects the signal sampled at the first sampling phase if the determined phase difference is less than or equal to the predetermined value. circuit.

3. the source clock signal is provided by or used by the device; the apparatus is coupled to the phase comparator for providing the source clock signal, and is coupled to the data signal synchronization circuit for providing the data signal; the digital circuit is a converter configured to convert data between analog and digital; the data signal is an enable signal that triggers the analog to digital conversion of a signal; The circuit of claim 1 .

4. the first-in-first-out circuit is coupled to a data source to receive the signal data, and is coupled to the second flip-flop circuit to receive the output signal of the second flip-flop circuit or a delayed version of the output signal of the second flip-flop circuit; 3. The circuit of claim 2.

5. the first-in-first-out circuit is coupled to the output of the second flip-flop circuit via a delay circuit that delays the output signal of the second flip-flop circuit; 5. The circuit of claim 4.

6. the signal selector includes a multiplexer; the multiplexer selecting one of the input signals based on information about the determined phase difference.

6. A circuit according to claim 2, 4 or 5.

7. the phase comparator includes a phase-to-digital converter; the phase-to-digital converter is configured to measure a phase difference between the source clock signal and the target clock signal to determine a phase difference between the source clock signal and the target clock signal.

7. A circuit according to any one of claims 1 to 6.

8. the circuit comprises an oscillator; the output signal of the oscillator is used as the target clock signal, or the circuit is configured to derive the target clock signal from the output signal of the oscillator. A circuit according to any one of claims 1 to 7.

9. the circuitry is configured to derive the source clock signal and the target clock signal from a common reference signal such that the frequencies of the source clock signal and the target clock signal have a predetermined relationship and are phase asynchronous between the source clock signal and the target clock signal. A circuit according to any one of claims 1 to 8.

10. the converter is a digital-to-analog converter; A circuit as claimed in claim 3 or any one of claims 7 to 9 which derives from claim 3.

11. the converter is an analog-to-digital converter; A circuit as claimed in claim 3 or any one of claims 7 to 9 which derives from claim 3.

12. A test apparatus for testing a device under test, comprising:

12. A circuit comprising: a circuit according to any one of claims 1 to 11; Test equipment.

13. the test apparatus is configured to execute a test flow in synchronization with the source clock signal; 13. The test device of claim 12.

14. the test apparatus is configured to provide an analog signal obtained using a converter based on a signal value provided by the device under test; and / or the processor of the test apparatus is configured to obtain digital data provided based on the digitized device under test signal obtained from the digital circuit using fractional delay filtering, and to evaluate the digital data.

14. The test device of claim 13.

15. 1. A method of transferring data from one clock domain to another clock domain, comprising: a phase comparator receiving a source clock signal from the one clock domain and a target clock signal from the digital circuit for use by the digital circuit in the other clock domain; the phase comparator determining a phase difference between the source clock signal and the target clock signal; a data signal synchronization circuit receiving a data signal from the one clock domain and, based thereon, providing a data signal synchronized with the target clock signal to the digital circuit; the data signal synchronization circuit switches between providing a data signal synchronized with the target clock signal based on sampling of the data signal in response to a rising edge of the target clock signal and providing a data signal synchronized with the target clock signal based on sampling of the data signal in response to a falling edge of the target clock signal, based on the determined phase difference; the data signal synchronization circuit provides a synchronized data signal corresponding to a rising edge of the target clock signal when the determined phase difference is within a predetermined phase range, and provides a synchronized data signal corresponding to a falling edge of the target clock signal when the determined phase difference is smaller than a lower limit of the phase range or larger than an upper limit of the phase range. method.

16. 1. A method of transferring data from one clock domain to another clock domain, comprising: a phase comparator receiving a source clock signal from the one clock domain and a target clock signal from the digital circuit for use by the digital circuit in the other clock domain; the phase comparator determining a phase difference between the source clock signal and the target clock signal; a data signal synchronization circuit receiving a data signal from the one clock domain whose transitions are synchronized with the source clock signal, receiving signal data from the one clock domain, and providing signal data synchronized with the target clock signal to the digital circuit based on the data signal and the signal data from the one clock domain; the data signal synchronization circuit switches between generating a data signal synchronized with the target clock signal based on sampling of the data signal in response to a rising edge of the target clock signal and generating a data signal synchronized with the target clock signal based on sampling of the data signal in response to a falling edge of the target clock signal, based on the determined phase difference; The data signal synchronization circuit a first flip-flop circuit configured to receive the data signal, the first flip-flop circuit configured to sample the data signal at a first sampling phase to obtain a sampled signal; a signal selector configured to receive the data signal and coupled to the first flip-flop circuit to receive the sampled signal, the signal selector configured to select one of the received data signal and the signal sampled at the first sampling phase to obtain a selection signal; a second flip-flop circuit coupled to the signal selector to receive the select signal, the second flip-flop circuit configured to sample the select signal at a second sampling phase to generate a data signal synchronized with the target clock signal; a first-in-first-out circuit that receives signal data from the one clock domain and provides signal data synchronized with the target clock signal in response to an enable signal that delays a data signal synchronized with the target clock signal of the second flip-flop circuit by N cycles (N is an integer equal to or greater than 1); the first sampling phase is the phase of an inverted signal of the target clock signal; the second sampling phase is a phase of the target clock signal; the signal selector selects the data signal if the determined phase difference is greater than a predetermined value, and selects the signal sampled at the first sampling phase if the determined phase difference is less than or equal to the predetermined value. method.

17. A computer program for causing a computer to carry out the method according to claim 15 or 16.

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