Display panel and display device

Abstract

To provide a display panel that can adjust a ratio of a plurality of areas whose viewing angles can be individually controlled in a display area.SOLUTION: A display panel includes a plurality of mode control line sets individually connected with a plurality of pixel blocks, and the plurality of mode control line sets includes a first mode control line supplying a first mode control signal and a second mode control line supplying a second mode control signal. A subpixel includes a drive transistor connected with a first power supply line, a first light-emitting device connected with the drive transistor via a first mode control transistor controlled according to the first mode control signal, a second light-emitting device connected with the drive transistor via a second mode control transistor controlled according to the second mode control signal, a first lens arranged on the first light-emitting device, and a second lens arranged on the second light-emitting device. A first lens area and a second lens area can be controlled to have different viewing angles in a first direction.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present specification relates to a display panel and a display device capable of controlling a viewing angle. [Background technology]

[0002] 2. Description of the Related Art Electronic devices in various fields include display devices for displaying images. For example, a car may have multiple display devices to provide desired information and content to the driver and passengers.

[0003] 2. Description of the Related Art Among the display devices mounted on automobiles, display devices arranged in the center of the dashboard are becoming larger.

[0004] The display device may include a first area in a wide viewing angle mode for the driver and front passenger, and a second area that is switchable between the wide viewing angle mode and the narrow viewing angle mode.

[0005] This display device requires a method that allows the ratio of the first and second areas to be freely adjusted according to the user's requirements and content.

[0006] The content of the background art described above is technical information that the inventors of this specification held in order to derive the examples of this specification or that they acquired in the process of deriving the examples of this specification, and is not necessarily publicly known art that was made public to the general public prior to the filing of this specification. Summary of the Invention [Problem to be solved by the invention]

[0007] The present specification provides a display panel and a display device capable of adjusting the ratio of multiple regions in the display area, each of which has its own viewing angle controllable independently.

[0008] The problems to be solved in the various embodiments of this specification are not limited to those mentioned above, and other problems not mentioned will be clearly understood by a person having ordinary skill in the art to which the technical idea of ​​this specification belongs from the following description. [Means for solving the problem]

[0009] A display panel according to some embodiments includes a plurality of pixel blocks, each including a plurality of subpixels, arranged in a display area, a bezel area outside the display area, and a plurality of mode control line sets individually connecting to the plurality of pixel blocks, each of the plurality of mode control line sets including a first mode control line for supplying a first mode control signal and a second mode control line for supplying a second mode control signal. Each of the plurality of subpixels includes a drive transistor connected to a first power line, a first light-emitting element connected to the drive transistor via a first mode control transistor controlled by the first mode control signal, a second light-emitting element connected to the drive transistor via a second mode control transistor controlled by a second mode control signal, a first lens disposed over the first light-emitting element, and a second lens disposed over the second light-emitting element, and the first lens area and the second lens area can differently control a viewing angle in a first direction.

[0010] A display panel apparatus according to some embodiments includes the display panel and a data driver arranged in the bezel region and driving data lines arranged in the display region, wherein the data driver can individually supply a first mode control signal and a second mode control signal to each of a plurality of mode control line sets.

[0011] Specific details of various embodiments other than the above-mentioned means for solving the problems are included in the following description and drawings. [Effects of the Invention]

[0012] In some embodiments, the display panel and the display device selectively drive the first light-emitting element corresponding to the first lens region and the second light-emitting element corresponding to the second lens region in each subpixel using the first and second mode control signals, thereby controlling the viewing angle of each of multiple regions in the display region to a wide viewing angle or a narrow viewing angle, and reducing power consumption.

[0013] The display panel and display device according to some embodiments can control a plurality of regions to have a wide viewing angle or a narrow viewing angle separately using first and second mode control signals, so that not only the positions of the wide viewing angle regions and the narrow viewing angle regions but also the ratio (area) of the wide viewing angle regions and the narrow viewing angle regions can be freely adjusted in the first and second directions.

[0014] The display panel and display device according to some embodiments can improve user convenience and satisfaction by freely adjusting not only the positions of the wide viewing angle area and the narrow viewing angle area, but also the ratio (area) of the wide viewing angle area and the narrow viewing angle area in the first and second directions according to the user's requirements or content.

[0015] The above-mentioned problems to be solved, means for solving the problems, and effects do not specify the essential features of the claims, and therefore the scope of the claims is not limited by the matters described in the contents of the invention. [Brief explanation of the drawings]

[0016] The drawings attached below are intended to aid in understanding the embodiments of the present specification, and together with the detailed description, provide examples. However, the technical features of the embodiments are not limited to the specific drawings, and the features disclosed in each drawing can be combined with each other to form new embodiments. [Figure 1] 1 is a diagram illustrating a schematic configuration of a display device according to an embodiment; [Figure 2]1 is a diagram illustrating a configuration in which a display device according to an embodiment is applied to a vehicle; [Figure 3A] FIG. 3A illustrates various examples of changes in the ratio of the first and second regions in a display panel according to an embodiment. [Figure 3B] FIG. 3B illustrates various examples of changes in the ratio of the first and second regions in a display panel according to an embodiment. [Figure 3C] FIG. 3C illustrates various examples of changes in the ratio of the first and second regions in a display panel according to an embodiment. [Figure 3D] FIG. 3D illustrates various examples of changes in the ratio of the first and second regions in a display panel according to an embodiment. [Figure 4A] FIG. 4A is a perspective view illustrating first and second lens structures of a display panel according to an embodiment. [Figure 4B] FIG. 4B is a perspective view illustrating first and second lens structures of a display panel according to an embodiment. [Figure 5] FIG. 2 is a plan view illustrating a pixel structure of a display panel according to an embodiment. [Figure 6] FIG. 6 is a cross-sectional view of the first lens region taken along line II' shown in FIG. 5. [Figure 7] FIG. 6 is a cross-sectional view of the second lens region taken along line II-II' shown in FIG. 5. [Figure 8] 1 is an equivalent circuit diagram illustrating a configuration of a subpixel in a display panel according to an embodiment. [Figure 9] 10 is a diagram illustrating a schematic layout structure of first and second mode control lines in a partial region of a display panel according to an embodiment. [Figure 10] 10 is a diagram illustrating a schematic layout structure of the bezel region shown in FIG. 9. FIG. [Figure 11] 10 is a diagram illustrating a schematic layout structure of first and second mode control lines in a partial region of a display panel according to an embodiment. [Figure 12]12 is a diagram illustrating a schematic layout structure of the bezel region shown in FIG. 11. FIG. [Figure 13] 12 is a diagram illustrating an example of the layout structure of main signal lines in the first type pixel region shown in FIGS. 9 and 11. FIG. [Figure 14] 12 is a diagram illustrating an example of the layout structure of main signal lines in the second type pixel region shown in FIGS. 9 and 11. FIG. [Figure 15] 12 is a diagram illustrating an example of the layout structure of main signal lines in the third type pixel region shown in FIGS. 9 and 11. FIG. [Figure 16] FIG. 2 is a plan view illustrating a pixel arrangement structure of a display panel according to an embodiment. [Figure 17] 1 is a diagram illustrating an example of an arrangement structure of a plurality of pixel blocks in a display device according to an embodiment; DETAILED DESCRIPTION OF THE INVENTION

[0017] The advantages and features of the present invention, as well as methods for achieving them, will become more apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be embodied in various different forms. These embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully convey the scope of the invention to those skilled in the art. The present invention is defined solely by the claims.

[0018] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for illustrating the embodiments of this specification are illustrative only and do not limit the present specification to the details shown in the drawings. The same reference numerals may refer to the same elements throughout the specification. In addition, if a detailed description of related prior art is deemed to unnecessarily obscure the gist of this specification, the detailed description will be omitted. When terms such as "comprise," "have," and "consist of" are used in this specification, other parts may be added unless "only" is used. When a component is expressed in the singular, the plural is also included unless otherwise explicitly stated.

[0019] When interpreting elements, the error range is interpreted as being included even if there is no separate explicit description of the error range.

[0020] When describing a positional relationship, for example, when the positional relationship of two parts is described using "above," "on top," "below," or "beside," one or more other parts may be located between the two parts, unless the words "immediately" or "directly" are used.

[0021] When describing a temporal relationship, for example, when the temporal precedence relationship is described using "after," "following," "next to," or "before," it can also include cases where the relationship is not consecutive, unless the words "immediately" or "directly" are used.

[0022] Although terms such as "first," "second," and the like are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, a first component referred to below may also be a second component within the technical concept of this specification.

[0023] When describing components in this specification, terms such as first, second, A, B, (a), (b), etc. may be used. Such terms are used to distinguish the component from other components, and do not limit the nature, order, sequence, or number of the components. When a component is described as being "coupled," "coupled," or "connected" to another component, it should be understood that the component can be directly connected or connected to the other component, but that other components may be "intervening" between each component that can be indirectly connected or connected without any specific explicit description.

[0024] "At least one" should be understood to include all combinations of one or more of the associated components. For example, the meaning of "at least one of a first, second, and third component" can include not only the first, second, or third component, but also all combinations of two or more of the first, second, and third components.

[0025] The features of each of the several embodiments of this specification can be partially or wholly combined or combined with each other, and various technical interlocking and driving mechanisms are possible, and each embodiment can be implemented independently of each other or can be implemented together in a linked relationship.

[0026] The present specification will be described with reference to the accompanying drawings and examples as follows: The scales of the components shown in the drawings are different from the actual scales for the convenience of explanation, and are not limited to the scales shown in the drawings.

[0027] FIG. 1 is a block diagram illustrating a schematic configuration of a display device according to an embodiment.

[0028] The display device according to one embodiment may be an electroluminescent display device, including an organic light emitting diode (OLED) display device, a quantum-dot light emitting diode (QLD) display device, or an inorganic light emitting diode (ILD) display device.

[0029] 1, a display device according to an embodiment may include a display panel 100, a gate driver 200 built in the display panel 100, a data driver 300 connected to the display panel 100, a timing controller 400 that controls the gate driver 200 and the data driver 300, a gamma voltage generator 600, and a power management circuit 700. In an embodiment, the display device may further include a level shifter 500 connected between the timing controller 400 and the gate driver 200. In an embodiment, the data driver 300, the timing controller 400, the gamma voltage generator 600, and the level shifter 500 may be integrated into the display driver.

[0030] The display panel 100 may be a rigid display panel or a flexible display panel that can be deformed into a different shape, such as a foldable, bendable, rollable, or stretchable display panel.

[0031] The display panel 100 may include a display area DA for displaying an image, and bezel areas BZ1 to BZ4 that surround the display area DA and are located on the outer periphery of the display area DA.

[0032] The display panel 100 can display an image using a display area (DA) in which a plurality of sub-pixels (SP) are arranged in a matrix form. The pixel matrix arranged in the display area (DA) can include a plurality of row lines and a plurality of column lines each consisting of a plurality of sub-pixels (SP).

[0033] Each subpixel (SP) may be any one of a red subpixel that emits red light, a green subpixel that emits green light, a blue subpixel that emits blue light, and a white subpixel that emits white light. A unit pixel may include at least two subpixels (SP).

[0034] The display panel 100 may have a number of signal lines, including a data line 22, gate lines 12, 16, power supply lines 24, 32, 34, and mode control lines 42, 44, connected to each subpixel (SP).

[0035] The data line 22 can supply a data voltage (Vdata) supplied from the data driver 300 to each sub-pixel (SP).

[0036] Any one of the gate lines 12, 16 can supply a scan signal (SCAN) supplied from the gate driver 200 to each sub-pixel (SP), and the other gate line 16 can supply an emission control signal (EM) supplied from the gate driver 200 to each sub-pixel (SP).

[0037] Of the power supply lines 24, 32, and 34, the initialization voltage line 24 can supply the initialization voltage (Vref) supplied from the power supply management circuit 700 to each subpixel (SP), the first power supply line 32 can supply a high potential power supply voltage (EVDD), and the second power supply line 34 can supply a low potential power supply voltage (EVSS) to each subpixel (SP) via a common electrode (cathode electrode).

[0038] Of the mode control lines 42 and 44, the first mode control line 42 can supply a first mode control signal (SH) supplied from the data driver 300 or a separate mode control unit (not shown) to each sub-pixel (SP), and the second mode control line 44 can supply a second mode control signal (PR) supplied from the data driver 300 or a separate mode control unit to each sub-pixel (SP).

[0039] Each subpixel (SP) can include first and second light-emitting elements, a pixel circuit consisting of multiple transistors that independently drive the first and second light-emitting elements, a first lens region disposed on the first light-emitting element, and a second lens region disposed on the second light-emitting element. The first lens region and the second lens region can control different light emission angles, i.e., viewing angles.

[0040] For example, each subpixel (SP) can drive a first light-emitting element to realize a wide viewing angle mode or a shared mode through a first lens region, and can drive a second light-emitting element to realize a narrow viewing angle mode or a privacy mode that limits the viewing angle to a smaller value than the wide viewing angle mode through a second lens region.

[0041] The display device or display panel 100 can control the viewing angle of each subpixel (SP) by selectively driving the first and second light-emitting elements of each subpixel (SP) using mode control signals (SH, PR). The display device or display panel 100 can divide and drive the display area (DA) into multiple regions that can be controlled to have different viewing angles by selectively driving the first and second light-emitting elements of each subpixel (SP) using mode control signals (SH, PR), and can freely adjust the ratio or area of ​​the multiple regions in the first direction (X) and the second direction (Y). This will be described in detail later.

[0042] For example, one of the plurality of regions in the display area (DA) may operate in a wide viewing angle mode through a first lens region when a first light-emitting element is driven in each subpixel (SP), and may operate in a narrow viewing angle mode through a second lens region when a second light-emitting element is driven. Another of the plurality of regions may operate in a narrow viewing angle mode through a second lens region when a second light-emitting element is driven, and may operate in a wide viewing angle mode through a first lens region when a first light-emitting element is driven. Each of the plurality of regions may be driven in a different viewing angle mode or in the same viewing angle mode.

[0043] The display panel 100 according to an embodiment may further include a touch sensor screen disposed in the display area (DA) to sense a user's touch.

[0044] The display panel 100 according to an embodiment may be a touch display panel incorporating a touch sensor array. For example, the display panel 100 according to an embodiment may include a pixel array including a circuit element layer including a plurality of transistors disposed on a substrate, a light emitting element layer including a plurality of light emitting elements disposed on the circuit element layer, an encapsulation layer disposed on the pixel array to encapsulate the light emitting element layer, a touch sensor array including a plurality of touch electrodes disposed on the encapsulation layer, and a lens array including first and second lenses disposed on the touch sensor array. The display panel 100 according to an embodiment may further include an optical film, an optical clear adhesive (OCA), a cover substrate, a protective film, etc., sequentially disposed on the lens array. The display panel 100 according to an embodiment may further include a color filter array including a color filter and a black matrix disposed between the touch sensor array and the lens array.

[0045] The gate driver 200 may be disposed in at least one of a plurality of bezel regions (BZ1 to BZ2) located on the periphery of the display region (DA). For example, the gate driver 200 may be disposed in one of the first and second bezel regions (BZ1 and BZ2) facing each other across the display region (DA), or on both sides of the first and second bezel regions (BZ1 and BZ2). The gate driver 200 may be disposed as a GIP (Gate In Panel) type, in which transistors are formed in the same process as transistors disposed in the display region (DA).

[0046] The gate driver 200 may include a scan driver 210 that drives at least one gate line 12 out of multiple gate lines 12, 16 connected to the subpixels (SP) of each pixel row line, and a light emitting control driver 220 that drives the other gate line 16.

[0047] The number of gate lines 12, 16 connected to the subpixels (SP) of each pixel row (Row) line, the number of scan drivers 210, and the number of light emission control drivers 220 are not limited to the numbers shown in FIG. 1, and can be changed in various ways depending on the detailed configuration of the pixel circuit that constitutes each subpixel (SP).

[0048] Each of the scan driver 210 and the light emission control driver 220 can operate by receiving a plurality of gate control signals supplied from the timing controller 400 via the level shifter 500. In one embodiment, each of the scan driver 210 and the light emission control driver 220 can receive a plurality of gate control signals from the timing controller 400.

[0049] The level shifter 500 receives a control signal from the timing controller 400 and generates a plurality of gate control signals through level shifting or logic processing, and supplies the signals to the scan driver 210 and the light emission control driver 220 .

[0050] The scan driver 210 can supply at least one scan signal (SCAN) to each of the plurality of pixel row lines using the plurality of gate control signals supplied from the level shifter 500 or the timing controller 400. The scan driver 210 can supply the scan signal (SCAN) to at least one gate line 12 of the plurality of gate lines 12, 16 connected to the subpixels (SP) of each pixel row line.

[0051] The light emission control driver 220 can supply a plurality of light emission control signals to each of a plurality of pixel row lines using a plurality of gate control signals supplied from the level shifter 500 or the timing controller 400. The light emission control driver 220 can supply a light emission control signal (EM) to at least one gate line 16 of a plurality of gate lines 12, 16 connected to the subpixels (SP) of each pixel row line.

[0052] At least one of low temperature polysilicon (LTPS) transistors using LTPS semiconductors and oxide transistors using metal oxide semiconductors can be applied to the transistors arranged in the display area (DA) of the display panel 100 and in the bezel areas (BZ1 to BZ4) including the gate driver 200. The display panel 100 according to one embodiment can be configured so that LTPS transistors and oxide transistors coexist to reduce power consumption.

[0053] The gamma voltage generator 600 may generate a plurality of reference gamma voltages having different voltage levels and supply them to the data driver 300. The gamma voltage generator 600 may generate a plurality of reference gamma voltages corresponding to the gamma characteristics of the display device under the control of the timing controller 400 and supply them to the data driver 300. In one embodiment, the gamma voltage generator 600 may adjust the reference gamma voltage level according to the gamma data supplied from the timing controller 400 and output the reference gamma voltage to the data driver 300.

[0054] The data driver 300 converts digital data supplied together with a data control signal from the timing controller 400 into an analog data signal and supplies each data voltage (Vdata) to each data line 22 of the display panel 100. The data driver 300 can subdivide a plurality of reference gamma voltages supplied from the gamma voltage generator 600 and convert digital data into an analog data voltage using the subdivided gamma voltages.

[0055] The data driver 300 can include at least one data drive IC (Integrated Circuit) that drives a plurality of data lines 22 arranged on the display panel 100. Each data drive IC can be mounted on a respective circuit film and connected to the display panel 100. The circuit film on which the data drive IC is mounted can be bonded and connected to the bezel region (BZ3) of the display panel 100, in which the pad region is arranged, via an anisotropic conductive film (ACF). The circuit film can be a COF (Chip On Film), an FPC (Flexible Printed Circuit), or an FFC (Flexible Flat Cable).

[0056] In one embodiment, the data driver 300 can generate mode control signals (SH, PR) and supply them to mode control lines 42, 44 of the display panel 100. In one embodiment, the mode control signals (SH, PR) can be generated in a mode control unit separate from the data driver 300 and supplied to the display panel 100 via a circuit film on which a data drive IC is mounted.

[0057] The timing controller 400 can control the gate driver 200 and the data driver 300 using timing control signals supplied from the host system and timing setting information stored therein.

[0058] The timing controller 400 according to an embodiment can generate a plurality of gate control signals for controlling the driving timing of the gate driver 200 and supply them to the gate driver 200. The timing controller 400 according to an embodiment can generate a control signal for timing control and supply it to the level shifter 500 so that the level shifter 500 can generate a plurality of gate control signals and supply them to the gate driver 200.

[0059] The timing controller 400 can generate a plurality of data control signals for controlling the driving timing of the data driver 300 and supply them to the data driver 300. The timing controller 400 according to an embodiment can receive input image data and perform various image processes including image quality correction, degradation correction, and brightness correction for reducing power consumption, and can supply the image-processed data to the data driver 300.

[0060] The power management circuit 700 can generate and supply a plurality of driving voltages required for the operation of all circuit components of the display device using an input voltage. The power management circuit 700 can generate a first power supply voltage (EVDD), a second power supply voltage (EVSS), an initialization voltage (Vref), and a reference voltage and supply them to the display panel 100. The power management circuit 700 can generate and supply various driving voltages required for the operation of the gate driver 200, the data driver 300, the timing controller 400, the level shifter 500, and the gamma voltage generator 600.

[0061] Fig. 2 is a diagram illustrating a configuration in which a display device according to an embodiment is applied to an automobile, Figs. 3A to 3D are diagrams illustrating a form in which the ratio of the first and second regions varies in a display panel according to an embodiment, and Figs. 4A and 4B are perspective views showing first and second lens structures of a subpixel according to an embodiment.

[0062] 2 to 3D, a display device 1000 according to an embodiment is disposed in the center of a dashboard of a vehicle and can provide images to both the driver and a passenger in the front seat. The display panel 100 of the display device 1000 may include a first area (DA1) and a second area (DA2), and the ratio or area of ​​the first area (DA1) to the second area (DA2) may be variable in the first and second directions.

[0063] In one embodiment, the first area (DA1) can be represented as a Center Information Display (CID) area or a Share Mode area, and the second area (DA2) can be represented as a Co-driver Display (CDD) area or a Switchable Privacy Mode area.

[0064] Referring to Figures 3A to 3D, each of the subpixel (SP11) in the first region (DA1) and the subpixel (SP21) in the second region (DA2) may include a first light-emitting element (EL1), a second light-emitting element (EL2), a first lens (LZ1) disposed on the first light-emitting element (EL1), and a second lens (LZ2) disposed on the second light-emitting element (EL2).

[0065] In the embodiment, the first lens (LZ1) can be disposed on the light path of the first light-emitting element (EL1), and the second lens (LZ2) can be disposed on the light path of the second light-emitting element (EL2).

[0066] In each of the subpixels (SP11, SP21), the second light-emitting element (EL2) may include a plurality of second light-emitting elements (EL2) or a plurality of second light-emitting regions, and a plurality of second lenses (LZ2) may be individually disposed in the light paths of the plurality of second light-emitting elements (EL2) or the plurality of second light-emitting regions. In each of the subpixels (SP11, SP21), the plurality of second light-emitting elements (EL2) or the plurality of second light-emitting regions may be connected in parallel.

[0067] In each of the sub-pixels (SP11, SP21), the area where the first lens (LZ1) is arranged can be expressed as a first lens area, and the area where multiple second lenses (LZ2) are arranged can be expressed as a second lens area.

[0068] Referring to Figure 4B, the first lens (LZ1) may be a half-cylindrical lens elongated in the first direction (X), and referring to Figure 4A, the second lens (LZ2) may be a half-spherical lens.

[0069] 4A and 4B, the first direction (X) can be represented as the left-right direction, the lateral direction, the horizontal direction, or the X-axis direction. The second direction (Y) can be represented as the up-down direction, the longitudinal direction, the vertical direction, or the Y-axis direction. The third direction (Z) can be represented as the front-rear direction, the thickness direction of the display panel 100, or the Z-axis direction.

[0070] The first lens (LZ1) and the second lens (LZ2) can control (limit) the viewing angle in the left-right direction (X) differently, and can control (limit) the viewing angle in the up-down direction (Y) in the same way.

[0071] For example, the first lens (LZ1) can control the viewing angle to a wide viewing angle without restricting the traveling path of light emitted from the first light-emitting element (EL1) to within a specific angle in the left-right direction (X), and the second lens (LZ2) can control the viewing angle to a narrow viewing angle by restricting the traveling path of light emitted from the second light-emitting element (EL2) to within a specific angle in the left-right direction (X).

[0072] Both the first lens (LZ1) and the second lens (LZ2) can limit the light propagation path in the vertical direction (Y) to within a specific angle, thereby controlling the viewing angle to a narrow viewing angle. As a result, in one embodiment, when the display device 1000 is applied to an automobile as shown in Fig. 2, it is possible to prevent images displayed on the first and second areas (DA1, DA2) of the display panel 100 from being reflected by the windshield of the automobile and obstructing the driver's view.

[0073] When the first light-emitting element (EL1) of each of the subpixels (SP11, SP21) is driven, the corresponding subpixel can operate in a wide viewing angle mode that does not limit the viewing angle in the left-right direction (X). When the second light-emitting element (EL2) of each of the subpixels (SP11, SP21) is driven, the corresponding subpixel can operate in a narrow viewing angle mode that limits the viewing angle in the left-right direction (X). The wide viewing angle mode can be represented as a first mode, and the narrow viewing angle mode can be represented as a second mode.

[0074] In each of the subpixels (SP11, SP21), by switching between driving the first light-emitting element (EL1) and driving the second light-emitting element (EL2) based on the mode control signals (SH, PR, Figure 1), each of the subpixels (SP11, SP21) can switch between wide viewing angle driving and narrow viewing angle driving.

[0075] 3A to 3D, the display device 1000 according to one embodiment can independently control the viewing angles of the first region (DA1) and the second region (DA2) by selectively driving the first and second light-emitting elements (EL1, EL2) in each subpixel (SP11, SP21) using mode control signals (SH, PR, FIG. 1), and can freely adjust the ratio or area of ​​the first region (DA1) and the second region (DA2) in the left-right direction (X) and the up-down direction (Y) in the display panel 100.

[0076] For example, the first area (DA1) of the display panel 100 can provide the driver and passenger in the front seat with an image having a wide viewing angle in the left and right directions by driving the first light-emitting element (EL1) corresponding to the first lens (LZ1) in each subpixel (SP11).

[0077] The second area (DA2) of the display panel 100 can provide the passenger in the front seat with an image having a narrow viewing angle in the left and right directions so as not to interfere with the driver's driving by driving the second light-emitting element (EL2) corresponding to the second lens (LZ2) in each subpixel (SP21).

[0078] In one embodiment, when the driver is not driving, the first area (DA1) and the second area (DA2) of the display panel 100 can provide the driver and passengers with an image having a wide viewing angle in the left and right directions by driving the first light-emitting element (EL1) corresponding to the first lens (LZ1) in each of the sub-pixels (SP11, SP21) according to the user's selection.

[0079] The display device 1000 according to an embodiment is not limited to a display device for an automobile, but can be applied to various display devices such as a display for a mobile device, a display for an IT device, and a display for a TV.

[0080] FIG. 5 is a plan view illustrating a pixel structure of a display panel according to one embodiment, FIG. 6 is a cross-sectional view of a first lens region taken along line II' in FIG. 5, and FIG. 7 is a cross-sectional view of a second lens region taken along line II-II' in FIG. 5.

[0081] 5, a pixel area (PA) or pixel according to one embodiment may include a blue (hereinafter, B) subpixel area (BPA) that emits blue light, a red (hereinafter, R) subpixel area (RPA) that emits red light, and a green (hereinafter, G) subpixel area (GPA) that emits green light. The R, G, and B subpixel areas (RPA, GPA, BPA) may be referred to as a first type subpixel (first color subpixel), a second type subpixel (second color subpixel), and a third type subpixel (third color subpixel), respectively.

[0082] The B subpixel area (BPA) may include a first lens area (BWE) including a first light-emitting area (BE1) of the first light-emitting element (EL1) and a first lens (LZ1) superimposed on the first light-emitting area (BE1), and a second lens area (BNE) including a second light-emitting area (BE2) of the second light-emitting element (EL2) and a second lens (LZ2) superimposed on the second light-emitting area (BE2).

[0083] The R subpixel area (RPA) may include a first lens area (RWE) including a first light-emitting area (RE1) of the first light-emitting element (EL1) and a first lens (LZ1) superimposed on the first light-emitting area (RE1), and a second lens area (RNE) including a second light-emitting area (RE2) of the second light-emitting element (EL2) and a second lens (LZ2) superimposed on the second light-emitting area (RE2).

[0084] The G subpixel area (GPA) may include a first lens area (GWE) including a first light-emitting area (GE1) of the first light-emitting element (EL1) and a first lens (LZ1) superimposed on the first light-emitting area (GE1), and a second lens area (GNE) including a second light-emitting area (GE2) of the second light-emitting element (EL2) and a second lens (LZ2) superimposed on the second light-emitting area (GE2).

[0085] As described in Figures 4A and 4B, the first lens (LZ1) and the second lens (LZ2) can be controlled to have different viewing angles in the left-right direction (X) and the same viewing angle in the up-down direction (Y).

[0086] Each of the first lens regions (BWE, RWE, GWE) in the pixel region (PA) may include one first light-emitting region (BE1, RE1, GE1) and one first lens (LZ1). Each of the second lens regions (BNE, RNE, GNE) in the pixel region (PA) may include multiple second light-emitting regions (BE2, RE2, GE2) and multiple second lenses (LZ2). The size of the first lens LZ1 in the first lens region in each subpixel region may be different, and the number of second lenses LZ2 in the second lens region in each subpixel region may be different.

[0087] Each of the first light-emitting regions (BE1, RE1, GE1) included in the first lens region (BWE, RWE, GWE) of each pixel region (PA) may have the same or similar shape as the bottom surface of the first lens (LZ1). The size of the first lens (LZ1) is set to be larger than the size of each of the first light-emitting regions (BE1, RE1, GE1). For example, the first lens LZ1 may have a bottom surface wider than the bottom surfaces of each of the first light-emitting regions (BE1, RE1, GE1), thereby improving the luminous efficiency of light generated in each of the first light-emitting regions (BE1, RE1, GE1).

[0088] Each of the second light-emitting regions (BE2, RE2, GE2) included in the second lens region (BNE, RNE, GNE) of each pixel region (PA) may have the same or similar shape as the bottom surface of the second lens (LZ2). The size of the second lens (LZ2) is set to be larger than the size of each of the second light-emitting regions (BE2, RE2, GE2). For example, the second lens LZ2 may have a bottom surface wider than the bottom surface of each of the second light-emitting regions (BE2, RE2, GE2), thereby improving the luminous efficiency of light generated in each of the second light-emitting regions (BE2, RE2, GE2).

[0089] In an embodiment, the second light-emitting regions (BE2, RE2, GE2) included in the second lens regions (BNE, RNE, GNE) of each pixel region (PA) may have the same area, and the number of second light-emitting regions (RE2, GE2, BE2) may vary for each subpixel region (RPA, GPA, BPA). For example, the number of second light-emitting regions (BE2) arranged in the second lens region (BNE) of the B subpixel region (BPA) may be greater than the number of second light-emitting regions (RE2) arranged in the second lens region (RNE) of the R subpixel region (RPA), and may be greater than the number of second light-emitting regions (GE2) arranged in the second lens region (GNE) of the G subpixel region (GPA). The number of second light-emitting regions (GE2) arranged in the second lens region (GNE) of the G subpixel region (GPA) may be greater than the number of second light-emitting regions (RE2) arranged in the second lens region (RNE) of the R subpixel region (RPA). This allows the efficiency deviation of the second B, R, G light-emitting elements in each pixel area (PA) to be compensated for by the number of second light-emitting areas (BE2, RE2, GE2) arranged within the second lens area (BNE, RNE, GNE) of each pixel area (PA).

[0090] In one embodiment, the sizes of the first light-emitting regions (RE1, GE1, BE1) may differ for each sub-pixel region (RPA, GPA, BPA). For example, the size of the first light-emitting region (BE1) in the B sub-pixel region (BPA) may be larger than the size of the first light-emitting region (RE1) in the R sub-pixel region (RPA), and may be larger than the size of the first light-emitting region (GE1) in the G sub-pixel region (GPA). The size of the first light-emitting region (GE1) in the G sub-pixel region (GPA) may be larger than the size of the first light-emitting region (RE1) in the R sub-pixel region (RPA). This allows the efficiency deviation of the first B, R, and G light-emitting elements in each pixel region (PA) to be compensated for by the size of the first light-emitting regions (BE1, RE1, GE1) arranged in the first lens regions (BWE, RWE, GWE) of each pixel region (PA).

[0091] 6 and 7, the display panel 100 according to an embodiment may include a substrate 101, a circuit element layer including transistors (ET1, ET2) disposed on the substrate 101, a light emitting element layer including light emitting elements (EL1, EL2) disposed on the circuit element layer, an encapsulation layer 800 disposed on the light emitting element layer, and a lens layer including lenses (LZ1, LZ2) disposed on the encapsulation layer 800. The display panel 100 according to an embodiment may further include a touch sensor layer (not shown) disposed between the encapsulation layer 800 and the lens layer. The display panel 100 according to an embodiment may further include a color filter layer (not shown) including a color filter and a black matrix disposed between the touch sensor layer and the lens layer.

[0092] 6 and 7, the cross-sectional structure of the B sub-pixel region (BPA) among the R, G, and B sub-pixel regions (RPA, GPA, and BPA) in a display panel according to an embodiment will be described as an example. The R, G, and B sub-pixel regions (RPA, GPA, and BPA) may have the same cross-sectional structure.

[0093] Each sub-pixel area (BPA) of the display panel according to an embodiment may include a first lens area (BWE) as shown in FIG. 6 and a second lens area (BNE) as shown in FIG.

[0094] Referring to FIG. 6, the first lens area (BWE) of the subpixel area (BPA) may include a first mode control transistor (ET1) of the pixel circuit, a first light-emitting element (EL1) connected to the first mode control transistor (ET1), and a first lens (LZ1) arranged overlapping with the first light-emitting area (BE1) on the first light-emitting element (EL1).

[0095] Referring to FIG. 7, the second lens area (BNE) of the subpixel area (BPA) may include a second mode control transistor (ET2) of the pixel circuit, a second light-emitting element (EL2) connected to the second mode control transistor (ET2), and a plurality of second lenses (LZ2) respectively arranged to overlap with a plurality of second light-emitting areas (BE2) on the second light-emitting element (EL2).

[0096] In one embodiment of the display panel, the circuit element layer disposed on the substrate 101 may include a plurality of insulating layers stacked on the substrate 101. For example, the plurality of insulating layers may include a buffer layer 110, a gate insulating layer 120, an interlayer insulating layer 130, a protective layer 140, and a planarization layer 150.

[0097] The substrate 101 may include an insulating material such as glass or plastic. The plastic substrate may be made of a flexible material. For example, the substrate 101 may include at least one organic insulating material selected from the group consisting of acrylic resin, epoxy resin, siloxane resin, polyimide resin, and polyamide resin.

[0098] The buffer layer 110 may have a single layer or multi-layer structure including an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), aluminum oxide (Al2O3), etc. The buffer layer 110 may prevent impurities such as hydrogen from entering the semiconductor layers 211 and 221 through the substrate 101.

[0099] On the buffer layer 110, the transistors (ET1, ET2) can be disposed.

[0100] The first-mode emission control transistor (ET1) includes a semiconductor layer 211, a gate electrode 213, a source electrode 215, and a drain electrode 217 arranged on the buffer layer 110. The second-mode emission control transistor (ET2) includes a semiconductor layer 221, a gate electrode 223, a source electrode 225, and a drain electrode 227 arranged on the buffer layer 110. A gate insulating layer 110 is arranged between the semiconductor layers 211, 221 and the gate electrodes 213, 223. An interlayer insulating layer 130 is arranged between the gate electrodes 213, 223 and the source and drain electrodes 215, 217, 225, 227. The source electrode 215 and the drain electrode 217 of the first-mode emission control transistor (ET1) can be connected to the source region and the drain region of the semiconductor layer 211, respectively, via contact holes that penetrate the interlayer insulating layer 130 and the gate insulating layer 110, respectively. The source electrode 225 and the drain electrode 227 of the second-mode emission control transistor (ET2) can be connected to the source region and the drain region of the semiconductor layer 221, respectively, via contact holes that penetrate the interlayer insulating layer 130 and the gate insulating layer 110.

[0101] The semiconductor layers 211 and 221 may include polycrystalline silicon or an oxide semiconductor material. The semiconductor layers 211 and 221 may include low-temperature polysilicon (LTPS). The semiconductor layers 211 and 221 may include at least one oxide semiconductor material selected from the group consisting of IZO (InZnO)-based, IGO (InGaO)-based, ITO (InSnO)-based, IGZO (InGaZnO)-based, IGZTO (InGaZnSnO)-based, GZTO (GaZnSnO)-based, GZO (GaZnO)-based, and ITZO (InSnZnO)-based materials. A light-shielding layer (not shown) may be further disposed below the semiconductor layers 211 and 221.

[0102] The gate insulating layer 120 may include an inorganic insulating material such as silicon dioxide (SiOx) and silicon nitride (SiNx). The gate insulating layer 120 may include a material with a high dielectric constant. For example, the gate insulating layer 120 may include a high-K material such as hafnium oxide (HfO). The gate insulating layer 120 may have a multi-layer structure.

[0103] Gate lines (not shown) connected to the gate electrodes 213 and 223 can be disposed on the gate insulating layer 120 .

[0104] The interlayer insulating layer 130 may include inorganic insulating materials such as silicon oxide (SiOx) and silicon nitride (SiNx), etc. The interlayer insulating layer 130 may have a multi-layer structure.

[0105] On the interlayer insulating layer 130, data lines (not shown) and power supply lines (not shown) connected to the source electrodes 215, 225 or the drain electrodes 217, 227 may be disposed.

[0106] A protective layer 140 and a planarization layer 150 may be stacked on the first and second-mode light-emitting control transistors (ET1, ET2). The protective layer 140 may include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx). The planarization layer 150 may include an organic insulating material different from that of the protective layer 140, and may provide a flat surface.

[0107] A light emitting element layer including a first light emitting element (EL1) and a second light emitting element (EL2) can be disposed on the planarization layer 150.

[0108] The first light-emitting element (EL1) includes a first electrode 311 disposed on the planarization layer 150, an emitting layer 312 disposed on the first electrode 311, and a second electrode 313 disposed on the emitting layer 312. The second light-emitting element (EL2) includes a first electrode 321 disposed on the planarization layer 150, an emitting layer 322 disposed on the first electrode 321, and a second electrode 323 disposed on the emitting layer 322. The first light-emitting element (EL1) and the second light-emitting element (EL2) disposed in each subpixel area (BPA) can emit light of the same color.

[0109] The first electrode 311 of the first light-emitting element (EL1) can be connected to one of the source electrode 215 and the drain electrode 217 of the first mode control transistor (ET1) through a contact hole that penetrates the planarization layer 150 and the protective layer 140. The first electrode 321 of the second light-emitting element (EL2) can be connected to one of the source electrode 225 and the drain electrode 227 of the second mode control transistor (ET2) through a contact hole that penetrates the planarization layer 150 and the protective layer 140.

[0110] The first electrodes 311 and 321 may include a conductive material with high reflectivity. The first electrodes 311 and 321 may include a metal such as aluminum (Al), silver (Ag), titanium (Ti), or a silver-palladium-copper (APC) alloy. The first electrodes 311 and 321 may further include a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). For example, the first electrodes 311 and 321 may have a multilayer structure of titanium (Ti) and aluminum (Al) (Ti / Al / Ti), a multilayer structure of ITO and aluminum (Al) (ITO / Al / ITO), or a multilayer structure of ITO and APC (ITO / APC / ITO).

[0111] The light emitting layers 312 and 322 may include an emission material layer (EML) containing a light emitting material. The light emitting material may include an organic material, an inorganic material, or a hybrid material. The light emitting layer 312 of the first light emitting element EL11 and the light emitting layer 312 of the second light emitting element EL12 may be spaced apart from each other. This prevents light emission due to leakage current.

[0112] The light-emitting layers 312 and 322 may have a multi-layer structure, for example, the light-emitting layers 312 and 322 may further include at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0113] The second electrodes 313, 323 may include a conductive material that transmits light. The second electrodes 313, 323 may include a transparent conductive material such as ITO or IZO. The second electrodes 313, 323 may include aluminum (Al), magnesium (Mg), silver (Ag), or an alloy thereof, and may have a thin thickness that allows light to pass through. Therefore, light generated in each of the light-emitting layers 312, 322 may be emitted through each of the second electrodes 313, 323.

[0114] The first electrode 311 of the first light-emitting element EL1 may be spaced apart from the first electrode 321 of the second light-emitting element EL2, and a bank insulating layer 160 may be located between the first electrodes 311 and 321. The bank insulating layer 160 may cover each edge of the first electrodes 311 and 321. The bank insulating layer 160 may include an organic insulating material. The bank insulating layer 160 may include an organic material different from that of the planarization layer 150, and may have a single layer or a double layer structure.

[0115] The bank insulating layer 160 may have an opening through which the first electrode 311 is exposed, thereby defining a first light-emitting region (BE1). The light-emitting layer 312 and the second electrode 313 of the first light-emitting element (EL1) may be stacked on the first electrode 311 exposed by the opening of the bank insulating layer 160.

[0116] The bank insulating layer 160 may have an opening through which the first electrode 321 of the second light-emitting element (EL2) is exposed, thereby defining a second light-emitting region (BE2). In one embodiment, the bank insulating layer 160 may have a plurality of openings on the first electrode 321 of the second light-emitting element (EL2), thereby defining a plurality of second light-emitting regions (BE2). The light-emitting layer 322 and the second electrode 323 of the second light-emitting element (EL2) may be stacked on the first electrode 321 exposed by the opening in the bank insulating layer 160. The light-emitting layer 322 and the second electrode 323 of the second light-emitting element (EL2) may overlap the first electrode 321 with the bank insulating layer 160 sandwiched therebetween. In the second lens region (BNE), the second light-emitting regions (BE2) are independently spaced apart by the bank insulating layer 160, but may share the first electrode 321 of the second light-emitting element (EL2), the light-emitting layer 322 of the second light-emitting element (EL2), and the second electrode 323 of the second light-emitting element (EL2). This improves the luminous efficiency of the second light-emitting region (BE2). The size of the second light-emitting region (BE2) may be smaller than the size of the first light-emitting region (BE1).

[0117] The second electrode 313 of the first light emitting element (EL1) can be a common electrode electrically connected to the second electrode 323 of the second light emitting element (EL2).

[0118] An encapsulating layer 800 may be disposed on the light-emitting element layer including the first light-emitting element (EL1) and the second light-emitting element (EL2) of each subpixel area (BPA). The encapsulating layer 800 may prevent damage to the light-emitting elements (EL1, EL2) due to external moisture and impact. The encapsulating layer 800 may have a multi-layer structure. For example, the encapsulating layer 800 may include a first encapsulating layer 810, a second encapsulating layer 820, and a third encapsulating layer 830 stacked in order, but the present specification is not limited thereto. The first encapsulating layer 810, the second encapsulating layer 820, and the third encapsulating layer 830 may include an insulating material. The second encapsulating layer 820 may include a different material from the first encapsulating layer 810 and the third encapsulating layer 830. For example, the first encapsulating layer 810 and the third encapsulating layer 830 may be inorganic encapsulating layers including an inorganic insulating material, and the second encapsulating layer 820 may include an organic encapsulating layer including an organic insulating material. This makes it possible to more effectively prevent the light emitting elements (EL1, EL2) of the display device from being damaged by external moisture or impact.

[0119] A lens layer including a first lens (LZ1) and a second lens (LZ2) can be disposed on the sealing member 800 of each subpixel area (BPA).

[0120] The first lens (LZ1) is disposed on the first light-emitting region (BE1) of the first light-emitting element (EL1) in the first lens region (BWE), and can control the traveling path of light generated in the first light-emitting region (BE1) to a wide viewing angle without limiting it in the left-right direction. For example, the first lens (LZ1) can control the traveling path of light emitted from the first light-emitting region (BE1) of the first light-emitting element (EL1) to a wide viewing angle without limiting it within a specific angle in the left-right direction, and can control it to a narrow viewing angle by limiting it within a specific angle in the up-down direction.

[0121] The second lens (LZ2) is disposed on the second light-emitting region (BE2) of the second light-emitting element (EL2) in the second lens region (BNE), and can limit the traveling path of light generated in the second light-emitting region (BE2) in the left-right direction to control the viewing angle to a narrow one. For example, the second lens (LZ2) can limit the traveling path of light emitted from the second light-emitting region (BE2) of the second light-emitting element (EL2) in the left-right direction to control the viewing angle to a narrow one, and can limit the traveling path of light emitted from the second light-emitting region (BE2) of the second light-emitting element (EL2) in the up-down direction to control the viewing angle to a narrow one.

[0122] A lens protection layer 600 may be positioned on the first lens (LZ1) and the second lens (LZ2) of each subpixel area (BPA). The lens protection layer 600 may include an organic insulating material. The refractive index of the lens protection layer 600 may be smaller than the refractive index of the first lens (LZ1) and the refractive index of the second lens (LZ2). As a result, light passing through the first lens (LZ1) and the second lens (LZ2) may not be reflected toward the substrate 101 due to the difference in refractive index between the lens protection layer 600 and the lens protection layer 600.

[0123] FIG. 8 is an equivalent circuit diagram illustrating the circuit configuration of each subpixel in a display panel according to an embodiment.

[0124] Referring to FIG. 8, each subpixel (SP) may include a pixel circuit 10 including a plurality of transistors (DT, T1 to T8), first and second light-emitting elements (EL1, EL2), and a first lens (LZ1) and a second lens (LZ2) disposed on the first and second light-emitting elements (EL1, EL2), respectively.

[0125] The pixel circuit 10 of the subpixel (SP) shown in Fig. 8 may include, but is not limited to, eight switching transistors (T1 to T8), a driving transistor (DT), a storage capacitor (C1), and first and second light-emitting elements (EL1, EL2). In Fig. 8, the first mode control transistor (T8) may correspond to the first mode control transistor (ET1) shown in Fig. 6, and the second mode control transistor (T6) may correspond to the second mode control transistor (ET2) shown in Fig. 7.

[0126] The pixel circuit 10 of each sub-pixel (SP) can be driven so as to include an initialization period, a sampling and programming period, and an emission period for each frame period.

[0127] In each subpixel (SP), the first light-emitting element (EL1) is driven by a first mode control transistor (T8) controlled by a first mode control signal (SH), and the second light-emitting element (EL2) is driven by a second mode control transistor (T6) controlled by a second mode control signal (PR). The first lens (LZ1) arranged in the light propagation direction of the first light-emitting element (EL1) can control the viewing angle in the horizontal direction to a wide viewing angle. The second lens (LZ2) arranged in the light propagation direction of the second light-emitting element (EL2) can control the viewing angle in the horizontal direction to a narrow viewing angle.

[0128] Each of the transistors (DT, T1 to T8) of each subpixel (SP) includes a gate electrode, a source electrode, and a drain electrode. The source electrode and the drain electrode are not fixed but can be changed depending on the voltage and the direction of the current applied to the gate electrode, so one of the source electrode and the drain electrode can be represented as a first electrode, and the other can be represented as a second electrode. The transistors (DT, T1 to T8) of each subpixel (SP) can use at least one of polysilicon semiconductor, amorphous silicon semiconductor, and oxide semiconductor. The transistors can be P-type or N-type, or a mixture of P-type and N-type.

[0129] Each of the light-emitting elements (EL1, EL2) may include an anode electrode individually connected to a switching transistor (T8, T6), a cathode electrode supplied with a second power supply voltage (EVSS, low-potential power supply voltage) from a second power supply line 34, and a light-emitting layer between the anode and cathode electrodes. The anode electrode is an independent electrode for each light-emitting element, while the cathode electrode may be a common electrode shared by all the light-emitting elements. When a driving current is supplied from the driving transistor (DT) via each of the mode control transistors (T8, T6), electrons from the cathode electrode are injected into the light-emitting layer, and holes from the anode electrode are injected into the organic light-emitting layer. Recombination of the electrons and holes in the light-emitting layer causes a fluorescent or phosphorescent material to emit light, thereby generating light with a brightness proportional to the current value of the driving current.

[0130] A first electrode of the drive transistor (DT) may be connected to a first power line 32 that supplies a first power supply voltage (EVDD). The first power supply voltage (EVDD) may be supplied from the power management circuit 700. A second electrode of the drive transistor (DT) may be commonly connected to first electrodes of the first and second mode control transistors (T8, T6) via a fourth switching transistor (T4). The drive transistor (DT) may drive the first light emitting element (EL1) via the fourth switching transistor (T4) and the first mode control transistor (T8), or drive the second light emitting element (EL2) via the fourth switching transistor (T4) and the second mode control transistor (T6). The drive transistor (DT) may control the light emission intensity of the first light emitting element (EL1) or the second light emitting element (EL2) via the first mode control transistor (T8) or the second mode control transistor (T6) by controlling the drive current (Ids) according to the drive voltage (Vgs) of the storage capacitor (C1).

[0131] The storage capacitor C1 is connected between the gate electrode of the driving transistor DT and the first electrode of the first switching transistor T1, and can charge a driving voltage Vgs corresponding to the data voltage Vdata. The storage capacitor C1 can hold the charged driving voltage Vgs during the light-emitting period when the first switching transistor T1 is turned off, and supply it to the driving transistor DT.

[0132] The first switching transistor T1 can be turned on or off in response to a first scan signal SCAN1 supplied to a first gate line 12 arranged on an Nth (N is a natural number) pixel row line. In response to the first scan signal SCAN1, the first switching transistor T1 can supply a data voltage Vdata supplied via a data line 22 to a first electrode of a storage capacitor C1 during a sampling and programming period. The first scan signal SCAN1 can be supplied from a scan driver 210 (FIG. 1).

[0133] The second, fifth, and seventh switching transistors (T2, T5, and T7) can be turned on or off in response to a second scan signal (SCAN2) supplied to the second gate line 14 arranged on the Nth pixel row line. The second scan signal (SCAN2) can be supplied from the scan driver 210 (FIG. 1).

[0134] The second switching transistor T2 connects the gate electrode and the second electrode (or drain electrode) of the drive transistor DT in response to the second scan signal SCAN2 during the initialization period and the sampling and programming period, thereby connecting the drive transistor DT in a diode configuration. The second switching transistor T2 charges and compensates for the threshold voltage Vth of the drive transistor DT in the storage capacitor C1. As a result, the storage capacitor C1 can charge a data voltage (Vdata+Vth) that compensates for the threshold voltage Vth of the drive transistor DT during the sampling and programming period.

[0135] The fifth switching transistor (T5) can supply the initialization voltage (Vref, or reference voltage) supplied via the initialization voltage line 24 to the anode electrode of the second light-emitting element (EL2) during the initialization period and the sampling and programming period in response to the second scan signal (SCAN2).

[0136] The seventh switching transistor (T7) can supply the initialization voltage (Vref, or reference voltage) supplied via the initialization voltage line 24 to the anode electrode of the first light-emitting element (EL1) during the initialization period and the sampling and programming period in response to the second scan signal (SCAN2).

[0137] The third and fourth switching transistors (T3, T4) can be turned on or off in response to a light emission control signal (EM) supplied to the third gate line 16 arranged on the Nth pixel row line. The light emission control signal (EM) can be supplied from the light emission control driver 220 (FIG. 1).

[0138] The third switching transistor (T3) can supply the initialization voltage (VREF, or reference voltage) supplied via the initialization voltage line 30 to the first electrode of the storage capacitor (C1) during the initialization period and the emission period in response to the emission control signal (EM).

[0139] The fourth switching transistor (T4) can connect the driving transistor (DT) and the first and second mode control transistors (T8, T6) during the initialization period and the light emitting period in response to the light emitting control signal (EM).

[0140] The first mode control transistor (T8) can be turned on or off under the control of a first mode control signal (SH), and the second mode control transistor (T6) can be turned on or off under the control of a second mode control signal (PR).

[0141] The first mode control transistor T8 can connect the driving transistor DT to the first light emitting element EL1 during an emission period when the fourth switching transistor T4 is turned on by the emission control signal EM in the wide viewing angle mode or the shared mode in which the first mode control signal SH is activated. As a result, the first light emitting element EL1 is driven by the driving current from the driving transistor DT to emit light, and the subpixel SP can emit light at a wide viewing angle through the first lens LZ1 of the first lens region.

[0142] When the second mode control signal (PR) is activated to enable the narrow viewing angle mode or the privacy mode, the second mode control transistor (T6) can connect the driving transistor (DT) and the second light emitting element (EL2) during the light emitting period when the fourth switching transistor (T4) is turned on by the light emitting control signal (EM). As a result, the second light emitting element (EL2) is driven by the driving current from the driving transistor (DT) to emit light, and the subpixel (SP) can emit light at a narrow viewing angle through the second lens (LZ2) of the second lens region.

[0143] The first and second mode control signals (SH, PR) may be supplied from the data driver 300 or a mode control unit (not shown). When each subpixel (SP) is operated in a wide viewing angle mode, the first mode control signal (SH) may be activated by a gate-on voltage, and the second mode control signal (PR) may be deactivated by a gate-off voltage. When each subpixel (SP) is operated in a narrow viewing angle mode, the first mode control signal (SH) may be deactivated by a gate-off voltage, and the second mode control signal (PR) may be activated by a gate-on voltage.

[0144] Fig. 9 is a diagram illustrating a schematic layout structure of first and second mode control lines in a partial region of a display panel according to an embodiment, and Fig. 10 is a diagram illustrating a schematic layout structure of a bezel region shown in Fig. 9. Fig. 11 is a diagram illustrating a schematic layout structure of first and second mode control lines in a partial region of a display panel according to an embodiment, and Fig. 12 is a diagram illustrating a schematic layout structure of the bezel region shown in Fig. 11.

[0145] 9 and 11, in a display device according to one embodiment, a COF 310 on which one of a plurality of data drive ICs 320 is mounted, and the arrangement structure of the first and second mode control lines 42, 44 in a portion of a display panel 100a driven by the data drive IC 320 are schematically shown.

[0146] The first mode control lines (42(n), n=1, 2, 3, ..., k) that supply the first mode control signals (SH) can include first and second type first mode control lines (42x(n), 42y(n), n=1, 2, 3, ..., k) arranged in the display area (DA) and third and fourth type first mode control lines (42a(n), 42b(n), n=1, 2, 3, ..., k) arranged in the bezel area (BZ3). The second mode control lines (44(n), n=1, 2, 3, ..., k) that supply the second mode control signals (PR) may include first and second type second mode control lines (44x(n), 44y(n), n=1, 2, 3, ..., k) arranged in the display area (DA) and third and fourth type second mode control lines (44a(n), 44b(n), n=1, 2, 3, ..., k) arranged in the bezel area (BZ3).

[0147] In the third bezel region (BZ3) where the COF 310 is disposed, third-type mode control lines 42a(n), 44a(n) and fourth-type mode control lines 42b(n), 44b(n) can be disposed in a data link region between the COF 310 and the display region (DA). The third-type mode control lines 42a(n), 44a(n) can be connected to a mode control unit (not shown) disposed on the data drive IC 320 or a printed circuit board (PCB, not shown) via the COF 310. The fourth-type mode control lines 42b(n), 44b(n) can be disposed in the first direction (X) in the third bezel region (BZ3) and can be individually connected to the third-type mode control lines 42a(n), 44a(n).

[0148] 9, the third-type mode control lines 42a(n), 44a(n) in the third bezel region (BZ3) may be located within the data link region, and the fourth-type mode control lines 42b(n), 44b(n) may be located separated in the first direction (X). For example, the first set of fourth-type mode control lines 42b(1), 44b(1) may be located parallel to the first direction (X) while being separated in the first direction (X) from the second set of fourth-type mode control lines 42b(2), 44b(2) adjacent in the first direction (X). This reduces the increase in the third bezel region (BZ3) due to the third-type mode control lines 42a(n), 44a(n) and the fourth-type mode control lines 42b(n), 44b(n).

[0149] 11, the third type mode control lines 42a(n), 44a(n) in the third bezel region (BZ3) may be located outside the data link region, and the fourth type mode control lines 42b(n), 44b(n) may be located parallel to the second direction (Y). For example, the first set of fourth type mode control lines 42b(1), 44b(1), the second set of fourth type mode control lines 42b(2), 44b(2), and the i-th set of fourth type mode control lines 42b(i), 44b(i) may be located parallel to the second direction (Y). The i+1-th set of fourth type mode control lines 42b(i+1), 44b(i+1) through the k-th set of fourth type mode control lines 42b(k), 44b(k) may be located parallel to the second direction (Y) and separated from the first through i-th sets in the first direction (X). This makes it possible to suppress interference between the third type mode control lines 42a(n), 44a(n) and the data link area.

[0150] The second type mode control lines 42y(n), 44y(n) arranged in the display area (DA) in the second direction (Y) can be individually connected to the mode control lines 42b(n), 44b(n) in the bezel area (BZ3). The first type mode control lines 42x(n), 44x(n) arranged in the display area (DA) in the first direction (X) can be connected to subpixels and individually connected to the second type mode control lines 42y(n), 44y(n) in the second direction (Y).

[0151] The display area (DA) of the display panel 100a, 100b according to an embodiment may include a plurality of pixel blocks (B1 to Bk) that can be independently controlled for their viewing angles. Each of the pixel blocks (B1 to Bk) can be driven in an independent viewing angle mode by a plurality of mode control sets including mode control lines 42x(1) to 42x(k), 42y(1) to 42y(k), 44x(1) to 44x(k), and 44y(1) to 44y(k).

[0152] For example, the first pixel block (B1) is connected to a first mode control set 42(1), 44(1) including first-1 mode control lines 42(1): 42a(1), 42b(1), 42y(1), 42x(1) and second-1 mode control lines 44(1): 44a(1), 44b(1), 44y(1), 44x(1), and can be driven in a wide viewing angle mode or a narrow viewing angle mode by the first mode control set 42(1), 44(1). The second pixel block (B2) is connected to a second mode control set 42(2), 44(2) including first-second mode control lines 42(2): 42a(2), 42b(2), 42y(2), 42x(2) and second-second mode control lines 44(2): 44a(2), 44b(2), 44y(2), 44x(2), and can be driven in a wide viewing angle mode or a narrow viewing angle mode by the second mode control set 42(2), 44(2). Similarly, the kth pixel block (Bk) is connected to a kth mode control set 42(k), 44(k) including first-kth mode control lines 42(k): 42a(k), 42b(k), 42y(k), 42x(k) and second-kth mode control lines 44(k): 44a(k), 44b(k), 44y(k), 44x(k), and can be driven in a wide viewing angle mode or a narrow viewing angle mode by the kth mode control set 42(k), 44(k).

[0153] The second type mode control lines 42y(n), 44y(n) arranged in the second direction (Y) in each of the plurality of pixel blocks (B1 to Bk) may extend to other pixel blocks located in the same column in the second direction (Y) or to other pixel blocks adjacent to each other in the second direction (Y) and have similar lengths in the display area (DA).

[0154] The second-type mode control lines 42y(n), 44y(n) in the second direction (Y) may be connected to the eleventh-type mode control lines 42x(n), 44x(n) in the first direction (X) in the first-type pixel region (A1) of the corresponding pixel block through contact holes in the insulating layer, and may have a structure in which they intersect with each other across the insulating layer.

[0155] The second-type mode control lines 42y(n), 44y(n) in the second direction (Y) may have a structure in which they intersect with the first-type mode control lines in the first direction (X) in the second-type pixel areas (A2) of other pixel blocks without being connected across an insulating layer.

[0156] The first type mode control lines 42x(n), 44x(n) arranged in each of the plurality of pixel blocks (B1 to Bk) in the first direction (X) may have a structure in which they are disconnected from the first type mode control lines of other pixel blocks adjacent in the first direction (X), such as the third type pixel region (A3).

[0157] Referring to Figures 10 and 12, in one embodiment of the display panel 100a, 100b, the third bezel area (BZ3) may include an electrostatic discharge prevention circuit (ESD) area 102, an illumination inspection circuit (AP) area 104, a demultiplexer circuit (DEMUX) area 106, a mode control line area 108, and a power line area 110 arranged in the second direction (Y) between the pad area where the COF 320 is arranged and the display area (DA).

[0158] In the electrostatic discharge prevention circuit (ESD) area 102 and the lighting inspection circuit (AP) area 104, a plurality of data input lines 21, first and second mode control lines 42a, 44a, and power input lines 24a, 32a, 34a connected to the COF 320 via the pad area can be arranged parallel to the first direction (X) and extending in the second direction (Y).

[0159] An electrostatic discharge (ESD) circuit including a plurality of transistors may be connected to each of the plurality of data input lines 21 and the third-type first and second mode control lines 42a, 44a arranged in the electrostatic discharge (ESD) circuit area 102. Each of the electrostatic discharge (ESD) circuits operates when static electricity flows in through one of the plurality of data input lines 21 and the third-type first and second mode control lines 42a, 44a, and can discharge static electricity through the electrostatic discharge line 52.

[0160] An illumination inspection circuit (AP) including a plurality of transistors can be connected to each of the plurality of data input lines 21 and the third-type first and second mode control lines 42a, 44a arranged in the illumination inspection circuit (AP) region 104. The illumination inspection circuit (AP) can be connected to the control lines 62, 72 and the inspection signal supply lines 64, 66, 68, 74, 76.

[0161] The demultiplexer circuit (DEMUX) arranged in the demultiplexer circuit (DEMUX) region 106 can distribute and supply data signals (R, G, B) supplied via a plurality of data input lines 21 to a number of data lines 22 that is greater than the number of the data input lines 21. The demultiplexer circuit (DEMUX) can include a plurality of transistors that are connected to a plurality of control lines 82, 84, 86 and perform switching operations.

[0162] For example, the demultiplexer circuit (DEMUX) can time-divide R data signals sequentially supplied via any one R data input line 21 and supply them sequentially to three R data lines 22. The demultiplexer circuit (DEMUX) can time-divide G data signals sequentially supplied via any one G data input line 21 and supply them sequentially to three G data lines 22. The demultiplexer circuit (DEMUX) can time-divide B data signals sequentially supplied via any one B data input line 21 and supply them sequentially to three B data lines 22.

[0163] In the demultiplexer circuit (DEMUX) region 106, the third type first and second mode control lines 42a, 44a arranged between the demultiplexer circuit (DEMUX) and the power supply input lines 24a, 32a, 34a can extend in the second direction (Y).

[0164] The first and second mode control lines 42a, 44a of the third type may extend in the first direction (X) in the mode control line regions 108, 118 and connect to the first and second mode control lines 42b, 44b of the fourth type, respectively. The first and second mode control lines 42b, 44b of the fourth type may connect to the first and second mode control lines 42y, 44y of the second type in the second direction (Y) arranged in the display region (DA) to provide the first and second mode control signals (SH, PR), respectively.

[0165] The number of fourth-type first and second mode control lines 42 b, 44 b arranged in mode control line region 108 shown in Figure 10 may be smaller than the number of fourth-type first and second mode control lines 42 b, 44 b arranged in mode control line region 118 shown in Figure 16. This makes the area of ​​mode control line region 108 shown in Figure 10 smaller than the area of ​​mode control line region 118 shown in Figure 16, and minimizes an increase in the bezel area (BZ3).

[0166] The power input lines 24a, 32a, and 34a can be connected to the power lines 24b, 32b, and 34b, respectively, arranged in the first direction (X) in the power line area 110. The power lines 24b, 32b, and 34b can be connected to the power lines 24, 32, and 34, respectively, arranged in the second direction (Y) in the display area (DA), and can supply an initialization voltage (Vref) and first and second power voltages (EVDD, EVSS), respectively.

[0167] 13 to 15 are diagrams illustrating the layout structure of main signal lines in the first to third types of pixel regions (A1, A2, A3) shown in FIGS.

[0168] 13 to 15, each of the pixels (PX1, PX2, PX3) arranged in the first to third type pixel regions (A1, A2, A3) may include red, green, and blue subpixels (R, G, B) arranged in a first direction (X). A data line 22 for supplying a data voltage (Vdata), an initialization voltage line 24 for supplying an initialization voltage (Vref), and a first power supply line 32 for supplying a first power supply voltage (EVDD) may be arranged in a second direction (Y) for each of the red, green, and blue subpixels (R, G, B). A second-type first mode control line 42y for supplying a first mode control signal (SH), a second-type second mode control line 44y for supplying a second mode control signal (PR), and a second power supply line 34 for supplying a second power supply voltage (EVSS) may be arranged between each of the pixels (PX1, PX2, PX3).

[0169] 14, in the first-type pixel region (A1), the second-type first mode control line 42y and the second mode control line 44y arranged in the second direction (Y) can be connected to the first-type first mode control line 42x and the second mode control line 44x arranged in the first direction (X) through contact holes (CNT1, CNT2) in the insulating layer, respectively. The first-type first mode control line 42x and the second mode control line 44x arranged in the first direction (X) can be connected to a plurality of sub-pixels (R, G, B).

[0170] Referring to FIG. 15, in the second-type pixel region (A2), the second-type first mode control line 42y and the second mode control line 44y arranged in the second direction (Y) can cross the first-type first mode control line 42x and the second mode control line 44x arranged in the first direction (X) without being connected to each other across at least one insulating layer.

[0171] 13, in the third-type pixel region (A3), the first-type first mode control line 42x and the second-type second mode control line 44x arranged in the first direction (X) may be disconnected between the first pixel (PX1) and the second pixel (PX2) with respect to the second power line 34. The second-type first mode control line 42y and the second-type second mode control line 44y arranged in the second direction (Y) may cross the first-type first mode control line 42x and the second-type second mode control line 44x arranged in the first direction (X) without being connected, with at least one insulating layer interposed therebetween. The first-type first mode control line may be separated from the first-type first mode control line arranged in an adjacent pixel block, and the first-type second mode control line may be separated from the first-type second mode control line arranged in an adjacent pixel block.

[0172] FIG. 16 is a plan view illustrating a pixel arrangement structure in a display panel according to an embodiment.

[0173] 16 exemplarily shows the layout structure of main signal lines in the first to third subpixels (SP1, SP2, SP3) arranged in the first-type pixel region (A1) shown in FIG. 14, and the planar layout structure of the pixel circuit 10 (FIG. 8) of the first subpixel (SP1). The second and third subpixels (SP2, SP3) may have the same planar layout structure as the first subpixel (SP1).

[0174] Referring to FIGS. 14 and 16, the pixel circuit 10 of the sub-pixel (SP1) may include a driving transistor (DT), eight transistors (T1 to T8), and a storage capacitor (C1).

[0175] The pixel circuit 10 of the subpixel (SP1) may include a third gate line 16 and a first gate line 12 arranged in a first direction (X) at a lower portion based on the drive transistor (DT) and the storage capacitor (C1), and a second gate line 14, a second mode control line 44x, the third gate line 16, a first mode control line 42x, and a second gate line 14 arranged in the first direction (X) at an upper portion. The pixel circuit 10 of the subpixel (SP1) may include a data line 22, an initialization voltage line 24, and a first power supply line 32 arranged in a second direction (Y).

[0176] In the pixel circuit 10 of the subpixel (SP1), the third switching transistor (T3) may include a semiconductor layer overlapping with the third gate line 16 that supplies the light emitting control signal (EM), a first electrode (source electrode) connected to the initialization voltage line 24 that supplies the initialization voltage (Vref), and a second electrode (drain electrode) connected to the first electrode of the storage capacitor (C1).

[0177] The first switching transistor (T1) may include a semiconductor layer overlapping with the first gate line 12 that supplies the first scan signal (SCAN1), a first electrode (source electrode) connected to the data line 22 that supplies the data voltage (Vdata), and a second electrode (drain electrode) connected to the first electrode of the storage capacitor (C1).

[0178] The drive transistor (DT) may include a semiconductor layer overlapping with the storage capacitor (C1), a first electrode (source electrode) connected to a first power supply line 32 that supplies a first power supply voltage (EVDD), and a second electrode (drain electrode) connected to the first electrode (source electrode) of the second switching transistor (T2).

[0179] The second switching transistor (T2) may include a semiconductor layer overlapping with the second gate line 14 that supplies the second scan signal (SCAN2), a first electrode (source electrode) connected to the second electrode (drain electrode) of the driving transistor (DT), and a second electrode (drain electrode) connected to the second electrode of the storage capacitor (C1).

[0180] The fifth switching transistor T5 may include a semiconductor layer overlapping the second gate line 14 that supplies the second scan signal SCAN2, a first electrode (source electrode) connected to the initialization voltage line 24 that supplies the initialization voltage Vref, a second connecting electrode CE2, and a second electrode (drain electrode) connected to the second electrode (drain electrode) of the second mode control transistor T6. The second connecting electrode CE2 may be connected to the anode electrode of the second light emitting element EL2 (FIG. 8).

[0181] The second mode control transistor T6 may include a semiconductor layer overlapping with the second mode control line 44x that supplies the second mode control signal PR, a first electrode (source electrode) connected to the second electrode (drain electrode) of the fourth switching transistor T4, and a second electrode (drain electrode) connected to a second connection electrode CE2 that is connected to the anode electrode of the second light-emitting element EL2 (FIG. 8). The first connection electrode CE1 may be connected to the anode electrode of the first light-emitting element EL1 (FIG. 8).

[0182] The fourth switching transistor (T4) may include a semiconductor layer overlapping with the third gate line 16 that supplies the light emitting control signal (EM), a first electrode (source electrode) connected to the second electrode (drain electrode) of the driving transistor (DT), a first electrode (source electrode) of the first mode control transistor (T8), and a second electrode (drain electrode) connected to the first electrode (source electrode) of the second mode control transistor (T6).

[0183] The first mode control transistor (T8) may include a semiconductor layer overlapping with the first mode control line 42x that supplies the first mode control signal (SH), a first electrode (source electrode) connected to the second electrode (drain electrode) of the fourth switching transistor (T4), and a second electrode (drain electrode) connected to a first connection electrode (CE1) that connects to the anode electrode of the first light-emitting element (EL1, FIG. 8).

[0184] The seventh switching transistor (T7) may include a semiconductor layer overlapping with the second gate line 14 that supplies the second scan signal (SCAN2), a first electrode (source electrode) connected to the initialization voltage line 24 that supplies the initialization voltage (Vref), a first connection electrode (CE1), and a second electrode (drain electrode) connected to the second electrode (drain electrode) of the first mode control transistor (T8).

[0185] The second type first and second mode control lines 42y, 44y and the second power supply line 34 arranged in the second direction (Y) may be arranged parallel to the first power supply line 32 of the third subpixel (SP3). The second type first and second mode control lines 42y, 44y may be connected to the first type first and second mode control lines 42x, 44x arranged in the first direction (X) via contact holes (CNT1, CNT2) in the insulating layer.

[0186] FIG. 17 is a diagram illustrating an arrangement structure of a plurality of pixel blocks in a display device according to an embodiment.

[0187] The display panel 100 according to one embodiment may be connected to a plurality of COFs 310, each of which is equipped with a plurality of data drive ICs 320. The display area of ​​the display panel 100 may include a plurality of pixel blocks (B1 to Bm) each having independently controllable viewing angles. Each of the pixel blocks (B1 to Bm) may be independently controlled by a first and second mode control line set, thereby selectively controlling the pixel blocks to a wide viewing angle mode (shared mode) or a narrow viewing angle mode (privacy mode).

[0188] As described above, the display panel and display device according to some embodiments can selectively drive the first light-emitting element corresponding to the first lens region and the second light-emitting element corresponding to the second lens region in each sub-pixel using the first and second mode control signals, thereby controlling the viewing angle of each of multiple regions in the display region to a wide viewing angle or a narrow viewing angle, and reducing power consumption.

[0189] The display panel and display device according to some embodiments can control a plurality of regions to have a wide viewing angle or a narrow viewing angle separately for each region using first and second mode control signals, so that not only the positions of the wide viewing angle regions and the narrow viewing angle regions but also the ratio (area) of the wide viewing angle regions to the narrow viewing angle regions can be freely adjusted in the first and second directions.

[0190] The display panel and display device according to some embodiments can improve user convenience and satisfaction by freely adjusting not only the positions of the wide viewing angle area and the narrow viewing angle area, but also the ratio (area) of the wide viewing angle area and the narrow viewing angle area in the first and second directions according to the user's requirements or content.

[0191] A display panel according to some embodiments includes a plurality of pixel blocks, each including a plurality of sub-pixels, arranged in a display area, a bezel area outside the display area, and a plurality of mode control line sets individually connecting to the plurality of pixel blocks, each of the plurality of mode control line sets including a first mode control line for supplying a first mode control signal and a second mode control line for supplying a second mode control signal. Each of the plurality of sub-pixels includes a drive transistor connected to a first power line, a first light-emitting element connected to the drive transistor via a first mode control transistor controlled by the first mode control signal, a second light-emitting element connected to the drive transistor via a second mode control transistor controlled by a second mode control signal, a first lens disposed over the first light-emitting element, and a second lens disposed over the second light-emitting element, and the first lens area and the second lens area can differently control a viewing angle in a first direction.

[0192] In a display panel according to some embodiments, when a first mode control signal is activated, each subpixel drives a first light-emitting element to control the viewing angle in a first direction to a wide viewing angle through a first lens region, and when a second mode control signal is activated, the second light-emitting element drives a second light-emitting element to control the viewing angle in the first direction to a narrow viewing angle narrower than the wide viewing angle through a second lens region.

[0193] In each of a plurality of pixel blocks of a display panel according to some embodiments, the first mode control lines may include first mode control lines of a first type arranged in a first direction and first mode control lines of a second type arranged in a second direction, and the second mode control lines may include second mode control lines of the first type arranged in the first direction and second mode control lines of a second type arranged in the second direction.

[0194] In some embodiments of a display panel, a first type first mode control line and a first type second mode control line arranged in any one of a plurality of pixel blocks can be separated from a second type second mode control line and a second type first mode control line of another pixel block adjacent to the first direction.

[0195] In some embodiments of a display panel, a first mode control line of a second type and a second mode control line of a second type arranged in any one of a plurality of pixel blocks can be extended in the second direction to another pixel block adjacent in the second direction.

[0196] In each of the plurality of pixel blocks of the display panel according to some embodiments, the second type first-mode control line and the second type second-mode control line can be arranged parallel to the second power supply line between the unit pixels and extend in the second direction.

[0197] In each subpixel of a display panel according to some embodiments, the data line, the initialization voltage line, and the first power supply line connected to each subpixel may extend in the second direction.

[0198] In some embodiments, in a first type pixel region included in each pixel block of a display panel, a first mode control line of the first type and a first mode control line of the second type can be connected through a first contact hole in the insulating layer, and a second mode control line of the first type and a second mode control line of the second type can be connected through a second contact hole in the insulating layer.

[0199] In some embodiments, in a second-type pixel region included in each pixel block of a display panel, a first-type first-mode control line can cross a second-type first-mode control line across an insulating layer, and a first-type second-mode control line can cross a second-type second-mode control line across an insulating layer.

[0200] In some embodiments, in a third-type pixel region included in each pixel block of a display panel, a first-type first-mode control line can be separated from a first-type first-mode control line of an adjacent pixel block, and a first-type second-mode control line can be separated from a first-type second-mode control line of an adjacent pixel block.

[0201] Each of the plurality of mode control line sets of the display panel according to some embodiments may further include a third type first mode control line and a third type second mode control line arranged in the bezel area, an anti-static circuit respectively connected to the third type first mode control line and the third type second mode control line, and a lighting inspection circuit respectively connected to the third type first mode control line and the third type second mode control line.

[0202] In a display panel according to some embodiments, the third type first mode control line and the third type second mode control line can be arranged within a data link area arranged in a bezel area or outside the data link area.

[0203] In a display panel according to some embodiments, each of the plurality of mode control line sets may further include a first mode control line of a fourth type arranged in a first direction in the bezel region, connecting a first mode control line of a third type and a first mode control line of a second type, and a second mode control line of a fourth type arranged in the bezel region in the first direction, connecting a second mode control line of the third type and a second mode control line of the second type.

[0204] In some embodiments of the display panel, each subpixel may further include a storage capacitor connected to the gate electrode of the driving transistor, a first switching transistor configured to supply a data voltage of the data line to the first electrode of the storage capacitor in response to a first scan signal on a first gate line, a second switching transistor configured to connect the driving transistor to a diode structure in response to a second scan signal on a second gate line, a third switching transistor configured to supply an initialization voltage of the initialization voltage line to the first electrode of the storage capacitor in response to an emission control signal on a third gate line, a fourth switching transistor configured to connect the driving transistor and the first and second mode control transistors in response to the emission control signal on the third gate line, a fifth switching transistor configured to supply an initialization voltage of the initialization voltage line to an anode electrode of the second light-emitting element in response to a second scan signal on the second gate line, and a seventh switching transistor configured to supply an initialization voltage of the initialization voltage line to the anode electrode of the first light-emitting element in response to a second scan signal on the second gate line.

[0205] In a display panel according to some embodiments, the first light-emitting element may include a first light-emitting area, the first lens may overlap the first light-emitting area, and the first lens may have a bottom surface wider than the first light-emitting area.

[0206] In a display panel according to some embodiments, the second light-emitting element includes a plurality of second light-emitting regions, and the second lens includes a plurality of second lenses respectively overlapping with the plurality of second light-emitting regions, and each of the plurality of second lenses can have a base surface wider than each of the plurality of second light-emitting regions.

[0207] In a display panel according to some embodiments, the plurality of subpixels include a first color subpixel, a second color subpixel, and a third color subpixel, and the sizes of the first lenses of the first color, second color, and third color subpixels are different from each other, and the numbers of the second lenses of the first color, second color, and third color subpixels are different from each other.

[0208] A display panel apparatus according to some embodiments includes a display panel and a data driver arranged in a bezel region and driving data lines arranged in a display region, and the data driver can individually supply a first mode control signal and a second mode control signal to each of a plurality of mode control line sets.

[0209] The features, structures, effects, etc. described in the various examples of this specification are included in at least one example of this specification and are not necessarily limited to only one example. Furthermore, the features, structures, effects, etc. exemplified in at least one example of this specification can be combined or modified in other examples by a person skilled in the art to which the technical ideas of this specification belong. Therefore, content related to such combinations and modifications should be interpreted as being included in the technical scope or scope of rights of this specification.

[0210] The present specification described above is not limited to the above-mentioned examples and the attached drawings, and it will be apparent to those skilled in the art to which the present specification pertains that various substitutions, modifications, and alterations are possible within the scope of the technical idea of ​​the present specification. Therefore, the scope of the present specification is defined by the claims set forth below, and all modifications and variations derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included in the scope of the present specification. [Explanation of symbols]

[0211] 100: Display panel 200: Gate driver 210: Scan driver 220: Light emission control driver 300: Data driver 320: Data Drive IC 310:COF (BZ1~BZ4): Bezel area 400: Timing controller 500: Level shifter 600: Gamma voltage generator 700: Power management circuit 1000: Display device DA: Display Area DA1: 1st area DA2: 2nd area EL1, EL2: Light-emitting element LZ1, LZ2: Lens BPA, RPA, GPA: Subpixel area BWE, RWE, GWE: First lens region BNE, RNE, GNE: Second lens region BE1, RE1, RE1: First light-emitting area BE2, RE2, GE2: Second light-emitting region ET1, ET2, T6, T8: Mode control transistors 12, 14, 16: Gate Line 22: Data line 24: Initialization voltage line 32: First power line 34: Second power line 42: First mode control line 44: Second mode control line

Claims

1. a plurality of pixel blocks each including a plurality of sub-pixels arranged in a display area; a bezel area disposed outside the display area; a plurality of mode control line sets individually connected to the plurality of pixel blocks; each of the plurality of mode control line sets includes a first mode control line for providing a first mode control signal and a second mode control line for providing a second mode control signal; Each of the plurality of sub-pixels comprises: a drive transistor connected to a first power supply line; a first light emitting element connected to the driving transistor via a first mode control transistor controlled by the first mode control signal; a second light emitting element connected to the driving transistor via a second mode control transistor controlled by the second mode control signal; a first lens disposed on the first light-emitting element; a second lens disposed on the second light-emitting element; the first lens and the second lens control a viewing angle in a first direction differently; In each of the plurality of pixel blocks, the first mode control lines include first type first mode control lines arranged in the first direction and second type first mode control lines arranged in a second direction different from the first direction; the second mode control lines include second mode control lines of a first type arranged in the first direction and second mode control lines of a second type arranged in the second direction; A display panel in which the viewing angle of each of the plurality of pixel blocks is independently controlled by controlling the first mode control line and the second mode control line, respectively.

2. Each of the sub-pixels is When the first mode control signal is activated, the first light emitting element is driven to control the viewing angle in the first direction to a wide viewing angle through the first lens; 2. The display panel of claim 1, wherein when the second mode control signal is activated, the second light-emitting element is driven to control the viewing angle in the first direction through the second lens to a narrow viewing angle narrower than the wide viewing angle.

3. The first mode control line of the first type and the second mode control line of the first type arranged in any one pixel block of the plurality of pixel blocks are 2. The display panel of claim 1, wherein the second-type second-mode control lines and the second-type first-mode control lines of the pixel blocks adjacent to each other in the first direction are separated from each other.

4. The first mode control line of the second type and the second mode control line of the second type arranged in any one pixel block of the plurality of pixel blocks are The display panel of claim 1 , wherein the pixel blocks extend in the second direction to other pixel blocks adjacent in the second direction.

5. In each of the plurality of pixel blocks, 2. The display panel of claim 1, wherein the first-mode control lines of the second type and the second-mode control lines of the second type are arranged in parallel with a second power supply line between unit pixels and extend in the second direction.

6. In each of the sub-pixels, The display panel of claim 1 , wherein a data line, an initialization voltage line, and the first power supply line connected to each of the sub-pixels extend in the second direction.

7. In the first-type pixel region included in each pixel block, the first type first mode control line and the second type first mode control line are connected via a first contact hole in an insulating layer; 2. The display panel of claim 1, wherein the first type second-mode control line and the second type second-mode control line are connected through a second contact hole in the insulating layer.

8. In the second-type pixel region included in each of the pixel blocks, the first-type first mode control line intersects with the second-type first mode control line across an insulating layer; The display panel of claim 1 , wherein the first-type second-mode control lines intersect with the second-type second-mode control lines across an insulating layer.

9. In the third-type pixel region included in each pixel block, the first mode control line of the first type is separated from the first mode control line of the first type of an adjacent pixel block; 2. The display panel of claim 1, wherein the second-mode control lines of the first type are separated from the second-mode control lines of the first type of adjacent pixel blocks.

10. Each of the plurality of mode control line sets comprises: a third type first mode control line and a third type second mode control line disposed in the bezel area; an anti-static circuit connected to the third type first mode control line and the third type second mode control line, respectively; 2. The display panel of claim 1, further comprising a lighting inspection circuit connected to the third type first mode control line and the third type second mode control line, respectively.

11. 11. The display panel of claim 10, wherein the first mode control lines of the third type and the second mode control lines of the third type are arranged within a data link area arranged in the bezel area or outside the data link area.

12. Each of the plurality of mode control line sets comprises: a fourth-type first-mode control line disposed in the bezel area in the first direction, the fourth-type first-mode control line connecting the third-type first-mode control line and the second-type first-mode control line; 11. The display panel of claim 10, further comprising a fourth type second-mode control line arranged in the bezel area in the first direction and connecting the third type second-mode control line and the second type second-mode control line.

13. Each of the sub-pixels a storage capacitor connected to the gate electrode of the driving transistor; a first switching transistor for supplying a data voltage of a data line to a first electrode of the storage capacitor in response to a first scan signal of a first gate line; a second switching transistor for connecting the driving transistor to a diode configuration in response to a second scan signal on a second gate line; a third switching transistor for supplying an initialization voltage of an initialization voltage line to the first electrode of the storage capacitor in response to a light emission control signal of a third gate line; a fourth switching transistor connecting the driving transistor and the first and second mode control transistors in response to the light emission control signal of the third gate line; a fifth switching transistor for supplying the initialization voltage of the initialization voltage line to an anode electrode of the second light emitting element in response to the second scan signal of the second gate line; 2. The display panel of claim 1, further comprising: a seventh switching transistor for supplying the initialization voltage of the initialization voltage line to the anode electrode of the first light emitting element in response to the second scan signal of the second gate line.

14. the first light-emitting element includes a first light-emitting region; The display panel of claim 1 , wherein the first lens overlaps the first light-emitting region and has a bottom surface that is wider than the first light-emitting region.

15. the second light-emitting element includes a plurality of second light-emitting regions; the second lens includes a plurality of second lenses overlapping the plurality of second light-emitting regions, respectively; The display panel according to claim 1 , wherein each of the second lenses has a bottom surface wider than each of the second light-emitting regions.

16. the plurality of subpixels include a first color subpixel, a second color subpixel, and a third color subpixel; the first lenses of the first color subpixel, the second color subpixel, and the third color subpixel have different sizes; The display panel of claim 1 , wherein the first color subpixel, the second color subpixel, and the third color subpixel have different numbers of second lenses.

17. The display panel of claim 1 , wherein the first lens and the second lens control the same viewing angle in a second direction perpendicular to the first direction.

18. 2. The display panel of claim 1, wherein the first lens is a semi-cylindrical lens that is elongated in the first direction, and the second lens is a hemispherical lens.

19. the first color subpixel, the second color subpixel, and the third color subpixel are red subpixels, green subpixels, and blue subpixels, respectively; the number of the second lenses disposed in the blue subpixels is greater than the number of the second lenses disposed in the red subpixels and greater than the number of the second lenses disposed in the green subpixels; 17. The display panel of claim 16, wherein the number of the second lenses disposed in the green subpixels is greater than the number of the second lenses disposed in the red subpixels.

20. the first color subpixel, the second color subpixel, and the third color subpixel are red subpixels, green subpixels, and blue subpixels, respectively; a size of the second lens disposed in the blue subpixel is larger than a size of the second lens disposed in the red subpixel and is larger than a size of the second lens disposed in the green subpixel; The display panel of claim 16 , wherein the size of the second lens disposed in the green subpixel is larger than the size of the second lens disposed in the red subpixel.

21. The display panel of claim 11 , wherein a chip-on-film is disposed in the bezel area, and the data link area is located between the chip-on-film and the display area.

22. the third gate line and the first gate line are disposed in the first direction at lower ends with respect to the driving transistor and the storage capacitor; 14. The display panel of claim 13, wherein the second gate line, the second mode control line, the third gate line, the first mode control line, and the second gate line are arranged along the first direction at upper ends relative to the driving transistor and the storage capacitor.

23. 11. The display panel of claim 10, wherein in the bezel area corresponding to the static electricity prevention circuit and the lighting inspection circuit, a plurality of data input lines, the third type first and second mode control lines, and a power input line are arranged in parallel to the first type and extend in the second direction.

24. 24. The display panel of claim 23, wherein the anti-static circuit is configured to operate when static electricity enters through any of the plurality of data input lines and the third type first and second mode control lines, and to discharge static electricity through an electrostatic discharge line.

25. The display area includes at least one of a first display area and a second display area, the first display area including at least one first pixel block providing a first viewing angle, and the second display area including at least one second pixel block providing a second viewing angle narrower than the first viewing angle; The display panel according to claim 1 , wherein at least one of a positional relationship between the first display region and the second display region and an area ratio between the first display region and the second display region is adjusted in the display region.

26. A display panel according to any one of claims 1 to 25; a data driver disposed in the bezel region and driving data lines disposed in the display region; The data driver a display device that individually supplies the first mode control signal and the second mode control signal to each of the plurality of mode control line sets;

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