Multilayer electronic components

Abstract

To provide a multilayer electronic component including an inductor that can reduce characteristic variation.SOLUTION: An electronic component includes a stack 50 and an inductor wound about an axis orthogonal to a stacking direction. The inductor includes a conductor layer portion and two through hole columns. The conductor layer portion includes two conductor layers 725, 735 disposed at positions different from each other in the stacking direction T and connected in parallel to each other. An area of the conductor layer 725 is larger than an area of the conductor layer 735.SELECTED DRAWING: Figure 17

Description

[Technical Field]

[0001] The present invention relates to a multilayer electronic component including an inductor. [Background technology]

[0002] In small mobile communication devices, a common configuration is to provide an antenna that is shared by multiple applications with different systems and operating frequency bands, and to separate the multiple signals transmitted and received by this antenna using a duplexer.

[0003] In general, a duplexer that separates a first signal having a frequency within a first frequency band from a second signal having a frequency within a second frequency band higher than the first frequency band includes a common port, a first signal port, a second signal port, a first filter provided in the first signal path from the common port to the first signal port, and a second filter provided in the second signal path from the common port to the second signal port. The first and second filters are, for example, LC resonators configured using inductors and capacitors.

[0004] A known duplexer uses a laminate including a plurality of stacked dielectric layers, as disclosed in Patent Document 1. Also, a known inductor used in an LC resonator is an inductor in which via-hole conductors are connected to both ends of an inductor conductive layer, as disclosed in Patent Documents 1 and 2. In Patent Documents 1 and 2, a plurality of inductor conductive layers having the same planar shape are stacked.

[0005] The laminate that constitutes the duplexer is formed, for example, as follows. First, a plurality of ceramic green sheets that will later become a plurality of dielectric layers are produced. Each ceramic green sheet has a plurality of pre-fired conductor layers that will later become a plurality of conductor layers and a plurality of pre-fired through holes that will later become a plurality of through holes. Next, a plurality of ceramic green sheets are stacked to produce a green sheet laminate. Next, this green sheet laminate is cut to produce a pre-fired laminate. Next, the ceramic and conductor in this pre-fired laminate are fired in a low-temperature co-firing process to complete the laminate. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] International Publication No. 2016 / 152206 [Patent Document 2] Japanese Patent Application Laid-Open No. 2014-53689 Summary of the Invention [Problem to be solved by the invention]

[0007] When multiple inductor conductor layers having the same planar shape are stacked, as in the inductors disclosed in Patent Documents 1 and 2, if the multiple inductor conductor layers become misaligned due to misalignment of the ceramic green sheets, the characteristics of the inductor will change.

[0008] The above problem is not limited to duplexers, but applies to all multilayer electronic components including inductors.

[0009] The present invention has been made in view of the above problems, and an object of the present invention is to provide a multilayer electronic component having an inductor capable of suppressing fluctuations in characteristics. [Means for solving the problem]

[0010] The multilayer electronic component of the present invention includes a laminate including a plurality of stacked dielectric layers, and an inductor integrated with the laminate and wound around an axis perpendicular to the stacking direction of the plurality of dielectric layers. The inductor includes a first row of through holes, a second row of through holes, and a first conductor layer portion connecting one end of the first row of through holes with one end of the second row of through holes. Each of the first row of through holes and the second row of through holes is formed by connecting two or more through holes in series. The first conductor layer portion includes a first conductor layer and a second conductor layer arranged at different positions in the stacking direction and connected in parallel. The area of ​​the first conductor layer is larger than the area of ​​the second conductor layer.

[0011] In the multilayer electronic component of the present invention, the second conductor layer may be disposed inside the outer edge of the first conductor layer when viewed from a direction parallel to the stacking direction. Furthermore, the shape of the second conductor layer when viewed from a direction parallel to the stacking direction may be similar to the shape of the first conductor layer when viewed from a direction parallel to the stacking direction. Furthermore, the first conductor layer may be disposed between the second conductor layer and the axis.

[0012] In the multilayer electronic component of the present invention, each of the first and second conductor layers may include a first portion extending in a first direction perpendicular to the stacking direction and a second portion extending in a second direction perpendicular to the stacking direction, or each of the first and second conductor layers may extend in a direction perpendicular to the stacking direction.

[0013] The multilayer electronic component of the present invention may also include a plurality of inductors. In this case, the first conductor layer and the second conductor layer included in at least one of the plurality of inductors may each include a first portion extending in a first direction perpendicular to the stacking direction and a second portion extending in a second direction perpendicular to the stacking direction. The first conductor layer and the second conductor layer included in at least another inductor of the plurality of inductors may each extend in a direction perpendicular to the stacking direction.

[0014] In the multilayer electronic component of the present invention, the inductor may further include a second conductor layer portion connected to the other end of the second row of through holes. The second conductor layer portion may include a third conductor layer and a fourth conductor layer stacked in the stacking direction. The area of ​​the fourth conductor layer may be larger than the area of ​​the third conductor layer. The fourth conductor layer may be disposed between the third conductor layer and the axis. [Effects of the Invention]

[0015] In the multilayer electronic component of the present invention, the first conductor layer portion of the inductor includes a first conductor layer and a second conductor layer that are arranged at different positions in the stacking direction and connected in parallel. The area of ​​the first conductor layer is larger than the area of ​​the second conductor layer. This makes it possible to suppress fluctuations in the inductor characteristics. [Brief explanation of the drawings]

[0016] [Figure 1] 1 is a circuit diagram showing a circuit configuration of a multilayer electronic component according to an embodiment of the present invention. [Figure 2] 1 is a circuit diagram showing a circuit configuration of a multilayer electronic component according to an embodiment of the present invention. [Figure 3] 1 is a perspective view showing the appearance of a multilayer electronic component according to an embodiment of the present invention; [Figure 4] FIG. 2 is an explanatory diagram showing the pattern-forming surfaces of the first to third dielectric layers in the laminate of the multilayer electronic component according to the embodiment of the present invention. [Figure 5] FIG. 2 is an explanatory diagram showing pattern-forming surfaces of fourth to sixth dielectric layers in a laminate of a multilayer electronic component according to one embodiment of the present invention. [Figure 6] FIG. 2 is an explanatory diagram showing pattern-forming surfaces of seventh to ninth dielectric layers in a laminate of a multilayer electronic component according to one embodiment of the present invention. [Figure 7] FIG. 2 is an explanatory diagram showing pattern-forming surfaces of the tenth to twelfth dielectric layers in the laminate of the multilayer electronic component according to the embodiment of the present invention. [Figure 8] FIG. 2 is an explanatory diagram showing pattern-forming surfaces of the 13th to 22nd dielectric layers in the laminate of the multilayer electronic component according to one embodiment of the present invention. [Figure 9] FIG. 2 is an explanatory diagram showing pattern-forming surfaces of the 23rd and 24th dielectric layers in the laminate of the multilayer electronic component according to one embodiment of the present invention. [Figure 10] 1 is a perspective view showing the inside of a laminate of a multilayer electronic component according to an embodiment of the present invention; [Figure 11] 1 is a perspective view showing the inside of a laminate of a multilayer electronic component according to an embodiment of the present invention; [Figure 12] 12 is a side view showing a part of the inside of the stack shown in FIGS. 10 and 11. FIG. [Figure 13] 12 is a side view showing a part of the inside of the stack shown in FIGS. 10 and 11. FIG. [Figure 14] 12 is a side view showing a part of the inside of the stack shown in FIGS. 10 and 11. FIG. [Figure 15] 12 is a side view showing a part of the inside of the stack shown in FIGS. 10 and 11. FIG. [Figure 16] 12 is a plan view showing a part of the inside of the stack shown in FIGS. 10 and 11. FIG. [Figure 17] 12 is a plan view showing a part of the inside of the stack shown in FIGS. 10 and 11. FIG. [Figure 18] FIG. 3 is a characteristic diagram showing the transmission attenuation characteristics between a common port and a first signal port in a multilayer electronic component according to an embodiment of the present invention. [Figure 19] FIG. 4 is a characteristic diagram showing the attenuation characteristics of transmission signals between a common port and a second signal port in a multilayer electronic component according to an embodiment of the present invention. [Figure 20] FIG. 10 is an explanatory diagram showing pattern formation surfaces of the 22nd and 23rd dielectric layers in a laminate of a modified example of the multilayer electronic component according to the embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0017] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. First, with reference to Fig. 1, an outline of the configuration of a multilayer electronic component (hereinafter simply referred to as an electronic component) 1 according to an embodiment of the present invention will be described. Fig. 1 shows a duplexer as an example of the electronic component 1. The duplexer includes a first filter 10 that selectively passes a first signal having a frequency within a first passband, and a second filter 20 that selectively passes a second signal having a frequency within a second passband higher than the first passband.

[0018] The electronic component 1 further includes a common port 2, a first signal port 3, a second signal port 4, a first signal path 5 connecting the common port 2 and the first signal port 3, and a second signal path 6 connecting the common port 2 and the second signal port 4. A first filter 10 is provided between the common port 2 and the first signal port 3 in terms of the circuit configuration. A second filter 20 is provided between the common port 2 and the second signal port 4 in terms of the circuit configuration. The first signal path 5 is a path from the common port 2 to the first signal port 3 via the first filter 10. The second signal path 6 is a path from the common port 2 to the second signal port 4 via the second filter 20.

[0019] A first signal having a frequency within a first passband is selectively passed through a first signal path 5 provided with a first filter 10. A second signal having a frequency within a second passband is selectively passed through a second signal path 6 provided with a second filter 20. In this way, the electronic component 1 separates the first and second signals.

[0020] Next, an example of the configuration of the first filter 10 will be described with reference to FIG. 1. The first filter 10 includes inductors L11, L12, and L13, and capacitors C11, C12, C13, C14, C15, and C16. The inductors L11 and L12 are provided on the first signal path 5 in the circuit configuration. Furthermore, the inductor L11 is provided closer to the first signal port 3 than the inductor L12 in the circuit configuration. One end of the inductor L11 is connected to the first signal port 3. The other end of the inductor L11 is connected to one end of the inductor L12. The other end of the inductor L12 is connected to the common port 2.

[0021] The capacitor C11 is connected in parallel to the inductor L11. The capacitor C12 is connected in parallel to the inductor L12. One end of the capacitor C13 is connected to one end of the inductor L11. The other end of the capacitor C13 is connected to the other end of the inductor L12.

[0022] One end of the capacitor C14 is connected to one end of the inductor L11. One end of the capacitor C15 is connected to the connection point between the inductors L11 and L12. The other ends of the capacitors C14 and C15 are connected to one end of the inductor L13. The other end of the inductor L13 is connected to ground. The capacitor C16 is connected in parallel to the inductor L13. In terms of the circuit configuration, the inductor L13 is provided between the first signal path 5 and ground.

[0023] Next, an example of the configuration of the second filter 20 will be described with reference to Fig. 2. The second filter 20 includes inductors L21 and L22 and capacitors C21, C22, C23, C24, C25, C26, C27, C28, C29, C30, and C31. One end of the capacitor C21 is connected to the second signal port 4. The other end of the capacitor C21 is connected to one end of the capacitor C22. The other end of the capacitor C22 is connected to one end of the capacitor C23. The other end of the capacitor C23 is connected to the common port 2.

[0024] One end of the capacitor C24 is connected to one end of the capacitor C21. The other end of the capacitor C24 is connected to the other end of the capacitor C22. One end of the capacitor C25 is connected to the connection point between the capacitors C22 and C23.

[0025] In terms of the circuit configuration, inductor L21 is provided between the second signal path 6 and ground. Inductor L21 includes inductor portions 211 and 212. One end of inductor portion 211 is connected to the connection point between capacitors C21 and C22. The other end of inductor portion 211 is connected to one end of inductor portion 212. The other end of inductor portion 212 is connected to ground.

[0026] In terms of the circuit configuration, the inductor L22 is provided between the second signal path 6 and ground. Furthermore, in terms of the circuit configuration, the inductor L22 is provided closer to the common port 2 than the inductor L21. The inductor L22 includes inductor portions 221 and 222. One end of the inductor portion 221 is connected to the other end of the capacitor C25. The other end of the inductor portion 221 is connected to one end of the inductor portion 222. The other end of the inductor portion 222 is connected to ground.

[0027] The inductor portion 211 of the inductor L21 and the inductor portion 221 of the inductor L22 are magnetically coupled to each other. The inductor portion 212 of the inductor L21 and the inductor portion 222 of the inductor L22 are not magnetically coupled to each other.

[0028] Capacitor C26 is connected in parallel to inductor portion 211 of inductor L21. Capacitor C27 is connected in parallel to inductor portion 212 of inductor L21. One end of capacitor C28 is connected to one end of inductor portion 211. The other end of capacitor C28 is connected to the other end of inductor portion 212.

[0029] Capacitor C29 is connected in parallel to inductor portion 221 of inductor L22. Capacitor C30 is connected in parallel to inductor portion 222 of inductor L22. One end of capacitor C31 is connected to one end of inductor portion 221. The other end of capacitor C31 is connected to the other end of inductor portion 222.

[0030] Next, other configurations of the electronic component 1 will be described with reference to Fig. 3. Fig. 3 is a perspective view showing the appearance of the electronic component 1.

[0031] The electronic component 1 further includes a laminate 50 including a plurality of laminated dielectric layers and a plurality of conductors. The laminate 50 integrates the common port 2, the first signal port 3, the second signal port 4, the inductors L11, L12, L13, L21, and L22, and the capacitors C11 to C16 and C21 to C31. The first filter 10 and the second filter 20 are each constructed using a plurality of conductors.

[0032] The laminate 50 has a bottom surface 50A and a top surface 50B located at both ends in the stacking direction T of the multiple dielectric layers, and four side surfaces 50C to 50F connecting the bottom surface 50A and the top surface 50B. The side surfaces 50C and 50D face in opposite directions from each other, and the side surfaces 50E and 50F also face in opposite directions from each other. The side surfaces 50C to 50F are perpendicular to the top surface 50B and the bottom surface 50A.

[0033] Here, the X direction, Y direction, and Z direction are defined as shown in FIG. 3. The X direction, Y direction, and Z direction are perpendicular to each other. In this embodiment, a direction parallel to the stacking direction T is defined as the Z direction. Furthermore, the direction opposite to the X direction is defined as the −X direction, the direction opposite to the Y direction is defined as the −Y direction, and the direction opposite to the Z direction is defined as the −Z direction.

[0034] As shown in FIG. 3, the bottom surface 50A is located at the end of the laminate 50 in the -Z direction. The top surface 50B is located at the end of the laminate 50 in the Z direction. The bottom surface 50A and the top surface 50B each have a rectangular shape that is long in the X direction. The side surface 50C is located at the end of the laminate 50 in the -X direction. The side surface 50D is located at the end of the laminate 50 in the X direction. The side surface 50E is located at the end of the laminate 50 in the -Y direction. The side surface 50F is located at the end of the laminate 50 in the Y direction.

[0035] When viewed from the Z direction, the planar shape of the laminate 50, i.e., the shape of the bottom surface 50A (the shape of the top surface 50B), is rectangular. The long sides of this rectangle are parallel to the X direction, and the short sides of this rectangle are parallel to the Y direction.

[0036] The electronic component 1 further includes signal terminals 112, 113, and 114 provided on the bottom surface 50A of the laminate 50, and ground terminals 111, 115, 116, 117, 118, and 119 connected to ground. The ground terminal 111 is located near a corner at the intersection of the bottom surface 50A, the side surface 50D, and the side surface 50E. The signal terminal 113 is located near a corner at the intersection of the bottom surface 50A, the side surface 50D, and the side surface 50F. The signal terminal 114 is located near a corner at the intersection of the bottom surface 50A, the side surface 50C, and the side surface 50F. The ground terminal 115 is located near a corner at the intersection of the bottom surface 50A, the side surface 50C, and the side surface 50E.

[0037] The signal terminal 112 is disposed between the ground terminal 111 and the ground terminal 115. The ground terminal 116 is disposed between the ground terminal 111 and the signal terminal 113. The ground terminal 117 is disposed between the signal terminal 113 and the signal terminal 114. The ground terminal 118 is disposed between the signal terminal 114 and the ground terminal 115. The ground terminal 119 is disposed in the center of the bottom surface 50A.

[0038] Signal terminal 112 corresponds to common port 2, signal terminal 113 corresponds to first signal port 3, and signal terminal 114 corresponds to second signal port 4. Therefore, common port 2, first signal port 3, and second signal port 4 are provided on the bottom surface 50A of the laminate 50.

[0039] Next, an example of the plurality of dielectric layers and the plurality of conductors constituting the laminate 50 will be described with reference to Figures 4(a) to 9(b). In this example, the laminate 50 has 24 laminated dielectric layers. Hereinafter, these 24 dielectric layers will be referred to as the 1st to 24th dielectric layers, in order from the bottom up. The 1st to 24th dielectric layers will be denoted by reference numerals 51 to 74.

[0040] In Figures 4(a) to 8(c), multiple circles represent multiple through holes. Multiple through holes are formed in each of the dielectric layers 51 to 72. The multiple through holes are formed by filling holes for the through holes with conductive paste. Each of the multiple through holes is connected to a conductive layer or another through hole.

[0041] Fig. 4(a) shows the pattern-formed surface of the first dielectric layer 51. Terminals 111 to 119 are formed on the pattern-formed surface of the dielectric layer 51. Fig. 4(b) shows the pattern-formed surface of the second dielectric layer 52. Conductor layers 521, 522, 523, 524, and 525 are formed on the pattern-formed surface of the dielectric layer 52.

[0042] 4(c) shows the pattern formation surface of the third dielectric layer 53. Conductor layers 531, 532, 533, 534, 535, 536, 537, 538, 539, 5310, 5311, and 5312 are formed on the pattern formation surface of the dielectric layer 53. One end of the conductor layer 531 is connected to the conductor layer 5311. The other end of the conductor layer 531 is connected to the conductor layer 5312. In FIG. 4(c), the boundaries between the conductor layers 531 and 5311 and the boundaries between the conductor layers 531 and 5312 are indicated by dotted lines.

[0043] FIG. 5(a) shows the pattern formation surface of the fourth dielectric layer 54. Conductor layers 541, 542, 543, 544, 545, 546, 547, and 548 are formed on the pattern formation surface of the dielectric layer 54. The conductor layers 541 and 543 are connected to the conductor layer 542. FIG. 5(b) shows the pattern formation surface of the fifth dielectric layer 55. Conductor layers 551, 552, 553, and 554 are formed on the pattern formation surface of the dielectric layer 55. The conductor layer 554 is connected to the conductor layer 553. FIG. 5(c) shows the pattern formation surface of the sixth dielectric layer 56. Conductor layers 561 and 562 are formed on the pattern formation surface of the dielectric layer 56.

[0044] FIG. 6(a) shows the pattern formation surface of the seventh dielectric layer 57. Conductor layers 571 and 572 are formed on the pattern formation surface of the dielectric layer 57. Conductor layer 572 is connected to conductor layer 571. FIG. 6(b) shows the pattern formation surface of the eighth dielectric layer 58. No conductor layer is formed on the pattern formation surface of the dielectric layer 58. FIG. 6(c) shows the pattern formation surface of the ninth dielectric layer 59. Conductor layer 591 is formed on the pattern formation surface of the dielectric layer 59.

[0045] FIG. 7(a) shows the pattern-forming surface of the tenth dielectric layer 60. A conductor layer 601 is formed on the pattern-forming surface of the dielectric layer 60. FIG. 7(b) shows the pattern-forming surface of the eleventh dielectric layer 61. No conductor layer is formed on the pattern-forming surface of the dielectric layer 61. FIG. 7(c) shows the pattern-forming surface of the twelfth dielectric layer 62. Conductor layers 621 and 622 are formed on the pattern-forming surface of the dielectric layer 62. The shapes of the conductor layers 621 and 622 when viewed from a direction parallel to the stacking direction T (Z direction) may be the same.

[0046] FIG. 8(a) shows the pattern-formed surface of the 13th dielectric layer 63. Conductor layers 631 and 632 are formed on the pattern-formed surface of the dielectric layer 63. When viewed from a direction parallel to the stacking direction T (Z direction), the shapes of the conductor layers 631 and 632 may be the same. FIG. 8(b) shows the pattern-formed surfaces of the 14th to 21st dielectric layers 64 to 71. No conductor layer is formed on the dielectric layers 64 to 71. FIG. 8(c) shows the pattern-formed surface of the 22nd dielectric layer 72. Conductor layers 721, 722, 723, 724, 725, 726, and 727 are formed on the pattern-formed surface of the dielectric layer 72. When viewed from a direction parallel to the stacking direction T (Z direction), the shapes of the conductor layers 722, 723, and 724 may be the same. When viewed from one direction parallel to the stacking direction T (Z direction), the shapes of the conductor layers 726 and 727 may be the same.

[0047] FIG. 9(a) shows the pattern formation surface of the 23rd dielectric layer 73. Conductor layers 731, 732, 733, 734, 735, 736, and 737 are formed on the pattern formation surface of the dielectric layer 73. The shapes of the conductor layers 732, 733, and 734 when viewed from a direction parallel to the stacking direction T (Z direction) may be the same. The shapes of the conductor layers 736 and 737 when viewed from a direction parallel to the stacking direction T (Z direction) may be the same. FIG. 9(b) shows the pattern formation surface of the 24th dielectric layer 74. A mark 741 made of a conductor layer is formed on the pattern formation surface of the dielectric layer 74.

[0048] The laminate 50 shown in Figure 2 is constructed by stacking the first to twenty-fourth dielectric layers 51 to 74 so that the pattern-forming surface of the first dielectric layer 51 becomes the bottom surface 50A of the laminate 50, and the surface opposite the pattern-forming surface of the twenty-fourth dielectric layer 74 becomes the top surface 50B of the laminate 50.

[0049] Each of the multiple through holes shown in Figures 4(a) to 8(c) is connected to a conductor layer that overlaps it in the stacking direction T when the 1st to 22nd dielectric layers 51 to 72 are stacked, or to another through hole that overlaps it in the stacking direction T. Furthermore, of the multiple through holes shown in Figures 4(a) to 8(c), a through hole located within a terminal or a conductor layer is connected to that terminal or that conductor layer.

[0050] 10 and 11 show the inside of the laminate 50, which is formed by stacking the 1st to 24th dielectric layers 51 to 74. As shown in Fig. 10 and 11, the multiple conductor layers and multiple through holes shown in Fig. 4(a) to Fig. 9(a) are stacked inside the laminate 50. Note that the mark 741 is omitted in Fig. 10 and 11.

[0051] The laminate 50 is fabricated by a low-temperature co-firing method, for example, using ceramic as the material for the dielectric layers 51-74. In this case, first, a plurality of ceramic green sheets that will later become the dielectric layers 51-74 are fabricated. Each ceramic green sheet has a plurality of pre-fired conductor layers that will later become a plurality of conductor layers and a plurality of pre-fired through holes that will later become a plurality of through holes. Next, the plurality of ceramic green sheets are stacked to fabricate a green sheet laminate. Next, this green sheet laminate is cut to fabricate a pre-fired laminate. Next, the ceramic and conductor in this pre-fired laminate are fired in a low-temperature co-firing process to complete the laminate 50.

[0052] Next, the configurations of inductors L11, L12, L13, L21, and L22 will be described in detail with reference to FIGS. 4(a) to 15. FIGS. 12 to 15 are side views showing a portion of the interior of the laminate 50. FIG. 12 shows a portion of the interior of the laminate 50 as seen from the side surface 50D, mainly showing inductors L11, L12, and L13. FIG. 13 shows a portion of the interior of the laminate 50 as seen from the side surface 50E, mainly showing inductors L12, L13, and L22. FIG. 14 shows a portion of the interior of the laminate 50 as seen from the side surface 50C, mainly showing inductors L21 and L22. FIG. 15 shows a portion of the interior of the laminate 50 as seen from the side surface 50F, mainly showing inductors L11 and L21.

[0053] The inductors L11, L12, L13, L21, and L22 are each integrated into the laminate 50. As will be described later, each of the inductors L11, L12, L21, and L22 includes a plurality of through-hole rows. Each of the plurality of through-hole rows is configured by connecting two or more through-hole rows aligned in the lamination direction T in series.

[0054] First, the configuration of the inductor L11 will be described. As shown in Fig. 12 and Fig. 15, the inductor L11 is Parallel In this embodiment, the axis A11 extends in a direction parallel to the Y direction.

[0055] Furthermore, the inductor L11 includes one conductor portion wound less than one turn around the axis A11. The conductor portion of the inductor L11 includes a conductor layer portion 11C1 (see FIGS. 10 and 11). The conductor layer portion 11C1 has a shape that is elongated in a direction parallel to the X direction. The conductor layer portion 11C1 includes conductor layers 721 and 731 (see FIGS. 8(c) and 9(a)) that are arranged at different positions in the stacking direction T and are connected in parallel by four through holes. Each of the conductor layers 721 and 731 extends in a direction parallel to the X direction.

[0056] The conductor portion of the inductor L11 further includes two through-hole rows 11T1 and two through-hole rows 11T2 (see FIGS. 10 and 11). The two through-hole rows 11T1 are connected in parallel to a portion of the conductor layer portion 11C1 near one longitudinal end. The two through-hole rows 11T2 are connected in parallel to a portion of the conductor layer portion 11C1 near the other longitudinal end.

[0057] Next, the configuration of the inductor L12 will be described. As shown in Figures 12 and 13, the inductor L12 is wound around an axis A12 that is parallel to a direction perpendicular to the stacking direction T. In this embodiment, the axis A12 extends in a direction parallel to the X direction. The inductor L12 includes conductor portions L12A, L12B, and L12C that are each wound around the axis A12 less than one turn, a connection portion L12D that connects the conductor portions L12A and L12B in series, and a connection portion L12E that connects the conductor portions L12B and L12C in series.

[0058] The conductor portions L12A, L12B, and L12C include conductor layer portions 12C1, 12C2, and 12C3, respectively (see FIGS. 10 and 11). Each of the conductor layer portions 12C1, 12C2, and 12C3 has a shape that is elongated in a direction parallel to the Y direction.

[0059] The conductor layer portion 12C1 includes conductor layers 722 and 732 (see FIGS. 8(c) and 9(a)) that are arranged at different positions in the stacking direction T and that are connected in parallel by two through holes. The conductor layer portion 12C2 includes conductor layers 723 and 733 (see FIGS. 8(c) and 9(a)) that are arranged at different positions in the stacking direction T and that are connected in parallel by two through holes. The conductor layer portion 12C3 includes conductor layers 724 and 734 (see FIGS. 8(c) and 9(a)) that are arranged at different positions in the stacking direction T and that are connected in parallel by two through holes. Each of the conductor layers 722 to 724 and 732 to 734 extends in a direction parallel to the Y direction.

[0060] The conductor portion L12A further includes through-hole rows 12T1 and 12T2 (see FIGS. 10 and 11). The through-hole row 12T1 is connected to a portion of the conductor layer portion 12C1 near one end in the longitudinal direction. The through-hole row 12T2 is connected to a portion of the conductor layer portion 12C1 near the other end in the longitudinal direction.

[0061] The conductor portion L12B further includes through-hole rows 12T3 and 12T4 (see FIGS. 10 and 11). The through-hole row 12T3 is connected to a portion of the conductor layer portion 12C2 near one end in the longitudinal direction. 12T4 is connected to a portion of the conductor layer portion 12C2 near the other end in the longitudinal direction.

[0062] The conductor portion L12C further includes through-hole rows 12T5 and 12T6 (see FIGS. 10 and 11). The through-hole row 12T5 is connected to a portion of the conductor layer portion 12C3 near one longitudinal end. The through-hole row 12T6 is connected to a portion of the conductor layer portion 12C3 near the other longitudinal end.

[0063] The connection portion L12D connects the through-hole row 12T2 of the conductor portion L12A and the through-hole row 12T3 of the conductor portion L12B. The connection portion L12D also includes a conductor layer portion 12C4 (see FIG. 10). The conductor layer portion 12C4 includes conductor layers 621 and 631 (see FIGS. 7(c) and 8(a)) that are arranged at different positions in the stacking direction T and are connected in parallel by two through holes.

[0064] The connection portion L12E connects the through-hole row 12T4 of the conductor portion L12B and the through-hole row 12T5 of the conductor portion L12C. The connection portion L12E also includes a conductor layer portion 12C5 (see FIG. 10). The conductor layer portion 12C5 includes conductor layers 622 and 632 (see FIGS. 7(c) and 8(a)) that are arranged at different positions in the stacking direction T and are connected in parallel by two through holes.

[0065] 5(a) and 5(b) are arranged at different positions in the stacking direction T and are connected in parallel by three through holes. The conductor layers 542 and 552 connect the through hole rows 11T3 and 11T4 of the conductor portion of the inductor L11 to the through hole row 12T1 of the conductor portion L12A of the inductor L12.

[0066] Next, the configuration of the inductor L13 will be described. The inductor L13 is wound around an axis A13 parallel to the lamination direction T. The inductor L13 is formed by a conductor layer 531 (see FIG. 4(c)).

[0067] Next, the configuration of the inductor L21 will be described. As shown in Figures 14 and 15, the inductor L21 is wound around an axis A21 that is parallel to a direction perpendicular to the stacking direction T. In this embodiment, the axis A21 particularly extends in a direction parallel to the Y direction.

[0068] Furthermore, inductor L21 includes one conductor portion wound less than one turn around axis A21. The conductor portion of inductor L21 includes conductor layer portion 21C1 (see FIGS. 10 and 11). Conductor layer portion 21C1 includes conductor layers 725 and 735 (see FIGS. 8(c) and 9(a)) that are arranged at different positions in stacking direction T and connected in parallel by two through holes. Each of conductor layers 725 and 735 includes a first portion extending in the X direction and a second portion extending in the Y direction.

[0069] The conductor portion of the inductor L21 further includes through-hole rows 21T1 and 21T2 (see FIGS. 10 and 11). The through-hole row 21T1 is connected to a portion of the conductor layer portion 21C1 near one longitudinal end. The through-hole row 21T2 is connected to a portion of the conductor layer portion 21C1 near the other longitudinal end.

[0070] The inductor L21 further includes conductor layer portions 21C2 and 21C3 (see FIG. 11). The conductor layer portion 21C1 connects one end of the through-hole row 21T1 and one end of the through-hole row 21T2. The conductor layer portion 21C2 is connected to the other end of the through-hole row 21T1 and extends toward the other end of the through-hole row 21T2. The conductor layer portion 21C3 is connected to the other end of the through-hole row 21T2 and extends toward the other end of the through-hole row 21T1.

[0071] The conductor layer portion 21C2 includes conductor layers 561 and 571 (see FIGS. 5(c) and 6(a)) that are arranged at different positions in the stacking direction T and that are connected in parallel by two through holes. The conductor layer portion 21C3 includes conductor layers 544 and 553 (see FIGS. 5(a) and 5(b)) that are arranged at different positions in the stacking direction T and that are connected in parallel by two through holes.

[0072] The conductor layer portions 21C1 and 21C2 and the through-hole rows 21T1 and 21T2 form an inductor portion 211 of the inductor L21. The conductor layer portion 21C3 forms an inductor portion 212 of the inductor L21. The conductor layer portion 21C3 (conductor layers 544 and 553) is connected to the ground terminal 117 via the conductor layers 526 and 5310 (see FIGS. 4(b) and 4(c)) and a plurality of through-holes.

[0073] Next, the configuration of the inductor L22 will be described. As shown in Figures 13 and 14, the inductor L22 is wound around an axis A22 that is parallel to a direction orthogonal to the stacking direction T. In this embodiment, the axis A22 extends in a direction parallel to the Y direction. The inductor L22 also includes conductor portions L22A and L22B that are each wound around the axis A22 less than one turn, and a connection portion L22C that connects the conductor portions L22A and L22B in series.

[0074] The conductor portions L22A and L22B include conductor layer portions 22C1 and 22C2, respectively (see FIGS. 10 and 11). Each of the conductor layer portions 22C1 and 22C2 has a shape that is elongated in a direction parallel to the X direction.

[0075] The conductor layer portion 22C1 includes conductor layers 726 and 736 (see FIGS. 8(c) and 9(a)) that are arranged at different positions in the stacking direction T and that are connected in parallel by four through holes. The conductor layer portion 22C2 includes conductor layers 727 and 737 (see FIGS. 8(c) and 9(a)) that are arranged at different positions in the stacking direction T and that are connected in parallel by four through holes. Each of the conductor layers 726, 727, 736, and 737 extends in a direction parallel to the X direction.

[0076] The conductor portion L22A further includes two through-hole rows 22T1 and two through-hole rows 22T2 (see FIGS. 10 and 11). The two through-hole rows 22T1 are connected in parallel to a portion near one longitudinal end of the conductor layer portion 22C1. The two through-hole rows 22T2 are connected in parallel to a portion near the other longitudinal end of the conductor layer portion 22C1.

[0077] The conductor portion L22B further includes two through-hole rows 22T3 and two through-hole rows 22T4 (see FIGS. 10 and 11). The two through-hole rows 22T3 are connected in parallel to a portion near one longitudinal end of the conductor layer portion 22C2. The two through-hole rows 22T4 are connected in parallel to a portion near the other longitudinal end of the conductor layer portion 22C2.

[0078] The connection portion L22C connects the two through-hole rows 22T2 of the conductor portion L22A and the two through-hole rows 22T3 of the conductor portion L22B. The connection portion L22C also includes a conductor layer portion 22C3 (see FIGS. 10 and 11). The conductor layer portion 22C3 includes conductor layers 591 and 601 (see FIGS. 6(c) and 7(a)) that are arranged at different positions in the stacking direction T and are connected in parallel by four through holes.

[0079] The conductor portion L22A constitutes the inductor portion 221 of the inductor L22. The conductor portion L22B constitutes the inductor portion 222 of the inductor L22. In terms of the circuit configuration, the conductor portion L22B is provided between the conductor portion L22A and the ground. The two through-hole rows 22T4 of the conductor portion L22B are connected to the ground terminals 115 and 118 via the conductor layers 525 and 539 (see FIGS. 4(b) and 4(c)) and multiple through-holes.

[0080] Next, the correspondence between capacitors C11 to C16, C21 to C31 and the internal components of the laminate 50 shown in Figures 4(a) to 9(b) will be described. Capacitor C11 is composed of conductor layers 521, 532, 541, and 551 shown in Figures 4(b) to 5(a), 8(c), and 9(a), and dielectric layers 52, 53, and 54 between these conductor layers. Capacitor C12 is composed of conductor layers 621, 622, 631, 632, 722 to 724, and 732 to 734 shown in Figures 7(c), 8(a), 8(c), and 9(a), and dielectric layers 62 and 72 between these conductor layers. Capacitor C13 is composed of conductor layers 721 to 724 and 731 to 734.

[0081] Capacitor C14 is composed of conductor layers 5311 and 532 shown in Fig. 4(c). Capacitor C15 is composed of conductor layer 5311, conductor layer 542 shown in Fig. 5(a), and dielectric layer 53 between these conductor layers. Capacitor C16 is composed of conductor layers 5312 and 543 shown in Fig. 4(c) and Fig. 5(a), and dielectric layer 53 between these conductor layers.

[0082] Capacitor C21 is composed of conductor layers 533 and 545 shown in FIGS. 4(c) and 5(a) and a dielectric layer 53 between these conductor layers. Capacitor C22 is composed of conductor layers 534 and 545 shown in FIGS. 4(c), 5(a), and 5(c) and a dielectric layer 53 between these conductor layers. Capacitor C23 is composed of conductor layers 535 and 546 shown in FIGS. 4(c) and 5(a) and a dielectric layer 53 between these conductor layers. Capacitor C24 is composed of conductor layers 533 and 534. Capacitor C25 is composed of conductor layers 536, 546, and 547 shown in FIGS. 4(c), 5(a), and 5(c) and a dielectric layer 53 between these conductor layers.

[0083] Capacitor C26 is composed of conductor layers 561, 571, 725, and 735 shown in Figures 5(c), 6(a), 8(c), and 9(a), and dielectric layers 56 and 72 between these conductor layers. Capacitor C27 is composed of conductor layers 544 and 553 shown in Figures 5(a) and 5(b), and dielectric layer 54 between these conductor layers. Capacitor C28 is composed of conductor layers 554 and 572 shown in Figures 5(b) and 6(a), and dielectric layers 55 and 56 between these conductor layers.

[0084] The capacitor C29 is composed of the conductor layers 591, 601, 726, and 736 shown in Figures 6(c), 7(a), 8(c), and 9(a), and the dielectric layers 59 and 72 between these conductor layers. The capacitor C30 is composed of the conductor layers 591 and 601, and the dielectric layers 59 and 72 shown in Figures 8(c) and 9(a). Conductor layer 4(c) and 5(a), and the dielectric layer 53 between these conductor layers.

[0085] Next, structural features of electronic component 1 according to this embodiment will be described with reference to Figures 10 to 17. Figures 16 and 17 are plan views showing part of the interior of laminate 50 shown in Figures 10 and 11.

[0086] 10 to 15, the inductor L12 is disposed ahead of the inductor L11 in one direction perpendicular to the stacking direction T, i.e., in the −Y direction. The inductors L21 and L22 are disposed ahead of the inductors L11 and L12 in one direction perpendicular to the stacking direction T, i.e., in the −X direction.

[0087] 12 and 15, the area surrounded by a dashed line labeled S11 indicates the space that includes the axis A11 and is surrounded by inductor L11. Also, in FIGS. 12 and 13, the area surrounded by a dashed line labeled S12 indicates the space that includes the axis A12 and is surrounded by inductor L12. Also, in FIGS. 14 and 15, the area surrounded by a dashed line labeled S21 indicates the space that includes the axis A21 and is surrounded by inductor L21. Also, in FIGS. 13 and 14, the area surrounded by a dashed line labeled S22 indicates the space that includes the axis A22 and is surrounded by inductor L22.

[0088] 15, the area surrounded by the dashed line and marked with the symbol S11 is also the area obtained by vertically projecting the space S11 onto a virtual plane (XZ plane) perpendicular to the axis A11. Hereinafter, this area will be referred to as the projected area of ​​the space S11. The area of ​​the projected area of ​​the space S11 corresponds to the opening area of ​​the inductor L11.

[0089] 12, the area surrounded by the dashed line and marked with the symbol S12 is also the area obtained by vertically projecting the space S12 onto a virtual plane (YZ plane) perpendicular to the axis A12. Hereinafter, this area will be referred to as the projected area of ​​the space S12. The area of ​​the projected area of ​​the space S12 corresponds to the opening area of ​​the inductor L12.

[0090] 15, the area surrounded by the dashed line and marked with the symbol S21 is also the area obtained by vertically projecting the space S21 onto a virtual plane (XZ plane) perpendicular to the axis A21. Hereinafter, this area will be referred to as the projection area of ​​the space S21. The area of ​​the projection area of ​​the space S21 corresponds to the opening area of ​​the inductor L21.

[0091] 13, the area surrounded by the dashed line and marked with the symbol S22 is also the area obtained by vertically projecting the space S22 onto a virtual plane (XZ plane) perpendicular to the axis A22. Hereinafter, this area will be referred to as the projection area of ​​the space S22. The area of ​​the projection area of ​​the space S22 corresponds to the opening area of ​​the inductor L22.

[0092] 12 and 15, the area of ​​the projection region of the space S11 is larger than the area of ​​the projection region of the space S12. Also, as shown in Figures 12 and 15, the area of ​​the projection region of the space S21 is larger than the area of ​​the projection region of the space S12. Also, as shown in Figures 12 and 13, the area of ​​the projection region of the space S22 is larger than the area of ​​the projection region of the space S12.

[0093] 13 and 15, the area of ​​the projection region of the space S21 and the area of ​​the projection region of the space S22 are different from each other. In particular, in this embodiment, the area of ​​the projection region of the space S21 is larger than the area of ​​the projection region of the space S22. Furthermore, the dimension of the projection region of the space S21 in the stacking direction T is larger than the dimension of the projection region of the space S22 in the stacking direction T.

[0094] The inductor L11 is disposed so that a portion of the space S11 overlaps at least a portion of the space S12 when viewed from one direction (Y direction) parallel to the axis A11.

[0095] The inductor L12 is disposed so that at least a portion of the space S12 overlaps with the space S22 when viewed from one direction (X direction) parallel to the axis A12. The inductor L12 is also disposed so that the axis A12 is parallel to the long side of the bottom surface 50A of the laminate 50 (the long side of the top surface 50B).

[0096] The inductor L13 is disposed so that the axis A13 does not intersect with the spaces S11, S21, and S22 but intersects with the space S12. In other words, the inductor L13 is disposed so as to overlap with the inductor L12 when viewed from the Z direction. No capacitor conductor layer used to form a capacitor is interposed between the inductor L12 and the inductor L13, specifically, between the conductor layer 531 (see FIG. 4(c)) and the conductor layers 621 and 622 (see FIG. 7(c)).

[0097] The inductor L21 is disposed so that a portion of the space S21 overlaps with at least a portion of the space S22 when viewed from a direction parallel to the axis A21 (the Y direction). In other words, the inductor L22 is disposed so that at least a portion of the space S22 overlaps with a portion of the space S21 when viewed from a direction parallel to the axis A22 (the Y direction).

[0098] The conductor layer portion 21C3 of the inductor L21 is disposed between the conductor layer portion 21C1 of the inductor L21 and the bottom surface 50A. When viewed from one direction (Z direction) parallel to the stacking direction T, the conductor layer portion 21C3 extends so as to cross the signal terminal 114. The inductor L21 is electrically connected to the ground terminal 117. The inductor L22 is electrically connected to the ground terminals 115 and 118.

[0099] The inductor L22 includes a conductor portion L22A that constitutes an inductor portion 221 of the inductor L22 and a conductor portion L22B that constitutes an inductor portion 222 of the inductor L22. Conductor part The inductor L21 includes a connecting portion L22C that connects the conductor portions L22A and L22B in series. The conductor portion L22A (inductor portion 221) is magnetically coupled to the conductor layer portions 21C1 and 21C2 and the through-hole rows 21T1 and 21T2 that configure the inductor portion 211 of the inductor L21.

[0100] 17 shows two conductor layers 721 and 731 that constitute the conductor layer portion 11C1 of the inductor L11. As shown in FIG. 17, the area of ​​the conductor layer 721 is larger than the area of ​​the conductor layer 731. When viewed from one direction (Z direction) parallel to the stacking direction T, the conductor layer 731 is disposed inside the outer edge of the conductor layer 721. When viewed from the Z direction, the shape of the conductor layer 731 is similar to the shape of the conductor layer 721 when viewed from the Z direction. The conductor layer 721 is disposed between the conductor layer 731 and the axis A11.

[0101] The above description of the conductor layers 721 and 731 also applies to the set of conductor layers 72x and 73x (x is an integer between 2 and 7). If the conductor layers 721 and 731 in the above description of the conductor layers 721 and 731 are replaced with the conductor layers 72x and 73x, respectively, the description becomes the conductor layers 72x and 73x. Note that when describing the set of conductor layers 72x and 73x that form inductor L12, the axis A11 in the above description is replaced with the axis A12. Furthermore, when describing the set of conductor layers 725 and 735 that form inductor L21, the axis A11 in the above description is replaced with the axis A21. Furthermore, when describing the set of conductor layers 72x and 73x that form inductor L22, the axis A11 in the above description is replaced with the axis A22.

[0102] 16 shows two conductor layers 621, 631 that form the conductor layer portion 12C4 of the inductor L12. As shown in FIG. 16, the area of ​​the conductor layer 631 is larger than the area of ​​the conductor layer 621. When viewed from one direction (Z direction) parallel to the stacking direction T, the conductor layer 621 is disposed inside the outer edge of the conductor layer 631. When viewed from the Z direction, the shape of the conductor layer 621 is similar to the shape of the conductor layer 631 when viewed from the Z direction. The conductor layer 631 is disposed between the conductor layer 621 and the axis A12.

[0103] The above description of the conductor layers 621 and 631 also applies to the pair of conductor layers 622 and 632, the pair of conductor layers 561 and 571, the pair of conductor layers 543 and 553, and the pair of conductor layers 591 and 601. If the conductor layers 621 and 631 in the above description of the conductor layers 621 and 631 are replaced with the conductor layers 622 and 632, respectively, the description becomes the conductor layers 622 and 632.

[0104] Furthermore, if the conductor layers 621 and 631 in the above description of the conductor layers 621 and 631 are replaced with the conductor layers 561 and 571 or the conductor layers 543 and 553, respectively, and the axis A12 in the above description of the conductor layers 621 and 631 is replaced with the axis A21, the description becomes as to the conductor layers 561 and 571 or the conductor layers 543 and 553.

[0105] Furthermore, if the conductor layers 621 and 631 in the above description of the conductor layers 621 and 631 are replaced with the conductor layers 591 and 601, respectively, and the axis A12 in the above description of the conductor layers 621 and 631 is replaced with the axis A22, the description becomes as to the conductor layers 591 and 601.

[0106] Next, an example of the characteristics of the electronic component 1 according to this embodiment will be shown. Fig. 18 is a characteristics diagram showing the pass attenuation characteristics between the common port 2 and the first signal port 3, i.e., the pass attenuation characteristics of the first filter 10. Fig. 19 is a characteristics diagram showing the pass attenuation characteristics between the common port 2 and the second signal port 4, i.e., the pass attenuation characteristics of the second filter 20. In Figs. 18 and 19, the horizontal axis represents frequency, and the vertical axis represents attenuation.

[0107] 18, reference numeral 91 denotes an attenuation pole formed by the inductor L11, and reference numeral 92 denotes an attenuation pole formed by the inductor L12. The inductor L12 forms an attenuation pole 92 on the higher frequency side of the first pass band in the pass attenuation characteristics of the first filter 10. The inductor L11 forms an attenuation pole 91 between the first pass band and the attenuation pole 92 in the pass attenuation characteristics of the first filter 10. That is, in the pass attenuation characteristics of the first filter 10, the attenuation pole 91 formed by the inductor L11 is closer to the first pass band than the attenuation pole 92 formed by the inductor L12.

[0108] 19, reference numeral 93 denotes an attenuation pole formed by the inductor L21, and reference numeral 94 denotes an attenuation pole formed by the inductor L22. L21 In the pass attenuation characteristics of the second filter 20, the inductor L21 forms an attenuation pole 93 on the low-frequency side of the second pass band. The inductor L22 forms an attenuation pole 94 between the attenuation pole 93 and the second pass band in the pass attenuation characteristics of the second filter 20. That is, in the pass attenuation characteristics of the second filter 20, the attenuation pole 94 formed by the inductor L22 is closer to the second pass band than the attenuation pole 93 formed by the inductor L21.

[0109] An example of the inductance and Q value of each of inductors L11, L12, L13, L21, and L22 will be described below. In one example, the inductance of inductor L11 is 0.8 nH. The Q value of inductor L11 is 125. The inductance of inductor L12 is 3.4 nH. The Q value of inductor L12 is 113. The inductance of inductor L13 is 0.81 nH. The Q value of inductor L13 is 53. The inductance of inductor L21 is 1.5 nH. The Q value of inductor L21 is 73. The inductance of inductor L22 is 2.0 nH. The Q value of inductor L22 is 127.

[0110] Next, the operation and effect of electronic component 1 according to this embodiment will be described. In this embodiment, conductor layer portion 21C1 of inductor L21 includes two conductor layers 725, 735. As described above, in the manufacturing process of laminate 50, ceramic green sheets are laminated, each having a plurality of pre-fired conductor layers that will later become the plurality of conductor layers and a plurality of pre-fired through holes that will later become the plurality of through holes. If conductor layer 725 and conductor layer 735 are misaligned relative to each other due to misalignment of the ceramic green sheets or the plurality of pre-fired conductor layers, the characteristics of inductor L21 will change.

[0111] In contrast, in the present embodiment, the area of ​​the conductor layer 725 is larger than the area of ​​the conductor layer 735. Therefore, even if the conductor layer 735 is misaligned relative to the conductor layer 725, the entirety or most of the conductor layer 735 does not protrude from the conductor layer 725 when viewed from one direction (Z direction) parallel to the stacking direction T. As a result, according to the present embodiment, it is possible to suppress fluctuations in the characteristics of the inductor L21 caused by the conductor layer 725 and the conductor layer 735 being misaligned relative to each other.

[0112] The above description of conductor layers 725 and 735 also applies to the pair of conductor layers 72x and 73x (where x is an integer of 1 to 4, or 6 or 7), the pair of conductor layers 621 and 631, the pair of conductor layers 622 and 632, the pair of conductor layers 561 and 571, the pair of conductor layers 543 and 553, and the pair of conductor layers 591 and 601. Therefore, according to the present embodiment, it is possible to suppress variations in the characteristics of each of first filter 10 and second filter 20 caused by misalignment of the ceramic green sheets or multiple pre-fired conductor layers, etc., and as a result, it is possible to suppress variations in the characteristics of electronic component 1.

[0113] Here, the planar shape of the conductor layer refers to the shape of the conductor layer when viewed from a direction (Z direction) parallel to the stacking direction T. When viewed from a direction (Z direction) parallel to the stacking direction T, of the two conductor layers constituting each conductor layer portion, the conductor layer with the larger area may have a planar shape that protrudes from the conductor layer with the smaller area by 5 to 500 μm in all directions (directions parallel to the XY plane).

[0114] The effects of this embodiment will be described below with reference to the results of first to third simulations. First, the results of the first simulation, which investigated the variation in inductance of inductor L21, will be described. In the first simulation, a model of inductor L21 in this embodiment and a model of an inductor of a first comparative example were used. The configuration of the inductor of the first comparative example is the same as that of inductor L21, except for conductor layer portion 21C1. The inductor of the first comparative example includes the conductor layer portion of the comparative example instead of conductor layer portion 21C1. The conductor layer portion of the comparative example includes a first conductor layer and a second conductor layer that are arranged at different positions in the stacking direction T and connected in parallel by two through holes. The second conductor layer is located ahead of the first conductor layer in the Z direction.

[0115] In the first simulation, the planar shape of each of the first and second conductor layers is the same as the planar shape of conductor layer 735 in the present embodiment. That is, in the conductor layer portion of the comparative example, conductor layers having the same planar shape are stacked.

[0116] In the first simulation, the inductor L21 was designed to have an inductance of 1.452 nH, and the inductor of the first comparative example was designed to have an inductance of 1.444 nH. Here, the dimension in the planar shape of the conductor layer in a direction perpendicular to the longitudinal direction of the conductor layer is referred to as the width of the conductor layer. In the first simulation, the width of the conductor layer 725 of the inductor L21 was set to 225 μm, and the width of the conductor layer 735 of the inductor L21 was set to 175 μm. The widths of the first and second conductor layers were each set to 225 μm.

[0117] 1st simulationIn the first simulation, the inductance of inductor L21 was obtained when conductor layer 735 was shifted by 15 μm in each of the X direction, −X direction, Y direction, and −Y direction. In the second simulation, the inductance of the inductor of the first comparative example was obtained when the second conductor layer was shifted by 15 μm in each of the X direction, −X direction, Y direction, and −Y direction.

[0118] Tables 1 and 2 show the results of the first simulation. Table 1 shows the inductance values ​​(unit: nH) obtained by the first simulation. Table 2 shows the amount of inductance variation from the design value when the conductor layer 735 and the second conductor layer are shifted in the X direction, -X direction, Y direction, and -Y direction, respectively. Note that in the first simulation and the second simulation described below, the amount of variation is calculated as a percentage by dividing the difference between the inductance obtained by the simulation and the inductance of the design value by the inductance of the design value. In Tables 1 and 2, "First Comparative Example" and "L21" represent the inductor model of the first comparative example and the inductor L21 model, respectively. In Tables 1 and 2, "X direction," "-X direction," "Y direction," and "-Y direction" represent the directions in which the conductor layer 735 or the second conductor layer is shifted.

[0119] [Table 1]

[0120] [Table 2]

[0121] From Table 2, it can be seen that the absolute value of the amount of variation in inductance of inductor L21 is smaller than that of the inductor of the first comparative example.

[0122] Next, the results of a second simulation investigating the variation in inductance of inductor L12 will be described. In the second simulation, a model of inductor L12 in this embodiment and a model of an inductor of a second comparative example were used. The configuration of the inductor of the second comparative example is the same as the configuration of inductor L12, except for conductor layer portions 12C1, 12C2, and 12C3. The inductor of the second comparative example includes three conductor layer portions of the above-mentioned comparative example instead of conductor layer portions 12C1 to 12C3. In the second simulation, the shapes of the first and second conductor layers of the conductor layer portion of the comparative example are the same as the planar shape of conductor layer 732 in this embodiment.

[0123] In the second simulation, inductor L12 was designed to have an inductance of 3.289 nH, and the inductor of the second comparative example was designed to have an inductance of 3.274 nH. In the second simulation, the widths of the conductor layers 722, 723, and 724 of inductor L12 were each set to 246 μm, and the widths of the conductor layers 732, 733, and 734 of inductor L12 were each set to 196 μm. The widths of the first and second conductor layers were each set to 246 μm.

[0124] Second simulation Then, the inductance of the inductor L12 was calculated when each of the conductor layers 722, 723, and 724 was shifted by 15 μm in the X direction, the −X direction, the Y direction, and the −Y direction. No. 2 In the simulation, the inductance of the inductor of the second comparative example was obtained when the second conductor layer of each of the three conductor layer portions was shifted by 15 μm in the X direction, −X direction, Y direction, and −Y direction.

[0125] The results of the second simulation are shown in Tables 3 and 4. Table 3 shows the inductance values ​​(unit: nH) obtained by the second simulation. Table 4 shows the inductance values ​​(unit: nH) obtained by the second simulation. 722,723,724The figures show the amount of variation in inductance from the design value when the first and second conductor layers are shifted in the X, -X, Y, and -Y directions, respectively. In Tables 3 and 4, "Second Comparative Example" and "L12" represent the inductor model of the second comparative example and the inductor L12 model, respectively.

[0126] [Table 3]

[0127] [Table 4]

[0128] From Table 4, it can be seen that the absolute value of the inductor fluctuation amount of the inductor L12 is smaller than that of the inductor of the second comparative example.

[0129] As can be seen from the results of the first and second simulations, according to this embodiment, it is possible to suppress fluctuations in the characteristics of the inductor caused by misalignment of the conductor layers compared to an inductor including a conductor layer portion in which conductor layers of the same planar shape are stacked.

[0130] Tables 2 and 4 show that the inductance of the inductor of the first comparative example varies more significantly than that of the inductor of the second comparative example. That is, in inductors including conductor layer portions with an L-shaped planar shape, such as the inductor of the first comparative example and inductor L21, the amount of inductance variation when the conductor layers are misaligned is greater than in inductors including conductor layer portions with a linear planar shape, such as the inductor of the first comparative example and inductor L12. This is thought to be because, in the case of conductor layer portions with an L-shaped planar shape, the shortest path between the two through-hole rows connected by the conductor layer portions varies significantly depending on the misalignment of the conductor layers. Therefore, the effects of this embodiment are more pronounced in inductors including conductor layer portions with an L-shaped planar shape.

[0131] The above description of the inductor including a conductor layer portion having an L-shaped planar shape also applies to an inductor including a conductor layer portion having a U-shaped planar shape and an inductor including a conductor layer portion having a spirally wound planar shape.

[0132] Next, the results of a third simulation investigating the variation in the characteristics of the electronic component 1 will be described. In the third simulation, a model of an example corresponding to the electronic component 1 according to the present embodiment and a model of an electronic component according to a comparative example were used. The configuration of the electronic component according to the comparative example is the same as that of the electronic component 1, except for the conductor layer portions included in the inductors L11, L12, L21, and L22. The electronic component according to the comparative example includes the conductor layer portion of the comparative example described above as each conductor layer portion. The planar shape of each of the first and second conductor layers included in each conductor layer portion is the same as the planar shape of the conductor layer with the smaller area of ​​the two conductor layers included in the conductor layer portion of the present embodiment corresponding to that conductor layer portion.

[0133] In the third simulation, the fluctuations in the frequency characteristics of the first filter 10 and the second filter 20 were determined when the dielectric layer 23 was shifted by 15 μm in each of the X direction, the −X direction, the Y direction, and the −Y direction. Here, the frequency at which the attenuation amount is −10 dB when the frequency is increased from the first pass band in the frequency characteristics of the first filter 10 is referred to as the “first frequency.” Similarly, the frequency at which the attenuation amount is −10 dB when the frequency is decreased from the second pass band in the frequency characteristics of the second filter 20 is referred to as the “second frequency.” In the third simulation, the fluctuations in the first frequency were determined as the fluctuations in the frequency characteristics of the first filter 10. Specifically, the first frequency when the shift amount of the dielectric layer 23 was 0 μm was set as the reference frequency. The absolute value of the value expressed as a percentage was calculated as the fluctuations in the first frequency. In the third simulation, the amount of variation in the second frequency was calculated as the variation in the frequency characteristics of the second filter 20, similar to the amount of variation in the first frequency.

[0134] Tables 5 and 6 show the results of the third simulation. Table 5 shows the amount of variation in the first frequency obtained by the third simulation. Table 6 shows the amount of variation in the second frequency obtained by the third simulation. In Tables 5 and 6, "Comparative Example" and "Example" indicate the model of the electronic component of the comparative example and the model of the example, respectively. Also, in Tables 5 and 6, "X direction," "-X direction," "Y direction," and "-Y direction" indicate the directions in which the dielectric layer 23 is shifted.

[0135] [Table 5]

[0136] [Table 6]

[0137] Tables 5 and 6 show that the electronic component 1 according to this embodiment has smaller fluctuations in the first frequency and the second frequency than the electronic component of the comparative example. As can be seen from the results of the third simulation, this embodiment can suppress fluctuations in the characteristics of the first filter 10 and the second filter 20, and as a result, can suppress fluctuations in the characteristics of the electronic component 1.

[0138] Next, other effects of this embodiment will be described. In this embodiment, the area of ​​the projection region of the space S11 corresponding to the aperture area of ​​the inductor L11 is larger than the area of ​​the projection region of the space S12 corresponding to the aperture area of ​​the inductor L12. That is, in this embodiment, the area of ​​the projection region of the space S12 corresponding to the aperture area of ​​the inductor L12 is smaller than the area of ​​the projection region of the space S11 corresponding to the aperture area of ​​the inductor L11. This makes it possible to form a space for arranging another inductor near the inductor L12. In this embodiment, the inductor L13 is arranged in the space. As described above, the inductor L13 is arranged so that its axis A13 does not intersect with the space S11 but intersects with the space S12. Furthermore, in this embodiment, the inductors L11, L12, and L13 are wound around axes that are parallel and in different directions. In particular, in this embodiment, the axes A11, A12, and A13 are perpendicular to each other. For these reasons, according to this embodiment, the electronic component 1 can be made smaller while suppressing electromagnetic field coupling between the inductors L11, L12, and L13.

[0139] Furthermore, in this embodiment, the inductor L11 is arranged such that a portion of the space S11 overlaps at least a portion of the space S12 when viewed from one direction parallel to the axis A11. As a result, this embodiment allows the electronic component 1 to be made smaller than when the spaces S11 and S12 do not overlap each other.

[0140] Furthermore, according to the present embodiment, the first filter 10 includes inductors L11, L12, and L13. According to the present embodiment, the above-described characteristics of the inductors L11, L12, and L13 enable the area of ​​the first filter 10 within the laminate 50 to be reduced, and as a result, the electronic component 1 can be made smaller.

[0141] In addition, in this embodiment, the area of ​​the projection region of the space S12, which corresponds to the opening area of ​​the inductor L12, is smaller than the area of ​​the projection region of the space S22, which corresponds to the opening area of ​​the inductor L22. Furthermore, in this embodiment, the inductors L12, L13, and L22 are wound around axes that are parallel to each other and in different directions. In this embodiment, the axes A12, A13, and A22 are particularly perpendicular to each other. For these reasons, this embodiment enables the electronic component 1 to be miniaturized while suppressing electromagnetic field coupling between the inductors L12, L13, and L22.

[0142] Furthermore, in this embodiment, the inductor L12 is arranged such that a portion of the space S12 overlaps at least a portion of the space S22 when viewed from one direction parallel to the axis A12. This allows the electronic component 1 to be made smaller than when the spaces S12 and S22 do not overlap each other.

[0143] In addition, in this embodiment, no conductor layer for a capacitor is interposed between the inductor L12 and the inductor L13. As a result, according to this embodiment, the electronic component 1 can be made smaller than when a conductor layer for a capacitor is interposed between the inductor L12 and the inductor L13.

[0144] In this embodiment, the first filter 10 includes inductors L12 and L13, and the second filter 20 includes an inductor L22. According to this embodiment, the above-described characteristics of the inductors L12, L13, and L22 allow the first filter 10 and the second filter 20 to be closer to each other, thereby enabling the electronic component 1 to be miniaturized.

[0145] Incidentally, since the area of ​​the projection region of the space S12, which corresponds to the opening area of ​​the inductor L12, is small, the inductance of the inductor L12 is relatively small. In contrast, in this embodiment, the inductor L12 includes conductor portions L12A, L12B, and L12C, each wound less than one turn around the axis A12. That is, in this embodiment, the inductor L12 is wound approximately three times around the axis A12. As a result, according to this embodiment, the inductance of the inductor L12 can be increased. Furthermore, according to this embodiment, the dimension of the inductor L12 in the direction parallel to the axis A12 (the direction parallel to the X direction) can be increased. As a result, according to this embodiment, the space for arranging the inductor L13 can be increased.

[0146] Furthermore, in this embodiment, the inductor L12 is arranged so that the axis A12 is parallel to the long side of the bottom surface 50A (long side of the top surface 50B) of the laminate 50. As a result, according to this embodiment, the inductor L12 can be wound multiple times around the axis A12 while other inductors, specifically the inductor L22, are arranged in a direction parallel to the axis A12.

[0147] In this embodiment, the inductors L11 and L12 are provided on the first signal path 5 in the circuit configuration, and the inductor L13 is provided between the first signal path 5 and ground in the circuit configuration. The inductor L13 may have a smaller Q value than the inductors L11 and L12. As described above, in one example, the Q value of the inductor L11 is 125, the Q value of the inductor L12 is 113, and the Q value of the inductor L13 is 53. In this embodiment, the inductors L11 and L12, which preferably have a relatively large Q value, are wound around an axis perpendicular to the stacking direction T, and the inductor L13, which may have a relatively small Q value, is wound around an axis parallel to the stacking direction T. The inductor L13, which may have a relatively small Q value, is then disposed in a space formed near the inductor L12.

[0148] Furthermore, in this embodiment, the inductor L21 is disposed such that a portion of the space S21 overlaps with at least a portion of the space S22 when viewed from a direction parallel to the axis A21 (the Y direction). In other words, the inductor L22 is disposed such that at least a portion of the space S22 overlaps with a portion of the space S22 when viewed from a direction parallel to the axis A22 (the Y direction). In this embodiment, the axes A21 and A22 are particularly parallel. Therefore, in this embodiment, the inductors L21 and L22 are disposed such that the opening of the inductor L21 and the opening of the inductor L22 face each other and the inductors L21 and L22 overlap when viewed from the Y direction.

[0149] Here, inductor L21 and Consider adjusting the magnetic coupling between inductor L21 and inductor L22. For example, the magnetic coupling can be adjusted by shifting one of inductors L21 and L22 in the X direction or the -X direction. However, doing so results in wasted space within laminate 50, and the planar shape of electronic component 1 (shape viewed from the Z direction) becomes larger.

[0150] In contrast to this, in the present embodiment, the area of ​​the projection region of the space S21 and the area of ​​the projection region of the space S22 are made different from each other. As a result, according to the present embodiment, it is possible to adjust the magnetic coupling without shifting one of the inductors L21 and L22 in the X direction or the −X direction.

[0151] Incidentally, in order to adjust the area of ​​the projection region of the space S21, it is possible to increase the dimension of the inductor L21 in the stacking direction T. In this case, the distance from the bottom surface 50A of the laminate 50 to the inductor L21 becomes smaller. If a ground terminal is provided near the inductor L21, stray capacitance occurs between the inductor L21 and the ground terminal, which may prevent desired characteristics from being obtained.

[0152] In contrast, in this embodiment, the inductor L21 includes a conductor layer portion 21C2 connected to the other end of the through-hole row 21T1 and extending toward the other end of the through-hole row 21T2, and a conductor layer portion 21C3 connected to the other end of the through-hole row 21T2 and extending toward the other end of the through-hole row 21T1. According to this embodiment, at least one of the conductor layer portions 21C2 and 21C3 allows the inductor L21 to be positioned so as not to overlap with the ground terminal when viewed from one direction parallel to the stacking direction T (the Z direction). In particular, in this embodiment, the conductor layer portion 21C3 extends so as to cross the signal terminal 114 when viewed from one direction parallel to the stacking direction T (the Z direction). As a result, according to this embodiment, the dimension of the inductor L21 in the stacking direction T can be increased to adjust the area of ​​the projected region of the space S21.

[0153] As described above, according to this embodiment, the electronic component 1 can be reduced in size while adjusting the electromagnetic field coupling between the inductors L21 and L22.

[0154] Moreover, in this embodiment, the electronic component 1 includes a second filter 20 including inductors L21 and L22, and a first filter 10 that does not include inductors L21 and L22. In order to increase the isolation between the first filter 10 and the second filter 20, it is possible to provide a ground terminal at a position sandwiched between the first filter 10 and the second filter 20. In this embodiment, the conductor layer portion 21C3 is connected to the ground terminal 117 provided at a position sandwiched between the first filter 10 and the second filter 20. That is, according to this embodiment, the inductor L21 can be connected to the ground terminal 117 by the conductor layer portion 21C3 while increasing the isolation between the first filter 10 and the inductor L21.

[0155] In this embodiment, the inductor L22 includes conductor portions L22A and L22B. The conductor portion L22A is magnetically coupled to the inductor L21. That is, in this embodiment, a portion of the inductor L22 is magnetically coupled to the inductor L21. According to this embodiment, by configuring the inductors as described above, it is possible to adjust the magnetic coupling between the inductors L21 and L22.

[0156] In the present embodiment, in inductor L11, two through-hole rows are connected in parallel to each other near both longitudinal ends of conductor layer portion 11C1. In inductor L22, two through-hole rows are connected in parallel to each other near both longitudinal ends of conductor layer portion 22C1, and two through-hole rows are connected in parallel to each other near both longitudinal ends of conductor layer portion 22C2.

[0157] In inductor L12, one through-hole row is connected to each of the portions near both longitudinal ends of conductor layer portion 12C1, one through-hole row is connected to each of the portions near both longitudinal ends of conductor layer portion 12C2, and one through-hole row is connected to each of the portions near both longitudinal ends of conductor layer portion 12C3. In inductor L21, one through-hole row is connected to each of the portions near both longitudinal ends of conductor layer portion 21C1.

[0158] As described above, in this embodiment, in each of the inductors L11 and L22, multiple (two) through-hole rows are connected in parallel to one end of the conductor layer portion, thereby increasing the Q value of each of the inductors L11 and L22.

[0159] On the other hand, in the present embodiment, one row of through holes is connected to one end of the conductor layer portion in each of the inductors L12 and L21. As a result, according to the present embodiment, the electronic component 1 can be made smaller than when multiple rows of through holes are connected in parallel to one end of the conductor layer portion in all of the inductors L11, L12, L21, and L22.

[0160] In the first filter 10, it is preferable to increase the Q value of the inductor L11 that forms the attenuation pole 91 closest to the first pass band. In the second filter 20, it is preferable to increase the Q value of the inductor L22 that forms the attenuation pole 94 closest to the second pass band. From this perspective, in this embodiment, in each of the inductors L11 and L22, multiple (two) rows of through holes are connected in parallel to one end of the conductor layer portion, thereby increasing the Q value of each of the inductors L11 and L22.

[0161] Furthermore, in this embodiment, the inductor L12 is disposed ahead of the inductor L11 in the -Y direction, and the inductors L21 and L22 are disposed ahead of the inductors L11 and L12 in the -X direction, respectively. That is, in this embodiment, the inductors L11 and L12 are aligned in a row, and the inductors L21 and L22 are aligned in a row at a position different from the inductors L11 and L12. As a result, according to this embodiment, it is possible to reduce wasted space generated in the laminate 50 compared to a case where the inductors L11 and L22 are aligned in a row and the inductors L12 and L21 are aligned in a row at a position different from the inductors L11 and L22, and as a result, it is possible to reduce the size of the electronic component 1.

[0162] As described above, according to this embodiment, the electronic component 1 can be made smaller while increasing the Q value of each of the inductors L11 and L22.

[0163] In the present embodiment, the axis A11 around which the inductor L11 is wound and the axis A22 around which the inductor L22 is wound are parallel to each other. In particular, in the present embodiment, both the axes A11 and A22 extend in a direction parallel to the Y direction. Furthermore, in each of the inductors L11 and L22, the conductor layer portion has a shape that is elongated in the X direction. Therefore, according to the present embodiment, the dimension of the laminate 50 in the Y direction can be made smaller than when the axis A11 and the axis A22 are perpendicular to each other.

[0164] In this embodiment, the direction parallel to the axis A12 and the direction parallel to the axis A22 are perpendicular to each other. In particular, in this embodiment, the direction parallel to the axis A12 is the direction parallel to the X direction, and the direction parallel to the axis A22 is the direction parallel to the Y direction. In this embodiment, the inductor L12 is wound approximately three times around the axis A12 parallel to the X direction. As described above, the conductor layer portion of the inductor L22 has a shape that is long in the X direction. Therefore, according to this embodiment, it is possible to reduce wasted space that occurs when the inductor L12 is wound multiple times around the axis A12, compared to when the axis A22 is parallel to the X direction and the conductor layer portion of the inductor L22 has a shape that is short in the X direction.

[0165] [Variations] Next, a modified example of the electronic component 1 according to the present embodiment will be described with reference to Figures 20(a) and 20(b). In this modified example, the configuration of the 22nd dielectric layer 72 is different from the example shown in Figure 8(c). Figure 20(a) shows the pattern formation surface of the 22nd dielectric layer 72 in this modified example. On the pattern formation surface of the dielectric layer 72 shown in Figure 20(a), a conductor layer 1721 is formed instead of the conductor layer 721 shown in Figure 8(c).

[0166] In the modified example, the 23rd dielectric layer 73The configuration differs from the example shown in Fig. 9(a). Fig. 20(b) shows the pattern formation surface of the 23rd dielectric layer 73 in the modified example. On the pattern formation surface of the dielectric layer 73 shown in Fig. 20(b), a conductor layer 1731 is formed instead of the conductor layer 731 shown in Fig. 9(a).

[0167] The two conductor layers 1721 and 1731 constitute the conductor layer portion 11C1 of the inductor L11. do (See FIGS. 10 and 11.) The conductor layers 1721 and 1731 are arranged at different positions in the stacking direction T and are connected in parallel by four through holes. Each of the conductor layers 1721 and 1731 includes a first portion extending in the X direction and two second portions extending in the Y direction.

[0168] The area of ​​the conductor layer 1721 is larger than the area of ​​the conductor layer 1731. When viewed from one direction (Z direction) parallel to the stacking direction T, the conductor layer 1731 is disposed inside the outer edge of the conductor layer 1721. When viewed from the Z direction, the shape of the conductor layer 1731 is similar to the shape of the conductor layer 1721 when viewed from the Z direction. The conductor layer 1721 is disposed between the conductor layer 1731 and the axis A11 (see FIGS. 11 and 15).

[0169] The present invention is not limited to the above-described embodiment, and various modifications are possible. For example, the number of inductors included in each of first filter 10 and second filter 20 may be three or more.

[0170] Furthermore, the axes A11 and A12 may intersect at an angle other than 90°. Similarly, the axes A21 and A22 may intersect at an angle other than 90°.

[0171] Furthermore, in each of the inductors L11 and L22, three or more through-hole rows may be connected in parallel to one end of the conductor layer portion.

[0172] Furthermore, in each of the inductors L11, L12, L21, and L22, the conductor layer portion may include three or more conductor layers that are arranged at different positions in the stacking direction T and connected in parallel. When the conductor layer portion includes three conductor layers, the conductor layer with the smallest area among the three conductor layers may be interposed between the other two conductor layers. Alternatively, the conductor layer portion may be composed of a single conductor layer. [Explanation of symbols]

[0173] 1...electronic component, 2...common port, 3...first signal port, 4...second signal port, 5...first signal path, 6...second signal path, 10...first filter, 20...second filter, 50...laminated body, 50A...bottom surface, 50B...top surface, 50C-50F...side surfaces, 51-74...dielectric layers, 111, 115-119...ground terminals, 112-114...signal terminals, C11-C16, C21-C31...capacitors, L11, L12, L13, L21, L22...inductors, S11, S12, S21, S22...space.

Claims

1. A laminate including a plurality of laminated dielectric layers each formed of a ceramic green sheet; a first inductor integrated with the laminate and wound around a first axis perpendicular to the lamination direction of the plurality of dielectric layers; a second inductor integrated with the laminate and wound around a second axis perpendicular to the lamination direction; the first axis and the second axis are perpendicular to each other, each of the first inductor and the second inductor includes a first row of through holes, a second row of through holes, and a first conductor layer portion connecting one end of the first row of through holes to one end of the second row of through holes; each of the first through-hole row and the second through-hole row is configured by connecting two or more through-holes in series; the first conductor layer portion includes a first conductor layer and a second conductor layer that are arranged at different positions in the stacking direction and are connected in parallel, 10. A multilayer electronic component, wherein the area of ​​the first conductor layer is larger than the area of ​​the second conductor layer.

2. 2. The multilayer electronic component according to claim 1, wherein the second conductor layer is disposed inside the outer edge of the first conductor layer when viewed from a direction parallel to the stacking direction.

3. 3. The multilayer electronic component according to claim 1, wherein a shape of the second conductor layer when viewed from a direction parallel to the stacking direction is similar to a shape of the first conductor layer when viewed from a direction parallel to the stacking direction.

4. 4. The multilayer electronic component according to claim 1, wherein the first conductor layer is disposed between the second conductor layer and the first axis or the second axis.

5. 5. The multilayer electronic component according to claim 1, wherein each of the first conductor layer and the second conductor layer of at least one of the first inductor and the second inductor includes a first portion extending in a first direction perpendicular to the stacking direction, and a second portion extending in a second direction perpendicular to the stacking direction.

6. 5. The multilayer electronic component according to claim 1, wherein the first conductor layer and the second conductor layer of at least one of the first inductor and the second inductor extend in a direction perpendicular to the stacking direction.

7. each of the first conductor layer and the second conductor layer of the first inductor includes a first portion extending in a first direction perpendicular to the stacking direction and a second portion extending in a second direction perpendicular to the stacking direction; 5. The multilayer electronic component according to claim 1, wherein each of the first conductor layer and the second conductor layer of the second inductor extends in a direction perpendicular to the stacking direction.

8. each of the first inductor and the second inductor further includes a second conductor layer portion connected to the other end of the second row of through holes; the second conductor layer portion includes a third conductor layer and a fourth conductor layer stacked in the stacking direction, 8. The multilayer electronic component according to claim 1, wherein the fourth conductor layer has an area larger than that of the third conductor layer.

9. 9. The multilayer electronic component according to claim 8, wherein the fourth conductor layer is disposed between the third conductor layer and the first axis or the second axis.

10. Further, a filter is provided for selectively passing signals of frequencies within a specific passband; 10. The multilayer electronic component according to claim 1, wherein the filter includes the first inductor and the second inductor.

11. further comprising a first filter that selectively passes a first signal having a frequency within a first passband; a second filter that selectively passes a second signal having a frequency within a second passband; the first filter includes the first inductor; 10. The multilayer electronic component according to claim 1, wherein the second filter includes the second inductor.

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