Semiconductor Devices

Abstract

To address an issue that reduction of the power consumption is not sufficient in an existing semiconductor device.SOLUTION: In the semiconductor device according to an embodiment, a memory cell is controlled so that operation processing is stopped so that charge and discharge of charges for a data line is stopped for a part where an output value can be determined without performing information processing according to values stored in a memory cell and also so that information processing involving charge and discharge of charges for a data line can be properly performed for a part including a part where an output value needs to be determined by information processing.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, for example, a semiconductor device including a memory having a product-sum operation function. [Background technology]

[0002] In recent years, artificial intelligence has been used in many fields. This artificial intelligence requires the execution of a large number of product-sum operations. Therefore, the processing of product-sum operations is accelerated using a GPU (Graphics Processing Unit) or the like. Furthermore, in addition to the processing of product-sum operations, a large amount of data transfer processing also occurs in association with the processing. A problem arises in that the power consumption required for these processes becomes very large. Therefore, Patent Document 1 discloses a technology related to a semiconductor device that processes a large number of product-sum operations with low power consumption.

[0003] Patent Document 1 discloses a multiplication memory cell that is connected to two data lines, stores ternary data, and performs a multiplication-and-accumulation operation between the stored data, input data, and data on the data lines. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2020-129582 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the semiconductor device described in Patent Document 1, charging and discharging of electric charges to and from the data lines is repeated in all information processing cycles regardless of the type of operation, which results in a problem that the semiconductor device described in Patent Document 1 has a limited effect on reducing power consumption.

[0006] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] In one embodiment of a semiconductor device, in a portion where the output value can be determined without performing information processing based on the value stored in the memory cell, calculation processing is stopped so that charging and discharging of charge to the data line is stopped, while in a portion where the output value needs to be determined by information processing, the memory cell is controlled so that information processing involving charging and discharging of charge to the data line is performed appropriately. [Effects of the Invention]

[0008] In the semiconductor device according to the embodiment, the power consumption can be further reduced. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a block diagram of a semiconductor device according to a first embodiment. [Figure 2] 2 is a detailed block diagram of the periphery of a memory cell of the semiconductor device according to the first embodiment. FIG. [Figure 3] FIG. 2 is a circuit diagram of the data processing reference cell according to the first embodiment. [Figure 4] FIG. 2 is a circuit diagram of a memory cell according to the first embodiment. [Figure 5] FIG. 2 is a circuit diagram of a replica cell and a dummy cell according to the first embodiment. [Figure 6] FIG. 2 is a circuit diagram of a first determination circuit according to the first embodiment. [Figure 7] FIG. 3 is a circuit diagram of a second determination circuit according to the first embodiment. [Figure 8] 10 is a table illustrating the relationship between a set value and the number of data processing cycles at which the semiconductor device is stopped according to the first embodiment; [Figure 9] 4 is a timing chart illustrating an operation of the semiconductor device according to the first embodiment. [Figure 10] 10 is a table illustrating conditions for changing a set value in the semiconductor device according to the second embodiment. [Figure 11] FIG. 11 is a detailed block diagram of the periphery of a memory cell of a semiconductor device according to a third embodiment. [Figure 12] FIG. 11 is a circuit diagram of a second determination circuit according to a third embodiment. [Figure 13] FIG. 10 is a detailed block diagram of the periphery of a memory cell of a semiconductor device according to a fourth embodiment. [Figure 14] FIG. 10 is a circuit diagram of a first partial determination circuit according to a fourth embodiment. [Figure 15] FIG. 11 is a circuit diagram of a second partial determination circuit according to the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] For clarity of explanation, the following description and drawings have been omitted and simplified as appropriate. In addition, the same elements in each drawing are given the same reference numerals, and duplicate explanations are omitted as necessary.

[0011] The semiconductor device described below has a configuration in which multiple memory cells capable of holding ternary values ​​are connected to a data line provided in common to the multiple memory cells. A product of an input value to the memory cell and a value stored in the memory cell is added on the data line to perform a product-sum operation. The result of the product-sum operation is then successively compared with a reference value output by an information processing reference cell, and is finally output as a multi-bit output value. Such a semiconductor device will be described in detail below.

[0012] Embodiment 1 1 shows a block diagram of a semiconductor device according to the first embodiment. As shown in FIG. 1, the semiconductor device 1 according to the first embodiment includes a memory controller 10, an input buffer 11, a current source 12, a cell array 13, a constant current source 14, a determination circuit 15, and an interface controller 16.

[0013] The memory controller 10 is an external interface with the semiconductor device 1, and receives input values ​​from an externally provided semiconductor device, and outputs output values ​​generated within the semiconductor device 1 to the external device. The memory controller 10 may also have a function of controlling power supplies within the semiconductor device 1, such as a current source 12. The input buffer 11 converts the input values ​​input via the memory controller 10 into signals that control memory cells provided in the cell array 13, and drives the memory cells.

[0014] The current source 12 generates currents to be supplied to the first data line (hereinafter referred to as data line PBL), the second data line (hereinafter referred to as data line NBL), and the third data line (hereinafter referred to as data line DBL) of the cell array 13. The cell array 13 has memory cells arranged in a grid pattern. The constant current source 14 generates a constant current to drive the memory cells in the cell array 13. The decision circuit 15 decides the magnitude of the product-sum operation results from the memory cells in the cell array 13 and sequentially outputs the bits that make up the final output value, one bit at a time. The interface controller 16 generates, for example, a multi-bit final output value from the output value of the decision circuit 15 and transmits it to the memory controller 10. The interface controller 16 also functions as a control circuit that controls the constant current source 14 and the decision circuit 15 based on the decision signal output by the decision circuit 15.

[0015] The following description focuses on the configurations of the current source 12, cell array 13, constant current source 14, and decision circuit 15. Therefore, FIG. 2 shows a detailed block diagram of the memory cell periphery of the semiconductor device according to the first embodiment. In FIG. 2, the data lines PBL, NBL, and DBL are grouped into one data line group, and the circuits associated with one data line group are shown. In the semiconductor device 1 according to the first embodiment, the cell array 13 is provided with a plurality of data line groups, as well as a plurality of current sources 12, constant current sources 14, decision circuits 15, etc., associated with the data line groups.

[0016] As shown in FIG. 2, the semiconductor device 1 according to the first embodiment is provided with a plurality of memory cells (e.g., MC0 to MC127) connected to data lines PBL and NBL. An input value given to the memory cells is composed of multiple bits, and each memory cell receives a corresponding one bit of the input value. The memory cells output the product of the one-bit input value and a held value expressed as a ternary value. As will be described in detail later, the memory cells include a first memory cell that electrically connects the data line PBL to a constant current source 14 when a first value is held, and a second memory cell that electrically connects the data line NBL to the constant current source 14 when a second value is held. That is, the memory cell that outputs the first value among the plurality of memory cells is electrically connected to the data line PBL. The memory cell that outputs the second value among the plurality of memory cells is electrically connected to the data line NBL.

[0017] Further, an information processing reference cell (for example, an AD conversion REF cell 21) is provided so as to be connected to the data lines PBL and NBL. The AD conversion REF cell 21 provides a reference value, the value of which changes for each information processing cycle, to either the data line PBL or the data line NBL. The AD conversion REF cell 21 changes the reference value in response to a reference control signal REF. Further, the reference control signal REF is output by the interface controller 16.

[0018] A replica cell 23 and a plurality of dummy cells (e.g., dummy cells DC0 to DC127) are connected to the data line DBL. The cell array 13 outputs a comparison value indicating the number of memory cells connected to at least one of the data line PBL and the data line NBL according to a specified setting value (e.g., setting value REP) to the data line DBL. The dummy cells simulate the parasitic capacitance that the memory cells impart to the data line PBL or the data line NBL.

[0019] The current source 12 has PMOS transistors P1 to P5. The PMOS transistor P1 has a source connected to a power supply line Vd, a gate and a drain connected in common, and a drain connected to a data line PBL. The PMOS transistor P2 has a gate connected in common with the gate of the PMOS transistor P1, a source connected to the power supply line Vd, and a drain connected to a data line NBL. The PMOS transistor P3 has a gate connected in common with the gate of the PMOS transistor P4, a source connected to the power supply line Vd, and a drain connected to the data line PBL. The PMOS transistor P4 has a source connected to the power supply line Vd, a gate and a drain connected in common, and a drain connected to the data line NBL. The PMOS transistor P5 has a drain connected to the data line PBL.

[0020] That is, in the semiconductor device 1, a current flows through the data lines PBL and NBL, which is the sum of a current generated by a diode-connected PMOS transistor that supplies current to one data line and a current generated by a diode-connected PMOS transistor that supplies current to the other data line. Thus, in the semiconductor device 1, by using the current source 12, variations in the current supplied to the data lines PBL and NBL are reduced. In the example shown in FIG. 2, the data line DBL is supplied with current only from the PMOS transistor P5.

[0021] The constant current source 14 includes an NMOS transistor N1. The NMOS transistor N1 has a source grounded, a gate receiving a multiply-and-accumulate mode enable signal MACE, and a drain connected to a cell ground line CVSS. The cell ground line CVSS is connected to a plurality of memory cells, an AD conversion REF cell 21, a plurality of dummy cells, and a replica cell 23. The constant current source 14 generates a drive current via the cell ground line CVSS that causes the plurality of memory cells and the AD conversion REF cell 21 to drive the data line PBL and the data line NBL. The constant current source 14 also generates a drive current that causes the replica cell 23 to drive the data line DBL. The constant current source 14 supplies a ground voltage to the plurality of dummy cells. The product-sum operation mode enable signal MACE provided to the constant current source 14 is output by an interface controller 16.

[0022] The decision circuit 15 has a first decision circuit 22, a second decision circuit 24, an AND gate 25, and an AND gate 26 with an inverted input. The first decision circuit 22 outputs a binary signal indicating a different value depending on the magnitude relationship between the number of memory cells connected to the data line PBL and the number of memory cells connected to the data line NBL for each data processing cycle. The second decision circuit 24 activates a stop instruction signal MQS when at least one of the number of memory cells connected to the data line PBL and the number of memory cells connected to the data line NBL is smaller than a comparison value (a value determined based on the voltage generated by the data line DBL).

[0023] The AND gate 25 receives the sum-of-products operation mode enable signal MACE at one input and the trigger signal TRIG at the other input. The AND gate 25 performs a logical AND operation on the sum-of-products operation mode enable signal MACE and the trigger signal TRIG, and provides the result of the logical AND operation on the sum-of-products operation mode enable signal MACE and the trigger signal TRIG as the sense amplifier enable signal SAE to the first decision circuit 22. The inverting input AND gate 26 receives the least significant bit of the reference control signal REF at its inverting input terminal and the trigger signal TRIG at its non-inverting input terminal. The inverting input AND gate 26 then provides the trigger signal TRIG, which is input during a period when the least significant bit of the reference control signal REF is 0, to the second decision circuit 24 as the second sense enable signal SSE.

[0024] The first decision circuit 22 receives a power supply control enable signal PCEN and a sense amplifier enable signal SAE as control signals. The first decision circuit 22 operates during a period when both the power supply control enable signal PCEN and the sense amplifier enable signal SAE are in an enable state (for example, a high level). The second decision circuit 24 receives a power supply control enable signal PCEN and a second sense enable signal SSE as control signals. The second decision circuit 24 operates during a period when both the power supply control enable signal PCEN and the second sense enable signal SSE are in an enable state.

[0025] Next, a specific example of a circuit will be described for the circuit blocks shown in Fig. 2. Note that each circuit block can also be realized by circuits other than those shown below.

[0026] 3 shows a circuit diagram of the AD conversion REF cell 21 according to the first embodiment. As shown in FIG. 3, the AD conversion REF cell 21 has a plurality of pairs of two transistors connected in series between the data lines PBL and NBL. The AD conversion REF cell 21 also has control logic 31 that controls the transistors connected between the data lines PBL and NBL.

[0027] Each pair of two transistors connected in series between the data lines PBL and NBL has a different transistor size. FIG. 3 illustrates an example in which the AD conversion REF cell 21 is configured with transistor sizes of 64, 32, 16, 8, 4, 2, 1, and 0.5. The transistors constituting each transistor pair are connected to a node via a cell ground line CVSS. The control logic 31 includes an AND gate with an inverting input and an AND gate. A polarity control signal PNS is input to the inverting input terminal of the AND gate with an inverting input and one terminal of the AND gate. A bit of the reference control signal REF corresponding to the corresponding transistor pair is input to the non-inverting input terminal of the AND gate with an inverting input and the other terminal of the AND gate. For example, in the example illustrated in FIG. 3, the most significant bit of the reference control signal REF is input to the control logic 31 corresponding to the transistor pair with a transistor size of 64. As the transistor size decreases, the lower-order bits of the reference control signal REF are input. In the AD conversion REF cell 21, the output of an AND gate with an inverting input controls the transistor on the data line PBL side, and the output of the AND gate controls the transistor on the data line NBL side. Note that for the control logic 31 corresponding to the transistor set with a transistor size of 0.5, the output of an AND gate with an inverting input controls the transistor on the data line NBL side, and the output of the AND gate controls the transistor on the data line PBL side.

[0028] As a result, when the polarity control signal PNS selects the data line PBL side (for example, when it is at a low level), the AD conversion REF cell 21 extracts current from the data line PBL to the cell ground line CVSS using a transistor specified by the reference control signal REF for the data line PBL.On the other hand, when the polarity control signal PNS selects the data line NBL side (for example, when it is at a high level), the AD conversion REF cell 21 extracts current from the data line NBL to the cell ground line CVSS using a transistor specified by the reference control signal REF for the data line NBL.Note that transistors whose transistor size is set to 0.5 (for example, N308, N318) extract current from the data line on the opposite side to the other transistors to the cell ground line CVSS.

[0029] FIG. 4 shows a circuit diagram of a memory cell according to the first embodiment. Only one of the memory cells shown in FIG. 2 is shown in FIG. 4. As shown in FIG. 4, the memory cell includes a first memory cell 41 and a second memory cell 42. The memory cell also includes NMOS transistors N48, N49P, and N49N. One end of the NMOS transistor N48 is connected to the cell ground line CVSS, and the other end is connected to one end of the NMOS transistors N49P and N49N. The 0th bit of the input value INP is applied to the gate of the NMOS transistor N48. The other end of the NMOS transistor N49P is connected to the data line PBL. The gate of the NMOS transistor N49P is connected to the first memory cell 41. The other end of the NMOS transistor N49N is connected to the data line NBL. The gate of the NMOS transistor N49N is connected to the second memory cell 42.

[0030] The first memory cell 41 and the second memory cell 42 have a configuration that functions as an SRAM (Static Random Memory). Specifically, the first memory cell 41 has PMOS transistors P40 and P41 and NMOS transistors N40 to N43. The PMOS transistor P40 and the NMOS transistor N40 are connected in series between a power supply line and a ground line, and their gates are commonly connected. The PMOS transistor P41 and the NMOS transistor N41 are connected in series between a power supply line and a ground line, and their gates are commonly connected. The gates of the PMOS transistor P40 and the NMOS transistor N40 are connected to a node connecting the PMOS transistor P41 and the NMOS transistor N41 and one end of the NMOS transistor N43. The gates of the PMOS transistor P41 and the NMOS transistor N41 are connected to a node connecting the PMOS transistor P40 and the NMOS transistor N40 and one end of the NMOS transistor N42. The other end of the NMOS transistor N42 is connected to a complementary bit line BL. The other end of the NMOS transistor N43 is connected to the complementary bit line BLB. The word line WL[0] is connected to the gates of the NMOS transistors N42 and N43.

[0031] The second memory cell 42 also has PMOS transistors P42 and P43 and NMOS transistors N44 to N47. The PMOS transistor P42 and the NMOS transistor N44 are connected in series between the power supply line and the ground line, and their gates are commonly connected. The PMOS transistor P43 and the NMOS transistor N45 are connected in series between the power supply line and the ground line, and their gates are commonly connected. The gates of the PMOS transistor P42 and the NMOS transistor N44 are connected to a node connecting the PMOS transistor P43 and the NMOS transistor N45 and one end of the NMOS transistor N47. The gates of the PMOS transistor P43 and the NMOS transistor N45 are connected to a node connecting the PMOS transistor P42 and the NMOS transistor N45 and one end of the NMOS transistor N46. The other end of the NMOS transistor N46 is connected to the complementary bit line BL. The other end of the NMOS transistor N47 is connected to the complementary bit line BLB. Furthermore, the word line WL[1] is connected to the gates of the NMOS transistors N46 and N47.

[0032] A value is written in the memory cell by determining the state of the inverter in the first memory cell 41 using the complementary bit lines BL and BLB while the word line WL[0] is set to high level. A value is also written in the memory cell by determining the state of the inverter in the second memory cell 42 using the complementary bit lines BL and BLB while the word line WL[1] is set to high level.

[0033] The memory cell controls the open / close state of the NMOS transistor N49P based on the value held in the inverter formed by the PMOS transistor P40 and the NMOS transistor N40. The memory cell also controls the open / close state of the NMOS transistor N49N based on the value held in the inverter formed by the PMOS transistor P42 and the NMOS transistor N44.

[0034] In the memory cells shown in FIG. 4, when both the first memory cell 41 and the second memory cell 42 store a logical value of "0", the memory cells are considered to store a logical value of "0". When the first memory cell 41 stores a logical value of "1" and the second memory cell 42 stores a logical value of "0", the memory cells are considered to store a logical value of "+1". When the first memory cell 41 stores a logical value of "0" and the second memory cell 42 stores a logical value of "1", the memory cells are considered to store a logical value of "-1".

[0035] As a result, when a logical value of "0" is stored in the memory cell, both the NMOS transistor N49P and the NMOS transistor N49N are turned off, and no current flows from the data lines PBL and NBL to the constant current source 14, even if the input value INP is a logical value of "1".

[0036] On the other hand, when a logical value of "+1" is stored in the memory cell, the NMOS transistor N49P is turned on and the NMOS transistor N49N is turned off. At this time, if the input value INP is a logical value of "1", current flows from the data line PBL to the constant current source 14 via the NMOS transistor N49P and N48, which are on, and the voltage of the data line PBL drops. At this time, the voltage of the data line NBL does not drop. On the other hand, if the input value INP is a logical value of "0", the NMOS transistor N48 is turned off, so no current flows from the data lines PBL and NBL to the constant current source 14, and the voltages of the data lines PBL and NBL do not drop.

[0037] Furthermore, when a logical value of "-1" is stored in the memory cell, the NMOS transistor N49N is turned on and the NMOS transistor N49P is turned off. At this time, if the input value INP is a logical value of "1", a current flows from the data line NBL to the constant current source 14 via the NMOS transistor N49N and N48 which are on, causing the voltage of the data line NBL to drop, but not the voltage of the data line PBL. On the other hand, at this time, if the input value INP is a logical value of "0", the NMOS transistor N48 is turned off, so no current flows from the data lines PBL and NBL to the constant current source 14, and the voltages of the data lines PBL and NBL do not drop.

[0038] That is, the memory cells can be considered to have a first memory cell 41 used to store a logical value "+1" in the memory cell, and a second memory cell 42 used to store a logical value "-1" in the memory cell.

[0039] As a result, a multiplication operation is performed between the ternary value stored in the memory cell and the value of the input value INP. That is, six states are formed according to the logical value of the input value and the logical value of the memory cell: 0x0, 0x(+1), 0x(-1), 1x0, 1x(+1), and 1x(-1). In this case, a multiplication operation is performed between the logical value of the input value and the logical value stored in the memory cell. When the result of the multiplication operation is a logical value "1," a current flows between the data line PBL and the constant current source 14, and the voltage of the data line PBL drops. On the other hand, when the result of the multiplication operation is a logical value "-1," a current flows between the data line NBL and the constant current source 14, and the voltage of the data line NBL drops.

[0040] In the memory cells of the semiconductor device 1, currents according to the product operation results of the multiple memory cells connected to the data lines PBL and NBL are superimposed on each of the data lines PBL and NBL, and the current and voltage are determined on each of the data lines PBL and NBL. That is, a sum operation is performed by the data lines PBL and NBL to obtain the sum of the products obtained in the multiple memory cells. The result of the sum operation, which is the product-sum operation, is output via the data lines PBL and NBL.

[0041] Next, the replica cell 23 and the dummy cell will be described. FIG. 5 shows a circuit diagram of the replica cell and the dummy cell according to the first embodiment. First, the replica cell 23 has a replica transistor provided between the constant current source 14 and the data line DBL. The replica transistor changes either its logical transistor size or the time for which the constant current source 14 is connected to the data line DBL according to the magnitude of the set value REP. The example shown in FIG. 5 shows the replica cell 23 whose logical transistor size changes according to the magnitude of the set value. As shown in FIG. 5, the replica cell 23 has NMOS transistors N51 to N55 with different transistor sizes as replica transistors. In the example shown in FIG. 5, the NMOS transistor N51 has a transistor size of 16, the NMOS transistor N52 has a transistor size of 8, the NMOS transistor N53 has a transistor size of 4, the NMOS transistor N54 has a transistor size of 2, and the NMOS transistor N55 has a transistor size of 1. One end of the NMOS transistors N51 to N55 is connected to the data line DBL, and the other end is connected to the cell ground wiring CVSS. 5, the setting value REP is composed of five bits. The most significant bit of the setting value REP is input to the gate of the NMOS transistor N51, the fourth bit of the setting value REP is input to the gate of the NMOS transistor N52, the third bit of the setting value REP is input to the gate of the NMOS transistor N53, the second bit of the setting value REP is input to the gate of the NMOS transistor N54, and the least significant bit of the setting value REP is input to the gate of the NMOS transistor N55.

[0042] In other words, the replica cell 23 turns on at least one of the NMOS transistors N51 to N52 with a setting value REP whose logical value is 1, thereby drawing current from the data line DBL to the cell ground wiring CVSS at a current value according to the transistor size, thereby lowering the voltage of the data line DBL.

[0043] Each dummy cell has an NMOS transistor N56. One end of the NMOS transistor N56 is connected to the data line DBL, and the other end is open. The gate of the NMOS transistor N56 is connected to the cell ground line CVSS. This allows the dummy cell to simulate the parasitic capacitance that the NMOS transistor N49N of the memory cell imparts to the data line NBL or the parasitic capacitance that the NMOS transistor N49P imparts to the data line PBL on the data line DBL.

[0044] Next, a detailed description will be given of the first determination circuit 22. Fig. 6 shows a circuit diagram of the first determination circuit 22 according to the first embodiment. As shown in Fig. 6, the first determination circuit 22 includes PMOS transistors P61 to P65, NMOS transistors N61 to N63, an OR gate 61, inverters 62 and 63, an AND gate 64, a latch 65, a buffer 66, and transfer gates 67 and 68.

[0045] The sources of the PMOS transistors P61 and P62 are connected to the power supply line, and their drains are connected to one another by the PMOS transistor P63. The drain of the PMOS transistor P61 is connected to the node where the PMOS transistor P64 and the NMOS transistor N61 are connected. The drain of the PMOS transistor P62 is connected to the node where the PMOS transistor P65 and the NMOS transistor N62 are connected. A control signal is applied to the gates of the PMOS transistors P61 to P63 from an OR gate 61. The OR gate 61 outputs the logical sum of the power supply control enable signal PCEN and the sense amplifier enable signal SAE. In other words, when at least one of the power supply control enable signal PCEN and the sense amplifier enable signal SAE is at a high level, the PMOS transistors P61 to P63 are turned off. On the other hand, when both the power supply control enable signal PCEN and the sense amplifier enable signal SAE are at a low level, the PMOS transistors P61 to P63 are turned on.

[0046] The PMOS transistor P64 and the NMOS transistor N61 are connected in series between the power supply line and the drain of the NMOS transistor N63, and their gates are connected in common. The PMOS transistor P65 and the NMOS transistor N62 are connected in series between the power supply line and the drain of the NMOS transistor N63, and their gates are connected in common. The gates of the PMOS transistor P64 and the NMOS transistor N61 are connected to the node where the PMOS transistor P65 and the NMOS transistor N62 are connected, and are also connected to the data line NBL via a transfer gate 68. The gates of the PMOS transistor P65 and the NMOS transistor N62 are connected to the node where the PMOS transistor P64 and the NMOS transistor N61 are connected, and are also connected to the data line PBL via a transfer gate 67. In other words, the PMOS transistors P64, P65 and the NMOS transistors N61 to N63 form a latch-type sense amplifier structure using the NMOS transistor N63 as a current source.

[0047] The transfer gates 67 and 68 are turned on when the sense amplifier enable signal SAE goes low, and are turned off when the sense amplifier enable signal SAE goes high.

[0048] The AND gate 64 outputs the logical AND of the sense amplifier enable signal SAE and the product-sum operation mode enable signal MACE. In the first decision circuit 22, if both the sense amplifier enable signal SAE and the product-sum operation mode enable signal MACE are at a high level, the NMOS transistor N63 operates a decision cell formed by the PMOS transistors P64 and P65 and the NMOS transistors N61 and N62. In addition, the latch 65 enters an input passing state at the rising edge of the output of the AND gate 64, transmits the logical value of the connection node between the PMOS transistor P65 and the NMOS transistor N62 to the buffer 66, and captures the logical value at the falling edge.

[0049] That is, the first decision circuit 22 resets the decision cell while either the power control enable signal PCEN or the sense amplifier enable signal SAE is at a low level. Then, in a state where both the power control enable signal PCEN and the sense amplifier enable signal SAE are at a high level, the first decision circuit 22 sets the sense amplifier enable signal SAE and the product-accumulation operation mode enable signal MACE to a high level, so that the decision cell compares the magnitude of the potentials of the data lines PBL and NBL. Then, the first decision circuit 22 outputs the comparison result to the interface controller 16 as an MQ output by the buffer 66 via the latch 65, which is in an input passing state.

[0050] Next, a detailed description will be given of the second determination circuit 24. Fig. 7 shows a circuit diagram of the second determination circuit 24 according to the first embodiment. As shown in Fig. 7, the second determination circuit 24 includes PMOS transistors P71 to P77, NMOS transistors N71 to N77, an OR gate 71, a latch 72, and a buffer 73.

[0051] The sources of the PMOS transistors P71 and P72 are connected to the power supply wiring, and the drains are connected to each other by the PMOS transistor P73. The drain of the PMOS transistor P71 is connected to the node where the PMOS transistor P74 and the NMOS transistor N71 are connected. The drain of the PMOS transistor P72 is connected to the node where the PMOS transistor P75 and the NMOS transistor N72 are connected. The sources of the PMOS transistors P76 and P77 are connected to the power supply wiring. The drain of the PMOS transistor P76 is connected to the node where the NMOS transistor N71 and the NMOS transistor N73 are connected. The drain of the PMOS transistor P77 is connected to the node where the NMOS transistor N72 and the NMOS transistor N75 are connected.

[0052] A control signal is supplied to the gates of the PMOS transistors P71 to P73, P76, and P77 from an OR gate 71. The OR gate 71 outputs the logical sum of the power control enable signal PCEN and the second sense enable signal SSE. That is, when at least one of the power control enable signal PCEN and the second sense enable signal SSE is at a high level, the PMOS transistors P71 to P73, P76, and P77 are turned off. On the other hand, when both the power control enable signal PCEN and the second sense enable signal SSE are at a low level, the PMOS transistors P71 to P73, P76, and P77 are turned on.

[0053] Between the power supply wiring and the drain of NMOS transistor N77, PMOS transistor P74, NMOS transistor N71, NMOS transistor N73, and NMOS transistor N74 are connected in series in this order. The gate of PMOS transistor P74 and the gate of NMOS transistor N71 are connected in common. Between the power supply wiring and the drain of NMOS transistor N77, PMOS transistor P75, NMOS transistor N72, NMOS transistor N75, and NMOS transistor N76 are connected in series in this order. The gate of PMOS transistor P75 and the gate of NMOS transistor N72 are connected in common.

[0054] The gates of the PMOS transistor P74 and the NMOS transistor N71 are connected to the node connecting the PMOS transistor P75 and the NMOS transistor N72, and are also connected to the drain of the PMOS transistor P72. The gates of the PMOS transistor P75 and the NMOS transistor N72 are also connected to the node connecting the PMOS transistor P74 and the NMOS transistor N71, and are also connected to the drain of the PMOS transistor P71. The node connecting the NMOS transistor N71 and the NMOS transistor N73 is connected to the drain of the PMOS transistor P76. The node connecting the NMOS transistor N72 and the NMOS transistor N75 is connected to the drain of the PMOS transistor P77.

[0055] A second sense enable signal SSE is input to the gate of the NMOS transistor N77. The PMOS transistors P74, P75 and NMOS transistors N71 to N76 operate using the NMOS transistor N77 as a current source. The latch 72 passes the logical value of the connection node between the PMOS transistor P74 and the NMOS transistor N71 at the rising edge of the second sense enable signal SSE.

[0056] That is, the second decision circuit 24 resets the decision cell while both the power control enable signal PCEN and the second sense enable signal SSE are low. Then, with the power control enable signal PCEN at a high level, the second decision circuit 24 sets the second sense enable signal SSE at a high level, thereby causing the decision cell to compare the potential of the memory cells connected to the data line PBL and the total number of memory cells connected to the data line NBL with the number of cells designated by the set value REP. The second decision circuit 24 then raises the second sense enable signal SSE, causing the input of the latch 72 to pass through. The comparison result is output to the interface controller 16 as an MQS output by the buffer 73. In the semiconductor device 1, the interface controller 16 determines whether to enable or disable the multiply-accumulate operation mode enable signal MACE based on this MQS output.

[0057] FIG. 8 shows a table illustrating the relationship between the set value REP and the number of data processing cycles to be stopped in the semiconductor device 1 according to the first embodiment. As shown in FIG. 8, in the semiconductor device 1 according to the first embodiment, the number of data processing cycles required for AD conversion according to the number of cells performing the product-sum operation is originally eight, including the sign determination cycle, for 128 inputs. However, when the second determination circuit 24 determines that the number of cells connected to the data lines PBL and NBL is fewer than the number of cells specified by the set value REP output by the interface controller 16, the number of data processing cycles to be executed is determined by the value indicated by the number of data processing cycles associated with the set value REP. In the example shown in FIG. 8, when the NMOS transistor N51 of the replica cell 23 having a transistor size of 16 is specified by the set value REP, the number of data processing cycles can be changed to five. In this case, the data processing cycles performed using transistors having transistor sizes of 64 to 16 in the AD conversion REF cell 21 are stopped (three data processing cycles are stopped), and five data processing cycles are executed. The number of data processing cycles to be executed decreases as the set value REP decreases.

[0058] If the transistor in the replica cell 23 connected to the data line DBL by the set value REP is the NMOS transistor N51 with a transistor size of 16, the data line DBL will have the same potential as when 16 cells are connected to the data line PBL or the data line NBL. In this case, if the sum of the number of memory cells connected to the data line PBL and the number of memory cells connected to the data line NBL is less than 16, it is clear that the determination value of the data processing cycle when the transistor size of the transistor constituting the AD conversion REF cell 21 is 64, 32, or 16, which is greater than 16, is fixed at 0, and the correct value can be derived without calculating the part whose value is fixed. Therefore, in the semiconductor device 1 according to the first embodiment, the size of the part whose value is fixed is determined using the data line DBL, the replica cell 23, and the second determination circuit 24, and the current from the constant current source 14 supplied to the memory cells and the AD conversion REF cell 21 is cut off during the period when data processing is performed on the part that does not have a problem, thereby reducing power consumption.

[0059] Therefore, the operation of the semiconductor device 1 according to the first embodiment will be described. Fig. 9 shows a timing chart illustrating the operation of the semiconductor device 1 according to the first embodiment. In the example shown in Fig. 9, 8 is specified as the set value REP.

[0060] As shown in FIG. 9, in the semiconductor device 1, if one information processing period (the period during which the information processing result is switched in FIG. 8 ) is defined as the period during which the interface controller 16 determines one information processing result with a preset number of bits based on the output value of the first decision circuit 22, the second decision circuit 24 is selectively enabled in the first information processing cycle of the one information processing period. Specifically, one information processing period begins at timing T0. Therefore, the interface controller 16 sets the multiply-accumulate operation mode enable signal MACE to a high level at timing T0. Also, at timing T0, the least significant bit of the reference control signal REF is 0. Therefore, the sense amplifier enable signal SAE and the second sense enable signal SSE are set to a high level. This causes the first decision circuit 22 and the second decision circuit 24 to operate. In the example shown in FIG. 9 , the first decision circuit 22 outputs a high level MQ output, and the second decision circuit 24 outputs a low level MQS output. This means that the sum of the numbers of memory cells connected to the data lines PBL and NBL is smaller than eight for the input values ​​processed in the information processing period starting from timing T0.

[0061] After that, at timing T1, based on the MQS output being at a low level, the interface controller 16 sets the product-sum operation mode enable signal MACE to a low level so that the sense amplifier enable signal SAE is maintained at a low level for four data processing cycles. While the product-sum operation mode enable signal MACE is at a low level, the supply of current to the AD conversion REF cell 21, memory cells MC0 to MC127, and first decision circuit 22 is stopped. On the other hand, since conversion may be occurring on other data line groups in the cell array 13, the conversion processing cycle itself is not skipped even if the supply of current to the AD conversion REF cell 21, memory cells MC0 to MC127, and first decision circuit 22 is stopped.

[0062] Then, at timing T5, the interface controller 16 switches the multiply-accumulate operation mode enable signal MACE to high level, which causes the first decision circuit 22 to transmit an MQ output based on the result of the multiply-accumulate operation through information processing to the interface controller 16. After that, the result of the series of information processing is determined by the information processing up to T7.

[0063] Thereafter, a new information processing cycle is started, and at timing T8, similarly to timing T0, the interface controller 16 sets the multiply-accumulate operation mode enable signal MACE to high level, and the least significant bit of the reference control signal REF becomes 0, so that the second sense enable signal SSE and the sense amplifier enable signal SAE become high level. At this time, the second decision circuit 24 transmits a high level MQS output to the interface controller 16, so the interface controller 16 maintains the multiply-accumulate operation mode enable signal MACE at high level, and information processing is performed over one information processing period from timing T8 to T15 (not shown).

[0064] From the above explanation, in the semiconductor device 1 according to the first embodiment, attention is paid to the relationship between the number of memory cells connected to the data line PBL and the data line NBL and the bits whose values ​​are determined without the need for information processing, and power consumption is reduced by stopping the current supply to the AD conversion REF cell 21 and the memory cells for the bits whose values ​​are determined without the need for information processing.

[0065] In addition, in the semiconductor device 1 according to the first embodiment, when more memory cells than the number of memory cells specified by the setting value REP are connected to the data lines PBL and NBL, information processing is performed as usual to prevent information processing from being missed.

[0066] Furthermore, in recent years, the ratio of weighting coefficients with a value of 0 among the weighting coefficients used in deep learning and the like has decreased, and weighting coefficients with intermediate values ​​are often used, which has led to a demand for setting a range for stopping information processing according to the situation, as in the semiconductor device 1. For this reason, flexible settings such as those in the semiconductor device 1 have been effective in reducing power consumption in recent years. Furthermore, in deep learning, the weighting coefficients tend to become smaller as learning progresses, and the more advanced the artificial intelligence is in learning, the greater the power reduction effect can be achieved by applying the semiconductor device 1.

[0067] In the above embodiment, the set value REP is output by the interface controller 16, but the set value REP may be input from an external source. The set value REP may be specified not by the number of transistors connected to the data line, but by the number of data processing cycles to be stopped or the number of data processing cycles to be executed, and may be generated by a conversion process such as converting it into the number of transistors in an internal circuit of the interface controller 16 or the like.

[0068] Embodiment 2 In the second embodiment, an example in which the set value REP is dynamically changed will be described. The set value REP can be changed by, for example, the interface controller 16. Note that the set value REP may also be changed outside the semiconductor device 1.

[0069] Therefore, in the second embodiment, the interface controller 16 reduces the stop setting value when the activation rate of the stop instruction signal (e.g., MQS output) exceeds a predetermined first threshold, and increases the setting value when the activation rate of the MQS output falls below a second threshold that is smaller than the first threshold.

[0070] 10 shows a table for explaining the conditions for changing the set values ​​in the semiconductor device according to the second embodiment. Note that the table shown in FIG. 10 shows only an example, and the method for setting the conditions can be arbitrarily set depending on the specifications of the semiconductor device.

[0071] In the example shown in Figure 10, three conditions are shown for each maximum number of data bits (number of bits) of the input value. In Figure 10, the UP condition when the input value INP has 128 bits of data is defined as a condition to decrease the size of the set value REP by one when the number of transistors determined by the current set value REP is cleared eight consecutive times (i.e., when the MQS output is determined to be high level eight consecutive times). On the other hand, the DOWN condition when the input value INP has 128 bits of data is defined as a condition to increase the size of the set value REP by one when two overs are observed out of eight determinations made on the number of transistors determined by the current set value REP (i.e., when the MQS output is determined to be low level two times out of eight times).

[0072] 10, the UP condition when the input value INP has 64-bit data is that the size of the set value REP is decreased by one if the number of transistors determined by the current set value REP is cleared seven times in a row (i.e., the MQS output is determined to be high seven times in a row).On the other hand, the DOWN condition when the input value INP has 128-bit data is that the size of the set value REP is increased by one if two overs are observed in seven determinations of the number of transistors determined by the current set value REP (i.e., the MQS output is determined to be low two times out of seven).

[0073] 10, the UP condition when the input value INP has 32 bits of data is that the size of the set value REP is decreased by one if the number of transistors determined by the current set value REP is cleared six times in a row (i.e., the MQS output is determined to be high six times in a row).On the other hand, the DOWN condition when the input value INP has 128 bits of data is that the size of the set value REP is increased by one if two overs are observed in six determinations of the number of transistors determined by the current set value REP (i.e., the MQS output is determined to be low two times out of six).

[0074] In this way, by dynamically changing the setting value REP, an appropriate number of information processing cycle skips can be set even when the result of product-sum calculations increases or decreases in deep learning, etc., and power consumption can be reduced more than in the semiconductor device 1 of embodiment 1.

[0075] Embodiment 3 In the third embodiment, a semiconductor device 2 will be described, which is another embodiment of the semiconductor device 1 according to the first embodiment. A detailed block diagram of the periphery of a memory cell of the semiconductor device according to the third embodiment is shown in FIG.

[0076] 11, the semiconductor device 2 has a determination circuit 15a instead of the determination circuit 15. The determination circuit 15a is obtained by adding delay circuits 81 and 82 to the determination circuit 15 and replacing the second determination circuit 24 with a second determination circuit 84.

[0077] The delay circuit 81 delays the time at which the power supply control enable signal PCEN reaches the second determination circuit 84 compared to the first determination circuit 22. The delay circuit 82 delays the time at which the trigger signal TRIG reaches the second determination circuit 84 compared to the first determination circuit 22. That is, in the semiconductor device 2, the second determination circuit 84 operates with a time delay compared to the first determination circuit 22.

[0078] The second decision circuit 84 enables the MQS output when the difference between the number of memory cells connected to the data line PBL and the number of memory cells connected to the data line NBL is smaller than a comparison value derived from the set value REP. Therefore, a circuit diagram of the second decision circuit 84 according to the third embodiment is shown in FIG.

[0079] 12, the second decision circuit 84 is obtained by adding NMOS transistors N78 and N79, an inverter 83, and an EXOR gate 85 to the second decision circuit 24. Furthermore, the wiring of the second decision circuit 84 is changed from that of the second decision circuit 24.

[0080] Specifically, the NMOS transistor N78 is connected in parallel with the NMOS transistor N73, and the NMOS transistor N79 is connected in parallel with the NMOS transistor N75. The output of the latch 72 is output by an EXOR gate 85 as an exclusive OR with the MQ output.

[0081] In the second decision circuit 84, the MQ output is applied to the gate of the NMOS transistor N73. The inverted value of the MQ output is applied to the gate of the NMOS transistor N75. The data line DBL is connected to the gates of the NMOS transistors N78 and N79. The data line PBL is connected to the gate of the NMOS transistor N74. The data line NBL is connected to the gate of the NMOS transistor N76.

[0082] The second decision circuit 84 starts operating with a delay relative to the first decision circuit 22, in order to wait for the MQ output to be determined. When the MQ output is high, that is, when the number of memory cells connected to data line PBL is greater than the number of memory cells connected to data line NBL, the second decision circuit 84 inputs a high-level signal to the gate of NMOS transistor N73 and a low-level signal to the gate of NMOS transistor N75. This disables NMOS transistor N78, while NMOS transistor N79 passes a current according to the voltage of data line DBL.

[0083] By this operation, the sum of the number of memory cells on the data line with fewer memory cells connected and the number of memory cells specified by the set value REP is compared with the number of memory cells on the data line with more memory cells connected. In other words, the second decision circuit 84 enables the MQS output when the difference between the number of memory cells connected to the data line PBL and the number of memory cells connected to the data line NBL is smaller than the comparison value derived from the set value REP.

[0084] In the semiconductor device 1 according to the first embodiment, for example, the sum of the number of memory cells connected to the data line PBL and the number of memory cells connected to the data line NBL is compared with the number of memory cells indicated by the set value REP. Therefore, if the number of memory cells connected to the data line PBL is 5 and the number of memory cells connected to the data line NBL is 4, the total value is 9, so 6 data processing cycles are required.

[0085] On the other hand, in the second determination circuit 84 according to the third embodiment, if the number of memory cells connected to the data line PBL is 5 and the number of memory cells connected to the data line NBL is 4, the difference is 1. Therefore, in the third embodiment, the data processing cycle can be completed in two times.

[0086] That is, by using the second determination circuit 84 according to the third embodiment, the number of information processing cycles that must be executed can be reduced, thereby making it possible to further reduce power consumption.

[0087] Embodiment 4 In the fourth embodiment, a semiconductor device 3 will be described, which is another embodiment of the semiconductor device 1 according to the first embodiment. A detailed block diagram of the periphery of a memory cell of the semiconductor device according to the fourth embodiment is shown in FIG.

[0088] 13, the semiconductor device 3 has a judgment circuit 15b instead of the judgment circuit 15. The judgment circuit 15a is obtained by replacing the second judgment circuit 24 of the judgment circuit 15 with a second judgment circuit 94. The second judgment circuit 94 has a first partial judgment circuit (for example, a first partial judgment circuit 94p), a second partial judgment circuit (for example, a second partial judgment circuit 94n), and a selection circuit 91.

[0089] The first partial decision circuit 94p activates a first partial decision signal when the number of memory cells connected to the data line PBL is smaller than the sum of the comparison value and the number of memory cells connected to the data line NBL. The second partial decision circuit 94n activates a second partial decision signal when the number of memory cells connected to the data line NBL is smaller than the sum of the comparison value and the number of memory cells connected to the data line PBL. The selection circuit 91 selects the partial decision signal between the first and second partial decision signals, whichever is determined by the first decision circuit to have a larger number of memory cells connected to the data line, and outputs it as an MQS output.

[0090] FIG. 14 shows a circuit diagram of a first partial determination circuit 94p according to the fourth embodiment. As shown in FIG. 14, the first partial determination circuit 94p has wiring connections that are different from those of the second determination circuit 24. In the first partial determination circuit 94p, a power supply wiring is connected to the gate of the NMOS transistor N73. A data line PBL is connected to the gate of the NMOS transistor N74. A data line DBL is connected to the gate of the NMOS transistor N75. A data line NBL is connected to the gate of the NMOS transistor N76. With these connections, the first partial determination circuit 94p validates the first partial determination signal when the number of memory cells connected to the data line PBL is smaller than the sum of the comparison value and the number of memory cells connected to the data line NBL.

[0091] FIG. 15 shows a detailed block diagram of the periphery of a memory cell of a semiconductor device according to the fourth embodiment. As shown in FIG. 15, the second partial determination circuit 94n is obtained by changing the wiring connections of the second determination circuit 24. In the second partial determination circuit 94n, a data line DBL is connected to the gate of the NMOS transistor N73. A data line PBL is connected to the gate of the NMOS transistor N74. A power supply wiring is connected to the gate of the NMOS transistor N75. A data line NBL is connected to the gate of the NMOS transistor N76. With these connections, the second partial determination circuit 94n enables the second partial determination signal when the number of memory cells connected to the data line NBL is smaller than the sum of the comparison value and the number of memory cells connected to the data line PBL.

[0092] In the third embodiment, it was necessary to wait for the MQ output of the first decision circuit 22, but in the second decision circuit 94 according to the fourth embodiment, the first partial decision circuit 94p and the second partial decision circuit 94n each decide whether the difference in the number of memory cells connected to the data lines PBL and NBL is greater or smaller than the value designated by the set value REP, and the result of the decision is selected according to the MQ output. As a result, in the fourth embodiment, there is no need to provide a delay as in the third embodiment.

[0093] The invention made by the inventor has been specifically described above based on the embodiments, but it goes without saying that the present invention is not limited to the embodiments already described, and various modifications are possible within the scope of the gist of the invention. [Explanation of symbols]

[0094] 1-3 Semiconductor device 10 Memory Controller 11 Input Buffer 12 Current source 13 Cell Array 14 Constant current source 15 Judgment circuit 16 Interface Controller 21 AD conversion REF cell 22 First decision circuit 23 Replica Cells 24, 84, 94 Second decision circuit 31 Control Logic 41 first memory cell 42 second memory cell 81 Delay Circuit 82 Delay Circuit 91 Selection circuit 94p First partial decision circuit 94n Second partial decision circuit

Claims

1. a plurality of memory cells that output the product of an input value and a stored value expressed as a ternary value; a first data line electrically connected to a memory cell that outputs a first value among the plurality of memory cells; a second data line electrically connected to a memory cell that outputs a second value among the plurality of memory cells; a data processing reference cell that provides a reference value that changes for each data processing cycle to either the first data line or the second data line; a constant current source that generates a drive current for the plurality of memory cells and the information processing reference cell to drive the first data line and the second data line; a first determination circuit that outputs a binary signal indicating a different value in accordance with a magnitude relationship between the number of the memory cells connected to the first data line and the number of the memory cells connected to the second data line, for each data processing cycle; a third data line; a replica cell that outputs a comparison value indicating the number of memory cells connected to at least one of the first data line and the second data line to the third data line in accordance with a designated setting value; a second determination circuit that validates a stop instruction signal when at least one of the number of the memory cells connected to the first data line and the number of the memory cells connected to the second data line is smaller than the comparison value; a control circuit that outputs the set value and stops current output from the constant current source in response to the stop instruction signal indicating a valid state until the number of information processing cycles corresponding to the set value has elapsed; A semiconductor device having:

2. The plurality of memory cells each include a first memory cell that electrically connects the first data line to the constant current source when the first value is held; a second memory cell that electrically connects the second data line to the constant current source when the second value is held; 2. The semiconductor device according to claim 1, wherein the third value is represented by the first memory cell electrically isolating the first data line from the constant current source, and the second memory cell electrically isolating the second data line from the constant current source.

3. 2. The semiconductor device according to claim 1, wherein the control circuit selectively enables the second judgment circuit in the first information processing cycle of one information processing period, where the period during which one information processing result of a predetermined number of bits is determined by the output value of the first judgment circuit is defined as one information processing period.

4. 2. The semiconductor device according to claim 1, wherein the replica cell has a replica transistor arranged between the constant current source and the third data line, and the replica transistor changes either a logical transistor size or a time for connecting the constant current source and the third data line depending on the magnitude of the set value.

5. 2. The semiconductor device according to claim 1, further comprising a dummy cell connected to the third data line for simulating a parasitic capacitance that the memory cell imparts to the first data line or the second data line.

6. 2. The semiconductor device according to claim 1, wherein the second determination circuit enables the stop instruction signal when the sum of the number of memory cells connected to the first data line and the number of memory cells connected to the second data line is smaller than the comparison value.

7. 2. The semiconductor device according to claim 1, wherein the second determination circuit enables the stop instruction signal when a difference between the number of memory cells connected to the first data line and the number of memory cells connected to the second data line is smaller than the comparison value.

8. The second determination circuit a first partial determination circuit that enables a first partial determination signal when the number of memory cells connected to the first data line is smaller than the sum of the comparison value and the number of memory cells connected to the second data line; a second partial determination circuit that enables a second partial determination signal when the number of memory cells connected to the second data line is smaller than the sum of the comparison value and the number of memory cells connected to the first data line; a selection circuit that selects one of the first and second partial determination signals, which is determined by the first determination circuit to have a larger number of memory cells connected to a data line, and outputs the selected partial determination signal as the stop instruction signal; The semiconductor device according to claim 1 ,

9. 2. The semiconductor device according to claim 1, wherein the control circuit decreases the set value when the activation rate of the stop instruction signal exceeds a predetermined first threshold, and increases the set value when the activation rate of the stop instruction signal falls below a second threshold that is smaller than the first threshold.

10. 2. The semiconductor device according to claim 1, wherein the first data line, the second data line, and the third data line are grouped into one data line group, and the semiconductor device has a plurality of data line groups.

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