Semiconductor Devices

Abstract

To provide a semiconductor device with improved safety.SOLUTION: A semiconductor device comprises: a substrate; a first transistor of a depression type; a second transistor of an enhancement type; a gate control circuit; a gate terminal; and a power terminal. The first transistor is provided on the substrate and has a channel area including a nitride semiconductor of a first conductivity type. The second transistor is connected in series with the first transistor on the substrate and operates via an inversion layer of a second conductivity type being an opposite polarity of the first conductivity type. The gate control circuit is connected with a gate electrode of the second transistor on the substrate. The gate terminal is electrically connected with a gate electrode of the first transistor. The power terminal is electrically connected between the first transistor and the second transistor and constituted to supply power supply voltage to the gate control circuit.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The embodiments relate to a semiconductor device. [Background technology]

[0002] Transistors made of nitride semiconductors have a so-called HEMT (High Electron Mobility Transistor) structure, and most of them are depletion-mode. Therefore, it is preferable that power control semiconductor devices use a circuit configuration in which a nitride semiconductor transistor and an enhancement-mode transistor are connected in series. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2016-540477 Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiments provide a semiconductor device with improved safety. [Means for solving the problem]

[0005] A semiconductor device according to an embodiment includes a substrate, a first depletion-type transistor, a second enhancement-type transistor, a gate control circuit, a gate terminal, a power supply terminal, and an encapsulating member. The first transistor is provided on the substrate and has a channel region including a nitride semiconductor of a first conductivity type. The second transistor is connected in series to the first transistor on the substrate and operates via an inversion channel of a second conductivity type opposite to the first conductivity type. The gate control circuit is connected to a gate electrode of the second transistor on the substrate. The gate terminal is electrically connected to the gate electrode of the first transistor. The power supply terminal is electrically connected between the first transistor and the second transistor and is configured to supply a power supply voltage to the gate control circuit. The encapsulating member encapsulates the first transistor, the second transistor, and the gate control circuit on the substrate. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a schematic plan view showing a semiconductor device according to a first embodiment. [Figure 2] 1 is a schematic cross-sectional view showing a semiconductor device according to a first embodiment. [Figure 3] 1 is a circuit diagram illustrating a semiconductor device according to a first embodiment. [Figure 4] 3A to 3C are schematic diagrams illustrating the operation of the semiconductor device according to the first embodiment. [Figure 5] FIG. 10 is a schematic plan view showing a semiconductor device according to a second embodiment. [Figure 6] FIG. 10 is a circuit diagram illustrating a semiconductor device according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. Identical parts in the drawings are assigned the same numbers, and detailed descriptions thereof will be omitted as appropriate, and different parts will be described. Note that the drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc., are not necessarily the same as those in reality. Furthermore, even when the same part is shown, the dimensions and ratios may be different depending on the drawing.

[0008] (First embodiment) 1 is a schematic plan view showing a semiconductor device 1 according to a first embodiment. The semiconductor device 1 includes a transistor made of a nitride semiconductor, for example, gallium nitride (GaN).

[0009] As shown in FIG. 1, the semiconductor device 1 includes a first depletion-type transistor Tr1, a second enhancement-type transistor Tr2, a gate control element 30, and a substrate 40.

[0010] The first transistor Tr1 has a drain electrode 13, a gate electrode 15, and a source electrode 17. The first transistor Tr1 is, for example, a field effect transistor (FET) and has a channel region including a nitride semiconductor of a first conductivity type. In the following description, the first conductivity type is referred to as n-type and the second conductivity type is referred to as p-type.

[0011] The second transistor Tr2 has a source electrode 23, a gate electrode 25, and a drain electrode 27 (see FIG. 2). The second transistor Tr2 has, for example, a MOS gate structure and operates via an inversion channel of a second conductivity type that is opposite in polarity to the first conductivity type. The second transistor Tr2 is, for example, a PMOS transistor.

[0012] The gate control element 30 includes a gate control circuit and is electrically connected to the gate electrode 25 of the second transistor Tr2. The gate control element 30 is, for example, a silicon IC. The gate control element 30 has an input terminal 31, an output terminal 33, and a ground terminal 35. Note that the embodiment is not limited to this example, and a configuration in which the second transistor Tr2 and the gate control circuit are integrated and the gate control element 30 is not included may also be used.

[0013] The substrate 40 has an insulating base 41 (see FIG. 2), a mount bed 43, and a mount bed 45. The mount bed 43 and the mount bed 45 are provided on the insulating base 41. The mount bed 43 and the mount bed 45 are provided spaced apart from each other. The first transistor Tr1 and the second transistor Tr2 are mounted on the mount bed 43. The gate control element 30 is mounted on the mount bed 45.

[0014] The substrate 40 further has a source terminal 51, a drain terminal 53, a gate terminal 55, a power supply terminal 57, and a ground terminal 59. Each terminal is disposed on the insulating base 41 and spaced apart from one another.

[0015] The source terminal 51 is connected to, for example, the mount bed 43 and is electrically connected to the mount bed 43. The drain terminal 53 is provided at a position spaced apart from the mount beds 43 and 45 and is electrically insulated therefrom. The gate terminal 55 and the power supply terminal 57 are provided at a position spaced apart from the mount beds 43 and 45 and are electrically insulated therefrom. The ground terminal 59 is provided on, for example, the mount bed 45 and is electrically connected thereto.

[0016] The drain electrode 13 of the first transistor Tr1 is electrically connected to a drain terminal 53 via a metal wire MW1. The gate electrode 15 of the first transistor Tr1 is electrically connected to a gate terminal 55 via a metal wire MW2.

[0017] The source electrode 17 of the first transistor Tr1 is electrically connected to the source electrode 23 of the second transistor Tr2 via a metal wire MW3. The source electrode 17 of the first transistor Tr1 is also electrically connected to a power supply terminal 57 via a metal wire MW4. That is, the first transistor Tr1 and the second transistor Tr2 are connected in series, and the power supply terminal 57 is electrically connected between the first transistor Tr1 and the second transistor Tr2.

[0018] The input terminal 31 of the gate control element 30 is electrically connected to a power supply terminal 57 via a metal wire MW5. The output terminal 33 is electrically connected to the gate electrode 25 of the second transistor Tr2 via a metal wire MW6. The ground terminal 35 is electrically connected to a ground terminal 59 of the substrate 40 via, for example, a metal wire MW7.

[0019] 2 is a schematic cross-sectional view showing the semiconductor device 1 according to the first embodiment. FIG. 2 is a schematic cross-sectional view taken along line AA shown in FIG.

[0020] 2, the first transistor Tr1 and the second transistor Tr2 are provided on an insulating base 41 via a mount bed 43. The insulating base 41 includes, for example, ceramic or resin. The mount bed 43 is, for example, a metal film including copper (Cu) or the like.

[0021] The first transistor Tr1 is mounted on a mount bed 43 via a connection member 19. The connection member 19 is, for example, a solder material. The first transistor Tr1 includes a semiconductor portion 10. A drain electrode 13, a gate electrode 15 (see FIG. 1), and a source electrode 17 are provided on the surface of the semiconductor portion 10.

[0022] The semiconductor portion 10 of the first transistor Tr1 includes, for example, a semiconductor substrate 11 and a first conductivity type epitaxial growth layer 12. The semiconductor substrate 11 is, for example, a low-resistance silicon substrate. The epitaxial growth layer 12 is provided on the semiconductor substrate 11 and includes a first conductivity type nitride semiconductor, for example, a gallium nitride (GaN) layer and an aluminum gallium nitride (AlGaN) layer.

[0023] The epitaxial growth layer 12 has a multilayer structure including, for example, an undoped GaN layer provided on the semiconductor substrate 11, a GaN channel layer on the undoped GaN layer, and an AlGaN layer on the GaN channel layer. Two-dimensional electron gas, for example, is induced at the interface between the GaN channel layer and the AlGaN layer. That is, the epitaxial growth layer 12 has a FET channel region including the GaN channel layer and the AlGaN layer. The channel region of the epitaxial growth layer 12 is electrically insulated from the low-resistivity semiconductor substrate 11 and the mount bed 43 by the undoped GaN layer.

[0024] The second transistor Tr2 is mounted on the mount bed 43 via a connecting member 29. The connecting member 29 is, for example, a solder material. The second transistor Tr2 includes a semiconductor portion 20. A source electrode 23 and a gate electrode 25 (see FIG. 1) are provided on the front surface of the semiconductor portion 20. A drain electrode 27 of the second transistor Tr2 is provided on the back surface of the semiconductor portion 20. The drain electrode 27 is located between the semiconductor portion 20 and the connecting member 29.

[0025] The first transistor Tr1, the second transistor Tr2, and the gate control element 30 (see FIG. 1) are sealed on the substrate 40 by, for example, a resin member 47. The resin member 47 is formed so as to expose, for example, a portion of each of the source terminal 51, the drain terminal 53, the gate terminal 55, the power supply terminal 57, and the ground terminal 59. Note that the embodiment is not limited to this example, and, for example, hermetic sealing may be used instead of resin sealing.

[0026] Fig. 3 is a circuit diagram showing the semiconductor device 1 according to the first embodiment, which also shows external circuits such as a gate driver.

[0027] 3, an input signal for driving the first transistor Tr1 is supplied to the gate terminal 55 via a driver IC. The input signal is supplied to the gate electrode 15 of the first transistor Tr1 via the gate terminal 55.

[0028] A power supply voltage VDD is supplied to a power supply terminal 57. The power supply voltage VDD is supplied to a source electrode 17 of the first transistor Tr1 and a source electrode 23 of the second transistor Tr2 via the power supply terminal 57. The power supply voltage VDD is also supplied to an input terminal 31 of the gate control element 30.

[0029] The gate control element 30 includes a first circuit 37 and a second circuit 39. The first circuit 37 and the second circuit 39 constitute a gate control circuit. The first circuit 37 is configured to output a reference voltage Ref1 that is greater than the absolute value of the threshold voltage Vth1 (see FIG. 4) of the first transistor Tr1 relative to the ground potential. 9 compares the power supply voltage VDD with the reference voltage Ref1, and outputs 0 V (ground potential) when the power supply voltage VDD is higher than the reference voltage Ref1, and outputs the power supply voltage VDD when the power supply voltage VDD is lower than the reference voltage Ref1.

[0030] 4 is a schematic diagram illustrating the operation of the semiconductor device 1 according to the first embodiment. FIG. 4 is a timing chart illustrating the temporal changes of the power supply voltage VDD, the gate voltage VG1 of the first transistor Tr1, and the gate voltage VG2 of the second transistor Tr2. In this example, it is assumed that there is no input signal to the gate terminal 55.

[0031] 4, the power supply voltage VDD rises from 0 V to 15 V over time and then falls from 15 V to 0 V. Fig. 4 shows the process from power-on to power-off of a power conversion device in which the semiconductor device 1 is mounted.

[0032] The gate voltage VG1 of the first transistor Tr1 decreases as the power supply voltage VDD increases, and when it becomes lower than the threshold voltage Vth1, the first transistor Tr1 changes from the ON state to the OFF state. Furthermore, the gate voltage VG1 increases as the power supply voltage VDD decreases, and when the gate voltage VG1 becomes higher than the threshold voltage Vth1, the first transistor Tr1 changes from the OFF state to the ON state. In this example, the threshold voltage Vth1 is 12.5V, and the power supply voltage VDD is 15V.

[0033] On the other hand, the output of the second circuit 39 (see FIG. 3) is supplied to the gate electrode 25 of the second transistor Tr2. When the power supply voltage VDD is lower than the reference voltage Ref1, the power supply voltage VDD is supplied from the second circuit 39 to the gate electrode 25, and the gate voltage VG2 becomes 0V. The reference potential Ref is, for example, 13.5V. The gate voltage VG2 is the difference between the power supply voltage VDD and the output of the second circuit 39. When the power supply voltage VDD becomes higher than the reference voltage Ref1, the output of the second circuit 39 becomes 0V. As a result, the gate voltage VG2 drops to -VDD.

[0034] 4, the gate voltage VG2 starts to decrease from 0 V to −VDD when the power supply voltage VDD exceeds the reference voltage Ref1. When the gate voltage VG2 becomes lower than the threshold voltage Vth2 of the second transistor Tr2, the second transistor Tr2 changes from the OFF state to the ON state. When the power supply voltage VDD further decreases and the gate voltage VG2 becomes higher than the threshold voltage Vth2, the second transistor Tr2 changes from the ON state to the OFF state.

[0035] Subsequently, when the power supply voltage VDD drops and becomes smaller than the reference voltage Ref1, the power supply voltage VDD is supplied from the second circuit 39 to the gate electrode 25 of the second transistor Tr2, and the gate voltage Vth2 becomes 0 V. Thereafter, when the power supply voltage VDD becomes smaller than the absolute value of the threshold voltage Vth1 of the first transistor Tr1, the first transistor Tr1 changes from the off state to the on state.

[0036] In this way, the gate control element 30 controls the second transistor Tr2 so that it does not turn on when the first transistor Tr1 is on. By setting the reference voltage Ref1 to a value greater than the absolute value of the threshold voltage of the first transistor Tr1, the timing at which the gate voltage Vth2 is supplied to the gate electrode 25 of the second transistor Tr2 can be delayed. Furthermore, the timing at which the gate voltage Vth2 supplied to the gate electrode 25 of the second transistor Tr2 is set to 0 V can be made earlier than the timing at which the first transistor Tr turns on. This prevents the first transistor Tr1 and the second transistor Tr2 from turning on simultaneously, allowing the semiconductor device 1 to operate safely.

[0037] The semiconductor device 1 performs a switching operation in response to an input signal supplied to the gate terminal 55 while the gate control element 30 keeps the first transistor Tr1 in an off state and the second transistor Tr2 in an on state.

[0038] In the semiconductor device 1 according to the embodiment, the first transistor Tr1, the second transistor Tr2, and the gate control element 30 are housed in a package made up of an insulating base 41 and a resin member 47, which allows, for example, the lengths of the metal wires MW1 to MW9 to be shortened. This reduces parasitic inductance and prevents malfunction of the gate control element 30 due to external noise. In other words, the semiconductor device 1 can be operated more safely.

[0039] (Second embodiment) 5 is a schematic plan view showing a semiconductor device 2 according to the second embodiment. The semiconductor device 2 includes a gate control element 60 instead of the gate control element 30 of the semiconductor device 1.

[0040] The gate control element 60 has an input terminal 61 , an output terminal 63 , a ground terminal 65 , a first monitor terminal 67 , and a second monitor terminal 69 .

[0041] 5, the input terminal 61 is electrically connected to the power supply terminal 57 via a metal wire MW5. The output terminal 63 is electrically connected to the gate electrode 25 of the second transistor Tr2 via a metal wire MW6. The ground terminal 65 is electrically connected to the ground terminal 59 of the substrate 40 via a metal wire MW7.

[0042] The first monitor terminal 67 is electrically connected to the source electrode 23 of the second transistor Tr2 via a metal wire MW8. The second monitor terminal 69 is electrically connected to the mount bed 43 via a metal wire MW9. The gate control element 60 is configured to supply a gate voltage from the output terminal 63 to the gate electrode 25 of the second transistor Tr2, and to monitor the drain-source voltage of the second transistor Tr2 via the first monitor terminal 67 and the second monitor terminal 69.

[0043] 6 is a circuit diagram showing a semiconductor device 2 according to a second embodiment. In the semiconductor device 2, a first transistor Tr1 and a second transistor Tr2 are also connected in series, and a power supply voltage VDD is supplied between the first transistor Tr1 and the second transistor Tr2. An input signal is supplied from the outside to a gate electrode 15 of the first transistor Tr1.

[0044] The gate control element 60 includes a first circuit 71, a second circuit 73, a third circuit 75, a fourth circuit 77, and a fifth circuit 79.

[0045] The first circuit 71 is configured to output a reference voltage Ref1 that is greater than the absolute value of the gate threshold voltage Vth1 of the first transistor Tr1 relative to the ground potential.

[0046] The second circuit 73 compares the reference voltage Ref1 with the power supply voltage VDD and outputs a voltage corresponding to the comparison result. For example, when the power supply voltage VDD is lower than the reference voltage Ref1, the second circuit 73 outputs a low potential, and when the power supply voltage VDD becomes higher than the reference voltage Ref1, the second circuit 73 outputs a high potential.

[0047] The third circuit 75 is electrically connected to the mount bed 43 via the second monitor terminal 69. The third circuit 75 outputs a predetermined reference voltage Ref2 that corresponds to the potential of the mount bed 43. The reference voltage Ref2 is, for example, a voltage that corresponds to an overcurrent flowing through the second transistor Tr2.

[0048] The fourth circuit 77 is electrically connected to the source electrode 23 of the second transistor Tr2 via the first monitor terminal 67 (see FIG. 5). The fourth circuit 77 compares the voltage of the source electrode 23 of the second transistor Tr2 with a reference voltage Ref2 and outputs the result. For example, if the voltage of the source electrode 23 is higher than the reference voltage Ref2, the fourth circuit 77 outputs a High potential. On the other hand, if the voltage of the source electrode 23 is lower than the reference voltage Ref2, the fourth circuit 77 outputs a Low potential.

[0049] The fifth circuit 79 is connected to the second circuit 73 and the fourth circuit 7 7 , and supplies an output corresponding to the received output to the gate electrode 25 of the second transistor Tr2 via the output terminal 63.

[0050] When the output of the second circuit 73 is High and the output of the third circuit 75 is High, the fifth circuit 79 outputs VDD and turns off the second transistor Tr2.

[0051] When the output of the second circuit 73 is High and the output of the third circuit 75 is Low, the output of the fifth circuit 79 becomes 0V, turning on the second transistor Tr2.

[0052] When the output of the second circuit 73 is Low and the output of the third circuit 75 is High, the fifth circuit 79 outputs VDD and turns off the second transistor Tr2.

[0053] When the output of the second circuit 73 is low and the output of the third circuit 75 is low, the fifth circuit 79 outputs VDD and turns off the second transistor Tr2.

[0054] In the semiconductor device 2, for example, an overcurrent can be cut off by the above control by the gate control element 60. This allows the semiconductor device 2 to operate more safely.

[0055] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0056] REFERENCE SIGNS LIST 1, 2...Semiconductor device, 10, 20...Semiconductor portion, 11...Semiconductor substrate, 12...Epitaxial growth layer, 13, 27...Drain electrode, 15, 25...Gate electrode, 17, 23...Source electrode, 19, 29...Connecting member, 30, 60...Gate control element, 31, 61...Input terminal, 33, 63...Output terminal, 35, 65...Ground terminal, 37, 71...First circuit, 39, 73...Second circuit, 40...Substrate, 41...Insulating base, 43, 45...Mount bed, 47...Resin member, 51...Source terminal, 53...Drain terminal, 55...Gate terminal, 57...Power supply terminal, 59...Ground terminal, 67...First monitor terminal, 69...Second monitor terminal, 75...Third circuit, 77...Fourth circuit, 79...Fifth circuit, MW1 to MW9: metal wires, Tr1: first transistor, Tr2: second transistor

Claims

1. A substrate; a first depletion-type transistor provided on the substrate and having a channel region including a nitride semiconductor of a first conductivity type; a second enhancement-type transistor connected in series to the first transistor on the substrate and operating through an inversion layer of a second conductivity type opposite to the first conductivity type; a gate control element on the substrate connected to a gate electrode of the second transistor; a gate terminal electrically connected to the gate electrode of the first transistor; a power supply terminal electrically connected between the first transistor and the second transistor and supplying a power supply voltage to the gate control element; a sealing member that seals the first transistor, the second transistor, and the gate control element on the substrate; Equipped with the gate control element includes a first circuit and a second circuit; the first circuit is configured to output a reference voltage greater than an absolute value of a threshold voltage of the first transistor with respect to a ground potential; the second circuit is configured to compare the power supply voltage with the reference voltage, and to output the ground potential when the power supply voltage is higher than the reference voltage, and to output the power supply voltage when the power supply voltage is equal to or lower than the reference voltage.

2. 2. The semiconductor device according to claim 1, wherein the gate control element is configured to detect a source-drain voltage of the second transistor and turn off the second transistor when the source-drain voltage exceeds a predetermined value.

3. 3. The semiconductor device according to claim 1, wherein the gate control element is configured so that the first transistor and the second transistor are not simultaneously turned on.

4. 4. The semiconductor device according to claim 1, wherein the sealing member includes a resin molded on the substrate.

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