Techniques for combining operations

Abstract

To provide a processor that is a device for combining operations, a system, vehicle and method suitable for application to a computer vision system in an autonomous vehicle, and a machine-readable medium storing a set of instructions to be performed by the processor.SOLUTION: In a system 100 for combining operations, a deep learning (DL) compiler 102 uses a representation 104 of a computer program including, e.g., operations using a neural network, so as to generate a code 106 including operations combined into a software kernel having two or more dependent reduction operations. A reduction operation is an operation of generating an output with a number of dimensions that is less than the number of dimensions of an input. The dependent reduction operations are such that a first reduction operation is dependent on an output of a second reduction operation.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] At least one embodiment relates to processing resources used to implement and facilitate artificial intelligence, for example, at least one embodiment relates to a processor or computing system used to perform training and / or inference using neural networks according to various novel techniques described herein. [Background technology]

[0002] Training a neural network and / or inferencing using a neural network may use significant memory, time, or computing resources. The amount of memory, time, or computing resources used to train a neural network and / or inferencing using a neural network can be improved. Summary of the Invention [Means for solving the problem]

[0003] Provides techniques for combining operations. [Brief explanation of the drawings]

[0004] [Figure 1] FIG. 1 is a block diagram illustrating a system for combining operations, according to at least one embodiment. [Figure 2] FIG. 1 is a block diagram illustrating a graph of operations, according to at least one embodiment. [Figure 3] FIG. 1 is a block diagram illustrating a system for executing instructions that include combined operations, according to at least one embodiment. [Figure 4] 1 is a flowchart of a technique for generating instructions that include combined operations, according to at least one embodiment. [Figure 5] 1 is a flowchart of a technique for combining operations, according to at least one embodiment. [Figure 6] 1 is a flowchart of a technique for generating instructions that include combined operations, according to at least one embodiment. [Figure 7A] FIG. 1 illustrates inference and / or training logic, according to at least one embodiment. [Figure 7B] FIG. 1 illustrates inference and / or training logic, according to at least one embodiment. [Figure 8] FIG. 1 illustrates training and deployment of a neural network, according to at least one embodiment. [Figure 9] FIG. 1 illustrates an exemplary data center system, according to at least one embodiment. [Figure 10A] FIG. 1 illustrates an example of an autonomous vehicle, according to at least one embodiment. [Figure 10B] FIG. 10B illustrates example camera locations and fields of view for the autonomous vehicle of FIG. 10A, according to at least one embodiment. [Figure 10C] FIG. 10B is a block diagram illustrating an example system architecture of the autonomous vehicle of FIG. 10A, according to at least one embodiment. [Figure 10D] FIG. 10B illustrates a system for communication between a cloud-based server and the autonomous vehicle of FIG. 10A, according to at least one embodiment. [Figure 11] FIG. 1 is a block diagram illustrating a computer system according to at least one embodiment. [Figure 12] FIG. 1 is a block diagram illustrating a computer system according to at least one embodiment. [Figure 13] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 14] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 15A] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 15B] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 15C] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 15D] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 15E] FIG. 1 illustrates a shared programming model, according to at least one embodiment. [Figure 15F] FIG. 1 illustrates a shared programming model, according to at least one embodiment. [Figure 16] FIG. 1 illustrates an exemplary integrated circuit and associated graphics processor, according to at least one embodiment. [Figure 17A] FIG. 1 illustrates an exemplary integrated circuit and associated graphics processor, according to at least one embodiment. [Figure 17B] FIG. 1 illustrates an exemplary integrated circuit and associated graphics processor, according to at least one embodiment. [Figure 18A] FIG. 10 illustrates additional exemplary graphics processor logic, according to at least one embodiment. [Figure 18B] FIG. 10 illustrates additional exemplary graphics processor logic, according to at least one embodiment. [Figure 19] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 20A] FIG. 1 illustrates a parallel processor, according to at least one embodiment. [Figure 20B] FIG. 1 illustrates a partition unit, according to at least one embodiment. [Figure 20C] FIG. 1 illustrates a processing cluster, according to at least one embodiment. [Figure 20D] FIG. 1 illustrates a graphics multiprocessor according to at least one embodiment. [Figure 21] FIG. 1 illustrates a multi-graphics processing unit (GPU) system, according to at least one embodiment. [Figure 22] FIG. 1 illustrates a graphics processor according to at least one embodiment. [Figure 23]FIG. 1 is a block diagram illustrating a processor micro-architecture for a processor, according to at least one embodiment. [Figure 24] FIG. 1 illustrates a deep learning application processor, according to at least one embodiment. [Figure 25] FIG. 1 is a block diagram illustrating an exemplary neuromorphic processor, according to at least one embodiment. [Figure 26] FIG. 1 illustrates at least a portion of a graphics processor according to one or more embodiments. [Figure 27] FIG. 1 illustrates at least a portion of a graphics processor according to one or more embodiments. [Figure 28] FIG. 1 illustrates at least a portion of a graphics processor according to one or more embodiments. [Figure 29] FIG. 1 is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment. [Figure 30] FIG. 1 is a block diagram of at least a portion of a graphics processor core, according to at least one embodiment. [Figure 31A] FIG. 1 illustrates thread execution logic including an array of processing elements of a graphics processor core, according to at least one embodiment. [Figure 31B] FIG. 1 illustrates thread execution logic including an array of processing elements of a graphics processor core, according to at least one embodiment. [Figure 32] FIG. 1 illustrates a parallel processing unit (“PPU”), according to at least one embodiment. [Figure 33] FIG. 1 illustrates a general purpose processing cluster (“GPC”), according to at least one embodiment. [Figure 34] FIG. 1 illustrates a memory partition unit of a parallel processing unit (“PPU”), according to at least one embodiment. [Figure 35] FIG. 1 illustrates a streaming multiprocessor, according to at least one embodiment. [Figure 36]FIG. 1 is an example data flow diagram for an advanced computing pipeline, according to at least one embodiment. [Figure 37] FIG. 1 is a system diagram of an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline, according to at least one embodiment. [Figure 38] A diagram including an example of an advanced computing pipeline 3710A for processing imaging data, according to at least one embodiment. [Figure 39A] FIG. 10 is a diagram including an example data flow of a virtual instrument supporting an ultrasound device, according to at least one embodiment. [Figure 39B] FIG. 10 is a diagram including an example data flow of a virtual instrument supporting a CT scanner, according to at least one embodiment. [Figure 40A] FIG. 1 is a data flow diagram of a process for training a machine learning model, according to at least one embodiment. [Figure 40B] FIG. 1 illustrates an example client-server architecture for extending annotation tools with pre-trained annotation models, according to at least one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0005] FIG. 1 is a block diagram illustrating a system 100 for combining operations, according to at least one embodiment. In at least one embodiment, a deep learning (DL) compiler 102 uses a computer program representation 104 to generate code 106 that combines the operations represented in the computer program representation 104. In at least one embodiment, the DL compiler 102 is a computer program running on a processor (e.g., a CPU) and is accessible via an application programming interface (API). In at least one embodiment, the computer program representation 104 includes instructions to be invoked by a host (e.g., a computer system having a CPU) on a device (e.g., a parallel processing unit (PPU) such as a graphics processing unit (GPU)). In at least one embodiment, the computer program representation 104 includes operations using neural networks, such as convolutional neural networks (CNNs) and / or recurrent neural networks (RNNs). In at least one embodiment, the computer program representation 104 is a graph representation.

[0006] In at least one embodiment, code 106 includes instructions to be invoked on a device (e.g., a PPU, GPU, or other suitable acceleration device) by a host (e.g., a computer system having a CPU). In at least one embodiment, code 106 includes one or more software kernels to be invoked on the device. In at least one embodiment, code 106 is source code (e.g., for a parallel processing platform such as Compute Unified Device Architecture (CUDA)). In at least one embodiment, code 106 includes a software kernel (e.g., a software kernel to be invoked on a parallel processing device, such as a CUDA kernel) that combines two or more dependent reduction operations from computer program representation 104. In at least one embodiment, code 106 includes additional operations (e.g., element-wise operations, copy operations, and / or other suitable operations) combined into the software kernel having two or more dependent reduction operations.

[0007] In at least one embodiment, a reduction operation is an operation that includes a calculation and generates an output with fewer dimensions than the number of dimensions of the input. In at least one embodiment, a reduction operation performs a calculation (e.g., sum, product, mean, min, max, or any other suitable operation) using elements along an axis of an input tensor such that, after the calculation is performed, the output tensor generated by the reduction operation has a reduced dimensionality compared to the input tensor (e.g., a one-dimensional (1D) tensor is generated from a two-dimensional (2D) input tensor). In at least one embodiment, a reduction operation includes a calculation and also includes an operation that generates an output tensor with a number of elements along a dimension that is fewer than the number of elements along the same dimension of the input tensor (e.g., topk, which generates an output with the k highest values ​​along an axis). In at least one embodiment, two or more dependent reduction operations include when a first reduction operation depends on a second reduction operation. In at least one embodiment, a first reduction operation depends on a second reduction operation when the first reduction operation uses, directly or indirectly, as input the output of the second reduction operation (e.g., with one or more intervening operations, such as element-wise or copy operations). In at least one embodiment, a reduction operation is represented by y[n1,n2,n3,...,1,1,1,...]=reduce(x[n1,n2,n3,...,r1,r2,r3,...]), where r1, r2, r3,... are axes to be reduced.

[0008] In at least one embodiment, an element-wise operation is also referred to as a point-wise operation. In at least one embodiment, an element-wise operation may include any number of inputs (e.g., unary, binary, ternary, or any other number of inputs). In at least one embodiment, an element-wise operation includes an operation such as add, sub, rectified linear unit (relu) activation function, hyperbolic tangent (tanh), select, or any other suitable element-wise operation (e.g., an operation that performs a computation element by element on one or more input tensors). In at least one embodiment, a copy operation is also referred to as a memory operation. In at least one embodiment, a copy operation involves copying data from one or more input buffers to one or more output buffers, but does not perform computations on the copied data. In at least one embodiment, a copy operation includes an operation such as reshape, replicate, transpose, concat, split, reverse, squeeze, expand, gather, slice, or any other suitable copy operation. In at least one embodiment, although some copy operations produce output tensors with fewer dimensions than the number of dimensions of the input tensor and / or produce output tensors with fewer elements along an axis than the number of elements along the same axis of the input tensor, the copy operations are not considered reduction operations at least because the output tensor is produced by copying elements from the input tensor without performing a computation using the elements of the input tensor.

[0009] In at least one embodiment, computer program representation 104 includes a combination of reduction operations, element-wise operations, and / or copy operations. In at least one embodiment, copy operations are interspersed with other types of operations in a graph. In at least one embodiment, when copy operations are combined with other operations, the operations are implemented using scalar computations with no memory accesses. In at least one embodiment, computer program representation 104 also includes more advanced operations, such as matrix-vector multiplication operations, softmax operations, batchnorm operations, and / or any other suitable more advanced operations. In at least one embodiment, computer program representation 104 is a representation of a portion of a computer program. In at least one embodiment, computer program representation 104 is a graph (e.g., a directed acyclic graph (DAG)). In at least one embodiment, computer program representation 104 is a DAG, G, that represents data flow dependencies between operations. In at least one embodiment, graph G can contain any number of reduction, matrix-vector multiplication, element-wise, and memory operations. In at least one embodiment, computer program representation 104 is a subgraph of a larger graph. In at least one embodiment, computer program representation 104 includes aspects of the following pseudocode graph: ten_74=ten_73+input_82; ten_75=ten_74+ten_19; ten_76=mean(ten_75,std::vector <int>{1}); ten_77=ten_75-ten_76; ten_78=ten_77*ten_77; ten_79=mean(ten_78,std::vector <int>{1}); ten_80=ten_79+input_84; ten_81=sqrt(ten_80); ten_82=static_cast <float>(1) / ten_81; ten_83=ten_82*input_72; ten_84=ten_75*ten_83; ten_85=ten_76*ten_83; ten_86=input_112-ten_85; ten_87=ten_84+ten_86;

[0010] In at least one embodiment, the above pseudocode graph represents the operations that form a residual add+layer normalization (layernorm) layer in Bidirectional Encoder Representations from Transformers (BERT). In at least one embodiment, the above pseudocode graph includes two mean and 12 element-wise operations.

[0011] In at least one embodiment, DL compiler 102 generates modified computer program representation 108 that is based at least in part on computer program representation 104. In at least one embodiment, rewriter 110 of DL compiler 102 generates modified computer program representation 108. In at least one embodiment, rewriter 110 modifies computer program representation 104 to change representations of certain higher-level operations into one or more other types of operations. In at least one embodiment, changing a higher-level operation into another type of operation is referred to as degrading the higher-level operation. In at least one embodiment, rewriter 110 replaces a matrix-vector multiplication (e.g., general matrix-vector multiplication (GEMV)) operation with a reshape operation, an element-wise multiplication operation, and a sum reduction operation. In at least one embodiment, matrices used for GEMV operations are referred to as data sets. In at least one embodiment, modified computer program representation 108 includes reshape, element-wise multiplication, and sum reduction operations in place of matrix-vector multiplication operations that would have been present in computer program representation 104. In at least one embodiment, the operations used by rewriter 110 to replace the more advanced operations are referred to as a set of replacement operations. In at least one embodiment, rewriter 110 rewrites other types of more advanced operations to perform similar replacements (e.g., reducing a softmax operation to a max reduction operation, a subtraction operation, an exponential operation, a sum reduction operation, and a division operation that are used in modified computer program representation 108 in place of a softmax operation that would have been present in computer program representation 104). In at least one embodiment, rewriter 110 reduces the more advanced operations to point-wise and reduction operations. In at least one embodiment, computer program representation 104 does not include the more advanced operations, and modified computer program representation 108 is the same as computer program representation 104.In at least one embodiment, if the computer program representation 104 includes operations that the DL compiler 102 does not support for combination with other operations, the rewriter 110 rewrites the computer program representation 104 into modified computer program representations 108 such that the unsupported operations are separated into subgraphs and the supported operations are separated into one or more subgraphs for combination into one or more software kernels.

[0012] In at least one embodiment, replacing matrix-vector multiplication operations with reshape, element-wise multiplication, and sum reduction operations (eg, by rewriter 110) is implemented at least in part with the following pseudocode: Input: Operation DAG,G For each operation op in G If op is c=gemv(a,b) remove c=gemv(a,b) from G insert r=reshape(b,[1,k])in G insert m=mul(a,r)in G insert c=sum(m,axis=1)in G End if End for

[0013] In at least one embodiment, matrix-vector multiplication (GEMV) in the pseudocode above is represented as gemv(a,b), where a is an mxk matrix and b is a vector of length k. In at least one embodiment, the techniques in the pseudocode above may also be applied to batch matrix-vector multiplication, but are shown for a single batch for clarity.

[0014] In at least one embodiment, the DL compiler 102 generates the schedule 112. In at least one embodiment, the DL compiler generates the schedule 112 based at least in part on the modified representation 108 of the computer program. In at least one embodiment, a scheduler 114 of the DL compiler 102 generates the schedule 112. In at least one embodiment, the schedule 112 is a data structure that groups nodes of an input graph (e.g., the modified representation 108 of the computer program) into steps and indicates which nodes in each step are reduction, prolog, epilog, and modulo operations. In at least one embodiment, the scheduler 114 generates the schedule 112 based at least in part on the modified representation 108 of the computer program. In at least one embodiment, the scheduler 114 assigns operations in the modified representation 108 of the computer program (e.g., the modified DAG) to the steps. In at least one embodiment, each step includes one or more reduction operations. In at least one embodiment, one or more steps include two or more dependent reduction operations. In at least one embodiment, a step is represented as step[i] for each step number i. In at least one embodiment, each step has a prolog, which includes element-wise and / or memory operations on which the reduction depends. In at least one embodiment, epilogue operations are element-wise and / or memory operations on which the reduction in a particular step depends. In at least one embodiment, scheduler 114 performs a backward graph analysis to find prolog operations and a forward graph analysis to find epilogue operations. In at least one embodiment, modified representation 108 of the computer program includes operations that are not relevant to the reduction. In at least one embodiment, operations that are not relevant to the reduction are marked as modulo operations.

[0015] In at least one embodiment, at least one aspect of generating schedule 112 (eg, by scheduler 114) is expressed by at least one aspect of the following pseudocode: Input: Operation DAG,G i=0; While (all reductions are not scheduled) step[i]=next_step(); / / reduction node at step[i] prolog[i]=compute_prolog(step[i]); epilogue[i]=compute_epilogue(step[i]); Mark nodes in step[i], prolog[i], and epilogue[i] as visited i++; End While Mark the remaining unvisited operations in the DAG as modulo operations In at least one embodiment, in each iteration, the next_step function traverses graph G and returns a set of unvisited reduction operations that do not depend on other unvisited reduction operations. In at least one embodiment, the compute_prolog function performs a backward graph analysis starting with the reduction operation in step[i]. In at least one embodiment, compute_prolog returns a set of unvisited element-wise and memory operations on which the reduction in step[i] depends. Similarly, in at least one embodiment, compute_epilogue performs a forward graph analysis and returns a set of unvisited element-wise and memory operations on which the reduction in step[i] depends. In at least one embodiment, in each iteration, nodes in step[i], prolog[i], and epilogue[i] are marked as visited. In at least one embodiment, the loop terminates when there are no unvisited reductions in G.

[0016] In at least one embodiment, generating schedule 112 includes implementing at least one aspect described with respect to FIG.

[0017] In at least one embodiment, DL compiler 102 performs reuse analysis to identify data that is reused across multiple steps in schedule 112. In at least one embodiment, scheduler 114 performs the reuse analysis. In at least one embodiment, performing the reuse analysis includes marking data as local or shared based at least in part on whether the data is reused by a single thread or multiple threads. In at least one embodiment, marking data as local or shared enables shared memory and / or registers to be allocated during code generation to eliminate redundant accesses to global memory.

[0018] In at least one embodiment, the residual add+layer normalized graph for BERT discussed above, after scheduling and reuse analysis, can be expressed in terms of the following pseudocode to illustrate the scheduling and reuse analysis: ten_74=ten_73+input_82; / / Step 0 prolog ten_75=ten_74+ten_19; / / Step 0 prolog ten_76=mean(ten_75,std::vector <int>{1}); / / Step 0 reduction ten_77=ten_75-ten_76; / / Step 1 prolog,ten_75 reused from prolog0 ten_78=ten_77*ten_77; / / Step 1 prolog ten_79=mean(ten_78,std::vector <int>{1}); / / Step 1 reduction ten_80=ten_79+input_84; / / Step 1 epilogue ten_81=sqrt(ten_80); / / Step 1 epilogue ten_82=static_cast <float>(1) / ten_81; / / Step 1 epilogue ten_83=ten_82*input_72; / / Step 1 epilogue ten_84=ten_75*ten_83; / / Step 1 epilogue, ten_75 reused from prolog0 ten_85=ten_76*ten_83; / / Step 1 epilogue, ten_76 reused from step 0 ten_86=input_112-ten_85; / / Step 1 epilogue ten_87=ten_84+ten_86; / / Step 1 epilogue

[0019] In at least one embodiment, in the pseudocode above, ten_75, calculated in the prolog of step 0, is used in the prolog and epilogue of step 1. In at least one embodiment, this recalculation, and the associated redundant read from global memory, is avoided by caching it in a register array.

[0020] In at least one embodiment, DL compiler 102 generates code 106 based at least in part on schedule 112. In at least one embodiment, DL compiler 102 generates code 106 based at least in part on schedule 112 and modified representation 108 of the computer program. In at least one embodiment, code generator 116 of DL compiler 102 generates code 106. In at least one embodiment, DL compiler 102 generates coordinates for tensors used in modified representation 108 of the computer program. In at least one embodiment, DL compiler 102 generates logical coordinates (e.g., indices of elements in tensors) for input and output tensors. In at least one embodiment, DL compiler 102 generates physical coordinates (e.g., thread assignments for elements of tensors) for input and output tensors. In at least one embodiment, DL compiler 102 generates physical coordinates based at least in part on the generated logical coordinates. In at least one embodiment, code generator 116 generates logical and / or physical coordinates. In at least one embodiment, some other component of DL compiler 102 generates at least one aspect of the logical and / or physical coordinates instead of or in addition to code generator 116.

[0021] In at least one embodiment, the DL compiler 102 performs coordinate generation prior to generating the code 106. In at least one embodiment, coordinate generation ties together code generation for different steps in the schedule 112 (e.g., a kernel including nodes from different steps is generated based at least in part on the generated coordinates). In at least one embodiment, generating logical coordinates includes propagating logical coordinates through the graph. In at least one embodiment, when multiple operations are fused into a single kernel, the code generation (e.g., by the code generator 116) ensures that the correct coordinates are used for each operation. In at least one embodiment, the combining operation is referred to as a fused operation, and / or the combined operation is referred to as a fused operation. In at least one embodiment, the code generator 116 ensures that the correct coordinates are used for each operation based at least in part on the symbolic propagation of coordinates through the graph (e.g., the modified representation 108 of the computer program). In at least one embodiment, the code generator 116 uses a set of rules to calculate the coordinates of the input tensors from the coordinates of the output tensors. In at least one embodiment, for example, the coordinates to the input tensor T1 of the transpose operation are calculated from the coordinates to the output tensor T2, where T2 = transpose(T1, perm), as expressed in the following pseudocode: for i=0 to T2.crds.size() crds[perm[i]]=T2.crds[i]; / / Sort the coordinates T1.crds=T1.crds U crds; / / union

[0022] In at least one embodiment, for the transpose operation and the pseudocode above, perm is an array that contains the axis permutation for the transpose operation. In at least one embodiment, code generator 116 generates coordinates using a set of rules, where a particular rule in the set of rules corresponds to a particular operation type, and thus code generator 116 uses the rule associated with each particular node operation type when propagating coordinates through the graph.

[0023] In at least one embodiment, rules for calculating the coordinates of input tensors from the coordinates of output tensors are applied to a graph starting at the output and performing backward propagation through the graph. In at least one embodiment, the coordinates for each of the output tensors are initialized with unique symbols. In at least one embodiment, for example, the coordinates of a 3-dimensional tensor are set to (i1, i2, i3), where i1, i2, and i3 are unique symbols. In at least one embodiment, when the propagation reaches a reduce operation (e.g., y[n1, n2, n3, ..., 1, 1, 1...] = reduce(x[n1, n2, n3, ..., r1, r2, r3, ...])), coordinates are not propagated directly from the output to the input because the input coordinate space (n1, n2, n3, ..., r1, r2, r3, ...) is larger than the output space (n1, n2, n3, ...). In at least one embodiment, for the reduction operation, the DL compiler 102 (e.g., using the code generator 116) generates new symbols to represent the coordinates (r1, r2, r3, ...) on these axes and continues the propagation algorithm. In at least one embodiment, for the reduction operation y[n1, n2, n3, ..., 1, 1, 1 ...] = reduce(x[n1, n2, n3, ..., r1, r2, r3, ...])), the operation "reduce" generally refers to a reduction operation (e.g., mean, sum, product, min, max).

[0024] In at least one embodiment, the DL compiler 102 (e.g., using the code generator 116) performs a mapping from logical coordinates to physical coordinates based at least in part on the propagated logical coordinates. In at least one embodiment, coordinates i1, i2, ... in a tensor access t[i1, i2, ...] are mapped to physical coordinates (e.g., threads). In at least one embodiment, the mapping from logical coordinates to physical coordinates is performed at least in part based on a function of a thread index (e.g., threadIdx.x), a thread block index (e.g., blockIdx.x), and a loop index J. In at least one embodiment, the loop index corresponds to a prolog, epilogue, or loop for computing a modulo operation. In at least one embodiment, for example, if the input size of a reduction is N and there are T threads working on the reduction, the DL compiler 102 generates a prolog loop with (N+T-1) iterations. Similarly, in at least one embodiment, if the size of the epilogue result is M and there are T threads working on its computation, the epilogue loop will run for (M+T-1) iterations.

[0025] In at least one embodiment, the logical-to-physical mapping identifies which particular thread will compute each particular element in each particular iteration. In at least one embodiment, the DL compiler 102 performs the logical-to-physical mapping by starting with mapping coordinates for the reduction operation. In at least one embodiment, the DL compiler 102 defines two-dimensional physical coordinates (X,Y) where a first coordinate X identifies the reduction and a second coordinate Y identifies an element within the reduction. In at least one embodiment, for a block reduction, the two-dimensional physical coordinate is defined as (X,Y) = (blockIdx.x, threadIdx.x + J), where J is the loop index.

[0026] In at least one embodiment, for a reduction operation y[n1, n2, n3, ..., 1, 1, 1...] = reduce(x[n1, n2, n3, ..., r1, r2, r3, ...]), the DL compiler 102 maps a first coordinate of physical coordinate X to the non-reduced axis (n1, n2, n3, ...) and a second coordinate of physical coordinate Y to the reduced axis (r1, r2, r3, ...). In at least one embodiment, once these coordinates are assigned, all operations connected to the reduction will have physical coordinates. In at least one embodiment, a one-dimensional coordinate (X or Y) is mapped to an n-dimensional coordinate ((n1, n2, ...) or (r1, r2, ...)) using divide and modulo operations.

[0027] In at least one embodiment, the modulo operation is not involved in the reduction and therefore does not have mapped coordinates at this point. In at least one embodiment, the DL compiler 102 generates the coordinates of the modulo operation by linearizing the two-dimensional physical coordinates (X, Y) and mapping the linearized coordinates to the axes (i1, i2, i3, ...) of the modulo operation. In at least one embodiment, for example, for a block reduction, the linearized coordinate is blockIdx.x * blockDim.x + threadIdx.x + J.

[0028] In at least one embodiment, code generator 116 generates code 106 based at least in part on modified representation 108 of the computer program and schedule 112. In at least one embodiment, code generator 116 iterates through different steps in schedule 112 and generates code for each of the steps. In at least one embodiment, while generating code for each operation, code generator 116 generates code for calculating the physical coordinates of each tensor (e.g., from coordinate generation). In at least one embodiment, code generator 116 uses a function (e.g., labeled gen_code) to generate code for operations in a graph (e.g., modified representation 108 of the computer program) for a particular set of coordinates by traversing the graph in a backward direction.

[0029] In at least one embodiment, code generator 116 generates a loop for the prolog for each of the steps. In at least one embodiment, the loop computes the inputs to the reduction and also performs a partial in-register reduction. In at least one embodiment, code generator 116 uses another loop to compute and write the results of the epilogue and modulo operations into the graph.

[0030] In at least one embodiment, DL compiler 102 generates code 106 based at least in part on schedule 112. In at least one embodiment, one or more aspects of code generation (e.g., by code generator 116 of DL compiler 102) are expressed by one or more aspects of the following pseudocode: Each operation is reused across For steps Allocate shared memory / register arrays to cache values ​​between uses End for For each step in the schedule Generate a start loop to read the input for reduction bc=gen_coordinates(non_red_index,{baxes}) / / Coordinates of non-reduced axes rc=gen_coordinates(red_index,{raxes}) / / Coordinates of the reduced axes For each reduction r in step s gen_code(r,{bc,rc}) / / This generates the code to calculate the reduced input End for Generate an end loop Generate code to implement the reduction Generates a reduction write to the output End For Generates a start loop to calculate the epilogue / modulo operation For each output in the epilogue gen_code(o,{bc,rc}) / / This generates the code for the epilogue operation End for Linearize non_red_index and red_index to the linear index i c=gen_coordinates(i,{axes}) For rop in residual_ops gen_code(rop,c); End For Generate an end loop

[0031] In at least one embodiment, DL compiler 102 generates code 106 (e.g., using code generator 116) based at least in part on the generated coordinates of the tensors of two or more dependency reduction operations in modified representation 108 of the computer program, where the two or more dependency reduction operations are combined (e.g., into a single software kernel) in code 106. In at least one embodiment, DL compiler 102 combines one or more other operations (e.g., element-wise operations, copy operations, and / or further reduction operations) with the two or more dependency reduction operations in code 106 (e.g., into a single software kernel).

[0032] In at least one embodiment, the DL compiler 102 selects a reduction algorithm (e.g., to achieve high memory efficiency and / or high occupancy) based at least in part on one or more of the dimensions of the reduced axis, the dimensions of the non-reduced axis, and / or a predetermined maximum occupancy level. In at least one embodiment, the DL compiler 102 (e.g., using the code generator 116) selects a warp reduction algorithm, a block reduction algorithm, a tiled reduction algorithm, or a split-k reduction algorithm. In at least one embodiment, a warp refers to a collection or group of threads. In at least one embodiment, a warp includes a predetermined number of threads (e.g., 32 threads or any other suitable number of threads supported by a particular PPU or GPU hardware architecture).

[0033] In at least one embodiment, for a warp reduction algorithm, each reduction is performed by a warp, and code generator 116 invokes as many warps as there are reductions. In at least one embodiment, for example, for a sum reduction X[1,b,1,d]=sum(Y[a,b,c,d], axis={0,2}) that reduces axis {0,2}, each warp reduces a*c elements, and the total number of warps is b*d. In at least one embodiment, code generator 116 selects a warp reduction algorithm when the size of a single reduction is small enough to be performed by a single thread and there are enough independent reductions to achieve full occupancy.

[0034] In at least one embodiment, for a block reduction algorithm, each reduction is performed by a thread block, and code generator 116 launches a number of thread blocks equal to the number of reductions. In at least one embodiment, using block reduction for the sum reduction example discussed above, a thread block reduces a*c elements, and the total number of thread blocks is b*d. In at least one embodiment, code generator 116 selects a block reduction algorithm when there are enough independent reductions to achieve full occupancy.

[0035] In at least one embodiment, for tiled reduction, each thread block performs multiple reductions to achieve coalescence (e.g., when the reduction axis is not contiguous in memory). In at least one embodiment, code generator 116 selects tiled reduction when the reduction axis is not contiguous in memory. In at least one embodiment, for split-k reduction, code generator 116 distributes the reduction across multiple thread blocks when the number of independent reductions is not large enough to achieve full occupancy. In at least one embodiment, code generator 116 selects split-k reduction when the number of independent reductions is not large enough to achieve full occupancy.

[0036] In at least one embodiment, DL compiler 102 (e.g., using code generator 116) generates code 106 based at least in part on the algorithm selected for the reduction. In at least one embodiment, DL compiler 102 (e.g., using code generator 116) calculates grid and block dimensions for kernel invocations and reduction operation dimensions based at least in part on the selected algorithm (e.g., warp reduction, block reduction, tiled reduction, split-k reduction, or any other suitable algorithm). In at least one embodiment, the reduction algorithm is predetermined and / or DL ​​compiler 102 does not select a reduction algorithm.

[0037] In at least one embodiment, during code generation (e.g., by code generator 116), operands identified for reuse are saved in registers or shared memory based at least in part on the results of the reuse analysis. Similarly, in at least one embodiment, if there is a use of an operand that was previously calculated or used, the cached value is reused instead of recalculating the value.

[0038] In at least one embodiment, the kernel generated for a modulo add+layer normalized graph (e.g., the modulo add+layer normalized graph for BERT discussed above) can be expressed in terms of a code fragment from the kernel generated in the pseudocode below: extern”C”__global__void__myl_bb0_2_AddAddMeaSubMulMeaAddSqrDivMulMulMulSubAdd( half*__v1, half*__v2, half*__v3, half*__v4, half*__v5, half*__v6, half*__v7) { __shared__half__v8[1]; __shared__half__v9[1]; half__v10[8]; void*__v11

[10] ; __v11[0]=__v1; __v11[1]=__v2; __v11[2]=__v3; __v11[3]=__v4; __v11[4]=__v5; __v11[5]=__v6; __v11[6]=__v7; __v11[7]=__v8; __v11[8]=__v9; __v11[9]=__v10; block_reduce <1> (__v11); / / Block reduction corresponding to the first mean __syncthreads(); block_reduce <2> (__v11); / / Block reduction corresponding to the second mean }

[0039] In at least one embodiment, for the pseudocode above, the code generator 116 generates a kernel with seven input / output arguments. In at least one embodiment, these arguments correspond to tensors in the input graph. In at least one embodiment, the kernel itself includes two calls to block_reduce to perform two mean operations on the graph, although the implementation of block_reduce is not shown for simplicity and clarity.

[0040] In at least one embodiment, code generator 116 also generates device functions corresponding to the prolog and epilog of the steps in schedule 112. In at least one embodiment, for a modulo add+layer normalized graph (e.g., the modulo add+layer normalized graph for BERT discussed above), code generator 116 generates four device functions corresponding to the prolog and epilog of step 0 and step 1. In at least one embodiment, these device functions are called from the block_reduce function. In at least one embodiment, the generated device functions can be expressed in terms of the fragment of the generated device function corresponding to prolog 0 in the pseudocode below: __device__vtype<half,8,16> prolog0(void**live_inouts,int index){ / / Vectorized loads every 8 vtype<half,8,16> __v24; if(true&&(__v23<128)&&(__v22<128)){ __v24=__v12[0+(__v23*1)+(__v22*128)]; } vtype<half,8,16> __v25; if(true&&(__v23<128)){ __v25=__v13[0+(__v23*1)]; } / / Arithmetic on vector types vtype<half,8,16> __v28; __v28.values[0]=__v26.values[0]+__v27.values[0]; ... __v28.values[7]=__v26.values[7]+__v27.values[7]; / / Save it in a register for later use __v21[(index-threadIdx.x) / 128]=__v28; return__v28; }

[0041] In at least one embodiment, for the pseudocode above, loads from global memory are vectorized by 8. In at least one embodiment, vtype<half,8,16> represents a vector data type with 8 elements of half-precision floating-point type and a memory alignment of 16. In at least one embodiment, the value of ten_75 in a graph (e.g., the modulo add+layer normalized graph for BERT discussed above) is cached in a register for later reuse by the statement __v21[(index-threadIdx.x) / 128]=__v28.

[0042] In at least one embodiment, the epilogue for step 0 (e.g., from schedule 112 for the remainder add+layer normalized graph for BERT discussed above) stores the results of the reduction in shared memory, as shown in the following pseudocode: __device__void epilog0(void**live_inouts,int index,half val){ / / Save the result in shared memory __v37[0]=val; }

[0043] In at least one embodiment, the prolog for step 1 (e.g., from schedule 112 for the modulo add+layer normalized graph for BERT discussed above) computes the input for the second mean, and the value of ten_75 is read from a register array instead of going to global memory (e.g., as shown in the pseudocode below). __device__vtype<half,8,16> prolog1(void**live_inouts,int index){ vtype<half,8,16> __v53; / / __v50 points to the register array, __v49 points to a shared memory location __v53.values[0]=__v21[(index-threadIdx.x) / 128].values[0]-__v37[0]; ... __v53.values[7]=__v21[(index-threadIdx.x) / 128].values[7]-__v37[0]) ... return__v54; }

[0044] Similarly, in at least one embodiment, the epilogue for step 1 (e.g., from schedule 112 for the modulo add+layer normalized graph for BERT discussed above) computes the final result and writes the final result to global memory (e.g., as shown in the pseudocode below). template<>__device__void epilog1(void**live_inouts,int index,half val){ vtype<half,8,16> __v78; __v78.values[0]=__v63[0]*__v75.values[0]; ... __v78.values[7]=__v63[0]*__v75.values[7]; vtype<half,8,16> __v80; __v80.values[0]=__v76.values[0]+__v79.values[0]; ... __v80.values[7]=__v76.values[7]+__v79.values[7]; / / Vectorized write to global memory if(true&&(__v68<128)&&(__v67<128)){ __v61[0+(__v68*1)+(__v67*128)]=__v80; } }

[0045] In at least one embodiment, the DL compiler 102 generates vectorized code for one or more instructions of the code 106. In at least one embodiment, the code generator 116 performs vectorization during generation of the code 106. In at least one embodiment, vectorization of global memory accesses is an optimization that provides performance improvements, particularly for bandwidth-limited kernels. In at least one embodiment, the code generator 116 generates vectorized code for a fused deep learning graph involving reduction, arithmetic operations (e.g., element-wise operations), and memory operations. In at least one embodiment, the code generator 116 calculates vector widths (e.g., number of single instruction multiple data (SIMD) lanes) based at least in part on memory efficiency and / or occupancy, and generates vectorized code for the fused graph. In at least one embodiment, global memory accesses in a kernel occur in the prolog, epilogue, and / or modulo operations in the graph. In at least one embodiment, if the graph has an empty prolog or epilogue, the inputs and outputs of the reduction operations are read and written to global memory.

[0046] In at least one embodiment, code generator 116 generates vectorized code based, at least in part, on calculating vector widths for a particular kernel and selecting vectorization axes for each tensor based on memory layout, alignment, padding, and / or other parameters. In at least one embodiment, code generator 116 checks the vectorizability of each tensor memory access by performing a backward graph analysis starting at each graph output. In at least one embodiment, the backward graph analysis includes mapping axes in the input tensor to axes in the output tensor. In at least one embodiment, generating vectorized code can be further discussed for the example operation X[2,1024,3,4]=reshape(Y[2,2,512,3,4]). In at least one embodiment, when analyzing the vectorizability of axis 2 in Y (e.g., of length 512), code generator 116 maps it to axis 1 in X (e.g., of length 1024). In at least one embodiment, code generator 116 marks a graph (e.g., a DAG) as non-vectorizable if code generator 116 notices that an operation and / or memory access is non-vectorizable. In at least one embodiment, code generator 116 calculates information (e.g., tensor accesses to vectorize, vectorized axes, vector widths) used during code generation (e.g., of code 106) to generate vectorized code (e.g., vectorized CUDA code). In at least one embodiment, vectorization (e.g., by code generator 116) can be further expressed in terms of the following pseudocode: ten_74=ten_73[128,1024]+input_82[1,1024]; ten_75=ten_74+ten_19[128,1024]; ten_76=mean(ten_75,std::vector <int>{1}); ten_77=ten_75-ten_76; ten_78=ten_77*ten_77; ten_79=mean(ten_78,std::vector <int>{1}); ten_80=ten_79+input_84[1,1]; ten_81=sqrt(ten_80); ten_82=static_cast <float>(1) / ten_81; ten_83=ten_82*input_72[1,1024]; ten_84=ten_75*ten_83; ten_85=ten_76*ten_83; ten_86=input_112[1,1024]-ten_85; ten_87[128,1024]=ten_84+ten_86;

[0047] In at least one embodiment, for the pseudocode above, the inputs to the layer normalization kernel are ten_73, input_82, ten_19, input_84, input_72, and input_112. In at least one embodiment, the only output of the kernel is ten_87. In at least one embodiment, the dimensions of the input / output tensors are as shown in the pseudocode. In at least one embodiment, after applying vectorization, all memory accesses except input_84 are vectorized by eight. In at least one embodiment, input_84 has only one element and is therefore broadcast.

[0048] In at least one embodiment, deep learning compiler 102, although referred to as a compiler, generates code 106 (e.g., in code generator 116) but does not generate runtime code sufficient to execute a computer program corresponding to computer program representation 104. In at least one embodiment, computer program representation 104 is generated by a deep learning framework (e.g., TensorFlow or PyTorch). In at least one embodiment, computer program representation 104 is a graph. In at least one embodiment, rewriter 110, scheduler 114, and / or code generator 116 operate via a common API. In at least one embodiment, compiler and / or interpreter 118 generates runtime code 120 based at least in part on code 106. In at least one embodiment, compiler / interpreter 118 generates runtime code 120 based at least in part on other inputs 122 in addition to code 106 (e.g., portions of the computer program not represented by the graph representation of a neural network). In at least one embodiment, DL compiler 102 generates runtime code 120 (e.g., by integrating compiler / interpreter 118 in DL compiler 102). In at least one embodiment, runtime code 120 and / or code 106 are stored (e.g., in memory and / or a persistent storage device) for later use. In at least one embodiment, runtime code 120 and / or code 106 are used immediately after generation (e.g., compiled just in time for execution). In at least one embodiment, rewriter 110, scheduler 114, code generator 116, and compiler / interpreter 118 are integrated (e.g., as a compiler) into a combined compiler that performs the operations described for rewriter 110, scheduler 114, code generator 116, and compiler / interpreter 118 to generate runtime code 120 at compile time. In at least one embodiment, the combined compiler is accessible via an API.

[0049] In at least one embodiment, computer program representation 104 is structured data (e.g., data in a predetermined format and / or syntax) that represents an entire computer program. In at least one embodiment, computer program representation 104 is structured data that represents a portion of a computer program rather than the entire computer program, where the representation may define a directed acyclic graph (DAG) to illustrate the use of tensor data in a deep learning neural network. In at least one embodiment, each node in the DAG represents an operation that produces some tensor output, and each edge represents a tensor producer-consumer relationship. In at least one embodiment, a client using system 100 (e.g., an application using system 100 to compile and / or run deep learning neural network training and / or inference techniques) invokes instructions in a software kernel that combine two or more dependency reduction operations based at least in part on code 106.

[0050] In at least one embodiment, the DL compiler 102 can fully automatically fuse (e.g., combine operations from) a diverse set of DL layers, including any combination of reduction, matrix-vector multiplication, element-wise operations, and memory operations, into a single kernel (e.g., in code 106). In at least one embodiment, the DL compiler 102 is not limited by the structure of the graph and can handle arbitrary graphs, which provides a performance advantage over legacy techniques that perform unique pattern-based prolog or epilogue fusion and cannot handle arbitrary graphs or graphs with dependent reduction operations. In at least one embodiment, the DL compiler 102 technique enables optimization and generation of a single kernel for DAGs with reduction, matrix-vector multiplication, element-wise operations, and memory operations, which covers a significant portion of all operations in DL networks. In at least one embodiment, the DL compiler 102 generates a single software kernel for the entire graph when the graph consists of operations including one or more of reduction, matrix-vector multiplication, element-wise operations, and memory operations. In at least one embodiment, DL compiler 102 generates code (eg, code 106) that provides performance advantages (eg, reduced runtime) over legacy techniques.

[0051] 2 is a block diagram of a graph of operations 200, according to at least one embodiment. In at least one embodiment, the graph of operations 200 is a representation of a computer program. In at least one embodiment, a first graph 202 illustrates a modulo Add+layernorm layer in the Open Neural Network Exchange (ONNX) BERT model. In at least one embodiment, a second graph 204 illustrates a modified version of the same Add+layernorm layer in the BERT model. In at least one embodiment, at least one aspect of generating the schedule 112 of FIG. 1 can be further illustrated with respect to the first graph 202 and / or the second graph 204.

[0052] In at least one embodiment, first graph 202 includes six inputs in1, in2, in3, in4, in5, and in6 used by various nodes in first graph 202. In at least one embodiment, first graph 202 includes labeled outputs. In at least one embodiment, first graph 202 includes an addition operation (op) 206, an add op 208, a mean op 210, a subtraction op 212, a multiplication op 214, a mean op 216, an add op 218, a square root op 220, a reciprocal op 224, a mul op 226, a mul op 228, a mul op 230, a sub op 232, and an add op 234 arranged relative to each other and to inputs in1, in2, in3, in4, in5, and in6 as shown. In at least one embodiment, the operations in the first graph 202 are associated with an operation number for scheduling, such as add op206:1, add op208:2, mean op210:3, sub op212:4, mul op214:4, mean op216:5, add op218:6, sqrt op220:7, recipe op224:8, mul op226:9, mul op228:10, mul op230:12, sub op232:13, add op234:14.

[0053] In at least one embodiment, the first graph 202 includes a first partition 236, a second partition 238, and a third partition 240. In at least one embodiment, a schedule is generated for all operations within the partitions. In at least one embodiment, the scheduler 114 of FIG. 1 assigns nodes to partitions (e.g., performs graph partitioning). In at least one embodiment, some other component of the DL compiler 102 performs graph partitioning instead of or in addition to the scheduler 114. In at least one embodiment, generating the schedule includes ordering reduction nodes in the DAG (e.g., the first graph 202) based at least in part on dependencies. In at least one embodiment, two reductions with no dependencies between them are grouped together. In at least one embodiment, the remaining pointwise and copy operations are then marked as the prolog or epilog of the reduction. In at least one embodiment, the scheduling assumes that results from the first computation are saved and reused for the second computation. In at least one embodiment, the schedule is constructed using a scheduling list extension. In at least one embodiment, the schedule for the first graph 202 is expressed in terms of the following pseudocode: 1) REDUCTIONS={3},PROLOG={1,2} 2) REDUCTIONS={6},PROLOG={4,5},EPILOG={7,8,9,10,11,12,13,14} In at least one embodiment, the pseudocode above shows that there are two reductions (3 and 6), which are scheduled in this order. In at least one embodiment, nodes 1 and 2 form the prolog of 3. In at least one embodiment, nodes 4-5 form the prolog, and nodes 7-14 form the epilogue of node 6.

[0054] In at least one embodiment, second graph 204 includes six inputs in1, in2, in3, in4, in5, and in6 used by various nodes in second graph 204. In at least one embodiment, second graph 204 includes labeled outputs. In at least one embodiment, second graph 204 includes add op242, add op244, mean op246, mul op248, mean op250, mul op252, sub op254, add op256, sqrt op258, recipe op260, mul op262, mul op264, mul op266, sub op268, and add op270 arranged relative to each other and to inputs in1, in2, in3, in4, in5, and in6 as shown. In at least one embodiment, the operations in the second graph 204 are associated with an operation number for scheduling, such as add op242:1, add op244:2, mean op246:3, mul op248:4, mean op250:5, mul op252:6, sub op254:7, add op256:8, sqrt op258:9, recipe op260:10, mul op262:11, mul op264:12, mul op266:13, sub op268:14, add op270:15.

[0055] In at least one embodiment, second graph 204 includes first partition 272, second partition 274, and third partition 276. In at least one embodiment, a schedule is generated for all operations in the partitions. In at least one embodiment, generating the schedule includes ordering the reduction nodes in a DAG (e.g., second graph 204) based at least in part on dependencies. In at least one embodiment, two reductions with no dependencies between them are grouped together. In at least one embodiment, the remaining pointwise and copy operations are then marked as the prolog or epilog of the reduction. In at least one embodiment, the scheduling assumes that results from the first computation are saved and reused for the second operation. In at least one embodiment, the schedule is constructed using an extension of the scheduling list. In at least one embodiment, a schedule for second graph 204 is expressed with respect to the following pseudocode: 1)REDUCTIONS={3,5},PROLOG={1,2,4},EPILOG={6,7,8,9,10,11,12,13,14,15,16}

[0056] In at least one embodiment, the pseudocode above means that reduced nodes 3 and 5 will be executed concurrently, with the remaining operations forming their prologue or epilogue.

[0057] In at least one embodiment, before generating code for a fusion operation (e.g., in code generator 116 of FIG. 1 ), operations that will be explicitly saved to registers or shared memory are identified (e.g., using DL compiler 102 of FIG. 1 ). In at least one embodiment, when a graph includes a reduction, a thread can read multiple values ​​from an input tensor and reduce the values ​​so that only the final, reduced value resides in a register. In at least one embodiment, this can be further illustrated by an example where the reduction axis length is 1024, and assuming a thread block size of 256, each thread reads four values ​​from global memory, performs a set of pointwise operations, and then reduces the four values ​​read to one. In at least one embodiment, if one of the intermediate results is needed by a later operation, it is explicitly cached. In at least one embodiment, for example, for first graph 202, node 2 is computed as part of the prolog for reduced node 3. In at least one embodiment, the result is saved in a register to avoid recomputation and further global memory reads because the result is used by both nodes 4 and 12. In at least one embodiment, this information is derived from a schedule (e.g., schedule 112 in FIG. 1 ). In at least one embodiment, the result of a reduction is cached in shared memory if there are one or more dependent reduction operations in the same partition. In at least one embodiment, for example, for the first graph 202, the result of reduced node 3 is saved in shared memory because it is later used by nodes 11 and 13.

[0058] In at least one embodiment, the code generator 116 of Figure 1 defines the shared memory and registers. In at least one embodiment, this allows the read_input / write_output functions to read / write intermediate results from the shared memory and / or registers rather than global memory. In at least one embodiment, the code generated for the first graph 202 (e.g., by the DL compiler 102 of Figure 1 to generate the code 106 using the code generator 116) is expressed relative to the following pseudocode, where the kernel contains six inputs and one output: 1.__global__void fused_kernel_1(float*in1,float*in2,float*in3,float*in4,float*in5,float*in6,float*out){ 2. 3. float reg[VPT]; / / VPT is the number of values ​​read per thread. 4. __shared float shmem; 5. 6. void*inout_ptrs[9]; 7. inout_ptrs[0]=in1; 8. inout_ptrs[1]=in2; ... 9. inout_ptrs[7]=reg; 10. inout_ptrs[8]=&shmem; 11. 12. block_reduce<float,SumOp,0,...> (inout_ptrs); / / TId=0 13. 14. __syncthreads(); 15. 16. block_reduce<float,SumOp,1,...> (inout_ptrs); / / TId=1 17.}

[0059] In at least one embodiment, the kernel in the above pseudocode includes a register array to hold the result of node 2 (add) and a shared variable shmem to hold the result of node 3 (mean). In at least one embodiment, the block_reduce call on line 12 computes mean and also performs operations that are part of the prolog of mean (e.g., nodes 1 and 2). In at least one embodiment, block_reduce also stores the result of node 2 in reg and the result of node 3 in shmem. In at least one embodiment, the call to block_reduce on line 16 performs the remaining operations in first graph 202, from nodes 4 through 14. In at least one embodiment, nodes 4 and 5 form the prolog of the reduction, and nodes 7 through 14 form the epilogue of the reduction. In at least one embodiment, the fusion (combination) of the nodes of the first graph 202 into a single kernel provides several benefits, including lower kernel launch overhead, avoiding reads and writes to global memory if the result of node 2 is small enough to fit in a register, and the ability to store the results of the reduction (nodes 3 and 6) in shared memory rather than writing and reading from global memory again.

[0060] In at least one embodiment, the code generated for the block_reduce prolog function on line 12 is shown in the pseudocode below. template<>__device__float read_input<float,0> (void**live_inouts, int index,int i){ / / i is the call number that is incremented for each call float*v1=(float*)live_inouts[0]; / / in1 float*v2=(float*)live_inouts[1]; / / in2 float*v3=(float*)live_inouts[2]; / / in3 float*reg=(float*)live_inouts[7]; / / Array for storing values int v4=((blockIdx.x) / 1)%33; / / coordinate of axis 1 int v5=((blockIdx.x) / 33)%29; / / Coordinates of axis 2 float v6=v1[v12*157+v13*5181+index]; float v7=v2[v12*157+v13*5181+index]; float v8=v3[v12*157+v13*5181+index]; float v9=v6+v7; float v10=v8+v10; reg[i]=v10; return v10; }

[0061] In at least one embodiment, for the pseudocode above, in addition to performing the two adds in the prolog, the pseudocode also saves the result of node 2 in register "reg." The read_input and write_output functions for block_reduce on line 16 will retrieve the result of node 2 from "reg."

[0062] In at least one embodiment, the code generated for the second graph 204 (e.g., by the DL compiler 102 of FIG. 1 to generate the code 106 using the code generator 116) is expressed relative to the following pseudocode: 1.__global__void fused_kernel_2(float*in1,float*in2,float*in3,float*in4,float*in5,float*in6,float*out){ 2. 3. float reg[VPT]; 4. __shared__pair<float,float> shmem; 5. 6. void*inout_ptrs[9]; 7. inout_ptrs[0]=in1; 8. inout_ptrs[1]=in2; 9.... 10. inout_ptrs[7]=reg; 11. inout_ptrs[8]=&shmem; 12. 13. block_reduce(inout_ptrs); 14.}

[0063] In at least one embodiment, for the pseudocode above, block_reduce operates on pairs of floating-point values ​​to compute the mean of nodes 3 and 5. In at least one embodiment, combining (fusing) the second graph 204 and generating code for a single kernel provides similar benefits as those discussed for the first graph 202, and furthermore, because the two reductions (nodes 3 and 5) have no dependencies between them, they can be computed in parallel, and the type pairs are not affected.<T,T> A single reduction of type T can be performed in place of two separate reductions of type T. In at least one embodiment, the DL compiler 102 of FIG. 1 supports code generation into a single kernel for both dependent reduction operations (e.g., first graph 202) and independent reduction operations (e.g., second graph 204). In at least one embodiment, combining operations from an input graph that includes two or more dependent reduction operations (e.g., first graph 202) reduces global memory accesses and provides performance improvements over legacy approaches.

[0064] In general, for merging nodes n1 and n2, if there is an edge n1->n2 in the input graph where n1 is a reduction operation and n2 is a point-wise operation, merging is enabled for these nodes. In at least one embodiment, this enables the merging of point-wise operations into the reduction epilogue. In at least one embodiment, block reduction is used (e.g., for a BERT model). In at least one embodiment, for block reduction, the batch reduction is performed by a single cooperative thread array (CTA) (e.g., thread block) using shared memory. In at least one embodiment, an example implementation of block reduction is shown by the following pseudocode: template<typename T,typename TOp,unsigned TId,unsigned TSz,unsigned TBlksz,unsigned TNouts> __device__void block_reduce(void**live_inouts){ __shared__T shmem[TBlksz]; int tid=threadIdx.x; T val = TOp::identity(); for(int i=threadIdx.x;i <TSz;i+=TBlksz){ T current=read_input<TId,T> (live_inouts,i); val=TOp::op(val,current); } shmem[tid]=val; #pragma unroll for(int i=TBlksz / 2;i>0;i>>=1){ __syncthreads(); if (tid <i){ shmem[tid]=val=TOp::op(val,shmem[tid+i]); } } __syncthreads(); for(int i=0;i <TNouts;i+=TBlksz){ write_output<ID,T> (live_inouts,shmem[0]); } }

[0065] In at least one embodiment, for the pseudocode above, the template parameters for the function are the data type T, the reduction operation top (sum, prod, min, max, ...), a unique identifier TId, the total size of the reduction axis TSz, the number of threads per block TBlksy, and the number of output elements TNouts. In at least one embodiment, the functions read_input and write_output are generated by the DL compiler 102 of FIG. 1 and include reading / writing input / output tensors and fused point-wise operations. In at least one embodiment, block reduction allows for any number of threads and output samples, enabling general epilogue fusion. In at least one embodiment, for reductions without epilogue fusion, TNouts is set to 1, meaning that one thread (e.g., tid = 0) will write the results to global memory. In at least one embodiment, if point-wise operations of size Tsz (e.g., the same size as the input of the reduction) are fused to an epilogue, then TNouts = Tsz, and all threads participate in the epilogue computation.

[0066] 3 is a block diagram illustrating a system 300 for executing instructions including combined operations, according to at least one embodiment. In at least one embodiment, instructions including combined operations (e.g., code 106 of FIG. 1 generated by DL compiler 102) are launched from a host 302 to a device 304. In at least one embodiment, host 302 is a computer system including a processor 306 (e.g., a CPU) and memory 308. In at least one embodiment, device 304 is an accelerator including a processor 310 (e.g., one or more parallel processors) and memory 312. In at least one embodiment, device 304 is a PPU or a GPU. In at least one embodiment, DL compiler 102 of FIG. 1 runs on host 302.

[0067] In at least one embodiment, host 302 launches operations and / or instructions to be performed on device 304 (e.g., by launching parallel processing framework instructions such as Compute Unified Device Architecture (CUDA) kernels). In at least one embodiment, an executor, not shown for clarity, runs on host 302 and launches instructions including combined operations (e.g., as a software kernel such as code 106 or runtime code 120 in FIG. 1 ). In at least one embodiment, the executor runs on a CPU (e.g., processor 306) and launches instructions (e.g., as a kernel) on a parallel processing unit (e.g., GPU). In at least one embodiment, the executor is a virtual machine running on processor 306 (e.g., CPU).

[0068] In at least one embodiment, processor 310 of device 304 includes one or more circuits for implementing one or more instructions in a software kernel, the instructions including two or more dependency reduction operations, where the dependency reduction operations are combined in the software kernel by a compiler (e.g., DL compiler 102 of FIG. 1 ). In at least one embodiment, system 300 includes one or more memories (e.g., memory 308 before a kernel launch instruction and memory 312 after a kernel launch instruction while device 304 is executing the instructions) for storing the software kernel including the two or more dependency reduction operations combined in the software kernel by a compiler (e.g., DL compiler 102 of FIG. 1 ). In at least one embodiment, processor 310 is part of a PPU, and one or more circuits of processor 310 will implement the one or more instructions including the combined operations after receiving a kernel launch command from a host computer system (e.g., host 302).

[0069] In at least one embodiment, the processor 306 includes one or more circuits that combine two or more dependency reduction operations into a software kernel (e.g., code 106 of FIG. 1 ) (e.g., using DL compiler 102 of FIG. 1 ). In at least one embodiment, the two or more dependency reduction operations include a first reduction operation and a second reduction operation that is dependent on the first reduction operation, and the one or more circuits of the processor 306 generate coordinates for one or more elements of an input tensor to the second reduction operation and combine the two or more dependency reduction operations based at least in part on the generated coordinates. In at least one embodiment, the two or more dependency reduction operations include two or more of a mean operation, a sum operation, a product operation, a min operation, or a max operation. In at least one embodiment, the one or more circuits of the processor 306 assign one or more threads to elements of the tensor used by the two or more dependency reduction operations and combine the two or more dependency reduction operations into a software kernel based at least in part on the assigned threads. In at least one embodiment, one or more circuits of processor 306 replace one or more multiplication operations between a vector and a set of data (e.g., a GEMV operation between a vector and a matrix where the matrix is ​​the set of data) with a set of permutation operations (e.g., a reshape operation, an element-wise multiplication operation, and a sum reduction operation) and combine two or more dependent reduction operations with the set of permutation operations into a software kernel. In at least one embodiment, the combined two or more dependent reduction operations include a first reduction operation and a second reduction operation that is dependent on the first reduction operation, and the software kernel is to be implemented on a parallel processing unit (e.g., device 304).

[0070] In at least one embodiment, the processor 310 includes one or more circuits for implementing a software kernel (e.g., code 106 of FIG. 1 ) that includes two or more dependency reduction operations. In at least one embodiment, the two or more dependency reduction operations performed by the processor 310 are combined into the software kernel by a compiler (e.g., DL compiler 102 of FIG. 1 ) based at least in part on coordinates of tensors used by one or more reduction operations of the two or more combined dependency reduction operations. In at least one embodiment, the two or more dependency reduction operations performed by the processor 310 are combined into the software kernel by a compiler (e.g., DL compiler 102 of FIG. 1 ) along with one or more element-wise operations. In at least one embodiment, the two or more dependency reduction operations performed by the processor 310 are combined into the software kernel by a compiler (e.g., DL compiler 102 of FIG. 1 ) along with one or more copy operations. In at least one embodiment, the two or more dependency reduction operations performed by processor 310 include two or more of a mean operation, a sum operation, a product operation, a min operation, or a max operation. In at least one embodiment, one or more circuits of processor 310 will implement a software kernel after receiving a kernel launch command from a host computer system (e.g., host 302).

[0071] In at least one embodiment, the processor 310 executes a set of instructions (e.g., from a non-transitory machine-readable medium). In at least one embodiment, the set of instructions, when executed by the processor 310, causes the processor 310 to implement a software kernel (e.g., code 106 of FIG. 1 ) including at least two or more dependency reduction operations combined into the software kernel by a compiler (e.g., DL compiler 102 of FIG. 1 ). In at least one embodiment, the two or more dependency reduction operations were combined into the software kernel by the compiler along with one or more of an element-wise operation or a copy operation. In at least one embodiment, the software kernel includes instructions to be performed in parallel, and the two or more dependency reduction operations are combined into the software kernel by the compiler based at least in part on multiple threads assigned to one or more tensors used by one or more of the two or more dependency reduction operations, the multiple threads performing the one or more operations in parallel. In at least one embodiment, the two or more dependency operations include two or more of a mean operation, a sum operation, a product operation, a min operation, or a max operation. In at least one embodiment, the software kernel will be implemented on a parallel processing unit or a graphics processing unit (e.g., device 304).

[0072] In at least one embodiment, system 300 includes one or more processors (e.g., processor 306) for combining two or more dependency reduction operations into a software kernel and one or more memories (e.g., memory 308) for storing the software kernel. In at least one embodiment, the one or more processors combine the two or more dependency reduction operations with one or more element-wise operations and copy operations into the software kernel. In at least one embodiment, the two or more dependency reduction operations include two or more of a mean operation, a sum operation, a product operation, a min operation, or a max operation, and the software kernel includes instructions to be performed in parallel on a parallel processing unit (e.g., device 304). In at least one embodiment, the software kernel implements a portion of an inference operation using a neural network. In at least one embodiment, the software kernel includes instructions to be executed in parallel, and the one or more processors (e.g., processor 306) are first one or more processors, and the system further includes second one or more processors (e.g., processor 310), and the first one or more processors are to launch the software kernel for execution by the second one or more processors. In at least one embodiment, the one or more processors (e.g., processor 306) are to generate a schedule (e.g., schedule 112 of FIG. 1 ) based at least in part on a representation of a computer program (e.g., modified representation of the computer program 108 of FIG. 1 ) that includes two or more dependency reduction operations, identify reused data based at least in part on the schedule, and combine the two or more dependency reduction operations into the software kernel based at least in part on the reused data.

[0073] 4 illustrates a flowchart of a technique 400 for generating instructions including combined operations, according to at least one embodiment. In at least one embodiment, technique 400 is performed by at least one circuit, at least one system, at least one processor, at least one graphics processing unit, at least one parallel processor, and / or at least some other processors or components described and / or illustrated herein. In at least one embodiment, at least one aspect of technique 400 is performed by DL compiler 102 of FIG. 1.

[0074] In at least one embodiment, in block 402, technique 400 includes identifying a representation of a set of instructions (e.g., computer program representation 104 of FIG. 1 ). In at least one embodiment, the representation of the set of instructions includes two or more dependency reduction operations. In at least one embodiment, in block 404, technique 400 includes combining the operations (e.g., using DL compiler 102 of FIG. 1 ). In at least one embodiment, combining the operations in block 404 includes combining two or more dependency reduction operations.

[0075] In at least one embodiment, in block 406, technique 400 includes generating instructions (e.g., code 106 and / or runtime code 120 of FIG. 1 ). In at least one embodiment, generating instructions in block 406 includes combining two or more dependency reduction operations into a single software kernel. In at least one embodiment, the single software kernel includes one or more additional operations (e.g., one or more element-wise, memory, and / or additional reduction operations). In at least one embodiment, in block 408, technique 400 includes performing other actions. In at least one embodiment, performing other actions in block 408 includes returning to block 402 to identify additional representations of the set of instructions.

[0076] In at least one embodiment, technique 400 is implemented, at least in part, by executing a set of instructions (e.g., from a non-transitory machine-readable medium) using one or more processors (e.g., a processor of host 302 of FIG. 3 or any other suitable processor such as those shown or described herein). In at least one embodiment, technique 400 includes combining two or more dependency reduction operations into a software kernel. In at least one embodiment, technique 400 includes generating coordinates for one or more elements of one or more tensors used by one or more of the two or more dependency reduction operations, and combining the two or more dependency reduction operations based at least in part on the generated coordinates. In at least one embodiment, the two or more dependency reduction operations include two or more of a mean operation, a sum operation, a product operation, a min operation, or a max operation. In at least one embodiment, technique 400 includes replacing a first operation (e.g., a high-level operation such as a GEMV operation or a softmax operation) with a set of permutation operations (e.g., using rewriter 110 of FIG. 1 ) and combining two or more dependency reduction operations with the set of permutation operations into a software kernel. In at least one embodiment, technique 400 includes assigning one or more threads to elements of one or more tensors used by one or more of the two or more dependency reduction operations, wherein combining the two or more dependency reduction operations into the software kernel is based at least in part on the assigned one or more threads, and wherein the software kernel includes instructions to be performed in parallel using the assigned one or more threads. In at least one embodiment, technique 400 includes selecting a reduction algorithm, wherein combining the two or more dependency reduction operations into the software kernel is based at least in part on the selected reduction algorithm. In at least one embodiment, the software kernel is to be performed on a parallel processing unit or a graphics processing unit (e.g., device 304 of FIG. 3 ).

[0077] 5 illustrates a flowchart of a technique 500 for combining operations, according to at least one embodiment. In at least one embodiment, technique 500 is performed by at least one circuit, at least one system, at least one processor, at least one graphics processing unit, at least one parallel processor, and / or at least some other processors or components described and / or illustrated herein. In at least one embodiment, at least one aspect of technique 500 is performed by DL compiler 102 of FIG. 1. In at least one embodiment, one or more aspects of technique 500 are performed with respect to combining operations in block 404 of FIG. 4.

[0078] In at least one embodiment, in block 502, technique 500 includes rewriting the more advanced operations (e.g., using rewriter 110 of FIG. 1 ). In at least one embodiment, rewriting the more advanced operations in block 502 includes generating a modified computer program representation (e.g., modified computer program representation 108). In at least one embodiment, rewriting the more advanced operations includes replacing a matrix-vector multiplication (GEMV) operation. In at least one embodiment, rewriting the more advanced operations includes replacing the GEMV operation with a reshape operation, an element-wise multiplication, and a sum reduction operation. In at least one embodiment, rewriting the more advanced operations in block 502 includes replacing a softmax operation with a max reduction operation, an exponential operation, a sum reduction operation, and a division operation. In at least one embodiment, rewriting the more advanced operations in block 502 includes replacing some other type of more advanced operation (e.g., a batch normalization operation, or any other suitable operation). In at least one embodiment, the computer program representation (e.g., computer program representation 104) does not include the higher level operations, and rewriting of the higher level operations in block 502 is not performed (e.g., modified computer program representation 108 is the same as computer program representation 104 because no substitutions were performed by rewriter 110).

[0079] In at least one embodiment, in block 504, technique 500 includes generating a schedule (e.g., schedule 112 of FIG. 1 ). In at least one embodiment, generating the schedule includes assigning nodes of the input graph to steps. In at least one embodiment, generating the schedule includes indicating whether each node in a particular step is part of a prolog, epilogue, remainder, or reduction operation. In at least one embodiment, generating the schedule includes storing the indication of the steps and node categorization in a data structure for later use during code generation.

[0080] In at least one embodiment, in block 506, technique 500 includes generating coordinates. In at least one embodiment, generating coordinates includes assigning symbolic values ​​to outputs. In at least one embodiment, technique 500 includes propagating coordinates. In at least one embodiment, propagating coordinates includes propagating symbolic values ​​backward through the graph. In at least one embodiment, propagating coordinates includes propagating coordinates using specific rules for a particular operation type. In at least one embodiment, propagating coordinates includes propagating coordinates of tensors used by a reduction operation. In at least one embodiment, technique 500 includes allocating threads. In at least one embodiment, allocating threads includes mapping threads to logical coordinates. In at least one embodiment, allocating threads is referred to as generating and / or assigning physical coordinates. In at least one embodiment, technique 500 includes performing other actions in block 512.

[0081] 6 illustrates a flowchart of a technique 600 for generating instructions including combined operations, according to at least one embodiment. In at least one embodiment, technique 600 is performed by at least one circuit, at least one system, at least one processor, at least one graphics processing unit, at least one parallel processor, and / or at least some other processors or components described and / or illustrated herein. In at least one embodiment, at least one aspect of technique 600 is performed by DL compiler 102 of FIG. 1. In at least one embodiment, one or more aspects of technique 600 are performed with respect to generating instructions in block 406 of FIG. 4.

[0082] In at least one embodiment, in block 602, technique 600 includes selecting a reduction algorithm. In at least one embodiment, selecting a reduction algorithm includes selecting a warp reduction algorithm, a block reduction algorithm, a tiled reduction algorithm, a split-k reduction algorithm, or any other suitable reduction algorithm. In at least one embodiment, selecting a reduction algorithm is based at least in part on whether there are a sufficient number of independent reduction operations to achieve full occupancy. In at least one embodiment, selecting a reduction algorithm is based at least in part on whether the reduction axis is contiguous in memory. In at least one embodiment, the reduction algorithm is predetermined, and selecting a reduction algorithm in block 602 is not performed.

[0083] In at least one embodiment, in block 604, the technique 600 includes analyzing vectorization opportunities. In at least one embodiment, analyzing vectorization opportunities includes calculating vector widths for particular kernels. In at least one embodiment, analyzing vectorization opportunities includes selecting vectorization axes for each tensor based at least in part on memory layout, alignment, padding, and / or other parameters. In at least one embodiment, analyzing vectorization opportunities includes checking the vectorizability of each tensor memory access by performing a backward graph analysis starting at each graph output. In at least one embodiment, analyzing vectorization opportunities includes mapping axes in input tensors to axes in output tensors when the backward graph analysis is performed.

[0084] In at least one embodiment, in block 606, technique 600 includes generating instructions (e.g., code 106 generated by code generator 116 of FIG. 1 ). In at least one embodiment, generating the instructions in block 606 is based at least in part on the selected reduction algorithm and / or the analyzed vectorization opportunities. In at least one embodiment, generating the instructions is based at least in part on a modified representation of the computer program (e.g., generated in block 502 of FIG. 5 ) and a schedule (e.g., generated in block 504 of FIG. 5 ). In at least one embodiment, in block 608, technique 600 includes performing other actions.

[0085] Logic of inference and training 7A illustrates inference and / or training logic 715 used to perform inference and / or training operations for one or more embodiments. More details regarding inference and / or training logic 715 are provided below in conjunction with FIG. 7A and / or FIG. 7B.

[0086] In at least one embodiment, the inference and / or training logic 715 may include, without limitation, code and / or data storage 701 for storing forward and / or output weights, and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network that is trained and / or used to infer in one or more embodiments. In at least one embodiment, the training logic 715 may include or be coupled to code and / or data storage 701 for storing graph code or other software for controlling the timing and / or sequence of logic loaded with weights and / or other parameter information, including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)). In at least one embodiment, code such as graph code loads weights or other parameter information into processor ALUs based on the architecture of the neural network to which such code corresponds. In at least one embodiment, code and / or data storage 701 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments during forward propagation of the input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data storage 701 may be included with other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache, or system memory.

[0087] In at least one embodiment, any portion of code and / or data storage 701 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or code and / or data storage 701 may be cache memory, dynamic randomly addressable memory (“DRAM”), static randomly addressable memory (“SRAM”), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or code and / or data storage 701 is internal or external to a processor, or whether it includes DRAM, SRAM, flash, or some other type of storage, may depend on the available storage on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of data used in neural network inference and / or training, or any combination of these factors.

[0088] In at least one embodiment, the inference and / or training logic 715 may include, without limitation, code and / or data storage 705 for storing backpropagation and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used to infer in accordance with one or more aspects of the embodiment. In at least one embodiment, the code and / or data storage 705 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more aspects of the embodiment while backpropagating input / output data and / or weight parameters during training and / or inference using one or more aspects of the embodiment. In at least one embodiment, training logic 715 may include or be coupled to code and / or data storage 705 for storing graph code or other software for controlling timing and / or ordering, and code and / or data storage 705 may be loaded with weights and / or other parameter information to configure logic including integer and / or floating point units (collectively arithmetic logic units (ALUs)).

[0089] In at least one embodiment, code, such as graph code, loads weights or other parameter information into a processor ALU based on the architecture of the neural network to which such code corresponds. In at least one embodiment, any portion of code and / or data storage 705 may be included with other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and / or data storage 705 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 705 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 705 is internal or external to the processor, for example, or whether it includes DRAM, SRAM, flash memory, or some other type of storage, may depend on the storage available on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of data used in the inference and / or training of the neural network, or any combination of these factors.

[0090] In at least one embodiment, code and / or data storage 701 and code and / or data storage 705 may be separate storage structures. In at least one embodiment, code and / or data storage 701 and code and / or data storage 705 may be combined storage structures. In at least one embodiment, code and / or data storage 701 and code and / or data storage 705 may be partially combined and partially separate. In at least one embodiment, any portion of code and / or data storage 701 and code and / or data storage 705 may be included with other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory.

[0091] In at least one embodiment, the inference and / or training logic 715 may include one or more arithmetic logic units (“ALUs”) 710, including, without limitation, integer and / or floating point units, for performing logical and / or arithmetic operations based at least in part on or indicated by the training and / or inference code (e.g., graph code), the results of which may generate activations (e.g., output values ​​from layers or neurons in a neural network) stored in activation storage 720, which are functions of input / output and / or weight parameter data stored in code and / or data storage 701 and / or code and / or data storage 705. In at least one embodiment, the activations stored in activation storage 720 are generated according to linear algebra and / or matrix-based calculations performed by ALU 710 in response to executing instructions or other code, where weight values ​​stored in code and / or data storage 705 and / or data 701 are used as operands along with other values ​​such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data storage 705, or code and / or data storage 701, or in another storage, on-chip or off-chip.

[0092] In at least one embodiment, ALU 710 is included within one or more processors or other hardware logic devices or circuits, while in other embodiments, ALU 710 may be external to the processors or other hardware logic devices or circuits that use them (e.g., a coprocessor). In at least one embodiment, ALU 710 may be included within an execution unit of a processor or may otherwise be included within an ALU bank accessible by execution units of a processor, either within the same processor or distributed among different processors of different types (e.g., central processing unit, graphics processing unit, fixed function unit, etc.). In at least one embodiment, code and / or data storage 701, code and / or data storage 705, and activation storage 720 may share processors or other hardware logic devices or circuits, while in other embodiments, they may be in different processors or other hardware logic devices or circuits, or in some combination of the same processor or other hardware logic devices or circuits and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage 720 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Additionally, inference and / or training code may be stored with other code accessible to the processor or other hardware logic or circuitry, and may be fetched and / or processed using the processor's fetch, decode, schedule, execute, retire, and / or other logic.

[0093] In at least one embodiment, activation storage 720 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, activation storage 720 may be completely or partially internal to or external to one or more processors or other logic circuits. In at least one embodiment, the choice of whether activation storage 720 is internal or external to a processor, for example, or whether it includes DRAM, SRAM, flash memory, or some other type of storage, may depend on available on-chip versus off-chip storage, latency requirements of the training and / or inference functions being performed, batch sizes of data used in inference and / or training of neural networks, or any combination of these factors.

[0094] In at least one embodiment, the inference and / or training logic 715 shown in Figure 7A may be used in conjunction with an application-specific integrated circuit ("ASIC"), such as a TensorFlow® processing unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® (e.g., "Lake Crest") processor from Intel Corporation. In at least one embodiment, the inference and / or training logic 715 shown in Figure 7A may be used in conjunction with other hardware, such as central processing unit ("CPU") hardware, graphics processing unit ("GPU") hardware, or a field programmable gate array ("FPGA").

[0095] FIG. 7B illustrates inference and / or training logic 715, according to at least one embodiment. In at least one embodiment, the inference and / or training logic 715 may include, without limitation, hardware logic in which computational resources are dedicated to, or otherwise used only in conjunction with, weight values ​​or other information corresponding to one or more layers of neurons in a neural network. In at least one embodiment, the inference and / or training logic 715 illustrated in FIG. 7B may be used in conjunction with an application-specific integrated circuit (ASIC), such as a TensorFlow® processing unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® (e.g., “Lake Crest”) processor from Intel Corporation. In at least one embodiment, the inference and / or training logic 715 illustrated in FIG. 7B may be used in conjunction with other hardware, such as central processing unit (CPU) hardware, graphics processing unit (“GPU”) hardware, or a field-programmable gate array (FPGA). In at least one embodiment, inference and / or training logic 715 includes, without limitation, code and / or data storage 701 and code and / or data storage 705, which may be used to store code (e.g., graph code), weight and / or bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. In at least one embodiment shown in FIG. 7B , code and / or data storage 701 and code and / or data storage 705 are each associated with dedicated computational resources, such as computation hardware 702 and computation hardware 706, respectively. In at least one embodiment, computation hardware 702 and computation hardware 706 each include one or more ALUs that perform mathematical functions, such as linear algebraic functions, solely on the information stored in code and / or data storage 701 and code and / or data storage 705, respectively, with the results stored in activation storage 720.

[0096] In at least one embodiment, each of the code and / or data storage 701 and 705 and the corresponding computational hardware 702 and 706 correspond to a different layer of a neural network, such that activations resulting from one storage / computation pair 701 / 702, between the code and / or data storage 701 and the computational hardware 702, are provided as input to a storage / computation pair 705 / 706, between the next code and / or data storage 705 and the computational hardware 706, to reflect the conceptual organization of the neural network. In at least one embodiment, the storage / computation pairs 701 / 702 and 705 / 706 may correspond to two or more layers of the neural network. In at least one embodiment, additional storage / computation pairs (not shown) may be included in the inference and / or training logic 715 after or in parallel with the storage / computation pairs 701 / 702 and 705 / 706.

[0097] Neural network training and deployment FIG. 8 illustrates training and deployment of a deep neural network, according to at least one embodiment. In at least one embodiment, an untrained neural network 806 is trained using a training data set 802. In at least one embodiment, the training framework 804 is the PyTorch framework, while in other embodiments, the training framework 804 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training framework. In at least one embodiment, the training framework 804 trains the untrained neural network 806 and enables it to be trained using processing resources described herein to generate a trained neural network 808. In at least one embodiment, the weights may be selected randomly or by pre-training using a deep belief network. In at least one embodiment, the training may be performed in a supervised, semi-supervised, or unsupervised manner.

[0098] In at least one embodiment, the untrained neural network 806 is trained using supervised learning, where the training data set 802 includes inputs paired with desired outputs, or the training data set 802 includes inputs with known outputs, and the outputs of the neural network 806 are manually scored. In at least one embodiment, the untrained neural network 806 is trained in a supervised manner, processing inputs from the training data set 802 and comparing the resulting outputs to a set of expected or desired outputs. In at least one embodiment, errors are then back-propagated through the untrained neural network 806. In at least one embodiment, the training framework 804 adjusts the weights that control the untrained neural network 806. In at least one embodiment, the training framework 804 includes tools to monitor how well the untrained neural network 806 is converging toward a model, such as the trained neural network 808, that is suitable for generating correct answers, such as in the results 814, based on input data, such as the new data set 812. In at least one embodiment, training framework 804 iteratively trains untrained neural network 806 while adjusting weights using a loss function and a tuning algorithm, such as stochastic gradient descent, to refine the output of untrained neural network 806. In at least one embodiment, training framework 804 trains untrained neural network 806 until untrained neural network 806 reaches a desired accuracy. In at least one embodiment, trained neural network 808 can then be deployed to implement any number of machine learning operations.

[0099] In at least one embodiment, the untrained neural network 806 is trained using unsupervised learning, where the untrained neural network 806 attempts to train itself using unlabeled data. In at least one embodiment, the training data set 802 for unsupervised learning includes input data without any associated output data or “ground truth” data. In at least one embodiment, the untrained neural network 806 can learn groupings within the training data set 802 and determine how individual inputs relate to the untrained data set 802. In at least one embodiment, unsupervised training can be used within the trained neural network 808 to generate self-organizing maps, which can perform operations useful for reducing the dimensionality of the new data set 812. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows for the identification of data points in the new data set 812 that deviate from the normal patterns of the new data set 812.

[0100] In at least one embodiment, semi-supervised learning may be used, which is a technique in which labeled and unlabeled data are mixed in the training data set 802. In at least one embodiment, the training framework 804 may be used to perform incremental learning, such as by transfer learning techniques. In at least one embodiment, incremental learning allows the trained neural network 808 to adapt to a new data set 812 without forgetting the knowledge instilled in the trained neural network 808 during initial training.

[0101] Data Center 9 illustrates an exemplary data center 900 in which at least one embodiment may be used. In at least one embodiment, the data center 900 includes a data center infrastructure layer 910, a framework layer 920, a software layer 930, and an application layer 940.

[0102] 9 , in at least one embodiment, data center infrastructure layer 910 may include a resource orchestrator 912, grouped computing resources 914, and node computing resources (“node CRs”) 916(1) through 916(N), where “N” represents a positive integer (although “N” may be a different integer than that used in other figures). In at least one embodiment, node CRs 916(1) through 916(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory storage devices 918(1) through 918(N) (e.g., dynamic read-only memory, solid-state storage drives, or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules. In at least one embodiment, one or more of the nodes CR 916(1)-916(N) may be a server having one or more of the computing resources described above.

[0103] In at least one embodiment, grouped computing resources 914 may include separate groups of node CRs housed within one or more racks (not shown), or multiple racks housed in a data center at various graphical locations (also not shown). In at least one embodiment, separate groups of node CRs within grouped computing resources 914 may include grouped compute resources, network resources, memory resources, or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide compute resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power supply modules, cooling modules, and network switches in any combination.

[0104] In at least one embodiment, resource orchestrator 912 may configure or otherwise control one or more nodes CR 916(1)-916(N) and / or grouped computing resources 914. In at least one embodiment, resource orchestrator 912 may include a software design infrastructure (“SDI”) management entity for data center 900. In at least one embodiment, resource orchestrator 712 may include hardware, software, or some combination thereof.

[0105] 9 , framework layer 920 includes a job scheduler 922, a configuration manager 924, a resource manager 926, and a distributed file system 928. In at least one embodiment, framework layer 920 may include frameworks to support software 932 in software layer 930 and / or one or more applications 942 in application layer 940. In at least one embodiment, software 932 or applications 942 may each include web-based service software or applications, such as those offered by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 920 may be a type of free and open-source software web application framework, such as, but not limited to, Apache Spark™ (hereinafter “Spark”), which can use distributed file system 928 for large-scale data processing (e.g., “big data”). In at least one embodiment, job scheduler 922 may include a Spark driver to facilitate scheduling of workloads supported by various tiers of data center 900. In at least one embodiment, configuration manager 924 may be capable of configuring different tiers, such as software tier 930, as well as framework tier 920, which includes Spark and distributed file system 928 to support large-scale data processing. In at least one embodiment, resource manager 926 may be capable of managing clustered or grouped computing resources that are mapped or allocated to support distributed file system 928 and job scheduler 922. In at least one embodiment, the clustered or grouped computing resources may include grouped computing resources 914 in data center infrastructure tier 910.In at least one embodiment, resource manager 926 may manage these mappings or allocated computing resources in conjunction with resource orchestrator 912.

[0106] In at least one embodiment, software 932 included in software layer 930 may include software used by nodes CR 916(1)-916(N), grouped computing resources 914, and / or at least a portion of distributed file system 928 of framework layer 920. In at least one embodiment, the one or more types of software may include, but are not limited to, internet web page searching software, email virus scanning software, database software, and streaming video content software.

[0107] In at least one embodiment, applications 942 included in application layer 940 may include one or more types of applications used by at least a portion of nodes CR 916(1)-916(N), grouped computing resources 914, and / or distributed file system 928 of framework layer 920. In at least one embodiment, the one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive compute, and applications including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), and machine learning applications, or other machine learning applications used in conjunction with one or more embodiments.

[0108] In at least one embodiment, any of configuration manager 924, resource manager 926, and resource orchestrator 912 may implement any number and types of self-correcting actions based on any amount and type of data obtained in any technically feasible manner. In at least one embodiment, the self-correcting actions may enable a data center operator of data center 900 to avoid determining potentially faulty configurations and eliminate underutilized and / or underperforming portions of the data center.

[0109] In at least one embodiment, data center 900 may include tools, services, software, or other resources for training one or more machine learning models or for predicting or inferring information using one or more machine learning models according to one or more embodiments described herein. For example, in at least one embodiment, machine learning models may be trained by calculating weight parameters according to a neural network architecture using the software and computing resources described above with respect to data center 900. In at least one embodiment, trained machine learning models corresponding to one or more neural networks may be used to infer or predict information using the resources described above with respect to data center 900 by using weight parameters calculated by one or more techniques described herein.

[0110] In at least one embodiment, the data center may use a CPU, application specific integrated circuit (ASIC), GPU, FPGA, or other hardware to perform training and / or inference using the resources described above. Additionally, one or more of the software and / or hardware resources described above may be configured as a service to enable a user to train or perform inference on information, such as image recognition, speech recognition, or other artificial intelligence services.

[0111] Inference and / or training logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, inference and / or training logic 715 may be used in the system of Figure 9 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0112] In at least one embodiment, at least one component shown or described with respect to Figure 9 is used to implement the techniques and / or functionality described with respect to Figures 1-6. In at least one embodiment, the inference and / or training logic 715 includes and / or operates at least one aspect (e.g., deep learning compiler 102, scheduler 114, code generator 116) described with respect to Figure 1. In at least one embodiment, the inference and / or training logic 715 trains at least one untrained or partially trained neural network using a computer program representation (e.g., code 106 or runtime code 120 of Figure 1) that combines two or more dependency reduction operations and / or instructions into a software kernel, as described with respect to one or more of Figures 1-6. In at least one embodiment, the inference and / or training logic performs at least one inference operation using a computer program representation (e.g., code 106 or runtime code 120 of FIG. 1) that combines two or more dependency reduction operations and / or instructions into a software kernel, as described with respect to one or more of FIGS. 1-6.

[0113] Autonomous Vehicles 10A illustrates an example of an autonomous vehicle 1000 according to at least one embodiment. In at least one embodiment, the autonomous vehicle 1000 (alternatively referred to herein as "vehicle 1000") may be a passenger vehicle, such as, without limitation, a car, truck, bus, and / or another type of vehicle that accommodates one or more occupants. In at least one embodiment, the vehicle 1000 may be a semi-tractor trailer truck for hauling cargo. In at least one embodiment, the vehicle 1000 may be an aircraft, a robotic vehicle, or other type of vehicle.

[0114] Autonomous vehicles may be described in terms of levels of automation as defined by the National Highway Traffic Safety Administration (“NHTSA”), a division of the U.S. Department of Transportation, and the Society of Automotive Engineers (“SAE”) “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., Standard No. J3016-201806, issued June 15, 2018, Standard No. J3016-201609, issued September 30, 2016, and previous and new versions of this standard). In at least one embodiment, vehicle 1000 may be capable of functionality according to one or more of Levels 1 through 5 of autonomous driving. For example, in at least one embodiment, vehicle 1000 may be capable of conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5), depending on the embodiment.

[0115] In at least one embodiment, vehicle 1000 may include components such as, without limitation, a chassis, a vehicle body, wheels (2, 4, 6, 8, 18, etc.), tires, axles, and other vehicle components. In at least one embodiment, vehicle 1000 may include a propulsion system 1050 such as, without limitation, an internal combustion engine, a hybrid power plant, a fully electric engine, and / or another type of propulsion system. In at least one embodiment, propulsion system 1050 may be coupled to a drive train of vehicle 1000, which may include, without limitation, a transmission to enable propulsion of vehicle 1000. In at least one embodiment, propulsion system 1050 may be controlled in response to receiving a signal from a throttle / accelerator 1052.

[0116] In at least one embodiment, a steering system 1054, which may include without limitation a steering wheel, is used to steer the vehicle 1000 (e.g., along a desired path or route) when the propulsion system 1050 is operating (e.g., when the vehicle 1000 is moving). In at least one embodiment, the steering system 1054 may receive signals from a steering actuator 1056. In at least one embodiment, the steering wheel may be optional for fully automated (Level 5) functionality. In at least one embodiment, a brake sensor system 1046 may be used to operate the vehicle brakes in response to receiving signals from a brake actuator 1048 and / or brake sensor.

[0117] In at least one embodiment, controller 1036, which may include, without limitation, one or more systems on chip (“SoC”) (not shown in FIG. 10A ) and / or graphics processing units (“GPUs”), provides signals (e.g., representing commands) to one or more components and / or systems of vehicle 1000. For example, in at least one embodiment, controller 1036 may send signals to operate vehicle brakes via brake actuators 1048, steering system 1054 via steering actuators 1056, and propulsion system 1050 via throttle / accelerator 1052. In at least one embodiment, controller 1036 may include one or more on-board (e.g., integrated) computing devices (e.g., supercomputers) that process sensor signals and output operational commands (e.g., signals representing commands) to enable autonomous driving and / or assist a human driver in driving vehicle 1000. In at least one embodiment, controller 1036 may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functions (e.g., computer vision), a fourth controller for infotainment functions, a fifth controller for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller may handle two or more of the above functionalities, two or more controllers may handle a single functionality, and / or some combination thereof.

[0118] In at least one embodiment, controller 1036 provides signals to control one or more components and / or systems of vehicle 1000 in response to sensor data (e.g., sensor inputs) received from one or more sensors. In at least one embodiment, sensor data may be received from, for example, without limitation, global navigation satellite system ("GNSS") sensors 1058 (e.g., global positioning system sensors), RADAR sensors 1060, ultrasonic sensors 1062, LIDAR sensors 1064, inertial measurement units ("IMUs"). 10A ), a speed sensor 1044 (e.g., for measuring the speed of the vehicle 1000), a vibration sensor 1042, a steering sensor 1040, a brake sensor (e.g., as part of a brake sensor system 1046), and / or other types of sensors.

[0119] In at least one embodiment, one or more of the controllers 1036 may receive input (e.g., represented by input data) from the instrument cluster 1032 of the vehicle 1000 and provide output (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 1034, an audible annunciator, a loudspeaker, and / or via other components of the vehicle 1000. In at least one embodiment, the output may include information such as vehicle speed, speed, time, map data (e.g., a high-definition map (not shown in FIG. 10A )), location data (e.g., the location of the vehicle 1000 on a map, etc.), direction, locations of other vehicles (e.g., occupancy grid), information about objects and object conditions sensed by the controller 1036, etc. For example, in at least one embodiment, the HMI display 1034 may display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about a driving maneuver the vehicle has performed, is performing, or will perform (e.g., currently changing lanes, leaving exit 34B in 2 miles, etc.).

[0120] In at least one embodiment, vehicle 1000 further includes network interface 1024, which may use a wireless antenna 1026 and / or a modem for communicating over one or more networks. For example, in at least one embodiment, network interface 1024 may be capable of communicating over a Long-Term Evolution ("LTE"), Wideband Code Division Multiple Access ("WCDMA"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile communications ("GSM"), IMT-CDMA Multi-Carrier ("CDMA2000") network, etc. Additionally, in at least one embodiment, the wireless antenna 1026 may enable communication between objects in the environment (e.g., vehicles, mobile devices, etc.) using a local area network such as Bluetooth, Bluetooth Low Energy ("LE"), Z-Wave, ZigBee, etc., and / or a low power wide-area network ("LPWAN") such as LoRaWAN or SigFox.

[0121] Inference and / or training logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, inference and / or training logic 715 may be used in the system of Figure 10A for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0122] In at least one embodiment, at least one component shown or described with respect to Figure 10A is used to implement the techniques and / or functions described with respect to Figures 1-6. In at least one embodiment, the inference and / or training logic 715 of the vehicle 1000 (shown with respect to Figure 10C as part of the CPU 1006 and GPU 1008) includes and / or operates at least one aspect (e.g., deep learning compiler 102, scheduler 114, code generator 116) described with respect to Figure 1. In at least one embodiment, the inference and / or training logic 715 trains at least one untrained or partially trained neural network using a computer program representation (e.g., code 106 or runtime code 120 of Figure 1) that combines two or more reduction operations into a software kernel, as described with respect to one or more of Figures 1-6. In at least one embodiment, the inference and / or training logic 715 performs at least one inference operation using a computer program representation (e.g., code 106 or runtime code 120 of FIG. 1 ) that combines two or more dependent reduction operations into a software kernel, as described with respect to one or more of FIGs. 1-6. In at least one embodiment, the vehicle 1000 includes a computer vision system including one or more processors for identifying one or more objects based at least in part on performing one or more inference operations using two or more dependent reduction operations (e.g., code 106 or runtime code 120 of FIG. 1 ) combined into a software kernel by a compiler, as described with respect to one or more of FIGs. 1-6. In at least one embodiment, the vehicle 1000 includes one or more of a propulsion system, a directional control system, and a vehicle operator notification system for performing one or more actions (e.g., acceleration, braking control, steering, alert signal) based at least in part on the identified one or more objects.

[0123] 10B illustrates example camera locations and fields of view for the autonomous vehicle 1000 of FIG. 10A, according to at least one embodiment. In at least one embodiment, the cameras and their respective fields of view are an example example and are not limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or cameras may be positioned at different locations on the vehicle 1000.

[0124] In at least one embodiment, the camera type may include, but is not limited to, a digital camera that may be adapted for use with components and / or systems of vehicle 1000. In at least one embodiment, the camera may operate at Automotive Safety Integrity Level (“ASIL”) B and / or another ASIL. In at least one embodiment, the camera type may be capable of any image capture rate, such as 60 frames per second (fps), 1220 fps, 240 fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In at least one embodiment, the color filter array may include a red, clear, clear, clear ("RCCC") color filter array, a red, clear, clear, blue ("RCCB") color filter array, a red, blue, green, clear ("RBGC") color filter array, a Foveon X3 color filter array, a Bayer sensor (RGGB) color filter array, a monochrome sensor color filter array, and / or another type of color filter array. In at least one embodiment, a clear pixel camera may be used, such as a camera with RCCC, RCCB, and / or RBGC color filter arrays, to increase light sensitivity.

[0125] In at least one embodiment, one or more of the cameras may be used to perform advanced driver assistance systems ("ADAS") functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-function mono camera may be installed to provide functions including lane departure warning, traffic sign assist, and intelligent headlight control. In at least one embodiment, one or more of the cameras (e.g., all of the cameras) may simultaneously record and provide image data (e.g., video).

[0126] In at least one embodiment, one or more cameras may be mounted on a mounting assembly, such as a custom-designed (e.g., three-dimensionally (“3D”) printed) assembly, to eliminate stray light and reflections from inside the vehicle 1000 (e.g., reflections reflected from the dashboard onto the windshield) that may interfere with the camera's image data capture capabilities. With reference to a door mirror mounting assembly, in at least one embodiment, the door mirror assembly may be custom 3D printed so that the camera mounting plate conforms to the shape of the door mirror. In at least one embodiment, the camera may be integral with the door mirror. In at least one embodiment, for a side view camera, the camera may again be integrated into the four pillars at each corner of the cabin.

[0127] In at least one embodiment, a camera (e.g., a front-facing camera) having a field of view that includes a portion of the environment ahead of vehicle 1000 may be used for a surroundings view to facilitate identification of the forward path and obstacles, and may be used in conjunction with controller 1036 and / or one or more of the control SoCs to assist in providing information essential for generating an occupancy grid and / or determining a preferred vehicle path. In at least one embodiment, the front-facing camera may be used to perform many of the same ADAS functions as LIDAR, including, without limitation, emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the front-facing camera may also be used for ADAS features and systems, including, without limitation, other features such as lane departure warnings ("LDW"), autonomous cruise control ("ACC"), and / or traffic sign recognition.

[0128] In at least one embodiment, various cameras may be used in a front-facing configuration, including, for example, a monocular camera platform including a CMOS (complementary metal oxide semiconductor) color imager. In at least one embodiment, a wide-angle camera 1070 may be used to sense objects (e.g., pedestrians, cross traffic, or bicycles) coming into view from the periphery. While FIG. 10B shows only one wide-angle camera 1070, in other embodiments, there may be any number (including zero) of wide-angle cameras on the vehicle 1000. In at least one embodiment, any number of long-range cameras 1098 (e.g., a pair of long-view stereo cameras) may be used for depth-based object detection, particularly for objects for which a neural network has not yet been trained. In at least one embodiment, the long-range cameras 1098 may also be used for object detection and classification, as well as basic object tracking.

[0129] In at least one embodiment, any number of stereo cameras 1068 may also be included in a front-facing configuration. In at least one embodiment, one or more stereo cameras 1068 may include an integrated control unit with a scalable processing unit, which may provide a programmable gate array ("FPGA") and a multi-core microprocessor with an integrated controller area network ("CAN") or Ethernet interface on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the vehicle's 1000 environment, including distance estimates for all points in the image. In at least one embodiment, one or more of the stereo cameras 1068 may include, without limitation, a compact stereo vision sensor, which may include, without limitation, two camera lenses (one on each side) and an image processing chip that can measure the distance from the vehicle 1000 to target objects and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning features. In at least one embodiment, other types of stereo cameras 1068 may be used in addition to or instead of those described herein.

[0130] In at least one embodiment, cameras having a field of view that includes a portion of the environment to the sides of the vehicle 1000 (e.g., side view cameras) may be used for the surroundings view to provide information used to create and update the occupancy grid and generate side collision warnings. For example, in at least one embodiment, surrounding cameras 1074 (e.g., four surrounding cameras as shown in FIG. 10B ) may be disposed on the vehicle 1000. In at least one embodiment, the surrounding cameras 1074 may include, without limitation, any number and combination of wide-angle cameras, fisheye cameras, 360-degree cameras, and / or the like. For example, in at least one embodiment, four fisheye cameras may be disposed in front, behind, and on the sides of the vehicle 1000. In at least one embodiment, the vehicle 1000 may use three surrounding cameras 1074 (e.g., left, right, and rear) and may utilize one or more other cameras (e.g., a front camera) as a fourth surrounding camera.

[0131] In at least one embodiment, a camera having a field of view that includes a portion of the environment behind the vehicle 1000 (e.g., a rear view camera) may be used for parking assistance, surrounding view, rear collision warning, and to create and update the occupancy grid. In at least one embodiment, a variety of cameras may be used, including, but not limited to, cameras that are also suitable as front cameras as described herein (e.g., long-range camera 1098, and / or mid-range camera 1076, stereo camera 1068, infrared camera 1072, etc.).

[0132] Inference and / or training logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, inference and / or training logic 715 may be used in the system of Figure 10B for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0133] In at least one embodiment, at least one component shown or described with respect to Figure 10B is used to implement the techniques and / or functionality described with respect to Figures 1-6. In at least one embodiment, the inference and / or training logic 715 of the vehicle 1000 (shown with respect to Figure 10C as part of the CPU 1006 and the GPU 1008) includes and / or operates at least one aspect (e.g., the deep learning compiler 102, the scheduler 114, the code generator 116) described with respect to Figure 1. In at least one embodiment, the inference and / or training logic 715 trains at least one untrained or partially trained neural network using a computer program representation (e.g., the code 106 or the runtime code 120 of Figure 1) that combines two or more dependency reduction operations into a software kernel, as described with respect to one or more of Figures 1-6. In at least one embodiment, the inference and / or training logic performs at least one inference operation using a computer program representation (e.g., code 106 or runtime code 120 of FIG. 1) that combines two or more dependency reduction operations into a software kernel, as described with respect to one or more of FIGS. 1-6.

[0134] FIG. 10C is a block diagram illustrating an example system architecture for the autonomous vehicle 1000 of FIG. 10A , according to at least one embodiment. In at least one embodiment, each of the components, features, and systems of the vehicle 1000 of FIG. 10C is shown as connected via a bus 1002. In at least one embodiment, the bus 1002 may include, without limitation, a CAN data interface (alternatively referred to herein as a (CAN bus)). In at least one embodiment, the CAN may be a network internal to the vehicle 1000 used to help control various features and functions of the vehicle 1000, such as brake application, acceleration, brake control, steering, windshield wipers, etc. In at least one embodiment, the bus 1002 may be configured to have tens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). In at least one embodiment, the bus 1002 may be read to determine steering wheel angle, ground speed, engine revolutions per minute (“RPM”), button position, and / or other vehicle status indicators. In at least one embodiment, bus 1002 may be an ASIL B compliant CAN bus.

[0135] In at least one embodiment, FlexRay and / or Ethernet protocols may be used in addition to or instead of CAN. In at least one embodiment, there may be any number of buses forming bus 1002, including, without limitation, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using other protocols. In at least one embodiment, two or more buses may be used to perform different functions and / or provide redundancy. For example, a first bus may be used for collision avoidance functions and a second bus may be used for actuation control. In at least one embodiment, each bus of bus 1002 may communicate with one of the components of vehicle 1000, and two or more of buses of bus 1002 may communicate with corresponding components. In at least one embodiment, each of any number of systems-on-chip (“SoC”) 1004 (e.g., SoC 1004(A) and SoC 1004(B)), each of the controllers 1036, and / or each computer in the vehicle may have access to the same input data (e.g., input from sensors in the vehicle 1000) and may be connected to a common bus, such as a CAN bus.

[0136] In at least one embodiment, vehicle 1000 may include one or more controllers 1036, such as those described herein with respect to FIG. 10A . In at least one embodiment, controller 1036 may be used for a variety of functions. In at least one embodiment, controller 1036 may be coupled to any of a variety of other components and systems of vehicle 1000 and may be used to control vehicle 1000, artificial intelligence of vehicle 1000, infotainment and / or other functions of vehicle 1000.

[0137] In at least one embodiment, vehicle 1000 may include any number of SoCs 1004. In at least one embodiment, each of SoCs 1004 may include, without limitation, a central processing unit ("CPU") 1006, a graphics processing unit ("GPU") 1008, a processor 1010, a cache 1012, an accelerator 1014, a data store 1016, and / or other components and features not shown. In at least one embodiment, SoCs 1004 may be used to control vehicle 1000 in a variety of platforms and systems. For example, in at least one embodiment, SoC 1004 may be incorporated into a system (e.g., the system of vehicle 1000) having a high definition ("HD") map 1022 that can obtain map refreshes and / or updates via a network interface 1024 from one or more servers (not shown in FIG. 10C ).

[0138] In at least one embodiment, CPU 1006 may include a CPU cluster, or CPU complex (also referred to herein as a "CCPLEX"). In at least one embodiment, CPU 1006 may include multiple cores and / or level 2 ("L2") caches. For example, in at least one embodiment, CPU 1006 may include eight cores in a coherent multiprocessor configuration. In at least one embodiment, CPU 1006 may include four dual-core clusters, where each cluster has a dedicated L2 cache (e.g., 2 megabytes (MB) of L2 cache). In at least one embodiment, CPU 1006 (e.g., a CCPLEX) may be configured to support simultaneous cluster operation, allowing any combination of clusters of CPUs 1006 to be active at any given time.

[0139] In at least one embodiment, one or more of the CPUs 1006 may implement power management functionality, including, without limitation, one or more of the following features: individual hardware blocks may be automatically clock gated when idle to save dynamic power; each core clock may be gated when the core is not actively executing instructions due to execution of a Wait for Interrupt ("WFI") / Wait for Event ("WFE") instruction; each core may be independently power gated; when all cores are clock gated or power gated, each core cluster may be independently clock gated; and / or when all cores are power gated, each core cluster may be independently power gated. In at least one embodiment, the CPU 1006 may further implement an advanced algorithm for managing power states, where, given allowed power states and expected wake-up times, hardware / microcode determines what the best power state for cores, clusters, and CCPLEXes to enter is. In at least one embodiment, a processing core may support in software a simple sequence of entering power states, with work offloaded to microcode.

[0140] In at least one embodiment, GPU 1008 may include an integrated GPU (alternatively referred to herein as an “iGPU”). In at least one embodiment, GPU 1008 may be programmable and efficient for parallel workloads. In at least one embodiment, GPU 1008 may use an extended tensor instruction set. In at least one embodiment, GPU 1008 may include one or more streaming microprocessors, where each streaming microprocessor may include a level 1 (“L1”) cache (e.g., an L1 cache having at least 96 KB of storage capacity) and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache having 512 KB of storage capacity). In at least one embodiment, GPU 1008 may include at least eight streaming microprocessors. In at least one embodiment, GPU 1008 may use a compute application programming interface (API). In at least one embodiment, the GPU 1008 may use one or more parallel computing platforms and / or programming modules (e.g., NVIDIA's CUDA model).

[0141] In at least one embodiment, one or more of the GPUs 1008 may be power-optimized for best performance in automotive and embedded use cases. For example, in at least one embodiment, the GPUs 1008 may be fabricated on Fin field-effect transistor ("FinFET") circuitry. In at least one embodiment, each streaming microprocessor may incorporate a number of mixed-precision processing cores partitioned into multiple blocks. For example, without limitation, 64 PF32 cores and 32 PF64 cores may be partitioned into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA Tensor Cores for deep learning matrix operations, a level-zero ("L0") instruction cache, a warp scheduler, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor includes independent parallel integer and floating-point data paths to achieve efficient execution of workloads by mixing computational and addressing calculations. In at least one embodiment, the streaming microprocessor may include independent thread scheduling to enable finer-grained synchronization and coordination between parallel threads. In at least one embodiment, the streaming microprocessor may include a combination of an L1 data cache and a shared memory unit to improve performance while simplifying programming.

[0142] In at least one embodiment, one or more of the GPUs 1008 may include high bandwidth memory (“HBM”) and / or a 16 GB HBM2 memory subsystem, providing, in some instances, a peak memory bandwidth of approximately 900 GB / s. In at least one embodiment, synchronous graphics random-access memory (“SGRAM”), such as graphics double data rate type five (“GDDR5”), may be used in addition to or in place of the HBM memory.

[0143] In at least one embodiment, the GPU 1008 may include unified memory technology. In at least one embodiment, address translation services ("ATS") support may be used to allow the GPU 1008 to directly access the page tables of the CPU 1006. In at least one embodiment, when the GPU 1008 memory management unit ("MMU") experiences a GPU miss, an address translation request may be sent to the CPU 1006. In at least one embodiment, in response, two of the CPUs 1006 may look up the virtual-to-physical address mapping in their own page tables and send the translation back to the GPU 1008. In at least one embodiment, the unified memory technology allows for a single, unified virtual address space for both the CPU 1006 and the GPU 1008 memory, thereby simplifying programming the GPU 1008 and porting applications to the GPU 1008.

[0144] In at least one embodiment, GPU 1008 may include any number of access counters that can record the frequency of GPU 1008's accesses to the memory of other processors. In at least one embodiment, the access counters may help ensure that memory pages are moved to the physical memory of the processor that is accessing the pages most frequently, thereby improving the efficiency of memory ranges shared between processors.

[0145] In at least one embodiment, one or more of the SoCs 1004 may include any number of caches 1012, including those described herein. For example, in at least one embodiment, the caches 1012 may include a level 3 (“L3”) cache available to both the CPU 1006 and the GPU 1008 (e.g., connected to both the CPU 1006 and the GPU 1008). In at least one embodiment, the caches 1012 may include a write-back cache that can record line state through the use of a cache coherence protocol or the like (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, the L3 cache may include 4 MB of memory or more, depending on the embodiment, although smaller cache sizes may also be used.

[0146] In at least one embodiment, one or more of the SoCs 1004 may include one or more accelerators 1014 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, the SoCs 1004 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, the large on-chip memory (e.g., 4 MB of SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other calculations. In at least one embodiment, the hardware acceleration cluster may be used to complement the GPU 1008 and offload some of the GPU 1008's tasks (e.g., freeing up more cycles for the GPU 1008 to perform other tasks). In at least one embodiment, accelerator 1014 may be used for targeted workloads that are stable enough to accommodate acceleration (e.g., perception, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.). In at least one embodiment, CNNs may include region-based, i.e., regional convolutional neural networks (“RCNNs”), and Fast RCNNs (e.g., used for object detection), or other types of CNNs.

[0147] In at least one embodiment, accelerator 1014 (e.g., a hardware-accelerated cluster) may include one or more deep learning accelerators (“DLAs”). In at least one embodiment, the DLAs may include, without limitation, one or more tensor processing units (“TPUs”), which may be further configured to provide tens of trillions of operations per second for deep learning applications and inference. In at least one embodiment, the TPUs may be accelerators configured and optimized for performing image processing functions (e.g., CNN, RCNN, etc.). In at least one embodiment, the DLAs may be further optimized for a specific set of neural network types and floating-point operations, as well as for inference. In at least one embodiment, the design of the DLAs allows for improved performance per millimeter over typical general-purpose GPUs, typically greatly exceeding the performance of a CPU. In at least one embodiment, the TPU may execute several functions, including, for example, single-instance convolution functions supporting INT8, INT16, and FP16 data types for both features and weights, as well as post-processing functions. In at least one embodiment, the DLA may quickly and efficiently execute neural networks, particularly CNNs, on processed or unprocessed data for any of a variety of functions, including, for example, without limitation, CNNs for object identification and detection using data from a camera sensor, CNNs for distance estimation using data from a camera sensor, CNNs for emergency vehicle detection and identification using data from a microphone, CNNs for face recognition and vehicle owner identification using data from a camera sensor, and / or CNNs for security and / or safety events.

[0148] In at least one embodiment, the DLA may perform any function of the GPU 1008, and by using, for example, an inference accelerator, a designer may target either the DLA or the GPU 1008 for any function. For example, in at least one embodiment, a designer may centralize CNN and floating-point processing in the DLA and offload other functions to the GPU 1008 and / or other accelerators 1014.

[0149] In at least one embodiment, the accelerator 1014 may include a programmable vision accelerator (“PVA”), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, the PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (“ADAS”) 1038, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. In at least one embodiment, the PVA may balance performance and versatility. For example, in at least one embodiment, each PVA may include, by way of example and without limitation, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”) processors, and / or any number of vector processors.

[0150] In at least one embodiment, the RISC core may interact with an image sensor (e.g., an image sensor of any camera described herein), an image signal processor, etc. In at least one embodiment, each RISC core may include any amount of memory. In at least one embodiment, the RISC core may use any of a number of protocols, depending on the embodiment. In at least one embodiment, the RISC core may execute a real-time operating system ("RTOS"). In at least one embodiment, the RISC core may be implemented using one or more integrated circuit devices, application specific integrated circuits ("ASICs"), and / or memory devices. For example, in at least one embodiment, the RISC core may include an instruction cache and / or tightly coupled RAM.

[0151] In at least one embodiment, the DMA may allow components of the PVA to access system memory independent of the CPU 1006. In at least one embodiment, the DMA may support any number of features used to provide optimizations to the PVA, including, but not limited to, multi-dimensional addressing and / or circular addressing. In at least one embodiment, the DMA may support up to six or more addressing dimensions, which may include, without limitation, block width, block height, block depth, horizontal block stepping, vertical block stepping, and / or depth stepping.

[0152] In at least one embodiment, the vector processor may be a programmable processor that may be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing functions. In at least one embodiment, the PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core may include a processor subsystem, a DMA engine (e.g., two DMA engines), and / or other peripheral devices. In at least one embodiment, the vector processing subsystem may operate as the primary processing engine of the PVA and may include a vector processing unit ("VPU"), an instruction cache, and / or a vector memory (e.g., "VMEM"). In at least one embodiment, the VPU may include a digital signal processor, such as a single instruction, multiple data ("SIMD"), very long instruction word ("VLIW") digital signal processor. In at least one embodiment, the combination of SIMD and VLIW may improve throughput and speed.

[0153] In at least one embodiment, each of the vector processors may include an instruction cache and may be coupled to dedicated memory. As a result, in at least one embodiment, each of the vector processors may be configured to execute independently of other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to employ data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute a common computer vision algorithm on different regions of an image. In at least one embodiment, the vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on an image, or even execute different algorithms on consecutive images or portions of an image. In at least one embodiment, among other things, any number of PVAs may be included in a hardware-accelerated cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVA may include additional error correction code ("ECC") memory to enhance the overall security of the system.

[0154] In at least one embodiment, the accelerator 1014 may include an on-chip computer vision network and static random access memory (“SRAM”) to provide high-bandwidth, low-latency SRAM for the accelerator 1014. In at least one embodiment, the on-chip memory may include, for example, without limitation, at least 4 MB of SRAM including eight field-configurable memory blocks, which may be accessible from both the PVA and the DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and DLA may access the memory through a backbone that provides the PVA and DLA with high-speed access to the memory. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and DLA to the memory (e.g., using the APB).

[0155] In at least one embodiment, the on-chip computer vision network may include an interface that determines whether both the PVA and DLA provide ready and enable signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for transmitting control signals / addresses / data, as well as burst-based communication for continuous data transfer. In at least one embodiment, the interface may conform to International Organization for Standardization ("ISO") 26262 or International Electrotechnical Commission ("IEC") 61508 standards, although other standards and protocols may be used.

[0156] In at least one embodiment, one or more of the SoCs 1004 may include a real-time ray tracing hardware accelerator, which may be used to quickly and efficiently determine the location and range of objects (e.g., within a world model) to generate real-time visualization simulations for RADAR signal interpretation, sound propagation synthesis and / or analysis, SONAR system simulation, general waveform propagation simulation, comparison with LIDAR data for localization and / or other functions, and / or other uses.

[0157] In at least one embodiment, the accelerator 1014 can have a variety of uses for autonomous driving. In at least one embodiment, the PVA can be used for key processing stages in ADAS and autonomous vehicles. In at least one embodiment, the performance of the PVA is well suited to algorithm domains that require low-power, low-latency, and predictable processing. In other words, the PVA works well for semi-dense or dense regular computations that may require low-latency, low-power, and predictable run times, even with small data sets. In at least one embodiment, the PVA can be designed to run traditional computer vision algorithms, such as in the vehicle 1000, because they can be useful for object detection and integer arithmetic.

[0158] For example, according to at least one embodiment of the technology, computer stereo vision may be performed using the PVA. In at least one embodiment, algorithms based on semi-global matching may be used in some instances, but this is not intended to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use motion estimation / stereo matching (e.g., structure from motion, pedestrian recognition, lane detection, etc.) on the fly. In at least one embodiment, the PVA may perform computer stereo vision functions on input from two monocular cameras.

[0159] In at least one embodiment, the PVA may be used to perform dense optical flow. For example, in at least one embodiment, the PVA may process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, the PVA may be used for time-of-flight depth processing, e.g., by processing raw time-of-flight data to provide processed time-of-flight data.

[0160] In at least one embodiment, the DLA may be used to implement any type of network for enhancing control and driving safety, including, for example, without limitation, a neural network that outputs a confidence measure for each object detection. In at least one embodiment, the confidence may be expressed or interpreted as the probability of each detection compared to other detections or as providing its relative “weight.” In at least one embodiment, the confidence measure allows the system to make further decisions regarding which detections should be considered positive detections rather than false detections. In at least one embodiment, the system may set a threshold for confidence and consider only detections above the threshold to be positive detections. In embodiments where automatic emergency braking (“AEB”) is used, a false detection may cause the vehicle to automatically apply the emergency brakes, which is clearly undesirable. In at least one embodiment, a highly confident detection may be considered to trigger AEB. In at least one embodiment, the DLA may implement a neural network to regress the confidence value. In at least one embodiment, the neural network may take as its input at least some subset of parameters, such as, among others, the bounding box dimensions, a ground surface estimate obtained (e.g., from another subsystem), an output from the IMU sensor 1066 that correlates with the orientation of the vehicle 1000, distance, and a 3D location estimate of the object obtained from the neural network and / or other sensors (e.g., the LIDAR sensor 1064 or the RADAR sensor 1060).

[0161] In at least one embodiment, one or more of the SoCs 1004 may include a data store 1016 (e.g., memory). In at least one embodiment, the data store 1016 may be on-chip memory of the SoC 1004, which may store neural networks running on the GPU 1008 and / or DLA. In at least one embodiment, the capacity of the data store 1016 may be large enough to store multiple instances of the neural network for redundancy and safety. In at least one embodiment, the data store 1016 may comprise an L2 or L3 cache.

[0162] In at least one embodiment, one or more of the SoCs 1004 may include any number of processors 1010 (e.g., embedded processors). In at least one embodiment, the processors 1010 may include a boot and power management processor, which may be a dedicated processor and subsystem for handling boot power and management functions and related security enforcement. In at least one embodiment, the boot and power management processor may be part of the boot sequence of the SoC 1004 and may provide run-time power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist in transitioning the system to a low power state, manage the thermal and temperature sensors of the SoC 1004, and / or manage the power state of the SoC 1004. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and the SoC 1004 may use the ring oscillator to detect the temperature of the CPU 1006, the GPU 1008, and / or the accelerator 1014. In at least one embodiment, if the temperature is determined to exceed a threshold, the boot and power management processor may enter a temperature fault routine, place the SoC 1004 in a low power state, and / or place the vehicle 1000 in a driver-safety shutdown mode (e.g., bring the vehicle 1000 to a safety shutdown).

[0163] In at least one embodiment, processor 1010 may further include a set of embedded processors capable of acting as an audio processing engine, which may be an audio subsystem that enables full hardware support for multi-channel audio over multiple interfaces and a wide variety of flexible audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core with a digital signal processor with dedicated RAM.

[0164] In at least one embodiment, processor 1010 may further include an always-on processor engine capable of providing the hardware features necessary to support low-power sensor management and wake-up use cases. In at least one embodiment, the always-on processor engine may include, without limitation, a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0165] In at least one embodiment, the processor 1010 may further include a safety cluster engine, which may include, without limitation, a processor subsystem dedicated to handling safety management for automotive applications. In at least one embodiment, the safety cluster engine may include, without limitation, two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.), and / or routing logic. In safety mode, in at least one embodiment, two or more cores may operate in lockstep mode and function as a single core with comparison logic to detect any differences between their operations. In at least one embodiment, the processor 1010 may further include a real-time camera engine, which may include, without limitation, a processor subsystem dedicated to handling real-time camera management. In at least one embodiment, the processor 1010 may further include a high dynamic range signal processor, which may include, without limitation, an image signal processor, which is a hardware engine that is part of a camera processing pipeline.

[0166] In at least one embodiment, the processor 1010 may include a video image composer, which may be a processing block (e.g., implemented in a microprocessor) that implements video post-processing functions required by a video playback application to generate a final image in a playback device window. In at least one embodiment, the video image composer may perform lens distortion correction for the wide-angle camera 1070, the surrounding camera 1074, and / or the in-cabin surveillance camera sensor. In at least one embodiment, the in-cabin surveillance camera sensor is preferably monitored by a neural network running on a separate instance of the SoC 1004 that is configured to identify in-cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform lip reading to, without limitation, activate cellular service, make phone calls, write emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, and provide voice-activated web surfing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode and are unavailable at other times.

[0167] In at least one embodiment, the video image combiner may include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, when motion occurs in the video, the noise reduction appropriately weights spatial information and downweights information provided by adjacent frames. In at least one embodiment, when an image or portion of an image does not contain motion, the temporal noise reduction performed by the video image combiner may use information from previous images to reduce noise in the current image.

[0168] In at least one embodiment, the video image combiner may also be configured to perform stereo rectification on the input stereo lens frames. In at least one embodiment, the video image combiner may also be used to combine user interfaces when the operating system desktop is in use, eliminating the need for the GPU 1008 to continually render new surfaces. In at least one embodiment, the video image combiner may be used to offload the GPU 1008 when it is powered on and actively performing 3D rendering, improving performance and responsiveness.

[0169] In at least one embodiment, one or more of the SoCs 1004 may further include a mobile industry processor interface ("MIPI") camera serial interface for receiving input from video and cameras, a high-speed interface, and / or a video input block that may be used for camera and associated pixel input functions. In at least one embodiment, one or more of the SoCs 1004 may further include an input / output controller, which may be controlled by software and may be used to receive I / O signals that are not tied to a specific role.

[0170] In at least one embodiment, one or more of the SoCs 1004 may further include peripherals, audio encoders / decoders (“codecs”), power management, and / or a wide range of peripheral interfaces to enable communication with other devices. In at least one embodiment, the SoC 1004 may be used to process data from cameras (e.g., connected via a gigabit multimedia serial link and an Ethernet channel), data from sensors (e.g., a LIDAR sensor 1064, a RADAR sensor 1060, etc., which may be connected via an Ethernet channel), data from the bus 1002 (e.g., vehicle 1000 speed, steering wheel position, etc.), data from a GNSS sensor 1058 (e.g., connected via an Ethernet bus or a CAN bus), etc. In at least one embodiment, one or more of the SoCs 1004 may further include a dedicated high-performance mass storage controller, which may include its own DMA engine and may be used to offload routine data management tasks from the CPU 1006.

[0171] In at least one embodiment, the SoC 1004 may be an end-to-end platform with a flexible architecture spanning levels 3-5 of automation, providing a comprehensive functional safety architecture that leverages and efficiently utilizes computer vision and ADAS techniques for diversity and redundancy, and a flexible, reliable driving software stack, along with deep learning tools. In at least one embodiment, the SoC 1004 is faster, more reliable, and more energy- and space-efficient than conventional systems. For example, in at least one embodiment, the accelerator 1014, when combined with the CPU 1006, GPU 1008, and data store 1016, can provide a fast and efficient platform for levels 3-5 of autonomous vehicles.

[0172] In at least one embodiment, computer vision algorithms may run on a CPU, which may be configured using a high-level programming language such as C to perform various processing algorithms across various visual data. However, in at least one embodiment, CPUs often cannot meet the performance requirements of many computer vision applications, such as those related to execution time and power consumption. In at least one embodiment, many CPUs are unable to run the complex object detection algorithms used in in-vehicle ADAS applications and realistic Level 3-5 autonomous vehicles in real time.

[0173] Embodiments described herein may enable multiple neural networks to run simultaneously and / or sequentially, with the results combined to enable Levels 3-5 autonomous driving capabilities. For example, in at least one embodiment, a CNN running on the DLA or a separate GPU (e.g., GPU1020) may include text and word recognition to enable the neural network to read and understand traffic signs, including signs for which it was not specifically trained. In at least one embodiment, the DLA may further include a neural network capable of identifying and interpreting signs and providing a semantic understanding of the signs, which can then be passed to a path planning module running on the CPU complex.

[0174] In at least one embodiment, for Level 3, 4, or 5 driving, multiple neural networks may be running simultaneously. For example, in at least one embodiment, a warning sign displaying "Caution: Flashing Icy Conditions" in conjunction with an electric light may be interpreted separately or collectively by several neural networks. In at least one embodiment, the warning sign itself may be identified as a traffic sign by a first deployed neural network (e.g., a neural network that has been trained), and the words "Flashing Icy Conditions" may be interpreted by a second deployed neural network, which, if the flashing light is detected, notifies the vehicle's route planning software (preferably running on the CPU complex) that an icy condition exists. In at least one embodiment, the flashing light may be identified by running a third deployed neural network over multiple frames, and the presence (or absence) of the flashing light is notified to the vehicle's route planning software. In at least one embodiment, all three neural networks may be running simultaneously, such as within the DLA and / or on the GPU 1008.

[0175] In at least one embodiment, a CNN for facial recognition and vehicle owner identification may use data from the camera sensor to identify the presence of an authorized driver and / or owner of the vehicle 1000. In at least one embodiment, an always-on sensor processing engine may be used to unlock the vehicle and turn on the lights when the owner approaches the driver's door, and to disable the vehicle in security mode when the owner leaves the vehicle. In this way, the SoC 1004 provides security against theft and / or carjacking.

[0176] In at least one embodiment, a CNN for emergency vehicle detection and identification may use data from microphone 1096 to detect and identify emergency vehicle sirens. In at least one embodiment, SoC 1004 uses a CNN to classify environmental and urban sounds as well as visual data. In at least one embodiment, the CNN running on the DLA is trained to identify the relative speed at which an emergency vehicle is approaching (e.g., by using the Doppler effect). In at least one embodiment, the CNN may also be trained to identify emergency vehicles specific to the region in which the vehicle is operating, as identified by GNSS sensor 1058. In at least one embodiment, when operating in Europe, the CNN attempts to detect European sirens, and when operating in North America, it attempts to identify only North American sirens. In at least one embodiment, when an emergency vehicle is detected, a control program for executing an emergency vehicle safety routine may be used to slow the vehicle, pull over, stop the vehicle, and / or idle the vehicle in conjunction with ultrasonic sensor 1062 until the emergency vehicle has passed.

[0177] In at least one embodiment, vehicle 1000 may include a CPU 1018 (e.g., a discrete CPU or dCPU), which may be coupled to SoC 1004 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, CPU 1018 may include, for example, an X86 processor. CPU 1018 may be used to perform any of a variety of functions, including, for example, reconciling potentially inconsistent results between ADAS sensors and SoC 1004 and / or monitoring the status and health of controller 1036 and / or infotainment system on a chip ("infotainment SoC") 1030.

[0178] In at least one embodiment, vehicle 1000 may include GPU 1020 (e.g., a discrete GPU or dGPU), which may be coupled to SoC 1004 via a high-speed interconnect (e.g., NVIDIA's NVLINK channel). In at least one embodiment, GPU 1020 may provide additional artificial intelligence functionality, such as by running redundant and / or different neural networks, and may be used to train and / or update neural networks based at least in part on input (e.g., sensor data) from sensors in vehicle 1000.

[0179] In at least one embodiment, vehicle 1000 may further include a network interface 1024, which may include, without limitation, a wireless antenna 1026 (e.g., one or more wireless antennas for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). In at least one embodiment, network interface 1024 may be used to enable wireless connections to Internet cloud services (e.g., servers and / or other network devices) with other vehicles and / or computing devices (e.g., occupant client devices). In at least one embodiment, to communicate with other vehicles, a direct link may be established between vehicle 1000 and the other vehicles and / or an indirect link (e.g., across a network and via the Internet) may be established. In at least one embodiment, the direct link may be provided using a vehicle-to-vehicle communication link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 1000 with information about vehicles in its vicinity (e.g., vehicles in front of, to the sides of, and / or behind vehicle 1000). In at least one embodiment, these aforementioned features may be part of a cooperative adaptive cruise control feature of the vehicle 1000.

[0180] In at least one embodiment, the network interface 1024 may include an SoC that provides modulation and demodulation functionality, enabling the controller 1036 to communicate over a wireless network. In at least one embodiment, the network interface 1024 may include a radio frequency front end for up-conversion from baseband to radio frequency and down-conversion from radio frequency to baseband. In at least one embodiment, the frequency conversion may be performed in any technically feasible manner. For example, the frequency conversion may be performed by well-known processes and / or using a super-heterodyne process. In at least one embodiment, the radio frequency front end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functionality for communicating via LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0181] In at least one embodiment, vehicle 1000 may further include a data store 1028, which may include, without limitation, off-chip (e.g., not on SoC 1004) storage. In at least one embodiment, data store 1028 may include one or more storage elements, including, without limitation, RAM, SRAM, dynamic random access memory (“DRAM”), video random-access memory (“VRAM”), flash memory, a hard disk, and / or other components and / or devices capable of storing at least one bit of data.

[0182] In at least one embodiment, vehicle 1000 may further include GNSS sensors 1058 (e.g., GPS and / or assisted GPS sensors) to assist in mapping, perception, occupancy grid generation, and / or route planning functions. In at least one embodiment, any number of GNSS sensors 1058 may be used, including, for example, without limitation, a GPS using a USB connector with an Ethernet to serial (e.g., RS-232) bridge.

[0183] In at least one embodiment, vehicle 1000 may further include a RADAR sensor 1060. In at least one embodiment, RADAR sensor 1060 may be used by vehicle 1000 for long-range vehicle detection, even in darkness and / or severe weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. In at least one embodiment, RADAR sensor 1060 may use a CAN bus and / or bus 1002 for control (e.g., to transmit data generated by RADAR sensor 1060) and to access object tracking data, and in some instances may have access to an Ethernet channel to access raw data. In at least one embodiment, various types of RADAR sensors may be used. For example, without limitation, RADAR sensor 1060 may be suitable for forward, rearward, and side RADAR use. In at least one embodiment, one or more of RADAR sensors 1060 are pulse-Doppler RADAR sensors.

[0184] In at least one embodiment, the RADAR sensor 1060 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, and short-range with side coverage. In at least one embodiment, the long-range RADAR may be used for adaptive cruise control functions. In at least one embodiment, the long-range RADAR system may provide a wide field of view, such as within a 250 m (meter) range, achieved by two or more independent scans. In at least one embodiment, the RADAR sensor 1060 may help distinguish between static and moving objects and may be used by the ADAS system 1038 to provide emergency braking assistance and forward collision warning. In at least one embodiment, the sensors 1060 included in a long-range RADAR system may include, without limitation, multiple (e.g., six or more) fixed RADAR antennas, as well as monostatic multi-mode RADAR with high-speed CAN and FlexRay interfaces. In at least one embodiment, where there are six antennas, the center four antennas may generate a focused beam pattern designed to record the surroundings of vehicle 1000 at higher speeds with minimal interference from adjacent lanes. In at least one embodiment, the other two antennas may extend the field of view, allowing for quick detection of vehicles entering or exiting the lane of vehicle 1000.

[0185] In at least one embodiment, the medium-range RADAR system may include, by way of example, a range of up to 160 meters (forward) or 80 meters (rearward) and a field of view of up to 42 degrees (forward) or 150 degrees (rearward). In at least one embodiment, the short-range RADAR system may include, without limitation, any number of RADAR sensors 1060 designed to be mounted on either end of the rear bumper. When mounted on either end of the rear bumper, in at least one embodiment, the RADAR sensor system may generate two beams that constantly monitor blind spots behind and adjacent to the vehicle. In at least one embodiment, the short-range RADAR system may be used in an ADAS system 1038 to provide blind spot detection and / or lane change assistance.

[0186] In at least one embodiment, vehicle 1000 may further include ultrasonic sensors 1062. In at least one embodiment, ultrasonic sensors 1062 may be located at the front, rear, and / or sides of vehicle 1000 and may be used for parking assistance and / or to generate and update an occupancy grid. In at least one embodiment, multiple ultrasonic sensors 1062 may be used, and different ultrasonic sensors 1062 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, ultrasonic sensors 1062 may operate at functional safety level ASIL B.

[0187] In at least one embodiment, vehicle 1000 may include a LIDAR sensor 1064. In at least one embodiment, LIDAR sensor 1064 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, LIDAR sensor 1064 may operate at functional safety level ASIL B. In at least one embodiment, vehicle 1000 may include multiple LIDAR sensors 1064 (e.g., two, four, six, etc.), which may use an Ethernet channel (e.g., to provide data to a Gigabit Ethernet switch).

[0188] In at least one embodiment, the LIDAR sensor 1064 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, a commercially available LIDAR sensor 1064 may, for example, have an advertised range of approximately 100 meters, an accuracy of 2 cm to 3 cm, and support a 100 Mbps Ethernet connection. In at least one embodiment, one or more non-protruding LIDAR sensors may be used. In such an embodiment, the LIDAR sensor 1064 may include a small device that can be integrated into the front, rear, side, and / or corner positions of the vehicle 1000. In at least one embodiment, the LIDAR sensor 1064 of such an embodiment may provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, with a range of 200 meters, even for low-reflectivity objects. In at least one embodiment, a front-mounted LIDAR sensor 1064 may be configured to provide a horizontal field of view of 45 degrees to 135 degrees.

[0189] In at least one embodiment, LIDAR technology such as 3D flash LIDAR may also be used. In at least one embodiment, the 3D flash LIDAR uses a laser flash as a transmission source to illuminate the area around the vehicle 1000 up to approximately 200 meters. In at least one embodiment, the flash LIDAR unit includes, without limitation, a receptor that records the transit time of the laser pulse and the reflected light at each pixel, which corresponds to the range from the vehicle 1000 to the object. In at least one embodiment, the flash LIDAR allows a highly accurate, undistorted image of the area to be generated with each laser flash. In at least one embodiment, four flash LIDARs may be deployed, one on each side of the vehicle 1000. In at least one embodiment, the 3D flash LIDAR system includes, without limitation, a solid-state 3D staring array LIDAR camera (e.g., a non-scanning LIDAR device) with no moving parts other than a fan. In at least one embodiment, the flash LIDAR device may use 5 nanosecond Class I (eye-safe) laser pulses per frame and may capture reflected laser light as a 3D range point cloud and co-registered intensity data.

[0190] In at least one embodiment, vehicle 1000 may further include an IMU sensor 1066. In at least one embodiment, IMU sensor 1066 may be positioned at the center of a rear axle of vehicle 1000. In at least one embodiment, IMU sensor 1066 may include, for example, without limitation, an accelerometer, a magnetometer, a gyroscope, a magnetic compass, multiple magnetic compasses, and / or other types of sensors. In at least one embodiment, such as in a 6-axis application, IMU sensor 1066 may include, without limitation, an accelerometer and a gyroscope. In at least one embodiment, such as in a 9-axis application, IMU sensor 1066 may include, without limitation, an accelerometer, a gyroscope, and a magnetometer.

[0191] In at least one embodiment, the IMU sensor 1066 may be implemented as a compact, high-performance GPS-Aided Inertial Navigation System ("GPS / INS") that combines micro-electro-mechanical systems ("MEMS") inertial sensors, a highly sensitive GPS receiver, and advanced Kalman filtering algorithms to provide estimates of position, velocity, and attitude. In at least one embodiment, the IMU sensor 1066 enables the vehicle 1000 to estimate its heading by directly observing velocity changes and correlating them from the GPS to the IMU sensor 1066 without requiring input from a magnetic sensor. In at least one embodiment, the IMU sensor 1066 and the GNSS sensor 1058 may be combined into a single integrated unit.

[0192] In at least one embodiment, vehicle 1000 may include microphones 1096 located in and / or around vehicle 1000. In at least one embodiment, microphones 1096 may be used for, among other things, detection and identification of emergency vehicles.

[0193] In at least one embodiment, vehicle 1000 may further include any number of camera types, including stereo cameras 1068, wide-angle cameras 1070, infrared cameras 1072, perimeter cameras 1074, long-range cameras 1098, mid-range cameras 1076, and / or other camera types. In at least one embodiment, cameras may be used to capture image data around the entire perimeter of vehicle 1000. In at least one embodiment, the types of cameras used vary depending on vehicle 1000. In at least one embodiment, any combination of camera types may be used to provide the required coverage around vehicle 1000. In at least one embodiment, the number of cameras deployed may vary depending on the embodiment. For example, in at least one embodiment, vehicle 1000 may include six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. In at least one embodiment, the cameras may support, by way of example and not limitation, Gigabit Multimedia Serial Link ("GMSL") and / or Gigabit Ethernet communications. In at least one embodiment, each camera may be as described in further detail herein above with respect to Figures 10A and 10B.

[0194] In at least one embodiment, vehicle 1000 may further include a vibration sensor 1042. In at least one embodiment, vibration sensor 1042 may measure vibration of a component of vehicle 1000, such as an axle. For example, in at least one embodiment, a change in vibration may indicate a change in the road surface. In at least one embodiment, if two or more vibration sensors 1042 are used, the difference in vibration may be used to determine the amount of friction or slippage of the road surface (e.g., if there is a vibration difference between a powered axle and a free-spinning axle).

[0195] In at least one embodiment, vehicle 1000 may include an ADAS system 1038. In at least one embodiment, ADAS system 1038 may include, without limitation, an SoC in some instances. In at least one embodiment, the ADAS systems 1038 may include, without limitation, any number and combination of autonomous / adaptive / automatic cruise control ("ACC") systems, cooperative adaptive cruise control ("CACC") systems, forward crash warning ("FCW") systems, automatic emergency braking ("AEB") systems, lane departure warning ("LDW") systems, lane keep assist ("LKA") systems, blind spot warning ("BSW") systems, rear cross-traffic warning ("RCTW") systems, collision warning ("CW") systems, lane centering ("LC") systems, and / or other systems, features, and / or functions.

[0196] In at least one embodiment, the ACC system may use a RADAR sensor 1060, a LIDAR sensor 1064, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle directly in front of the vehicle 1000 and automatically adjusts the speed of the vehicle 1000 to maintain a safe distance from the vehicle in front. In at least one embodiment, the lateral ACC system enforces distance maintenance and notifies the vehicle 1000 to change lanes when necessary. In at least one embodiment, the lateral ACC is related to other ADAS applications, such as LC and CW.

[0197] In at least one embodiment, the CACC system uses information from other vehicles, which may be received by the network interface 1024 and / or wireless antenna 1026 from other vehicles via a wireless link or indirectly via a network connection (e.g., via the Internet). In at least one embodiment, a vehicle-to-vehicle ("V2V") communication link may provide a direct link, while an infrastructure-to-vehicle ("I2V") communication link may provide an indirect link. Generally, V2V communication provides information about the immediate preceding vehicle (e.g., a vehicle immediately in front of and in the same lane as vehicle 1000), while I2V communication provides information about traffic ahead of that. In at least one embodiment, the CACC system may include either or both I2V and V2V information sources. In at least one embodiment, information about vehicles in front of vehicle 1000 may make the CACC system more reliable, potentially allowing for smoother traffic flow and reducing congestion on the roads.

[0198] In at least one embodiment, the FCW system is designed to warn drivers of hazards so that they can take corrective action. In at least one embodiment, the FCW system uses a front-facing camera and / or RADAR sensor 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC that is electrically coupled to provide feedback to the driver, such as a display, speaker, and / or vibration components. In at least one embodiment, the FCW system may provide warnings in the form of an audible, visual warning, vibration, and / or a quick brake pulse.

[0199] In at least one embodiment, the AEB system may detect an imminent frontal collision with another vehicle or other object and automatically apply the brakes if the driver does not take corrective action within specified time or distance parameters. In at least one embodiment, the AEB system may use a front-facing camera and / or RADAR sensor 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, the AEB system typically first advises the driver to take corrective action to avoid the collision, and if the driver does not take corrective action, the AEB system may automatically apply the brakes to prevent or at least mitigate the severity of the predicted collision. In at least one embodiment, the AEB system may include techniques such as dynamic brake support and / or pre-collision braking.

[0200] In at least one embodiment, the LDW system provides visual, audible, and / or tactile warnings, such as vibration of the steering wheel or seat, to advise the driver when the vehicle 1000 crosses a lane marker. In at least one embodiment, the LDW system does not engage if the driver indicates an intentional lane departure, such as by activating a turn signal. In at least one embodiment, the LDW system may use a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC that can be electrically coupled to provide feedback to the driver, such as a display, speaker, and / or vibration component. In at least one embodiment, the LKA system is a variation of the LDW system. In at least one embodiment, the LKA system provides steering input or brake control to correct the vehicle 1000 if the vehicle 1000 begins to stray from its lane.

[0201] In at least one embodiment, the BSW system detects vehicles in the vehicle's blind spot and warns the driver. In at least one embodiment, the BSW system may provide visual, audible, and / or haptic alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system may provide an additional warning when the driver uses a turn signal. In at least one embodiment, the BSW system may use a rearview camera and / or RADAR sensor 1060 coupled to dedicated processors, DSPs, FPGAs, and / or ASICs, which are electrically coupled to feedback to the driver, such as a display, speaker, and / or vibration components.

[0202] In at least one embodiment, the RCTW system may provide visual, audible, and / or tactile notifications when an object is detected outside the range of the rear camera when reversing the vehicle 1000. In at least one embodiment, the RCTW system includes an AEB system to ensure vehicle braking is applied to avoid a collision. In at least one embodiment, the RCTW system may use one or more rear RADAR sensors 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC that is electrically coupled to provide feedback to the driver, such as a display, speaker, and / or vibration components.

[0203] In at least one embodiment, conventional ADAS systems may be prone to false positive results, which can be annoying and distracting to the driver, but are typically not a major concern because conventional ADAS systems advise the driver and allow the driver to determine whether a safety condition truly exists and respond accordingly. In at least one embodiment, in the event of conflicting results, the vehicle 1000 itself determines whether to follow the results from a primary computer (e.g., a first controller of the controller 1036) or a secondary computer (e.g., a second controller of the controller 1036). For example, in at least one embodiment, the ADAS system 1038 may be a backup and / or secondary computer for transmitting perceptual information to a rationality module of the backup computer. In at least one embodiment, a rationality monitor of the backup computer may run redundant software on various hardware components to detect perceptual errors and dynamic driving tasks. In at least one embodiment, output from the ADAS system 1038 may be provided to a supervisory MCU. In at least one embodiment, if the output from the primary computer and the output from the secondary computer conflict, the supervisory MCU determines how to reconcile the conflict to ensure safe operation.

[0204] In at least one embodiment, the primary computer may be configured to provide the monitor MCU with a reliability score indicating the reliability of the primary computer's selected result. In at least one embodiment, if the reliability score exceeds a threshold, the monitor MCU may follow the primary computer's instructions regardless of whether the secondary computers are providing conflicting or inconsistent results. In at least one embodiment, if the reliability score does not meet the threshold and the primary and secondary computers provide different (e.g., conflicting) results, the monitor MCU may arbitrate between the computers to determine the appropriate result.

[0205] In at least one embodiment, the monitoring MCU may be configured to execute a neural network trained and configured to determine conditions under which the secondary computer will provide a false alarm based at least in part on outputs from the primary computer and the secondary computer. In at least one embodiment, the neural network of the monitoring MCU may learn when the output of the secondary computer may be trusted and when it may not be trusted. For example, in at least one embodiment, if the secondary computer is a RADAR-based FCW system, the neural network of the monitoring MCU may learn when the FCW system identifies a metal object that is not actually a hazard, such as a drain grate or manhole cover, which triggers an alarm. In at least one embodiment, if the secondary computer is a camera-based LDW system, the neural network of the monitoring MCU may learn to disable LDW when a bicyclist or pedestrian is present and lane departure is actually the safest maneuver. In at least one embodiment, the monitoring MCU may include at least one of a DLA or a GPU suitable for executing the neural network along with associated memory. In at least one embodiment, the supervisory MCU may comprise and / or be included as a component of the SoC 1004.

[0206] In at least one embodiment, the ADAS system 1038 may include a secondary computer that performs ADAS functions using traditional rules of computer vision. In at least one embodiment, the secondary computer may use traditional computer vision rules (if-then rules), and neural networks may reside in the supervisory MCU, improving reliability, safety, and performance. For example, in at least one embodiment, diverse implementations and intentional non-identity may increase the overall system's error tolerance, particularly against errors caused by software (or software-hardware interface) functionality. For example, in at least one embodiment, if there is a bug or error in the software running on the primary computer and non-identical software code running on the secondary computer provides overall consistent results, the supervisory MCU may have greater confidence that the overall results are correct and that a software or hardware bug on the primary computer did not cause a critical error.

[0207] In at least one embodiment, the output of the ADAS system 1038 may be provided to a perception block of the primary computer and / or a dynamic driving task block of the primary computer. For example, in at least one embodiment, if the ADAS system 1038 indicates a frontal collision warning due to an immediately preceding object, the perception block may use this information when identifying the object. In at least one embodiment, the secondary computer may have its own neural network that is pre-trained, as described herein, thus reducing the risk of false positives.

[0208] In at least one embodiment, vehicle 1000 may further include an infotainment SoC 1030 (e.g., an in-vehicle infotainment system (IVI)). While infotainment system 1030 is shown and described as an SoC, in at least one embodiment, it may not be an SoC and may include, without limitation, two or more separate components. In at least one embodiment, infotainment SoC 1030 may include, without limitation, a combination of hardware and software that may be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), telephony (e.g., hands-free calling), network connectivity (e.g., LTE, Wi-Fi, etc.), and / or information services (e.g., navigation system, reverse parking assist, wireless data system, vehicle-related information such as fuel level, total mileage, brake fuel level, oil level, door opening / closing, air filter information, etc.) to vehicle 1000. For example, infotainment SoC 1030 may include a radio, a disc player, a navigation system, a video player, USB and Bluetooth connectivity, a car computer, in-car entertainment, Wi-Fi, steering wheel audio controls, hands-free voice control, a heads-up display (“HUD”), an HMI display 1034, telematics devices, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, infotainment SoC 1030 may also be used to provide information (e.g., visual and / or auditory) to a user of vehicle 1000, such as information from ADAS system 1038, autonomous driving information such as vehicle maneuver plans, trajectories, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0209] In at least one embodiment, infotainment SoC 1030 may include any amount and type of GPU functionality. In at least one embodiment, infotainment SoC 1030 may communicate with other devices, systems, and / or components of vehicle 1000 via bus 1002. In at least one embodiment, infotainment SoC 1030 may be coupled to a supervisory MCU, such that the infotainment system's GPU may perform some self-driving functions when primary controller 1036 (e.g., vehicle 1000's primary and / or backup computer) fails. In at least one embodiment, infotainment SoC 1030 may place vehicle 1000 in a driver-safety shutdown mode, as described herein.

[0210] In at least one embodiment, vehicle 1000 may further include an instrument cluster 1032 (e.g., a digital dashboard, an electronic instrument cluster, a digital instrument panel, etc.). In at least one embodiment, instrument cluster 1032 may include, without limitation, a controller and / or a supercomputer (e.g., a separate controller or supercomputer). In at least one embodiment, instrument cluster 1032 may include any number and combination of instrument sets, such as, without limitation, a speedometer, fuel level, oil pressure, a tachometer, an odometer, turn signals, a shift lever position indicator, a seat belt warning light, a parking brake warning light, an engine malfunction light, supplemental restraint system (e.g., airbag) information, light control, safety system control, navigation information, etc. In some instances, information may be displayed and / or shared between infotainment SoC 1030 and instrument cluster 1032. In at least one embodiment, instrument cluster 1032 may be included as part of infotainment SoC 1030, or vice versa.

[0211] Inference and / or training logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, inference and / or training logic 715 may be used in the system of Figure 10C for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0212] In at least one embodiment, at least one component shown or described with respect to FIG. 10C is used to implement the techniques and / or functionality described with respect to FIGS. 1-6. In at least one embodiment, the inference and / or training logic 715 includes and / or operates at least one aspect described with respect to FIG. 1 (e.g., deep learning compiler 102, scheduler 114, code generator 116). In at least one embodiment, the inference and / or training logic 715 trains at least one untrained or partially trained neural network using a computer program representation (e.g., code 106 or runtime code 120 of FIG. 1) that combines two or more dependency reduction operations into a software kernel, as described with respect to one or more of FIGS. 1-6. In at least one embodiment, the inference and / or training logic performs at least one inference operation using a computer program representation (e.g., code 106 or runtime code 120 of FIG. 1) that combines two or more dependency reduction operations, as described with respect to one or more of FIGS. 1-6.

[0213] 10D is a diagram of a system for communicating between a cloud-based server and the autonomous vehicle 1000 of FIG. 10A , according to at least one embodiment. In at least one embodiment, the system may include any number and type of vehicles, including, without limitation, a server 1078, a network 1090, and the vehicle 1000. In at least one embodiment, the server 1078 may include, without limitation, multiple GPUs 1084(A)-1084(H) (collectively referred to herein as GPUs 1084), PCIe switches 1082(A)-1082(D) (collectively referred to herein as PCIe switches 1082), and / or CPUs 1080(A)-1080(B) (collectively referred to herein as CPUs 1080). In at least one embodiment, the GPUs 1084, CPUs 1080, and PCIe switches 1082 may be interconnected by a high-speed interconnect, such as, for example, without limitation, an NVLink interface 1088 developed by NVIDIA and / or a PCIe connection 1086. In at least one embodiment, the GPUs 1084 are connected to each other via an NVLink and / or an NVSwitch SoC, and the GPUs 1084 and PCIe switches 1082 are connected via a PCIe interconnect. While eight GPUs 1084, two CPUs 1080, and four PCIe switches 1082 are illustrated, this is not intended to be limiting. In at least one embodiment, each of the servers 1078 may include any number of GPUs 1084, CPUs 1080, and / or PCIe switches 1082 in any combination, without limitation. For example, in at least one embodiment, the servers 1078 may each include 8, 16, 32, and / or more GPUs 1084.

[0214] In at least one embodiment, server 1078 may receive image data from a vehicle over network 1090 representing images showing unexpected or changed road conditions, such as recently begun road construction. In at least one embodiment, server 1078 may transmit updated or unupdated neural network 1092 and / or map information 1094, including, without limitation, information about traffic and road conditions, to the vehicle over network 1090. In at least one embodiment, updates to map information 1094 may include, without limitation, updates to HD map 1022, such as information about construction sites, potholes, detours, floods, and / or other obstacles. In at least one embodiment, neural network 1092 and / or map information 1094 may be derived from new training and / or experience represented in data received from any number of vehicles in the environment and / or may be derived based at least in part on training performed at a data center (e.g., using server 1078 and / or other servers).

[0215] In at least one embodiment, server 1078 may be used to train a machine learning model (e.g., a neural network) based at least in part on the training data. In at least one embodiment, the training data may be generated by the vehicle and / or generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of the training data may be tagged and / or otherwise preprocessed (e.g., if the associated neural network benefits from supervised learning). In at least one embodiment, any amount of the training data may not be tagged and / or preprocessed (e.g., if the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, it may be used by the vehicle (e.g., transmitted to the vehicle via network 1090) and / or used by server 1078 to remotely monitor the vehicle.

[0216] In at least one embodiment, server 1078 may receive data from vehicles and apply the data to state-of-the-art, real-time neural networks to enable real-time intelligent inference. In at least one embodiment, server 1078 may include a deep learning supercomputer and / or dedicated AI computer powered by a GPU 1084, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, server 1078 may also include a deep learning infrastructure using a CPU-powered data center.

[0217] In at least one embodiment, the deep learning infrastructure of server 1078 may be capable of rapid real-time inference and may use that capability to assess and verify the health of the processor, software, and / or associated hardware of vehicle 1000. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 1000, such as a series of images and / or objects that vehicle 1000 has located in the series of images (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them to those identified by vehicle 1000; if the results do not match and the deep learning infrastructure concludes that the AI ​​of vehicle 1000 has failed, server 1078 may send a signal to vehicle 1000 instructing the vehicle's 1000 fail-safe computer to take control, notify the occupants, and complete a safe stopping maneuver.

[0218] In at least one embodiment, server 1078 may include a GPU 1084 and one or more programmable inference accelerators (e.g., NVIDIA TensorRT3 devices). In at least one embodiment, the combination of a GPU-powered server and inference acceleration can enable real-time response. In at least one embodiment, CPU, FPGA, and other processor-powered servers may be used for inference, such as when performance is less critical. In at least one embodiment, a hardware structure 715 is used to execute one or more embodiments. Details regarding hardware structure 715 are provided herein in conjunction with FIG. 7A and / or FIG. 7B.

[0219] Computer Systems 11 is a block diagram illustrating an exemplary computer system, which may be a system having interconnected devices and components, a system-on-a-chip (SoC), or some combination thereof, formed with a processor that may include an execution unit for executing instructions, according to at least one embodiment. In at least one embodiment, computer system 1100 may include components such as, without limitation, processor 1102 for using an execution unit that includes logic for executing algorithms for processing data in accordance with the present disclosure, such as in the embodiments described herein. In at least one embodiment, computer system 1100 may include a processor such as the PENTIUM® processor family, Xeon™, Itanium®, XScale™ and / or StrongARM™, Intel® Core™, or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems may be used (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.). In at least one embodiment, computer system 1100 may run a version of the WINDOWS® operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (e.g., UNIX® and Linux®), embedded software, and / or graphical user interfaces may also be used.

[0220] Embodiments may be used in other devices, such as portable devices and embedded applications. Some examples of portable devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants ("PDAs"), and portable PCs. In at least one embodiment, embedded applications may include microcontrollers, digital signal processors ("DSPs"), systems-on-chips, network computers ("NetPCs"), set-top boxes, network hubs, wide area network ("WAN") switches, or any other system capable of executing one or more instructions according to at least one embodiment.

[0221] In at least one embodiment, computer system 1100 may include, without limitation, a processor 1102, which may include one or more execution units 1108 for performing machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, computer system 1100 is a single-processor desktop or server system, while in other embodiments, computer system 1100 may be a multiprocessor system. In at least one embodiment, processor 1102 may include, without limitation, a complex instruction set computer ("CISC") microprocessor, a reduced instruction set computing ("RISC") microprocessor, a very long instruction word ("VLIW") microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 1102 may be coupled to a processor bus 1110, which may transmit digital signals between processor 1102 and other components within computer system 1100.

[0222] In at least one embodiment, processor 1102 may include, without limitation, level 1 ("L1") internal cache memory ("cache") 1104. In at least one embodiment, processor 1102 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may be external to processor 1102. Other embodiments may include a combination of both internal and external cache, depending on the particular implementation and needs. In at least one embodiment, register file 1106 may store different types of data in various registers, including, without limitation, integer registers, floating-point registers, status registers, and instruction pointer registers.

[0223] In at least one embodiment, processor 1102 also includes an execution unit 1108, including, without limitation, logic for performing integer and floating-point operations. In at least one embodiment, processor 1102 may also include microcode (“u-code”) read-only memory (“ROM”) that stores microcode for certain macroinstructions. In at least one embodiment, execution unit 1108 may include logic for a packed instruction set 1109. In at least one embodiment, including a packed instruction set 1109, along with associated circuitry for executing the instructions, in a general-purpose processor's instruction set allows operations used by many multimedia applications to be performed using packed data in processor 1102. In at least one embodiment, many multimedia applications can be accelerated and executed more efficiently by performing operations on packed data using the full width of the processor's data bus, thereby eliminating the need to transfer smaller units of data between the processor's data bus to perform one or more operations on one data element at a time.

[0224] In at least one embodiment, execution unit 1108 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 1100 may include, without limitation, memory 1120. In at least one embodiment, memory 1120 may be a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or other memory device. In at least one embodiment, memory 1120 may store instructions 1119 and / or data 1121 represented by data signals that may be executed by processor 1102.

[0225] In at least one embodiment, a system logic chip may be coupled to the processor bus 1110 and the memory 1120. In at least one embodiment, the system logic chip may include, without limitation, a memory controller hub (“MCH”) 1116, and the processor 1102 may communicate with the MCH 1116 via the processor bus 1110. In at least one embodiment, the MCH 1116 may provide a high-bandwidth memory path 1118 to the memory 1120 for storing instructions and data, and for storing graphics commands, data, and textures. In at least one embodiment, the MCH 1116 may route data signals between the processor 1102, the memory 1120, and other components of the computer system 1100, and may bridge data signals between the processor bus 1110, the memory 1120, and a system I / O interface 1122. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1116 may be coupled to memory 1120 via a high-bandwidth memory path 1118, and the graphics / video card 1112 may be coupled to the MCH 1116 via an Accelerated Graphics Port (“AGP”) interconnect 1114.

[0226] In at least one embodiment, computer system 1100 may use system I / O interface 1122 as a proprietary hub interface bus to couple MCH 1116 to I / O controller hub (“ICH”) 1130. In at least one embodiment, ICH 1130 may provide direct connectivity to several I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, without limitation, a high-speed I / O bus for connecting peripherals to memory 1120, a chipset, and processor 1102. Examples may include, without limitation, an audio controller 1129, a firmware hub ("flash BIOS") 1128, a wireless transceiver 1126, data storage 1124, a legacy I / O controller 1123 including a user input and keyboard interface 1125, a serial expansion port 1127 such as a Universal Serial Bus ("USB") port, and a network controller 1134. In at least one embodiment, data storage 1124 may comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0227] In at least one embodiment, Figure 11 illustrates a system including interconnected hardware devices or "chips," while in other embodiments, Figure 11 may illustrate an exemplary SoC. In at least one embodiment, the devices illustrated in Figure 11 may be interconnected using a proprietary interconnect, a standard interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 1100 may be interconnected using a compute express link (CXL) interconnect.

[0228] Inference and / or training logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, inference and / or training logic 715 may be used in the system of Figure 11 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0229] In at least one embodiment, at least one component shown or described with respect to FIG. 11 is used to implement the techniques and / or functionality described with respect to FIGS. 1-6. In at least one embodiment, the inference and / or training logic 715 includes and / or operates at least one aspect described with respect to FIG. 1 (e.g., deep learning compiler 102, scheduler 114, code generator 116). In at least one embodiment, the inference and / or training logic 715 trains at least one untrained or partially trained neural network using a computer program representation (e.g., code 106 or runtime code 120) that combines two or more dependency reduction operations, as described with respect to one or more of FIGS. 1-6. In at least one embodiment, the inference and / or training logic performs at least one inference operation using a computer program representation (e.g., code 106 or runtime code 120 of FIG. 1) that combines two or more dependency reduction operations, as described with respect to one or more of FIGS. 1-6. In at least one embodiment, the processor 1102 and / or other components of the computer system 1100 of FIG. 11 are utilized to implement the techniques and / or functionality described in connection with FIGS. 1-6.

[0230] 12 is a block diagram illustrating an electronic device 1200 for utilizing a processor 1210, according to at least one embodiment. In at least one embodiment, electronic device 1200 may be, for example, without limitation, a notebook, a tower server, a rack server, a blade server, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0231] In at least one embodiment, electronic device 1200 may include, without limitation, a processor 1210 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. 2 The devices may be coupled using a bus or interface such as a C bus, a System Management Bus (“SMBus”), a Low Pin Count (LPC) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advance Technology Attachment (“SATA”) bus, a Universal Serial Bus (“USB”) (versions 1, 2, 3, etc.), or a Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, FIG. 12 illustrates a system including interconnected hardware devices or “chips,” while in other embodiments, FIG. 12 may illustrate an exemplary SoC. In at least one embodiment, the devices illustrated in FIG. 12 may be interconnected using a proprietary interconnect, a standard interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of FIG. 12 may be interconnected using a Compute Express Link (CXL) interconnect.

[0232] In at least one embodiment, FIG. 12 illustrates a display 1224, a touch screen 1225, a touch pad 1230, a Near Field Communications unit ("NFC") 1245, a sensor hub 1240, a thermal sensor 1246, an Express Chipset ("EC") 1235, a Trusted Platform Module ("TPM") 1238, a BIOS / firmware / flash memory ("BIOS,FW flash") 1222, a DSP 1260, a drive 1220, such as a solid state disk ("SSD") or hard disk drive ("HDD"), a wireless local area network unit ("WLAN") 1250, a Bluetooth unit 1252, a wireless wide area network unit ("WWAN") 1254, a Bluetooth module 1254, a Bluetooth-enabled device ("Bluetooth") 1256, a Bluetooth-enabled device ("Bluetooth") 1258, a Bluetooth-enabled device ("Bluetooth") 1260, a Bluetooth-enabled device ("Bluetooth") 1262, a Bluetooth-enabled device ("Bluetooth") 1264, a Bluetooth-enabled device ("Bluetooth") 1266, a Bluetooth-enabled device ("Bluetooth") 1268 ... The memory may include a memory controller (RAM) 1256, a Global Positioning System (GPS) unit 1255, a camera such as a USB 3.0 camera ("USB 3.0 camera") 1254, and / or a Low Power Double Data Rate ("LPDDR") memory unit ("LPDDR3") 1215, implemented, for example, to the LPDDR3 standard. Each of these components may be implemented in any suitable manner.

[0233] In at least one embodiment, other components may be communicatively coupled to processor 1210 via the aforementioned components. In at least one embodiment, accelerometer 1241, ambient light sensor (“ALS”) 1242, compass 1243, and gyroscope 1244 may be communicatively coupled to sensor hub 1240. In at least one embodiment, thermal sensor 1239, fan 1237, keyboard 1236, and touchpad 1230 may be communicatively coupled to EC 1235. In at least one embodiment, speaker 1263, headphones 1264, and microphone (“mic”) 1265 may be communicatively coupled to audio unit (audio codec and class D amplifier) ​​1262, which may be communicatively coupled to DSP 1260. In at least one embodiment, audio unit 1262 may include, for example, without limitation, an audio coder / decoder (“codec”) and a class D amplifier. In at least one embodiment, a SIM card (“SIM”) 1257 may be communicatively coupled to the WWAN unit 1256. In at least one embodiment, components such as the WLAN unit 1250 and Bluetooth unit 1252, and the WWAN 1256 may be implemented in a Next Generation Form Factor (“NGFF”).

[0234] Inference and / or training logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, inference and / or training logic 715 may be used in the system of Figure 12 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0235] In at least one embodiment, at least one component shown or described with respect to FIG. 12 is used to implement the techniques and / or functionality described with respect to FIG. 1-6. In at least one embodiment, the inference and / or training logic 715 includes and / or operates at least one aspect described with respect to FIG. 1 (e.g., deep learning compiler 102, scheduler 114, code generator 116). In at least one embodiment, the inference and / or training logic 715 trains at least one untrained or partially trained neural network using a computer program representation (e.g., code 106 or runtime code 120) that combines two or more dependency reduction operations, as described with respect to one or more of FIG. 1-6. In at least one embodiment, the inference and / or training logic performs at least one inference operation using a computer program representation (e.g., code 106 or runtime code 120) that combines two or more dependency reduction operations, as described with respect to one or more of FIG. 1-6. In at least one embodiment, the system 1200 and / or processor 1210 of FIG. 12 are utilized to implement the techniques and / or functionality described in connection with FIGS.

[0236] 13 illustrates, according to at least one embodiment, a computer system 1300. In at least one embodiment, the computer system 1300 is configured to implement the various processes and methods described throughout this disclosure.

[0237] In at least one embodiment, computer system 1300 includes at least one central processing unit ("CPU") 1302 connected to a communication bus 1310 implemented using any suitable protocol, such as, without limitation, PCI (Peripheral Component Interconnect), Peripheral Component Interconnect Express ("PCI-Express"), AGP (Accelerated Graphics Port), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, computer system 1300 includes main memory 1304 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data is stored in main memory 1304, which may be in the form of random access memory ("RAM"). In at least one embodiment, network interface subsystem (“network interface”) 1322 provides an interface with other computing devices and networks to receive data from other systems comprising computer system 1300 and to transmit data to other systems comprising computer system 1300.

[0238] In at least one embodiment, computer system 1300 includes, without limitation, input device(s) 1308, a parallel processing system 1312, and a display device 1306, which may be implemented using a conventional cathode ray tube ("CRT"), liquid crystal display ("LCD"), light emitting diode ("LED") display, plasma display, or other suitable display technology. In at least one embodiment, user input is received from input device(s) 1308, such as a keyboard, mouse, touch pad, microphone, or the like. In at least one embodiment, each of the modules described herein may be located on a single semiconductor platform to form a processing system.

[0239] Inference and / or training logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, training logic 715 may be used in the system of Figure 13 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0240] In at least one embodiment, at least one component shown or described with respect to Figure 13 is used to implement the techniques and / or functionality described with respect to Figures 1-6. In at least one embodiment, the inference and / or training logic 715 includes and / or operates at least one aspect (e.g., deep learning compiler 102, scheduler 114, code generator 116) described with respect to Figure 1. In at least one embodiment, the inference and / or training logic 715 trains at least one untrained or partially trained neural network using a computer program representation (e.g., code 106 or runtime code 120 of Figure 1) that combines two or more dependency reduction operations into a software kernel, as described with respect to one or more of Figures 1-6. In at least one embodiment, the inference and / or training logic performs at least one inference operation using a computer program representation (e.g., code 106 or runtime code 120 of FIG. 1) that combines two or more dependency reduction operations into a software kernel, as described with respect to one or more of FIGs. 1-6. In at least one embodiment, computer system 1300 and / or at least one PPU 1314 of FIG. 13 are utilized to implement the techniques and / or functionality described with respect to FIGs. 1-6.

[0241] 14 illustrates a computer system 1400 according to at least one embodiment. In at least one embodiment, computer system 1400 may include, without limitation, a computer 1410 and a USB stick 1420. In at least one embodiment, computer system 1410 may include, without limitation, any number and type of processor (not shown) and memory. In at least one embodiment, computer 1410 includes, without limitation, a server, a cloud instance, a laptop, and a desktop computer.

[0242] In at least one embodiment, USB stick 1420 includes, without limitation, a processing unit 1430, a USB interface 1440, and USB interface logic 1450. In at least one embodiment, processing unit 1430 may be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, processing unit 1430 may include, without limitation, any number and type of processing cores (not shown). In at least one embodiment, processing unit 1430 comprises an application specific integrated circuit (“ASIC”) optimized to perform any quantity and type of operations related to machine learning. For example, in at least one embodiment, processing unit 1430 is a tensor processing unit (“TPC”) optimized to perform machine vision and machine learning inference operations. In at least one embodiment, processing unit 1430 is a vision processing unit (“VPU”) optimized to perform machine vision and machine learning inference operations.

[0243] In at least one embodiment, USB interface 1440 may be any type of USB connector or socket. For example, in at least one embodiment, USB interface 1440 is a USB 3.0 Type-C socket for data and power. In at least one embodiment, USB interface 1440 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1450 may include any amount and type of logic that enables processing unit 1430 to interface with a device (e.g., computer 1410) via USB connector 1440.

[0244] Inference and / or training logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, inference and / or training logic 715 may be used in the system of Figure 14 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0245] In at least one embodiment, at least one component shown or described with respect to FIG. 14 is used to implement the techniques and / or functionality described with respect to FIGS. 1-6. In at least one embodiment, the inference and / or training logic 715 includes and / or operates at least one aspect described with respect to FIG. 1 (e.g., deep learning compiler 102, scheduler 114, code generator 116). In at least one embodiment, the inference and / or training logic 715 trains at least one untrained or partially trained neural network using a computer program representation (e.g., code 106 or runtime code 120) that combines two or more dependency reduction operations into a software kernel, as described with respect to one or more of FIGS. 1-6. In at least one embodiment, the inference and / or training logic performs at least one inference operation using a computer program representation (e.g., code 106 or runtime code 120) that combines two or more dependency reduction operations into a software kernel, as described with respect to one or more of FIGS. 1-6. In at least one embodiment, processing unit 1430 of FIG. 14 is utilized to implement the techniques and / or functionality described in connection with FIGS.

[0246] FIG. 15A illustrates an exemplary architecture in which multiple GPUs 1510(1)-1510(N) are communicatively coupled to multiple multi-core processors 1505(1)-1505(M) via high-speed links 1540(1)-1540(N) (e.g., buses, point-to-point interconnects, etc.). In at least one embodiment, the high-speed links 1540(1)-1540(N) support communication throughputs of 4 GB / s, 30 GB / s, 80 GB / s, or more. In at least one embodiment, various interconnect protocols may be used, including, but not limited to, PCIe 4.0 or 5.0 and NVLink 2.0. In the various figures, "N" and "M" represent positive integers, the values ​​of which may vary from figure to figure.

[0247] Additionally, in at least one embodiment, two or more of the GPUs 1510 are interconnected via high-speed links 1529(1)-1529(2), which may be implemented using similar or different protocols / links as used for high-speed links 1540(1)-1540(N). Similarly, two or more of the multi-core processors 1505 may be connected via high-speed link 1528, which may be a symmetric multiprocessor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or more. Alternatively, all communications between the various system components shown in FIG. 15A may be achieved using similar protocols / links (e.g., via a common interconnect fabric).

[0248] In at least one embodiment, each multi-core processor 1505 is communicatively coupled to processor memory 1501(1)-1501(M) via memory interconnect 1526(1)-1526(M), respectively, and each GPU 1510(1)-1510(N) is communicatively coupled to GPU memory 1520(1)-1520(N) via GPU memory interconnect 1550(1)-1550(N), respectively. In at least one embodiment, memory interconnects 1526 and 1550 may utilize similar or different memory access technologies. By way of example, and not limitation, processor memory 1501(1)-1501(M) and GPU memory 1520 may be volatile memory such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high-bandwidth memory (HBM), and / or may be non-volatile memory such as 3D XPoint or Nano-Ram. In at least one embodiment, some portions of processor memory 1501 may be volatile memory and other portions may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0249] As described herein, various multi-core processors 1505 and GPUs 1510 may each be physically coupled to specific memories 1501, 1520, and / or a unified memory architecture may be implemented in which a virtual system address space (also referred to as an "effective address" space) is distributed among various physical memories. For example, processor memories 1501(1) through 1501(M) may each have 64 GB of system memory address space, and GPU memories 1520(1) through 1520(N) may each have 32 GB of system memory address space, resulting in a total of 256 GB of addressable memory when M=2 and N=4. Other values ​​for N and M are contemplated.

[0250] 15B shows further details of the interconnection between multi-core processor 1507 and graphics acceleration module 1546 according to one example embodiment. In at least one embodiment, graphics acceleration module 1546 may include one or more GPU chips integrated on a line card that is coupled to processor 1507 via high-speed link 1540 (e.g., PCIe bus, NVLink, etc.). Alternatively, in at least one embodiment, graphics acceleration module 1546 may be integrated into the package or chip that includes processor 1507.

[0251] In at least one embodiment, the processor 1507 includes multiple cores 1560A-1560D, each having a translation lookaside buffer (“TLB”) 1561A-1561D and one or more caches 1562A-1562D. In at least one embodiment, the cores 1560A-1560D may include various other components, not shown, for executing instructions and processing data. In at least one embodiment, the caches 1562A-1562D may comprise level 1 (L1) and level 2 (L2) caches. Additionally, one or more shared caches 1556 may be included in the caches 1562A-1562D and shared by the set of cores 1560A-1560D. For example, one embodiment of the processor 1507 includes 24 cores, each with its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one or more L2 and L3 caches are shared by two adjacent cores. In at least one embodiment, processor 1507 and graphics acceleration module 1546 are coupled to system memory 1514, which may include processor memories 1501(1) through 1501(M) of FIG. 15A.

[0252] In at least one embodiment, coherence is maintained for data and instructions stored in the various caches 1562A-1562D, 1556, and system memory 1514 through inter-core communication via coherence bus 1564. In at least one embodiment, for example, each cache may have associated cache coherence logic / circuitry for communicating via coherence bus 1564 in response to detecting a read or write to a particular cache line. In at least one embodiment, a cache snooping protocol is implemented via coherence bus 1564 to monitor cache accesses.

[0253] In at least one embodiment, proxy circuit 1525 communicatively couples graphics acceleration module 1546 to coherence bus 1564 to enable graphics acceleration module 1546 to participate in cache coherence protocols as a peer of cores 1560A-1560D. In particular, in at least one embodiment, interface 1535 provides a connection to proxy circuit 1525 over high-speed link 1540, and interface 1537 connects graphics acceleration module 1546 to high-speed link 1540.

[0254] In at least one embodiment, the accelerator integrated circuit 1536 provides cache management, memory access, content management, and interrupt management services on behalf of the multiple graphics processing engines 1531(1)-1531(N) of the graphics acceleration module 1546. In at least one embodiment, the graphics processing engines 1531(1)-1531(N) may each comprise a separate graphics processing unit (GPU). Alternatively, in at least one embodiment, the graphics processing engines 1531(1)-1531(N) may comprise different types of graphics processing engines within a GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module 1546 may be a GPU having multiple graphics processing engines 1531(1)-1531(N), or the graphics processing engines 1531(1)-1531(N) may be individual GPUs integrated into a common package, line card, or chip.

[0255] In at least one embodiment, accelerator integrated circuitry 1536 includes a memory management unit (MMU) 1539 for performing various memory management functions, such as virtual-to-physical memory translation (also referred to as effective-to-real memory translation), and a memory access protocol for accessing system memory 1514. In at least one embodiment, MMU 1539 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective-to-physical / real address translations. In at least one embodiment, cache 1538 may store commands and data for efficient access by graphics processing engines 1531(1)-1531(N). In at least one embodiment, data stored in cache 1538 and graphics memory 1533(1)-1533(M) is kept coherent with core caches 1562A-1562D, 1556, and system memory 1514, possibly using fetch unit 1544. As noted, this may be accomplished via proxy circuitry 1525 (e.g., sending updates to cache 1538 regarding modifications / accesses of cache lines in processor caches 1562A-1562D, 1556, and receiving updates from cache 1538) on behalf of cache 1538 and memory 1533(1)-1533(M).

[0256] In at least one embodiment, a set of registers 1545 stores context data for threads executed by graphics processing engines 1531(1)-1531(N), and a context management circuit 1548 manages thread contexts. For example, the context management circuit 1548 may perform save and restore operations to save and restore the context of various threads during a context switch (e.g., where a first thread is saved and a second thread is saved so that the second thread can be executed by the graphics processing engine). For example, during a context switch, the context management circuit 1548 may store current register values ​​in a designated area of ​​memory (e.g., identified by a context pointer). Then, when returning to the context, the context management circuit 1548 may restore the register values. In at least one embodiment, the interrupt management circuit 1547 receives and processes interrupts received from system devices.

[0257] In at least one embodiment, virtual / effective addresses from the graphics processing engine 1531 are translated to real / physical addresses in the system memory 1514 by the MMU 1539. In at least one embodiment, one embodiment of the accelerator integrated circuit 1536 supports multiple (e.g., four, eight, or sixteen) graphics accelerator modules 1546 and / or other accelerator devices. In at least one embodiment, the graphics accelerator modules 1546 may be dedicated to a single application executing on the processor 1507 or may be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment exists in which the resources of the graphics processing engines 1531(1)-1531(N) are shared with multiple applications or virtual machines (VMs). In at least one embodiment, the resources may be subdivided into “slices,” which are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0258] In at least one embodiment, the accelerator integrated circuit 1536 acts as a bridge to the system for the graphics acceleration module 1546 and provides address translation and system memory caching services. Additionally, in at least one embodiment, the accelerator integrated circuit 1536 may provide a virtualization facility for the host processor to manage virtualization, interrupts, and memory management for the graphics processing engines 1531(1)-1531(N).

[0259] In at least one embodiment, the hardware resources of graphics processing engines 1531(1)-1531(N) are explicitly mapped into the real address space seen by host processor 1507, allowing any host processor to directly address these resources using effective address values. In at least one embodiment, one function of accelerator integrated circuit 1536 is to physically separate graphics processing engines 1531(1)-1531(N) so that they appear to the system as independent units.

[0260] In at least one embodiment, one or more graphics memories 1533(1) through 1533(M) are each coupled to a respective one of the graphics processing engines 1531(1) through 1531(N), where N = M. In at least one embodiment, the graphics memories 1533(1) through 1533(M) store instructions and data to be processed by the respective graphics processing engines 1531(1) through 1531(N). In at least one embodiment, the graphics memories 1533(1) through 1533(M) may be volatile memory such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memory such as 3D XPoint or Nano-Ram.

[0261] In at least one embodiment, to reduce data traffic over high-speed link 1540, biasing techniques may be used to ensure that the data stored in graphics memory 1533(1)-1533(M) is data that will be most frequently used by graphics processing engines 1531(1)-1531(N), and preferably is data that is not used (or at least not frequently used) by cores 1560A-1560D. Similarly, in at least one embodiment, biasing mechanisms attempt to keep data needed by the cores (and thus preferably not needed by graphics processing engines 1531(1)-1531(N)) in the cores' caches 1562A-1562D, 1556, and system memory 1514.

[0262] 15C shows another exemplary embodiment in which accelerator integration circuitry 1536 is integrated within processor 1507. In at least this embodiment, graphics processing engines 1531(1)-1531(N) communicate directly with accelerator integration circuitry 1536 via high-speed link 1540 (which again may be any form of bus or interface protocol) via interface 1537 and interface 1535. In at least one embodiment, accelerator integration circuitry 1536 may perform operations similar to those described with respect to FIG. 15B, but may potentially operate at a higher throughput given its proximity to coherence bus 1564 and caches 1562A-1562D, 1556. In at least one embodiment, the accelerator integrated circuitry supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by the accelerator integrated circuitry 1536 and a programming model controlled by the graphics acceleration module 1546.

[0263] In at least one embodiment, graphics processing engines 1531(1)-1531(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel other application requests to graphics processing engines 1531(1)-1531(N) to achieve virtualization within a VM / partition.

[0264] In at least one embodiment, graphics processing engines 1531(1)-1531(N) may be shared by multiple VM / application partitions. In at least one embodiment, the sharing model may use a system hypervisor to virtualize graphics processing engines 1531(1)-1531(N) to allow access by each operating system. In at least one embodiment, in a single-partition system without a hypervisor, graphics processing engines 1531(1)-1531(N) are owned by the operating system. In at least one embodiment, the operating system may virtualize graphics processing engines 1531(1)-1531(N) to provide access to each process or application.

[0265] In at least one embodiment, graphics acceleration module 1546 or individual graphics processing engines 1531(1)-1531(N) selects a process element using a process handle. In at least one embodiment, the process element is stored in system memory 1514 and is addressable using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle may be an implementation-specific value provided to a host process when registering the host process's context with graphics processing engines 1531(1)-1531(N) (i.e., calling system software to add the process element to the process element linked list). In at least one embodiment, the low-order 16 bits of the process handle may be the offset of the process element within the process element linked list.

[0266] FIG. 15D illustrates an exemplary accelerator integration slice 1590. In at least one embodiment, a "slice" comprises a designated portion of the processing resources of accelerator integration circuitry 1536. In at least one embodiment, application effective address space 1582 in system memory 1514 stores process element 1583. In at least one embodiment, process element 1583 is stored in response to a GPU call 1581 from an application 1580 executing on processor 1507. In at least one embodiment, process element 1583 contains the process state of the corresponding application 1580. In at least one embodiment, work descriptor (WD) 1584 contained in process element 1583 can be a single job requested by the application or may contain a pointer to a queue of jobs. In at least one embodiment, WD 1584 is a pointer to a job request queue in application effective address space 1582.

[0267] In at least one embodiment, graphics acceleration module 1546 and / or individual graphics processing engines 1531(1)-1531(N) may be shared by all or a subset of processes in the system. In at least one embodiment, infrastructure may be included for setting process state and sending WD 1584 to graphics acceleration module 1546 to start a job in a virtualized environment.

[0268] In at least one embodiment, the dedicated process programming model is implementation specific. In at least one embodiment, in this model, a single process owns the graphics acceleration module 1546 or an individual graphics processing engine 1531. In at least one embodiment, when the graphics acceleration module 1546 is owned by a single process, the hypervisor initializes the accelerator integration circuitry 1536 for the owning partition when the graphics acceleration module 1546 is allocated, and the operating system initializes the accelerator integration circuitry 1536 for the owning process.

[0269] In at least one embodiment, in operation, WD fetch unit 1591 in accelerator integrated slice 1590 fetches the next WD 1584, which contains an indication of work to be performed by one or more graphics processing engines of graphics acceleration module 1546. In at least one embodiment, as shown, data from WD 1584 may be stored in register 1545 and used by MMU 1539, interrupt management circuit 1547, and / or context management circuit 1548. For example, one embodiment of MMU 1539 includes segment / page walk circuitry for accessing segment / page table 1586 within OS virtual address space 1585. In at least one embodiment, interrupt management circuit 1547 may process interrupt events 1592 received from graphics acceleration module 1546. In at least one embodiment, when performing graphics operations, effective addresses 1593 generated by graphics processing engines 1531(1)-1531(N) are translated into real addresses by MMU 1539.

[0270] In at least one embodiment, registers 1545 may be replicated for each graphics processing engine 1531(1)-1531(N) and / or graphics acceleration module 1546 and initialized by a hypervisor or operating system. In at least one embodiment, each of these replicated registers may be included in accelerator integration slice 1590. Exemplary registers that may be initialized by a hypervisor are shown in Table 1. [Table 1]

[0271] Exemplary registers that may be initialized by the operating system are shown in Table 2. [Table 2]

[0272] In at least one embodiment, each WD 1584 is specific to a particular graphics acceleration module 1546 and / or graphics processing engine 1531(1)-1531(N). In at least one embodiment, WD 1584 may contain all the information that graphics processing engine 1531(1)-1531(N) needs to do its work, or may be a pointer to a memory location where an application has set up a command queue for work to be completed.

[0273] 15E shows further details of an exemplary embodiment of the sharing model. This embodiment includes a hypervisor real address space 1598 in which a process element list 1599 is stored. In at least one embodiment, the hypervisor real address space 1598 is accessible through a hypervisor 1596 that virtualizes the graphics acceleration module engine of the operating system 1595.

[0274] In at least one embodiment, a shared programming model allows all or a subset of processes from all or a subset of partitions in a system to use the graphics acceleration module 1546. In at least one embodiment, there are two programming models in which the graphics acceleration module 1546 is shared by multiple processes and partitions: timeslice shared and graphics-directed shared.

[0275] In at least one embodiment, in this model, system hypervisor 1596 owns graphics acceleration module 1546 and makes its functionality available to all operating systems 1595. In at least one embodiment, in order for graphics acceleration module 1546 to support virtualization by system hypervisor 1596, graphics acceleration module 1546 may comply with several requirements, such as: 1) application job requests must be autonomous (i.e., no state needs to be maintained between jobs) or graphics acceleration module 1546 must provide a mechanism for saving and restoring context, 2) application job requests must be guaranteed by graphics acceleration module 1546 to complete in a specified amount of time, including any translation errors, or graphics acceleration module 1546 must provide the ability to preempt job processing, and 3) graphics acceleration module 1546 must ensure fairness between processes when operating in a specified shared programming model.

[0276] In at least one embodiment, application 1580 must make a system call to operating system 1595 with a graphics acceleration module type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore area pointer (CSRP). In at least one embodiment, the graphics acceleration module type describes the acceleration function targeted by the system call. In at least one embodiment, the graphics acceleration module type may be a system-specific value. In at least one embodiment, the WD is formatted specifically for graphics acceleration module 1546 and may be in the form of graphics acceleration module 1546 commands, an effective address pointer to a user-defined structure, an effective address pointer to a queue of commands, or any other data structure for describing the work to be performed by graphics acceleration module 1546.

[0277] In at least one embodiment, the AMR value is the AMR state to use for the current process. In at least one embodiment, the value passed to the operating system is the same as the application setting the AMR. In at least one embodiment, if the implementation of the accelerator integrated circuit 1536 (not shown) and the graphics acceleration module 1546 does not support a User Authorization Mask Override Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR to the hypervisor call. In at least one embodiment, the hypervisor 1596 may optionally apply the current Authorization Mask Override Register (AMOR) value before placing the AMR in the process element 1583. In at least one embodiment, the CSRP is one of the registers 1545 that contains the effective address of an area in the application's effective address space 1582 for the graphics acceleration module 1546 to save and restore context state. In at least one embodiment, this pointer is optional if no state needs to be saved between jobs or when a job is preempted. In at least one embodiment, the context save / restore area may be pinned system memory.

[0278] Upon receiving the system call, operating system 1595 may verify that application 1580 is registered and authorized to use graphics acceleration module 1546. In at least one embodiment, operating system 1595 then calls hypervisor 1596 with the information shown in Table 3. [Table 3]

[0279] In at least one embodiment, upon receiving the hypervisor call, the hypervisor 1596 verifies that the operating system 1595 is registered and authorized to use the graphics acceleration module 1546. In at least one embodiment, the hypervisor 1596 then places the process element 1583 into a process element linked list of the corresponding graphics acceleration module 1546 type. In at least one embodiment, the process element may include the information shown in Table 4. [Table 4]

[0280] In at least one embodiment, the hypervisor initializes registers 1545 of multiple accelerator integrated slices 1590.

[0281] As shown in FIG. 15F, at least one embodiment uses unified memory that is addressable via a common virtual memory address space used to access physical processor memory 1501(1)-1501(N) and GPU memory 1520(1)-1520(N). In this implementation, operations performed on GPUs 1510(1)-1510(N) utilize the same virtual / effective memory address space as those used to access processor memory 1501(1)-1501(N), and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1501(1), a second portion is allocated to second processor memory 1501(N), a third portion is allocated to GPU memory 1520(1), and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thereby distributed across each of the processor memory 1501 and GPU memory 1520, allowing either processor or GPU to access either physical memory, with virtual addresses mapped to physical memory.

[0282] In at least one embodiment, bias / coherence management circuits 1594A-1594E in one or more of MMUs 1539A-1539E ensure cache coherence between caches of one or more host processors (e.g., 1505) and caches of GPU 1510 and implement biasing techniques to indicate the physical memory in which certain types of data should be stored. In at least one embodiment, multiple instances of bias / coherence management circuits 1594A-1594E are shown in FIG. 15F, although bias / coherence circuits may be implemented within the MMUs of one or more host processors 1505 and / or within accelerator integration circuit 1536.

[0283] One embodiment enables GPU memory 1520 to be mapped as part of system memory and accessible using shared virtual memory (SVM) techniques, but without the performance penalty associated with full system cache coherence. In at least one embodiment, having GPU memory 1520 accessible as system memory without cumbersome cache coherence overhead provides a beneficial operating environment for GPU offload. In at least one embodiment, this configuration enables host processor 1505 software to set up operands and access computation results without the overhead of traditional I / O DMA data copies. In at least one embodiment, such traditional copies require driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, being able to access GPU memory 1520 without cache coherence overhead can be critical to the execution time of offloaded computations. In at least one embodiment, for example, in the presence of significant streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by the GPU 1510. In at least one embodiment, the efficiency of operand setup, the efficiency of result access, and the efficiency of GPU computation can be useful in determining the effectiveness of GPU offloading.

[0284] In at least one embodiment, the selection of the GPU bias and the host processor bias is determined by a bias tracker data structure. In at least one embodiment, for example, a bias table may be used, which may be a page-granular structure containing one or two bits per GPU-attached memory page (e.g., controlled at memory page granularity). In at least one embodiment, the bias table may be implemented in a stolen memory range of one or more GPU memories 1520, with or without a bias cache in GPU 1510 (e.g., for caching frequently / recently used entries of the bias table). Alternatively, in at least one embodiment, the bias table may be maintained entirely within the GPU.

[0285] In at least one embodiment, a bias table entry associated with each access to GPU-biased memory 1520 is accessed prior to the actual access to the GPU memory, resulting in the following actions: In at least one embodiment, a local request from the GPU 1510 to find its page in the GPU bias is forwarded directly to the corresponding GPU memory 1520. In at least one embodiment, a local request from the GPU to find its page in the host bias is forwarded to the processor 1505 (e.g., via the high-speed link described above). In at least one embodiment, a request from the processor 1505 to find the requested page in the host processor bias completes the request similar to a normal memory read. Alternatively, a request directed to a GPU-biased page may be forwarded to the GPU 1510. In at least one embodiment, the GPU may then migrate the page to the host processor bias if it is not currently using the page. In at least one embodiment, the bias state of a page can be changed by either a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited set of cases, simply a hardware-based mechanism.

[0286] In at least one embodiment, one mechanism for changing the bias state utilizes an API call (e.g., OpenCL) that calls the GPU's device driver, which sends a message (or queues a command descriptor) to the GPU to change the bias state and, for some transitions, directs the GPU to perform a cache flushing operation in the host. In at least one embodiment, a cache flushing operation is used for transitions from host processor 1505 bias to GPU bias, but not for transitions in the opposite direction.

[0287] In at least one embodiment, cache coherence is maintained by temporarily rendering GPU-biased pages uncacheable by the host processor 1505. In at least one embodiment, to access these pages, the processor 1505 may request access from the GPU 1510, which may or may not immediately grant the access. Thus, in at least one embodiment, to reduce communication between the processor 1505 and the GPU 1510, it is beneficial for GPU-biased pages to be requested by the GPU but not by the host processor 1505, or vice versa.

[0288] To implement one or more embodiments, a hardware structure 715 is used, details regarding the hardware structure 715 may be provided herein in conjunction with Figures 7A and / or 7B.

[0289] 16 illustrates an exemplary integrated circuit and associated graphics processor that can be fabricated using one or more IP cores according to various embodiments described herein. In addition to what is shown, in at least one embodiment, other logic and circuitry may be included, including additional graphics processors / cores, peripheral device interface controllers, or general-purpose processor cores.

[0290] 16 is a block diagram illustrating an exemplary system-on-chip integrated circuit 1600 that can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, integrated circuit 1600 includes one or more application processors 1605 (e.g., a CPU), at least one graphics processor 1610, and may further include an image processor 1615 and / or a video processor 1620, any of which may be modular IP cores. In at least one embodiment, integrated circuit 1600 includes a USB controller 1625, a UART controller 1630, an SPI / SDIO controller 1635, and an I / O controller 1640. 2 2S / I 2 The integrated circuit 1600 includes peripheral or bus logic including a HDMI™ controller 1640. In at least one embodiment, the integrated circuit 1600 may include a display device 1645 coupled to one or more of a high-definition multimedia interface (HDMI™) controller 1650 and a mobile industry processor interface (MIPI) display interface 1655. In at least one embodiment, storage may be provided by a flash memory subsystem 1660 including a flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1665 for accessing an SDRAM or SRAM memory device. In at least one embodiment, some integrated circuits further include an embedded security engine 1670.

[0291] Inference and / or training logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, inference and / or training logic 715 may be used in integrated circuit 1600 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0292] In at least one embodiment, at least one component shown or described with respect to FIG. 16 is used to implement the techniques and / or functionality described with respect to FIGS. 1-6. In at least one embodiment, the inference and / or training logic 715 includes and / or operates at least one aspect described with respect to FIG. 1 (e.g., deep learning compiler 102, scheduler 114, code generator 116). In at least one embodiment, the inference and / or training logic 715 trains at least one untrained or partially trained neural network using a computer program representation (e.g., code 106 or runtime code 120) that combines two or more dependency reduction operations into a software kernel, as described with respect to one or more of FIGS. 1-6. In at least one embodiment, the inference and / or training logic performs at least one inference operation using a computer program representation (e.g., code 106 or runtime code 120) that combines two or more dependency reduction operations into a software kernel, as described with respect to one or more of FIGS. 1-6. In at least one embodiment, the integrated circuit 1600 of FIG. 16 is utilized to implement the techniques and / or functionality described in connection with FIGS.

[0293] 17A-17B illustrate an exemplary integrated circuit and associated graphics processor that can be fabricated using one or more IP cores according to various embodiments described herein. In addition to what is shown, in at least one embodiment, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0294] 17A-17B are block diagrams illustrating exemplary graphics processors for use within an SoC, according to embodiments described herein. FIG. 17A illustrates an exemplary graphics processor 1710 of a system-on-chip integrated circuit that can be fabricated using one or more IP cores, according to at least one embodiment. FIG. 17B illustrates a further exemplary graphics processor 1740 of a system-on-chip integrated circuit that can be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, graphics processor 1710 of FIG. 17A is a low-power graphics processor core. In at least one embodiment, graphics processor 1740 of FIG. 17B is a high-performance graphics processor core. In at least one embodiment, each of graphics processors 1710, 1740 can be a variation of graphics processor 1610 of FIG. 16.

[0295] In at least one embodiment, graphics processor 1710 includes vertex processor 1705 and one or more fragment processors 1715A-1715N (e.g., 1715A, 1715B, 1715C, 1715D-1715N-1, and 1715N). In at least one embodiment, graphics processor 1710 can execute different shader programs through separate logic, such that vertex processor 1705 is optimized to perform operations for vertex shader programs, while one or more fragment processors 1715A-1715N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, vertex processor 1705 executes the vertex processing stage of a 3D graphics pipeline, generating primitive and vertex data. In at least one embodiment, fragment processors 1715A-1715N use the primitive and vertex data generated by vertex processor 1705 to generate a frame buffer that is displayed on a display device. In at least one embodiment, fragment processors 1715A-1715N are optimized to execute fragment shader programs provided in the OpenGL API, which may be used to perform operations similar to pixel shader programs provided in the Direct 3D API.

[0296] In at least one embodiment, graphics processor 1710 further includes one or more memory management units (MMUs) 1720A-1720B, caches 1725A-1725B, and circuit interconnects 1730A-1730B. In at least one embodiment, one or more MMUs 1720A-1720B provide virtual-to-physical address mapping for graphics processor 1710, including vertex processor 1705 and / or fragment processors 1715A-1715N, which may reference vertex or image / text data stored in memory in addition to vertex or image / text data stored in one or more caches 1725A-1725B. In at least one embodiment, one or more MMUs 1720A-1720B may be synchronized with other MMUs in the system, including one or more MMUs associated with one or more application processors 1605, image processor 1615, and / or video processor 1620 of Figure 16, allowing each processor 1605-1620 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1730A-1730B enable graphics processor 1710 to interface with other IP cores in the SoC via the SoC's internal bus or via a direct connection.

[0297] 17B, ​​graphics processor 1740 includes one or more shader cores 1755A-1755N (e.g., 1755A, 1755B, 1755C, 1755D, 1755E, 1755F-1755N-1, and 1755N), which provide a unified shader core architecture in which a single core, or type, or cores can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, graphics processor 1740 includes an inter-core task manager 1745 that acts as a thread dispatcher for dispatching execution threads to one or more shader cores 1755A-1755N, and a tiling unit 1758 for accelerating tiling operations for tile-based rendering, in which rendering operations of a scene are subdivided in image space, e.g., to exploit local spatial coherence within a scene or to optimize internal cache usage.

[0298] Inference and / or training logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, inference and / or training logic 715 may be used in integrated circuits 17A and / or 17B for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0299] In at least one embodiment, at least one component shown or described with respect to Figures 17A and / or 17B is used to implement the techniques and / or functionality described with respect to Figures 1-6. In at least one embodiment, the inference and / or training logic 715 includes and / or operates at least one aspect (e.g., deep learning compiler 102, scheduler 114, code generator 116) described with respect to Figure 1. In at least one embodiment, the inference and / or training logic 715 trains at least one untrained or partially trained neural network using a computer program representation (e.g., code 106 or runtime code 120) that combines two or more dependency reduction operations into a software kernel, as described with respect to one or more of Figures 1-6. In at least one embodiment, the inference and / or training logic performs at least one inference operation using a computer program representation (e.g., code 106 or runtime code 120) that combines two or more dependency reduction operations into a software kernel, as described with respect to one or more of Figures 1-6. In at least one embodiment, graphics processor 1710 of Figure 17A and / or graphics processor 1740 of Figure 17B are utilized to implement the techniques and / or functionality described with respect to Figures 1-6.

[0300] 18A-18B illustrate further exemplary graphics processor logic according to embodiments described herein. Figure 18A illustrates a graphics core 1800, which, in at least one embodiment, may be included in graphics processor 1610 of Figure 16, or, in at least one embodiment, may be integrated shader cores 1755A-1755N, as in Figure 17B. Figure 18B illustrates a highly parallel general-purpose graphics processing unit ("GPGPU") 1830 suitable for incorporation into a multi-chip module in at least one embodiment.

[0301] In at least one embodiment, graphics core 1800 includes a shared instruction cache 1802, a texture unit 1818, and a cache / shared memory 1820, which are common to execution resources within graphics core 1800. In at least one embodiment, graphics core 1800 may include multiple slices 1801A-1801N, or partitions per core, and a graphics processor may include multiple instances of graphics core 1800. In at least one embodiment, slices 1801A-1801N may include supporting logic, including local instruction caches 1804A-1804N, thread schedulers 1806A-1806N, thread dispatchers 1808A-1808N, and sets of registers 1810A-1810N. In at least one embodiment, slices 1801A-1801N may include a set of additional functional units (AFUs 1812A-1812N), floating point units (FPUs 1814A-1814N), integer arithmetic logic units (ALUs 1816-1816N), address calculation units (ACUs 1813A-1813N), double precision floating point units (DPFPUs 1815A-1815N), and matrix processing units (MPUs 1817A-1817N).

[0302] In at least one embodiment, the FPUs 1814A-1814N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, and the DPFPUs 1815A-1815N can perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 1816A-1816N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision and can be configured for mixed-precision operations. In at least one embodiment, the MPUs 1817A-1817N can also be configured for mixed-precision matrix operations, including half-precision floating-point and 8-bit integer operations. In at least one embodiment, the MPUs 1817A-1817N can perform various matrix operations to accelerate machine learning application frameworks, including being able to support general matrix-matrix multiplication (GEMM) acceleration. In at least one embodiment, AFUs 1812A-1812N can perform additional logical operations not supported by the floating-point unit or integer unit, including trigonometric operations (e.g., sine, cosine, etc.).

[0303] Inference and / or training logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 715 are provided herein in conjunction with FIG. 7A and / or 7B. In at least one embodiment, inference and / or training logic 715 may be used in graphics core 1800 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0304] In at least one embodiment, at least one component shown or described with respect to Figure 18A is used to implement the techniques and / or functionality described with respect to Figures 1-6. In at least one embodiment, the inference and / or training logic 715 includes and / or operates at least one aspect (e.g., deep learning compiler 102, scheduler 114, code generator 116) described with respect to Figure 1. In at least one embodiment, the inference and / or training logic 715 trains at least one untrained or partially trained neural network using a computer program representation (e.g., code 106 or runtime code 120 of Figure 1) that combines two or more dependency reduction operations into a software kernel, as described with respect to one or more of Figures 1-6. In at least one embodiment, the inference and / or training logic performs at least one inference operation using a computer program expression (e.g., code 106 or runtime code 120 of FIG. 1) that combines two or more dependency reduction operations into a software kernel, as described with respect to one or more of FIGs. 1-6. In at least one embodiment, graphics core 1800 of FIG. 18A is utilized to implement the techniques and / or functionality described with respect to FIGs. 1-6.

[0305] FIG. 18B illustrates a general-purpose processing unit (GPGPU) 1830, which, in at least one embodiment, can be configured to enable highly parallel computational operations by an array of graphics processing units. In at least one embodiment, the GPGPU 1830 can be directly linked to other instances of the GPGPU 1830 to create multiple GPU clusters to improve the training speed of deep neural networks. In at least one embodiment, the GPGPU 1830 includes a host interface 1832 for enabling connection to a host processor. In at least one embodiment, the host interface 1832 is a PCI Express interface. In at least one embodiment, the host interface 1832 can be a vendor-specific communications interface or fabric. In at least one embodiment, the GPGPU 1830 receives commands from the host processor and, using a global scheduler 1834, distributes execution threads associated with these commands to a set of compute clusters 1836A-1836H. In at least one embodiment, the compute clusters 1836A-1836H share a cache memory 1838. In at least one embodiment, the cache memory 1838 can act as a higher level cache for the cache memories within the compute clusters 1836A-1836H.

[0306] In at least one embodiment, GPGPU 1830 includes memory 1844A-1844B coupled to compute clusters 1836A-1836H via a set of memory controllers 1842A-1842B. In at least one embodiment, memory 1844A-1844B can include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0307] In at least one embodiment, compute clusters 1836A-1836H each include a set of graphics cores, such as graphics core 1800 of FIG. 18A, which may include multiple types of integer and floating-point logic units capable of performing computational operations with various precisions, including those suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each of compute clusters 1836A-1836H may be configured to perform 16-bit or 32-bit floating-point operations, while another subset of the floating-point units may be configured to perform 64-bit floating-point operations.

[0308] In at least one embodiment, multiple instances of GPGPU 1830 can be configured to operate as a compute cluster. In at least one embodiment, the communications used by compute clusters 1836A-1836H for synchronization and data exchange vary across embodiments. In at least one embodiment, multiple instances of GPGPU 1830 communicate through host interface 1832. In at least one embodiment, GPGPU 1830 includes an I / O hub 1839 that couples GPGPU 1830 to GPU links 1840 that enable direct connections to other instances of GPGPU 1830. In at least one embodiment, GPU links 1840 are coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1830. In at least one embodiment, GPU links 1840 are coupled to a high-speed interconnect for sending and receiving data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 1830 are located in separate data processing systems and communicate via a network device accessible via host interface 1832. In at least one embodiment, GPU link 1840 can be configured to allow connection to a host processor in addition to, or instead of, host interface 1832.

[0309] In at least one embodiment, the GPGPU 1830 can be configured to train a neural network. In at least one embodiment, the GPGPU 1830 can be used within an inference platform. In at least one embodiment, when the GPGPU 1830 is used for inference, the GPGPU 1830 may include fewer compute clusters 1836A-1836H than when the GPGPU 1830 is used to train a neural network. In at least one embodiment, the memory technology associated with the memories 1844A-1844B may be different between the inference configuration and the training configuration, with higher bandwidth memory technology being devoted to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 1830 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can support one or more 8-bit integer dot product instructions, which may be used during inference operations of a deployed neural network.

[0310] Inference and / or training logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, the inference and / or training logic 715 may be used in the GPGPU 1830 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0311] In at least one embodiment, at least one component shown or described with respect to Figure 18B is used to implement the techniques and / or functionality described with respect to Figures 1-6. In at least one embodiment, the inference and / or training logic 715 includes and / or operates at least one aspect (e.g., deep learning compiler 102, scheduler 114, code generator 116) described with respect to Figure 1. In at least one embodiment, the inference and / or training logic 715 trains at least one untrained or partially trained neural network using a computer program representation (e.g., code 106 or runtime code 120 of Figure 1) that combines two or more dependency reduction operations into a software kernel, as described with respect to one or more of Figures 1-6. In at least one embodiment, the inference and / or training logic performs at least one inference operation using a computer program expression (e.g., code 106 or runtime code 120 of FIG. 1) that combines two or more dependency reduction operations into a software kernel, as described with respect to one or more of FIGs. 1-6. In at least one embodiment, GPGPU 1830 of FIG. 12B is utilized to implement the techniques and / or functionality described with respect to FIGs. 1-6.

[0312] 19 is a block diagram illustrating a computing system 1900 according to at least one embodiment. In at least one embodiment, the computing system 1900 includes a processing subsystem 1901 having one or more processors 1902 and system memory 1904 that communicate via an interconnection path that may include a memory hub 1905. In at least one embodiment, the memory hub 1905 may be a separate component within a chipset component or may be integrated within the one or more processors 1902. In at least one embodiment, the memory hub 1905 is coupled to an I / O subsystem 1911 via a communication link 1906. In at least one embodiment, the I / O subsystem 1911 includes an I / O hub 1907 that can enable the computing system 1900 to receive input from one or more input devices 1908. In at least one embodiment, I / O hub 1907 can enable a display controller, which may be included in one or more processors 1902 and provide output to one or more display devices 1910A. In at least one embodiment, the one or more display devices 1910A coupled to I / O hub 1907 can include local, internal, or embedded display devices.

[0313] In at least one embodiment, processing subsystem 1901 includes one or more parallel processors 1912 coupled to memory hub 1905 via a bus or other communication link 1913. In at least one embodiment, communication link 1913 may use one of any number of standard-based communication link technologies or protocols, such as, but not limited to, PCI Express, or may be a vendor-specific communication interface or fabric. In at least one embodiment, one or more parallel processors 1912 form a computationally intensive parallel or vector processing system that may include multiple processing cores and / or processing clusters, such as a many integrated core (MIC) processor. In at least one embodiment, some or all of parallel processors 1912 form a graphics processing subsystem that can output pixels to one of one or more display devices 1910A coupled via I / O hub 1907. In at least one embodiment, parallel processor 1912 also includes a display controller and display interface (not shown) that enables direct connection to one or more display devices 1910B.

[0314] In at least one embodiment, a system storage unit 1914 may be connected to an I / O hub 1907 to provide a storage mechanism for the computing system 1900. In at least one embodiment, an I / O switch 1916 may be used to provide an interface mechanism to enable communication between the I / O hub 1907 and other components, such as a network adapter 1918 and / or a wireless network adapter 1919, which may be integrated into the platform, as well as various other devices that may be added via one or more add-in devices 1920. In at least one embodiment, the network adapter 1918 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 1919 may include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more wireless radios.

[0315] In at least one embodiment, computing system 1900 may include other components not shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to I / O hub 1907. In at least one embodiment, the communication paths interconnecting the various components of FIG. 19 may be implemented using any suitable protocol, such as a Peripheral Component Interconnect (PCI)-based protocol (e.g., PCI-Express), or other bus or point-to-point communication interface and / or protocol, such as an NV-Link high-speed interconnect, or other interconnection protocol.

[0316] In at least one embodiment, parallel processor 1912 incorporates circuitry optimized for graphics and video processing, including, for example, video output circuitry, forming a graphics processing unit (GPU). In at least one embodiment, parallel processor 1912 incorporates circuitry optimized for general-purpose processing. In at least one embodiment, components of computing system 1900 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, parallel processor 1912, memory hub 1905, processor 1902, and I / O hub 1907 may be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, components of computing system 1900 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computing system 1900 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules to form a modular computing system.

[0317] Inference and / or training logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, the inference and / or training logic 715 may be used in the system of Figure 1900 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0318] In at least one embodiment, at least one component shown or described with respect to Figure 19 is used to implement the techniques and / or functionality described with respect to Figures 1-6. In at least one embodiment, the inference and / or training logic 715 includes and / or operates at least one aspect described with respect to Figure 1 (e.g., deep learning compiler 102, scheduler 114, code generator 116). In at least one embodiment, the inference and / or training logic 715 trains at least one untrained or partially trained neural network using a computer program representation (e.g., code 106 or runtime code 120 of Figure 1) that combines two or more dependency reduction operations into a software kernel, as described with respect to one or more of Figures 1-6. In at least one embodiment, the inference and / or training logic performs at least one inference operation using a computer program representation (e.g., code 106 or runtime code 120) that combines two or more dependency reduction operations into a software kernel, as described with respect to one or more of Figures 1-6. In at least one embodiment, system 1900 of Figure 19 is utilized to implement the techniques and / or functionality described with respect to Figures 1-6.

[0319] Processor 20A illustrates a parallel processor 2000 according to at least one embodiment. In at least one embodiment, various components of the parallel processor 2000 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). In at least one embodiment, the illustrated parallel processor 2000 is a variation of one or more parallel processors 1912 shown in FIG. 19 according to an example embodiment.

[0320] In at least one embodiment, parallel processor 2000 includes parallel processing units 2002. In at least one embodiment, parallel processing units 2002 include I / O units 2004 that enable communication with other devices, including other instances of parallel processing units 2002. In at least one embodiment, I / O units 2004 may be directly connected to other devices. In at least one embodiment, I / O units 2004 are connected to other devices through the use of a hub or switch interface, such as memory hub 2005. In at least one embodiment, the connection between memory hub 2005 and I / O units 2004 forms communication link 2013. In at least one embodiment, I / O units 2004 are connected to host interface 2006 and memory crossbar 2016, where host interface 2006 receives commands directed to the execution of processing operations and memory crossbar 2016 receives commands directed to the execution of memory operations.

[0321] In at least one embodiment, when the host interface 2006 receives command buffers via the I / O unit 2004, the host interface 2006 can direct work operations to the front end 2008 to execute these commands. In at least one embodiment, the front end 2008 is coupled to a scheduler 2010, which is configured to distribute commands or other work items to the processing cluster array 2012. In at least one embodiment, the scheduler 2010 ensures that the processing cluster array 2012 is properly configured and in a valid state before tasks are distributed to clusters in the processing cluster array 2012. In at least one embodiment, the scheduler 2010 is implemented via firmware logic running on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 2010 is configurable to perform complex scheduling and work distribution operations at both coarse and fine granularities, enabling rapid preemption and context switching of threads executing in the processing array 2012. In at least one embodiment, host software can initiate scheduling workloads across processing cluster array 2012 via one of multiple graphics processing paths. In at least one embodiment, the workload can then be automatically distributed across processing cluster array 2012 by scheduler 2010 logic within the microcontroller that includes scheduler 2010.

[0322] In at least one embodiment, processing cluster array 2012 can include up to “N” processing clusters (e.g., cluster 2014A, cluster 2014B through cluster 2014N), where “N” represents a positive integer (although “N” may be a different integer than used in other figures). In at least one embodiment, each cluster 2014A through 2014N of processing cluster array 2012 can execute a large number of concurrent threads. In at least one embodiment, scheduler 2010 can allocate work to clusters 2014A through 2014N of processing cluster array 2012 using various scheduling and / or work distribution algorithms, which may vary depending on the workload generated by each program or type of computation. In at least one embodiment, scheduling may be handled dynamically by scheduler 2010 or may be partially assisted by compiler logic during compilation of program logic configured to be executed by processing cluster array 2012. In at least one embodiment, different clusters 2014A-2014N of processing cluster array 2012 may be allocated to process different types of programs or perform different types of calculations.

[0323] In at least one embodiment, the processing cluster array 2012 may be configured to perform various types of parallel processing operations. In at least one embodiment, the processing cluster array 2012 may be configured to perform general-purpose parallel compute operations. For example, in at least one embodiment, the processing cluster array 2012 may include logic for performing processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0324] In at least one embodiment, the processing cluster array 2012 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 2012 may include additional logic to support the execution of such graphics processing operations, including, but not limited to, texture sampling logic for performing texture operations, as well as mosaic logic and other vertex processing logic. In at least one embodiment, the processing cluster array 2012 may be configured to execute graphics processing related shader programs, such as, but not limited to, vertex shaders, mosaic shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2002 may transfer data from system memory via the I / O unit 2004 for processing. In at least one embodiment, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2022) during processing and then written back to system memory.

[0325] In at least one embodiment, when graphics processing is performed using parallel processing unit 2002, scheduler 2010 may be configured to divide the processing workload into roughly equal-sized tasks to better distribute graphics processing operations among multiple clusters 2014A-2014N of processing cluster array 2012. In at least one embodiment, portions of processing cluster array 2012 may be configured to perform different types of processing. For example, in at least one embodiment, to generate and display a rendered image, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform mosaic and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations. In at least one embodiment, intermediate data generated by one or more of clusters 2014A-2014N may be stored in a buffer so that the intermediate data can be transmitted between clusters 2014A-2014N for further processing.

[0326] In at least one embodiment, the processing cluster array 2012 can receive processing tasks to be performed via a scheduler 2010, which receives commands defining the processing tasks from the front end 2008. In at least one embodiment, a processing task can include an index of the data to be processed, e.g., surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data should be processed (e.g., which program to execute). In at least one embodiment, the scheduler 2010 can be configured to fetch the index corresponding to the task or can receive the index from the front end 2008. In at least one embodiment, the front end 2008 can be configured to ensure that the processing cluster array 2012 is configured to a valid state before a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.) is initiated.

[0327] In at least one embodiment, each of one or more instances of parallel processing unit 2002 may be coupled to parallel processor memory 2022. In at least one embodiment, parallel processor memory 2022 may be accessed via memory crossbar 2016, which may receive memory requests from processing cluster array 2012 as well as I / O unit 2004. In at least one embodiment, memory crossbar 2016 may access parallel processor memory 2022 via memory interface 2018. In at least one embodiment, memory interface 2018 may include multiple partition units (e.g., partition unit 2020A, partition unit 2020B through partition unit 2020N), each of which may be coupled to a portion (e.g., a memory unit) of parallel processor memory 2022. In at least one embodiment, the number of partition units 2020A-2020N is configured to be equal to the number of memory units, such that a first partition unit 2020A has a corresponding first memory unit 2024A, a second partition unit 2020B has a corresponding memory unit 2024B, and an Nth partition unit 2020N has a corresponding Nth memory unit 2024N. In at least one embodiment, the number of partition units 2020A-2020N does not have to be equal to the number of memory devices.

[0328] In at least one embodiment, the memory units 2024A-2024N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, the memory units 2024A-2024N may also include 3D stacked memory, including, but not limited to, high bandwidth memory (HBM). In at least one embodiment, to efficiently use the available bandwidth of the parallel processor memory 2022, render targets, such as frame buffers or texture maps, may be stored across the memory units 2024A-2024N, allowing the partition units 2020A-2020N to write portions of each render target in parallel. In at least one embodiment, local instances of the parallel processor memory 2022 may be omitted in favor of a unified memory design that uses a combination of system memory and local cache memory.

[0329] In at least one embodiment, any one of the clusters 2014A-2014N of the processing cluster array 2012 can process data that is to be written to any one of the memory units 2024A-2024N in the parallel processor memory 2022. In at least one embodiment, the memory crossbar 2016 can be configured to forward the output of each cluster 2014A-2014N to any partition unit 2020A-2020N or to another cluster 2014A-2014N that can perform further processing operations on the output. In at least one embodiment, each cluster 2014A-2014N can communicate with a memory interface 2018 through the memory crossbar 2016 to read from or write to various external memory devices. In at least one embodiment, the memory crossbar 2016 has connections to a memory interface 2018 for communicating with the I / O units 2004, as well as connections to local instances of parallel processor memory 2022, allowing processing units in different processing clusters 2014A-2014N to communicate with system memory or other memory not local to the parallel processing units 2002. In at least one embodiment, the memory crossbar 2016 can use virtual channels to separate traffic streams between the clusters 2014A-2014N and the partition units 2020A-2020N.

[0330] In at least one embodiment, multiple instances of parallel processing unit 2002 may be provided on a single add-in card, or multiple add-in cards may be interconnected. In at least one embodiment, different instances of parallel processing unit 2002 may be configured to interoperate even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other different configurations. For example, in at least one embodiment, some instances of parallel processing unit 2002 may include a higher precision floating-point unit than other instances. In at least one embodiment, systems incorporating one or more instances of parallel processing unit 2002 or parallel processor 2000 may be implemented in a variety of configurations and form factors, including, but not limited to, desktop, laptop, or portable personal computers, servers, workstations, game consoles, and / or embedded systems.

[0331] FIG. 20B is a block diagram of a partition unit 2020 according to at least one embodiment. In at least one embodiment, the partition unit 2020 is an instance of one of the partition units 2020A-2020N of FIG. 20A. In at least one embodiment, the partition unit 2020 includes an L2 cache 2021, a frame buffer interface 2025, and a raster operations unit (ROP) 2026. In at least one embodiment, the L2 cache 2021 is a read / write cache configured to execute load and store operations received from the memory crossbar 2016 and the ROP 2026. In at least one embodiment, read misses and urgent writeback requests are output by the L2 cache 2021 to the frame buffer interface 2025 for processing. In at least one embodiment, updates are also sent to the frame via the frame buffer interface 2025 for processing. In at least one embodiment, frame buffer interface 2025 interfaces with one of the memory units of a parallel processor memory, such as memory units 2024A-2024N (eg, in parallel processor memory 2022) of FIG.

[0332] In at least one embodiment, ROP2026 is a processing unit that performs raster operations such as stencil, z-test, and blending. In at least one embodiment, ROP2026 then outputs the processed graphics data stored in graphics memory. In at least one embodiment, ROP2026 includes compression logic for compressing depth or color data being written to memory and decompressing depth or color data being read from memory. In at least one embodiment, the compression logic can be lossless compression logic that utilizes one or more of a number of compression algorithms. In at least one embodiment, the type of compression performed by ROP2026 can be varied based on statistical characteristics of the data being compressed. For example, in at least one embodiment, delta color compression is performed on the depth and color data on a tile-by-tile basis.

[0333] In at least one embodiment, ROP 2026 is included within each processing cluster (e.g., clusters 2014A-2014N of FIG. 20A ) rather than within partition unit 2020. In at least one embodiment, read and write requests for pixel data, rather than pixel fragment data, are transmitted through memory crossbar 2016. In at least one embodiment, processed graphics data may be displayed on a display device, such as one of one or more display devices 1910 of FIG. 19 , may be routed for further processing by processor 1902, or may be routed for further processing by one of the processing entities in parallel processor 2000 of FIG. 20A .

[0334] FIG. 20C is a block diagram of a processing cluster 2014 within a parallel processing unit according to at least one embodiment. In at least one embodiment, the processing cluster is an instance of one of the processing clusters 2014A-2014N of FIG. 20A. In at least one embodiment, the processing cluster 2014 may be configured to execute multiple threads in parallel, where a "thread" refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, single-instruction, multiple-data (SIMD) instruction issue techniques are used to support parallel execution of multiple threads without providing multiple independent instruction units. In at least one embodiment, single-instruction, multiple-thread (SIMT) techniques are used to support parallel execution of multiple, generally synchronized threads using a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster.

[0335] In at least one embodiment, operation of the processing cluster 2014 may be controlled via a pipeline manager 2032, which distributes processing tasks to the SIMT parallel processors. In at least one embodiment, the pipeline manager 2032 receives instructions from the scheduler 2010 of FIG. 20A and manages the execution of those instructions via the graphics multiprocessor 2034 and / or the texture unit 2036. In at least one embodiment, the graphics multiprocessor 2034 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures may be included within the processing cluster 2014. In at least one embodiment, one or more instances of the graphics multiprocessor 2034 may be included within the processing cluster 2014. In at least one embodiment, the graphics multiprocessor 2034 may process data, and a data crossbar 2040 may be used to distribute the processed data to one of several possible destinations, including other shader units. In at least one embodiment, the pipeline manager 2032 can facilitate distribution of the processed data by specifying destinations for the processed data to be distributed through the data crossbar 2040.

[0336] In at least one embodiment, each graphics multiprocessor 2034 in a processing cluster 2014 may include an identical set of function execution logic (e.g., arithmetic logic units, load store units, etc.). In at least on...

Claims

1. one or more circuits for combining two or more dependency reduction operations into a software kernel; the two or more dependent reduction operations are a first reduction operation and a second reduction operation that is dependent on the first reduction operation, and the one or more circuits generate coordinates for one or more elements of an input tensor to the second reduction operation and combine the two or more dependent reduction operations based at least in part on the generated coordinates.

2. The processor of claim 1 , wherein the two or more dependency reduction operations include two or more of a mean operation, a sum operation, a product operation, a min operation, or a max operation.

3. 2. The processor of claim 1, wherein the one or more circuits assign one or more threads to elements of a tensor used by the two or more dependency reduction operations and combine the two or more dependency reduction operations into the software kernel based at least in part on the one or more assigned threads.

4. 2. The processor of claim 1, wherein the one or more circuits replace one or more multiplication operations between a vector and a set of data with a predetermined set of alternative operations and combine the two or more dependency reduction operations with the set of predetermined alternative operations into the software kernel.

5. 2. The processor of claim 1, wherein the two or more dependent reduction operations are a first reduction operation and a second reduction operation that is dependent on the first reduction operation, and the software kernel is to be implemented on a parallel processing unit.

6. one or more circuits for implementing a software kernel comprising two or more dependency reduction operations; the two or more dependency reduction operations are combined into the software kernel by a compiler based at least in part on coordinates of tensors used by one or more reduction operations of the two or more dependency reduction operations.

7. 7. The processor of claim 6, wherein the two or more dependency reduction operations are combined into the software kernel along with one or more element-wise operations by a compiler.

8. 7. The processor of claim 6, wherein the two or more dependency reduction operations are combined into the software kernel along with one or more copy operations by a compiler.

9. The processor of claim 6 , wherein the two or more dependency reduction operations include two or more of a mean operation, a sum operation, a product operation, a min operation, or a max operation.

10. 7. The processor of claim 6, wherein the one or more circuits implement the software kernel after receiving a kernel launch command from a host computer system.

11. When implemented by a processor, it at least: Implementing a software kernel with two or more dependency reduction operations A machine-readable medium having stored thereon a set of instructions for causing the processor to: the two or more dependent reduction operations are a first reduction operation and a second reduction operation that is dependent on the first reduction operation, and the one or more circuits generate coordinates for one or more elements of an input tensor to the second reduction operation and combine the two or more dependent reduction operations based at least in part on the generated coordinates.

12. 12. The machine-readable medium of claim 11, wherein the two or more dependency reduction operations are combined into the software kernel by a compiler.

13. 12. The machine-readable medium of claim 11, wherein the two or more dependency reduction operations, along with one or more of an element-wise operation or a copy operation, are combined into the software kernel by a compiler.

14. 12. The machine-readable medium of claim 11, wherein the software kernel includes instructions to be performed in parallel, and wherein the two or more dependency reduction operations are combined into the software kernel by a compiler based at least in part on a plurality of threads assigned to one or more tensors used by one or more of the two or more dependency reduction operations, the plurality of threads to perform one or more operations in parallel.

15. The machine-readable medium of claim 11 , wherein the two or more dependency reduction operations include two or more of a mean operation, a sum operation, a product operation, a min operation, or a max operation.

16. 12. The machine-readable medium of claim 11, wherein the software kernel is to be implemented on a parallel processing unit or a graphics processing unit.

17. 1. A processor-implemented method comprising combining two or more dependency reduction operations into a software kernel, the method comprising: generating coordinates of one or more elements of one or more tensors used by one or more of the two or more dependency reduction operations; and combining the two or more dependency reduction operations based at least in part on the generated coordinates.

18. The method of claim 17 , wherein the two or more dependency reduction operations include two or more of a mean operation, a sum operation, a product operation, a min operation, or a max operation.

19. 20. The method of claim 17, further comprising: replacing a first operation with a predetermined set of alternative operations; and combining the two or more dependency reduction operations with the predetermined set of alternative operations into the software kernel.

20. 18. The method of claim 17, further comprising: allocating one or more threads to elements of one or more tensors used by one or more of the two or more dependency reduction operations; combining the two or more dependency reduction operations into the software kernel based at least in part on the assigned one or more threads; and the software kernel including instructions to be performed in parallel using the assigned one or more threads.

21. 20. The method of claim 17, further comprising selecting a reduction algorithm, wherein combining the two or more dependent reduction operations into the software kernel is based at least in part on the selected reduction algorithm.

22. one or more processors for combining two or more dependency reduction operations into a software kernel; one or more memories for storing said software kernel; Equipped with the one or more processors are to generate a schedule based at least in part on a representation of a computer program including the two or more dependency reduction operations, identify reused data based at least in part on the schedule, and combine the two or more dependency reduction operations into the software kernel based at least in part on the reused data.

23. 23. The system of claim 22, wherein the one or more processors are to combine the two or more dependency reduction operations with one or more of an element-wise operation and a copy operation into the software kernel.

24. 23. The system of claim 22, wherein the two or more dependency reduction operations include two or more of a mean operation, a sum operation, a product operation, a min operation, or a max operation, and the software kernel includes instructions that are to be performed in parallel on parallel processing units.

25. 23. The system of claim 22, wherein the software kernel implements a portion of an inference operation using a neural network.

26. 23. The system of claim 22, wherein the software kernel includes instructions to be executed in parallel, the one or more processors are first one or more processors, the system further comprising second one or more processors, the first one or more processors launching the software kernel for execution by the second one or more processors.

27. a computer vision system including one or more processors for identifying one or more objects based at least in part on performing one or more inference operations using two or more dependency reduction operations combined into a software kernel by a compiler; one or more of a propulsion system, a directional control system, and a vehicle operator notification system for performing one or more actions based at least in part on the identified one or more objects; Equipped with the two or more dependency reduction operations are combined into the software kernel by the compiler based at least in part on coordinates of tensors used by one or more of the two or more dependency reduction operations.

28. 28. The vehicle of claim 27, wherein the two or more dependency reduction operations include two or more of a mean operation, a sum operation, a product operation, a min operation, or a max operation.

29. 28. The vehicle of claim 27, wherein the two or more dependency reduction operations are combined by the compiler into the software kernel along with one or more element-wise operations and one or more copy operations.

30. 28. The vehicle of claim 27, wherein the two or more dependency reduction operations are combined in the software kernel based at least in part on one or more threads assigned to elements of tensors used by the two or more dependency reduction operations.

31. 28. The vehicle of claim 27, wherein the two or more dependency reduction operations are combined into the software kernel based at least in part on an input graph representing the operations using a neural network.

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