Display panel and display device

Abstract

A display panel and a display device. The display panel comprises a first substrate (1) and a second substrate (2) arranged opposite to each other, the first substrate (1) comprising M*N sub-pixels defined by gate lines (4) and data lines, the thin film transistors (3) of the kth display row being connected to a first data line (6), and the thin film transistors (3) of the k+1th display row being connected to a second data line (7), the second substrate (2) comprising M*N filter units (22), a black matrix (21) disposed between adjacent filter units (22), the black matrix (21) comprising masking rows (211) and masking columns (212), the masking row (211) located between the kth display row and the k+1th display row having a first width, and the masking row (211) located between the k+1th display row and the k+2th display row having a second width, the first width being unequal to the second width, thereby reducing the difference in pixel aperture ratio between the sub-pixels of two adjacent display rows. The display device includes a display panel.

Description

[Technical Field]

[0001] This application claims priority from a Chinese patent application filed with the China Patent Office on June 18, 2020, bearing application number 202010559623.8 and entitled "Display Panel and Display Device," the contents of which are incorporated herein by reference. The present disclosure relates to the field of display technology, but is not limited thereto, and in particular to display panels and display devices. [Background technology]

[0002] Liquid crystal display devices (abbreviated as LCD) have been rapidly developed due to their small size, low power consumption, and no radiation. A liquid crystal display panel comprises a cell-aligned thin film transistor (abbreviated as TFT) array substrate and a color filter (abbreviated as CF) substrate. Liquid crystal (abbreviated as LC) molecules are disposed between the array substrate and the color filter substrate. By controlling the common electrode and pixel electrodes, an electric field is formed to deflect the liquid crystal, thereby realizing a gray scale display.

[0003] With the maturity of TFT-LCD technology, large-size, extra-large-size, and high-resolution LCD devices have been developing rapidly in recent years, and their market share has been gradually expanding.However, as the size of LCD devices increases, defects such as horizontal stripes and light leakage in dark states become more serious, which have a significant impact on product quality and yield. Summary of the Invention [Means for solving the problem]

[0004] The following is a general overview of the subject matter discussed in detail in the text, which is not intended to limit the scope of protection of the claims.

[0005] In one aspect, the present disclosure provides a display panel, comprising: a first substrate and a second substrate disposed opposite each other; the first substrate includes M*N sub-pixels defined by M gate lines and N pairs of data lines intersecting each other, each pair of data lines including a first data line and a second data line, the sub-pixels including a thin film transistor and a pixel electrode, the thin film transistors of all the sub-pixels in the m-th display row are connected to the m-th gate lines, the thin film transistors of the sub-pixels in the odd-numbered display rows in the n-th display column are connected to the first data line of the n-th pair of data lines, and the thin film transistors of the sub-pixels in the even-numbered display rows are connected to the second data line of the n-th pair of data lines, or the thin film transistors of the sub-pixels in the even-numbered display rows in the n-th display column are connected to the first data line of the n-th pair of data lines, and the thin film transistors of the sub-pixels in the odd-numbered display rows are connected to the second data line of the n-th pair of data lines, M and N are all positive integers greater than or equal to 1, m=1, 2, ..., M, n=1, 2, ..., N, the second substrate includes M*N filter units corresponding to the sub-pixels one-to-one, a black matrix is ​​disposed between adjacent filter units, and the black matrix includes a masking row disposed between adjacent display rows and a masking column disposed between adjacent display columns; In the extension direction of the data lines, the masked row located between the kth display row and the k+1th display row has a first width, and the masked row located between the k+1th display row and the k+2th display row has a second width, and the first width is not equal to the second width.

[0006] In some possible implementations, the sub-pixels in the m-th display row include first, second and third sub-pixels arranged periodically, and the masked row located between the k-th display row and the k+1-th display row includes an upper edge located within the k-th display row and a lower edge located within the k+1-th display row, the upper edge being a first upper edge located within the first sub-pixel of the k-th display row, a second upper edge located within the second sub-pixel of the k-th display row, and a third upper edge located within the third sub-pixel of the k-th display row. the lower edges include a first lower edge located in a first sub-pixel of the k+1-th display row, a second lower edge located in a second sub-pixel of the k+1-th display row, and a third lower edge located in a third sub-pixel of the k+1-th display row; the masked row located between the k+1-th and k+2-th display rows includes an upper edge located in the k+1-th display row and a lower edge located in the k+2-th display row; the upper edges include a fourth upper edge located in a first sub-pixel of the k+1-th display row and a fourth lower edge located in a first sub-pixel of the k+1-th display row. the fifth upper edge is located in the second subpixel of the +1th display row and the sixth upper edge is located in the third subpixel of the k+1th display row, and the lower edge includes a fourth lower edge located in the first subpixel of the k+2th display row, a fifth lower edge located in the second subpixel of the k+2th display row, and a sixth lower edge located in the third subpixel of the k+2th display row, and in the extension direction of the data lines, a distance between the first upper edge and the first lower edge is a first distance, and a distance between the second upper edge and the second lower edge is a the distance between the third upper edge and the third lower edge is a third distance, the distance between the fourth upper edge and the fourth lower edge is a fourth distance, the distance between the fifth upper edge and the fifth lower edge is a fifth distance, and the distance between the sixth upper edge and the sixth lower edge is a sixth distance; and the first width not being equal to the second width includes one or more of the first distance being smaller than the fourth distance, the second distance being smaller than the fifth distance, and the third distance being larger than the sixth distance.

[0007] In some possible implementations, the difference between the first distance and the fourth distance is 10 μm to 20 μm, the difference between the second distance and the fifth distance is 10 μm to 20 μm, and the difference between the third distance and the sixth distance is 1 μm to 5 μm.

[0008] In some possible implementations, the third distance is greater than the first distance and the third distance is greater than the second distance.

[0009] In some possible implementations, the difference between the third distance and the first distance is between 10 μm and 35 μm, and the difference between the third distance and the second distance is between 10 μm and 35 μm.

[0010] In some possible implementations, the sixth distance is greater than the fourth distance and the sixth distance is greater than the fifth distance.

[0011] In some possible implementations, the difference between the sixth distance and the fourth distance is between 10 μm and 20 μm, and the difference between the sixth distance and the fifth distance is between 10 μm and 20 μm.

[0012] In some possible implementations, a first protrusion is arranged in a masked row located within a first sub-pixel of the kth display row, the first protrusion being arranged at the first upper edge and extending away from the first lower edge, and a second protrusion is arranged in a masked row located within a second sub-pixel of the kth display row, the second protrusion being arranged at the second upper edge and extending away from the second lower edge.

[0013] In some possible implementations, in the extension direction of the gate line, the first protrusion is located on the side where the thin film transistor of the first sub-pixel is arranged, and the second protrusion is located on the side where the thin film transistor of the second sub-pixel is arranged.

[0014] In some possible implementations, the shapes of the first and second protrusions include rectangles or trapezoids.

[0015] In some possible implementations, in the extension direction of the data line, the first protrusion includes a first protrusion upper edge, the second protrusion includes a second protrusion upper edge, the distance between the first protrusion upper edge and the first upper edge is 10 μm to 20 μm, and the distance between the second protrusion upper edge and the second upper edge is 10 μm to 20 μm.

[0016] In some possible implementations, in the extension direction of the data line, the distance between the third upper edge and the first upper edge is greater than the distance between the first protrusion upper edge and the first upper edge, and the distance between the third upper edge and the second upper edge is greater than the distance between the second protrusion upper edge and the second upper edge.

[0017] In some possible implementations, the first, second, and third lower edges are all straight edges extending in the direction of the gate lines, the fourth, fifth, and sixth upper edges are all straight edges extending in the direction of the gate lines, and protruding blocks are disposed on the fourth, fifth, and sixth lower edges, respectively, and the protruding blocks are disposed adjacent to the shielding rows on both sides of the fourth, fifth, and sixth lower edges.

[0018] In some possible implementations, the protruding block includes a right-angled triangle, the first right-angled sides of which are respectively located at the fourth lower edge, the fifth lower edge, and the sixth lower edge, and the second right-angled sides of which are respectively located in the shielding rows on both sides of the fourth lower edge, the fifth lower edge, and the sixth lower edge.

[0019] In some possible implementations, the first substrate includes a first conductive layer, a first metal layer, a first insulating layer, a semiconductor layer, a second metal layer, a second insulating layer, and a second conductive layer, which are stacked together, the first conductive layer includes a common electrode disposed in each subpixel, the first metal layer includes a gate line, a common electrode line, a gate electrode disposed in each subpixel, and a first connection electrode disposed in the third subpixel, the gate line is connected to the gate electrode in each subpixel, the common electrode line is connected to the common electrode in each subpixel, and the first connection electrode is connected to the common electrode of the third subpixel, the semiconductor layer includes an active layer disposed in each subpixel, and the second metal layer includes a common electrode. The layer includes a first data line, a second data line, and a source electrode and a drain electrode arranged in each subpixel, in which in the kth display row, the source electrode of each subpixel is connected to the first data line, and in the k+1th display row, the source electrode of each subpixel is connected to the second data line, and a conductive channel is formed between the source electrode and the drain electrode, and the second conductive layer includes a pixel electrode arranged in each subpixel and a second connection electrode arranged in the third subpixel, and the pixel electrode is connected to the drain electrode of the subpixel where it is located through a through hole, and the second connection electrode is connected to the first connection electrode and the common electrode line through a through hole, respectively.

[0020] In some possible implementations, in the kth display row, a first common electrode protrusion is arranged on the common electrode of the first sub-pixel, the second sub-pixel, and the third sub-pixel, and the first common electrode protrusion of each sub-pixel is located on the side of the common electrode adjacent to the k-1th display row; a second common electrode protrusion is arranged on the common electrode of the third sub-pixel, and the second common electrode protrusion is located on the side of the common electrode adjacent to the next display row; and the first connection electrode is arranged on the second common electrode protrusion.

[0021] In some possible implementations, in a first spacing region between adjacent common electrode lines, the common electrode lines have a third width, and in a second spacing region between adjacent first spacing regions, the common electrode lines have a fourth width, the third width being smaller than the fourth width; in the first spacing region, the gate lines have a fifth width, and in the second spacing region, the gate lines have a sixth width, the fifth width being smaller than the sixth width.

[0022] In some possible implementations, the gate electrodes in the first sub-pixel, the second sub-pixel, and the third sub-pixel are all rectangular, and the long sides of the gate electrodes in the first sub-pixel and the second sub-pixel extend in the display row direction, and the long side of the gate electrode in the third sub-pixel extends in the display column direction.

[0023] In some possible implementations, one end of the second connection electrode is connected to the first connection electrode via a through hole provided in the first insulating layer and the second insulating layer, and the other end of the second connection electrode is connected to a common electrode line of the next display row via a through hole provided in the first insulating layer and the second insulating layer.

[0024] In some possible implementations, in each sub-pixel, the connection area between the pixel electrode and the drain electrode overlaps with the black matrix, and the edge area of ​​the pixel electrode overlaps with the black matrix.

[0025] In some possible implementations, the multiple filter units in the kth display row include a first filter unit, a second filter unit, and a third filter unit that are periodically arranged, wherein the first filter unit corresponds to the first sub-pixel, the second filter unit corresponds to the second sub-pixel, and the third filter unit corresponds to the third sub-pixel, and the first filter unit includes a red filter unit, the second filter unit includes a green filter unit, and the third filter unit includes a blue filter unit.

[0026] In another aspect, the present disclosure provides a display device, comprising the display panel described above.

[0027] Other aspects may be understood after reading and understanding the accompanying drawings and detailed description. [Brief explanation of the drawings]

[0028] The drawings are intended to facilitate a better understanding of the technical solutions of the present disclosure, constitute a part of the specification, and are used to explain the technical solutions of the present disclosure together with the embodiments of the present disclosure, and are not intended to limit the technical solutions of the present disclosure. The shapes and sizes of the components in the drawings do not reflect actual scale, and are intended only to explain the contents of the present disclosure.

[0029] [Figure 1] FIG. 1 is a structural schematic diagram of a display panel according to an exemplary embodiment of the present disclosure. [Figure 2] FIG. 2 is an equivalent circuit diagram of a first substrate according to an exemplary embodiment of the present disclosure. [Figure 3] FIG. 3 is a top view of a display panel according to an exemplary embodiment of the present disclosure. [Figure 4A] FIG. 4A is a schematic diagram after a first conductive layer pattern is formed, according to an exemplary embodiment of the present disclosure. [Figure 4B] FIG. 4B is a cross-sectional view taken along the line AA in FIG. 4A. [Figure 4C] FIG. 4C is a cross-sectional view taken along the line BB in FIG. 4A. [Figure 5A] FIG. 5A is a schematic diagram after a first metal layer pattern has been formed, according to an exemplary embodiment of the present disclosure. [Figure 5B] FIG. 5B is a cross-sectional view taken along the line AA in FIG. 5A. [Figure 5C] FIG. 5C is a cross-sectional view taken along the line BB in FIG. 5A. [Figure 6A] FIG. 6A is a schematic diagram after a semiconductor layer pattern has been formed, according to an exemplary embodiment of the present disclosure. [Figure 6B]FIG. 6B is a cross-sectional view taken along the line AA in FIG. 6A. [Figure 6C] FIG. 6C is a cross-sectional view taken along the line BB in FIG. 6A. [Figure 7A] FIG. 7A is a schematic diagram after a second metal layer pattern has been formed, according to an exemplary embodiment of the present disclosure. [Figure 7B] FIG. 7B is a cross-sectional view taken along the line AA in FIG. 7A. [Figure 7C] FIG. 7C is a cross-sectional view taken along the line BB in FIG. 7A. [Figure 8A] FIG. 8A is a schematic diagram after a second insulating layer pattern is formed according to an exemplary embodiment of the present disclosure. [Figure 8B] FIG. 8B is a cross-sectional view taken along the line AA in FIG. 8A. [Figure 8C] FIG. 8C is a cross-sectional view taken along the line BB in FIG. 8A. [Figure 9A] FIG. 9A is a schematic diagram after a second conductive layer pattern has been formed, according to an exemplary embodiment of the present disclosure. [Figure 9B] FIG. 9B is a cross-sectional view taken along the line AA in FIG. 9A. [Figure 9C] FIG. 9C is a cross-sectional view taken along the line BB in FIG. 9A. [Figure 10A] FIG. 10A is a schematic diagram after a black matrix pattern is formed according to an exemplary embodiment of the present disclosure. [Figure 10B] FIG. 10B is a cross-sectional view taken along the CC direction in FIG. 10A. [Figure 10C] FIG. 10C is a cross-sectional view taken along the DD direction in FIG. 10A. [Figure 11A] FIG. 11A is a schematic diagram after a filter unit pattern has been formed, according to an exemplary embodiment of the present disclosure. [Figure 11B] FIG. 11B is a cross-sectional view taken along the CC direction in FIG. 11A. [Figure 11C] FIG. 11C is a cross-sectional view taken along the DD direction in FIG. 11A. [Figure 12]FIG. 12 is a schematic diagram of a display panel formed according to an exemplary embodiment of the present disclosure. [Figure 13] FIG. 13 is an equivalent circuit diagram of another first substrate according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0030] The embodiments in this specification can be implemented in a variety of different forms. As those skilled in the art can easily understand, the implementation methods and contents can be converted into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments and features in the embodiments in the present disclosure can be arbitrarily combined.

[0031] In the drawings, the size of components, layer thicknesses, or areas may be exaggerated for clarity. Therefore, any one of the embodiments of the present disclosure is not necessarily limited to the sizes shown in the drawings, and the shapes and sizes of parts in the drawings do not reflect actual scale. Note that the drawings schematically show ideal examples, but any one of the embodiments of the present disclosure is not limited to the shapes, values, etc. shown in the drawings.

[0032] In this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of elements and are not intended to limit the number of elements.

[0033] For convenience, terms indicating orientations or positional relationships, such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer," are used in this specification to describe the positional relationships of components with reference to the drawings. However, these terms are merely for the purpose of easily describing the embodiments and do not explicitly or implicitly indicate that the indicated devices or elements necessarily have a specific orientation or are constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure. The positional relationships of components can be appropriately changed depending on the orientation of the components being described. Therefore, without being limited to the terms described in the specification, appropriate substitutions can be made depending on the situation.

[0034] In this specification, unless otherwise clearly specified or limited, the terms "attach" and "connect" should be understood in a broad sense. For example, they may mean fixedly connected, detachably connected, or integrally connected, may be mechanically connected or electrically connected, may be directly connected, may be indirectly connected via an intermediate part, or may be connected inside two elements. Those skilled in the art can understand the meaning of the above terms in this disclosure depending on the context.

[0035] In this specification, a transistor refers to an element that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor includes a drain electrode (or drain electrode terminal, drain Area and ) and a source electrode (or source electrode terminal, source Area and A channel region is formed between the drain electrode and the source electrode, and a current can flow between the drain electrode, the channel region, and the source electrode. In this specification, the channel region refers to a region through which a current mainly flows.

[0036] As used herein, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. When reverse polarity transistors are used, or when the direction of current flow during circuit operation changes, the functions of "source electrode" and "drain electrode" may be interchangeable. Thus, as used herein, "source electrode" and "drain electrode" may be interchangeable.

[0037] In this specification, "electrical connection" includes cases where components are connected via an element having some electrical function. The "element having some electrical function" is not particularly limited as long as it can transmit and receive electrical signals between the connected components. The "element having some electrical function" may be, for example, an electrode or wiring, a switching element such as a transistor, or other functional element such as a resistor, inductor, or capacitor.

[0038] In this specification, "parallel" refers to a state in which the angle between two lines is -10° or more and 10° or less, and therefore also includes a state in which the angle is -5° or more and 5° or less. "Perpendicular" refers to a state in which the angle between two lines is 80° or more and 100° or less, and therefore also includes a state in which the angle is 85° or more and 95° or less.

[0039] In this specification, the terms "film" and "layer" can be used interchangeably. For example, a "conductive layer" can be used interchangeably with a "conductive film." Similarly, an "insulating film" can be used interchangeably with a "conductive layer."

[0040] In this specification, "about" refers to not strictly limiting the limits but allowing for numerical values ​​within the error range of process and measurement.

[0041] An LCD device scans in a row-by-row, column-by-column manner, and a timing control circuit (T-CON) controls the subpixels of the display device to be turned on row by row and column by column, from left to right and top to bottom. In large- and extra-large-size LCD devices, the number of gate lines and data lines increases, resulting in increased lengths of the gate lines and data lines. Therefore, if the scanning frequency remains unchanged, the effective charging time of the subpixels is significantly reduced. To ensure the charging rate of large- and extra-large-size, high-resolution LCD devices, one pixel structure employs a gate line bilateral drive and dual data line structure, known as 2G2D drive. In 2G2D drive, the thin film transistors of one display row are arranged to the right of the first data line, and the thin film transistors of the adjacent display row are arranged to the left of the second data line. As a result of the investigation, it was found that because the positions of the thin film transistors in two adjacent display rows are different, there is a difference in pixel aperture ratio between the sub-pixels in the two adjacent display rows. The difference in pixel aperture ratio not only causes horizontal stripe defects, but also leads to light leakage defects in the dark state if the array substrate and the color filter substrate are misaligned.

[0042] An exemplary embodiment of the present disclosure provides a display panel, the display panel comprising: a first substrate and a second substrate disposed opposite to each other; the first substrate includes M*N sub-pixels defined by M gate lines and N pairs of data lines intersecting each other; each pair of data lines includes a first data line and a second data line; the sub-pixels include a thin film transistor and a pixel electrode; in the mth display row, the thin film transistors of all the sub-pixels are connected to the mth gate lines; in the nth display column, the thin film transistors of the sub-pixels in the odd-numbered display rows are connected to the first data line of the nth pair of data lines, and the thin film transistors of the sub-pixels in the even-numbered display rows are connected to the second data line of the nth pair of data lines; or in the nth display column, the thin film transistors of the sub-pixels in the even-numbered display rows are connected to the first data line of the nth pair of data lines, and the thin film transistors of the sub-pixels in the odd-numbered display rows are connected to the second data line of the nth pair of data lines; M and N are all positive integers equal to or greater than 1, and m=1, 2, ..., M, n=1, 2, ..., N; the second substrate includes M*N filter units corresponding to the sub-pixels one-to-one, a black matrix is ​​disposed between adjacent filter units, and the black matrix includes a masking row disposed between adjacent display rows and a masking column disposed between adjacent display columns; In the extension direction of the data lines, the masked row located between the kth display row and the k+1th display row has a first width, and the masked row located between the k+1th display row and the k+2th display row has a second width, and the first width is not equal to the second width.

[0043] 1 is a structural schematic diagram of a display panel according to an exemplary embodiment of the present disclosure. As shown in FIG. 1, the display panel includes a first substrate 1 and a second substrate 2 arranged opposite each other, and a liquid crystal layer (not shown) arranged between the first substrate 1 and the second substrate 2. The first substrate 1 includes at least thin film transistors 3 and pixel electrodes 8 arranged on a first base substrate 10, and the second substrate 2 includes at least a black matrix 21 and a filter unit 22 arranged on a second base substrate 20, with the black matrix 21 of the second substrate 2 being arranged to shield at least the thin film transistors 3 of the first substrate 1.

[0044] 2 is an equivalent circuit diagram of a first substrate according to an exemplary embodiment of the present disclosure. As shown in FIG. 2, the first substrate 1 includes M gate lines 4, M common electrode lines 5, and N pairs of data lines, each pair of data lines including a first data line 6 and a second data line 7. The gate lines 4 and the common electrode lines 5 extending horizontally and arranged in parallel define M display rows, and the first data lines 6 and the second data lines 7 extending vertically and arranged in parallel define N display columns. Thus, the M gate lines 4, the M common electrode lines 5, the N first data lines 6, and the N second data lines 7 vertically intersect to define M*N sub-pixels arranged in an array, where M and N are all positive integers greater than or equal to 1. Each subpixel includes a thin film transistor 3, a pixel electrode 8, and a common electrode 9. The source electrode of the thin film transistor 3 is connected to a first data line 6 or a second data line 7. The drain electrode of the thin film transistor 3 is connected to the pixel electrode 8 of the corresponding subpixel, and the common electrode 9 is connected to a common electrode line 5. In one display row, the gate line 4 is disposed adjacent to the next display row, and the common electrode line 5 is disposed adjacent to the previous display row. That is, the gate line 4 is disposed below the subpixels of the current display row, and the common electrode line 5 is disposed above the subpixels of the current display row. In one display column, the first data line 6 is disposed adjacent to the previous display column (the left display column in this example) and the second data line 7 is disposed adjacent to the next display column (the right display column in this example). That is, the first data line 6 is disposed to the left of the subpixels of the current display column, and is located between the current display column and the left display column. The second data line 7 is disposed to the right of the subpixels of the current display column, and is located between the current display column and the right display column. The M display rows include M / 2 odd display rows and M / 2 even display rows. The thin film transistors 3 of the sub-pixels in the M / 2 odd display rows are connected to the first data line 6, and the thin film transistors 3 of the sub-pixels in the M / 2 even display rows are connected to the second data line 7.

[0045] In an exemplary embodiment, the second substrate 2 includes M*N filter units 22 arranged in an array, the positions of the M*N filter units 22 and the M*N sub-pixels correspond one-to-one, and a black matrix 21 is disposed between two adjacent filter units 22.

[0046] 3 is a top view of a display panel according to an exemplary embodiment of the present disclosure, showing black matrices 21 and filter units 22 for two display rows and three display columns in the display panel. In the exemplary embodiment, the two display rows are the kth display row and the k+1th display row, respectively, the kth display row and the k+2th display row are odd-numbered display rows, and the k+1th display row is an even-numbered display row.

[0047] In an exemplary embodiment, each display row of the first substrate 1 includes first, second, and third sub-pixels periodically arranged in the display row direction, and each display row of the second substrate 2 includes first, second, and third filter units periodically arranged in the display row direction, where the positions of the first filter units correspond to the positions of the first sub-pixels, the positions of the second filter units correspond to the positions of the second sub-pixels, and the positions of the third filter units correspond to the positions of the third sub-pixels. Because the filter units of the second substrate 2 correspond one-to-one to the sub-pixels of the first substrate 1, in the following description of the present disclosure, the sub-pixels of the first substrate 1 and the filter units of the second substrate 2 will be collectively referred to as sub-pixels.

[0048] In an exemplary embodiment, on the second substrate 2, a black matrix 21 is located between two adjacent sub-pixels (filter units), and the black matrix 21 includes a shielding row 211 located between the sub-pixels of adjacent display rows and a shielding column 212 located between the sub-pixels of adjacent display columns, the shielding row 211 being arranged to shield the gate lines, common electrode lines, and thin film transistors of the first substrate 1, and the shielding column 212 being arranged to shield the first data lines and second data lines of the first substrate 1.

[0049] In an exemplary embodiment, in the extension direction Y of the data lines, the shielding row 211 located between the subpixels of the kth display row and the subpixels of the k+1th display row has a first width, and the shielding row 211 located between the subpixels of the k+1th display row and the subpixels of the k+2th display row has a second width, where the first width is not equal to the second width. Thin film transistors of the subpixels in the kth display row and the k+2th display row are connected to the first data line, and the thin film transistors of the subpixels in the k+1th display row are connected to the second data line. That is, when k is an odd number, the shielding row between the kth (odd) display row and the k+1th (even) display row has a first width, and the shielding row between the k+1th (even) display row and the k+2th (odd) display row has a second width, where the first width is not equal to the second width. Alternatively, when k is an even number, the masked row between the kth (even-numbered) display row and the k+1th (odd-numbered) display row has a first width, and the masked row between the k+1th (odd-numbered) display row and the k+2th (even-numbered) display row has a second width, and the first width is set not to be equal to the second width. In the present disclosure, the extension direction Y of the data lines refers to the direction parallel to the data lines.

[0050] In an exemplary embodiment, the masked row 211 located between the sub-pixels of the kth display row and the sub-pixels of the k+1th display row includes an upper edge located within the kth display row and a lower edge located within the k+1th display row. The upper edge located within the kth display row includes a first upper edge 101 located within a first sub-pixel of the kth display row, a second upper edge 201 located within a second sub-pixel of the kth display row, and a third upper edge 301 located within a third sub-pixel of the kth display row. The lower edge located within the k+1th display row includes a first lower edge 102 located within a first sub-pixel of the k+1th display row, a second lower edge 202 located within a second sub-pixel of the k+1th display row, and a third lower edge 302 located within a third sub-pixel of the k+1th display row. In the extension direction Y of the data line, the distance between the first upper edge 101 and the first lower edge 102 is a first distance L1, the distance between the second upper edge 201 and the second lower edge 202 is a second distance L2, and the distance between the third upper edge 301 and the third lower edge 302 is a third distance L3.

[0051] In the exemplary embodiment, the masked row 211 located between the subpixels of the k+1th display row and the subpixels of the k+2th display row includes an upper edge located within the k+1th display row and a lower edge located within the k+2th display row. The upper edge located within the k+1th display row includes a fourth upper edge 401 located within the first subpixel of the k+1th display row, a fifth upper edge 501 located within the second subpixel of the k+1th display row, and a sixth upper edge 601 located within the third subpixel of the k+1th display row. The lower edge located within the k+2th display row includes a fourth lower edge 402 located within the first subpixel of the k+2th display row, a fifth lower edge 502 located within the second subpixel of the k+2th display row, and a sixth lower edge 602 located within the third subpixel of the k+2th display row. In the extension direction Y of the data line, the distance between the fourth upper edge 401 and the fourth lower edge 402 is a fourth distance L4, the distance between the fifth upper edge 501 and the fifth lower edge 502 is a fifth distance L5, and the distance between the sixth upper edge 601 and the sixth lower edge 602 is a sixth distance L6.

[0052] In an exemplary embodiment, the first width not being equal to the second width includes one or more of: the first distance L1 being less than the fourth distance L4; the second distance L2 being less than the fifth distance L5; and the third distance L3 being greater than the sixth distance L6.

[0053] In an exemplary embodiment, the difference between the first distance L1 and the fourth distance L4 is approximately 10 μm to 20 μm, the difference between the second distance L2 and the fifth distance L5 is approximately 10 μm to 20 μm, and the difference between the third distance L3 and the sixth distance L6 is approximately 1 μm to 5 μm. In some possible implementations, the difference between the first distance L1 and the fourth distance L4 is approximately 13 μm to 15 μm, the difference between the second distance L2 and the fifth distance L5 is approximately 13 μm to 15 μm, and the difference between the third distance L3 and the sixth distance L6 is approximately 2.5 μm to 3.5 μm.

[0054] In the exemplary embodiment, the third distance L3 is greater than the first distance L1, the third distance L3 is greater than the second distance L2, and the first distance L1 is equal to the second distance L2.

[0055] In some possible implementations, the difference between the third distance L3 and the first distance L1 is about 10 μm to 35 μm, and the difference between the third distance L3 and the second distance L2 is about 10 μm to 35 μm.

[0056] In the exemplary embodiment, the sixth distance L6 is greater than the fourth distance L4, the sixth distance L6 is greater than the fifth distance L5, and the fourth distance L4 is equal to the fifth distance L5.

[0057] In some possible implementations, the difference between the sixth distance L6 and the fourth distance L4 is about 10 μm to 20 μm, and the difference between the sixth distance L6 and the fifth distance L5 is about 10 μm to 20 μm.

[0058] In an exemplary embodiment, a first protrusion 103 is disposed in a masked row located within a first sub-pixel of the kth display row, and a second protrusion 203 is disposed in a masked row located within a second sub-pixel of the kth display row. The first protrusion 103 is disposed at a first upper edge 101 and extends away from a first lower edge 102, and the second protrusion 203 is disposed at a second upper edge 201 and extends away from a second lower edge 202.

[0059] In the exemplary embodiment, in the extension direction X of the gate line, the first protrusion 103 is located on the side where the thin film transistor of the first subpixel is arranged, and the second protrusion 203 is located on the side where the thin film transistor of the second subpixel is arranged. Since the kth display row is an odd-numbered display row and the thin film transistor of the subpixel in the kth display row is connected to the first data line located on the left side of the subpixel, the thin film transistor of the subpixel in the kth display row is located on the left side of the subpixel, the first protrusion 103 is located on the left side of the first subpixel, and the second protrusion 203 is located on the left side of the second subpixel. In the present disclosure, the extension direction X of the gate line refers to the direction parallel to the gate line.

[0060] In an exemplary embodiment, in a plane parallel to the display panel, the shape of the first protrusion 103 and the second protrusion 203 may include a rectangle or a trapezoid.

[0061] In an exemplary embodiment, the first protrusion 103 and the second protrusion 203 are rectangular or trapezoidal in shape, the first protrusion 103 includes a first protrusion upper edge, and the second protrusion 203 includes a second protrusion upper edge, and in the extension direction Y of the data line, the distance L7 between the first protrusion upper edge and the first upper edge 101 is approximately 10 μm to 20 μm, and the distance L8 between the second protrusion upper edge and the second upper edge 201 is approximately 10 μm to 20 μm.

[0062] In an exemplary embodiment, in the extension direction Y of the data line, the distance between the third upper edge 301 and the first upper edge 101 is greater than the distance L7 between the first protrusion upper edge and the first upper edge 101, and the distance between the third upper edge 301 and the second upper edge 201 is greater than the distance L8 between the second protrusion upper edge and the second upper edge 201.

[0063] In an exemplary embodiment, the first lower edge, the second lower edge, and the third lower edge are all flat, straight edges extending in the direction of extension of the gate lines, the fourth upper edge, the fifth upper edge, and the sixth upper edge are all flat, straight edges extending in the direction of extension of the gate lines, and protruding blocks are arranged on the fourth lower edge, the fifth lower edge, and the sixth lower edge, and the protruding blocks are arranged at positions adjacent to the shielding rows on both sides of the fourth lower edge, the fifth lower edge, and the sixth lower edge, respectively.

[0064] In an exemplary embodiment, the protruding block includes a right-angled triangle, a first right-angled side of the right-angled triangle being located at the fourth lower edge, the fifth lower edge, and the sixth lower edge, respectively, and a second right-angled side of the right-angled triangle being located in the shielding rows on both sides of the fourth lower edge, the fifth lower edge, and the sixth lower edge, respectively.

[0065] In an exemplary embodiment, the first substrate includes a first conductive layer, a first metal layer, a first insulating layer, a semiconductor layer, a second metal layer, a second insulating layer, and a second conductive layer, which are stacked together, the first conductive layer including a common electrode disposed in each subpixel, the first metal layer including a gate line, a common electrode line, a gate electrode disposed in each subpixel, and a first connection electrode disposed in the third subpixel, the gate line being connected to the gate electrode in each subpixel, the common electrode line being connected to the common electrode in each subpixel, and the first connection electrode being connected to the common electrode of the third subpixel, the semiconductor layer including an active layer disposed in each subpixel, and the second metal layer including The display panel includes a first data line, a second data line, and a source electrode and a drain electrode arranged in each subpixel, wherein in the kth display row, the source electrode of each subpixel is connected to the first data line, and in the k+1th display row, the source electrode of each subpixel is connected to the second data line, and a conductive channel is formed between the source electrode and the drain electrode, and the second conductive layer includes a pixel electrode arranged in each subpixel and a second connection electrode arranged in the third subpixel, and the pixel electrode is connected to the drain electrode of the subpixel in which it is located through a through hole, and the second connection electrode is connected to the first connection electrode and the common electrode line through a through hole, respectively.

[0066] In an exemplary embodiment, in the kth display row, a first common electrode protrusion is arranged on the common electrode in the first subpixel, the second subpixel, and the third subpixel, and the first common electrode protrusion of each subpixel is located on the side of the common electrode adjacent to the k-1th display row, a second common electrode protrusion is arranged on the common electrode in the third subpixel, and the second common electrode protrusion is located on the side of the common electrode adjacent to the next display row, and the first connection electrode is arranged on the second common electrode protrusion.

[0067] In an exemplary embodiment, in a first spacing region between adjacent common electrode lines, the common electrode lines have a third width, and in a second spacing region between adjacent first spacing regions, the common electrode lines have a fourth width, the third width being smaller than the fourth width, and in the first spacing region, the gate lines have a fifth width, and in the second spacing region, the gate lines have a sixth width, the fifth width being smaller than the sixth width.

[0068] In an exemplary embodiment, the gate electrodes in the first subpixel, the second subpixel, and the third subpixel are all rectangular, and the long sides of the gate electrodes in the first subpixel and the second subpixel extend in the display row direction, and the long side of the gate electrode in the third subpixel extends in the display column direction.

[0069] In an exemplary embodiment, one end of the second connection electrode is connected to the first connection electrode via a through hole provided in the first insulating layer and the second insulating layer, and the other end of the second connection electrode is connected to the common electrode line of the next display row via a through hole provided in the first insulating layer and the second insulating layer.

[0070] In an exemplary embodiment, in each subpixel, a connection region between the pixel electrode and the drain electrode overlaps with the black matrix, and an edge region of the pixel electrode overlaps with the black matrix.

[0071] In an exemplary embodiment, the first subpixel (first filter unit) is a red subpixel (red filter unit), the second subpixel (second filter unit) is a green subpixel (green filter unit), and the third subpixel (third filter unit) is a blue subpixel (blue filter unit).

[0072] The following provides an exemplary description of the manufacturing process of a display panel. The "patterning process" referred to in this disclosure includes film layer deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping. The deposition can employ any one or more of sputtering, evaporation, and chemical vapor deposition; the coating can employ any one or more of spray coating and spin coating; and the etching can employ any one or more of dry etching and wet etching. A "thin film" refers to a layer of a material fabricated on a base substrate by a deposition or coating process. If the "thin film" does not require a patterning process during the entire manufacturing process, it may also be referred to as a "layer." If the "thin film" requires a patterning process during the entire manufacturing process, it is referred to as a "thin film" before the patterning process and as a "layer" after the patterning process. After the patterning process, the "layer" includes at least one "pattern." The term "A and B in the same layer" used in the present disclosure means that A and B are formed simultaneously by the same patterning process. In an exemplary embodiment of the present disclosure, the term "the orthogonal projection of A includes the orthogonal projection of B" means that the boundary of the orthogonal projection of B is within the boundary of the orthogonal projection of A, or that the boundary of the orthogonal projection of A and the boundary of the orthogonal projection of B completely overlap.

[0073] In an exemplary embodiment, the manufacturing process of a display panel may include two parts, the first part including substrate manufacturing and the second part including alignment pressing (cell alignment). In an exemplary embodiment, the substrate manufacturing includes first substrate manufacturing and second substrate manufacturing, and both can be performed simultaneously without any prior or subsequent order. In an exemplary embodiment, the first substrate may be an array substrate, and the second substrate may be a color filter substrate. The following describes the processing processes of the two parts respectively.

[0074] 1. Fabrication of the array substrate in the first part 4A to 9C show a fabrication process of an array substrate, which shows a structure of six sub-pixels in two display rows and three display columns on the array substrate. In an exemplary embodiment, the kth display row and the k+2th display row may be odd-numbered rows, and the k+1th display row may be even-numbered row. Each display row may include a first sub-pixel, a second sub-pixel, and a third sub-pixel, which correspond to the first filter unit, the second filter unit, and the third filter unit of the color filter substrate, respectively.

[0075] (1) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include depositing a first transparent conductive thin film on a first base substrate, patterning the first transparent conductive thin film by a patterning process, and forming a first conductive layer pattern on the first base substrate 10, where the first conductive layer pattern includes at least a common electrode 9 disposed in each subpixel, as shown in Figures 4A, 4B, and 4C, where Figure 4B is a cross-sectional view taken along the AA direction in Figure 4A, and Figure 4C is a cross-sectional view taken along the BB direction in Figure 4A.

[0076] In an exemplary embodiment, in each display row, the common electrode 9 is a plate-shaped electrode, the shape and size of the common electrode 9 of the first subpixel and the second subpixel are the same, the shape and size of the common electrode 9 of the third subpixel are different from those of the first subpixel and the second subpixel, the shape and size of the common electrode 9 of the first subpixel of the kth display row are different from those of the first subpixel of the k+1th display row, the shape and size of the common electrode 9 of the second subpixel of the kth display row are different from those of the second subpixel of the k+1th display row, and the shape and size of the common electrode 9 of the third subpixel of the kth display row are different from those of the third subpixel of the kth display row.

[0077] In an exemplary embodiment, a first common electrode protrusion is arranged on the common electrode 9 in the first sub-pixel, the second sub-pixel, and the third sub-pixel in the kth display row, and the first common electrode protrusion of each sub-pixel is located on the side of the common electrode 9 adjacent to the k-1th display row, and the first common electrode protrusion of each sub-pixel is arranged to be connected to a common electrode line to be formed subsequently, thereby realizing interconnection of the common electrodes 9 of each sub-pixel in the display row direction.

[0078] In an exemplary embodiment, a second common electrode protrusion is arranged on the common electrode 9 of the third subpixel in the kth display row and the third subpixel in the k+1th display row, the second common electrode protrusion of the third subpixel in the kth display row is located on the side of the common electrode 9 adjacent to the k+1th display row, and the second common electrode protrusion of the third subpixel in the k+1th display row is located on the side of the common electrode 9 adjacent to the k+2th display row, and the second common electrode protrusion is arranged to connect the common electrode 9 of the third subpixel in the kth display row to the common electrode 9 of the third subpixel in the k+1th display row via the subsequently formed first connection electrode and second connection electrode, thereby realizing mutual connection of the common electrodes 9 of the third subpixels in the display column direction. Common electrode 9 are interconnected through the second common electrode protrusion, the first connecting electrode, the second connecting electrode, and the common electrode line 5, so that the common electrodes 9 of all the sub-pixels are interconnected, and thereby the common electrodes 9 of all the sub-pixels have the same potential, improving the display effect of the display panel.

[0079] In an exemplary embodiment, in the kth display row, a portion of the area of ​​the common electrode line 5 in the orthogonal projection on the base substrate 10 overlaps with a portion of the area of ​​the common electrode 9 in the orthogonal projection on the base substrate 10. That is, a portion of the common electrode line 5 is disposed on the common electrode 9, and another portion is disposed on the base substrate 10. In the k+1th display row, the entire area of ​​the common electrode line 5 in the orthogonal projection on the base substrate 10 overlaps with a portion of the area of ​​the common electrode 9 in the orthogonal projection on the base substrate 10. That is, the common electrode line 5 is disposed on the common electrode 9.

[0080] (2) Forming a first metal layer pattern. In an exemplary embodiment, forming the first metal layer pattern includes depositing a first metal thin film on the first base substrate on which the above-described pattern has been formed, patterning the first metal thin film by a patterning process, and depositing the first metal thin film on the first base substrate 10, as shown in FIGS. 5A, 5B, and 5C. First metal layer pattern Forming First metal layer pattern may include at least a gate line 4 and a common electrode line 5 extending in the horizontal direction, a gate electrode 11 arranged in each sub-pixel, and a first connection electrode 31 arranged in the third sub-pixel, and FIG. 5B is a cross-sectional view taken along the AA direction in FIG. 5A, and FIG. 5C is a cross-sectional view taken along the BB direction in FIG. 5A.

[0081] In an exemplary embodiment, the gate line 4 of each display row is disposed below the display row and spaced a certain distance from the common electrode 9 of each subpixel in the display row. A common electrode line 5 parallel to the gate line 4 is disposed above the display row and is attached to the common electrode 9 of each subpixel in the display row, thereby realizing connection between the common electrode line 5 and the common electrode 9 of each subpixel in the display row direction. In each subpixel, the gate electrode 11 has an integral structure connected to the gate line 4. The first connection electrode 31 located in the third subpixel is disposed on the second common electrode protrusion of the common electrode 9 of the third subpixel, thereby realizing connection between the first connection electrode 31 and the common electrode 9 of the third subpixel. In the kth display row, the first connection electrode 31 is disposed to the right of the gate electrode 11 of the third subpixel, and in the k+1th display row, the first connection electrode 31 is disposed to the left of the gate electrode 11 of the third subpixel.

[0082] In an exemplary embodiment, the horizontally arranged common electrode lines 5 may be arranged with non-equidistant widths. In a first spacing region between adjacent common electrode lines 5, the common electrode lines 5 have a third width. In a second spacing region between adjacent first spacing regions, the common electrode lines 5 have a fourth width, the third width being smaller than the fourth width. Because the common electrode lines 5 and the common electrodes 9 are connected in the second spacing region, the wider common electrode lines 5 can ensure a reliable connection between the common electrode lines 5 and the common electrodes 9. In a subsequent process, because data lines are disposed in the first spacing region between adjacent common electrode lines 5, the narrower common electrode lines 5 can reduce the overlap area between the common electrode lines 5 and the subsequently formed data lines. This corresponds to the common electrode lines 5 being designed with a reduced width in the overlapping region with the data lines, thereby reducing the parasitic capacitance between the common electrode lines 5 and the data lines and improving the electrical performance of the display panel. In the embodiments of the present disclosure, the width of the common electrode line refers to the size of the common electrode line in a direction perpendicular to the common electrode line.

[0083] In an exemplary embodiment, horizontally arranged gate lines 4 may be arranged with non-uniform widths. In a first spacing region between adjacent common electrode lines 5, the gate lines 4 have a fifth width, and in a second spacing region between adjacent first spacing regions, the gate lines 4 have a sixth width, the fifth width being smaller than the sixth width. Because the gate lines 4 are connected to the gate electrodes 11 in the second spacing region, a wider gate line 4 increases the area of ​​the gate electrodes 11 and improves the electrical performance of the thin film transistor. Because data lines are disposed in the first spacing region between adjacent common electrode lines 5 in a subsequent process, a narrower gate line 4 can reduce the overlap area between the gate line 4 and the subsequently formed data line. This corresponds to the gate line 4 being designed with a reduced width in the overlap region with the data line, thereby reducing the parasitic capacitance between the gate line 4 and the data line and improving the electrical performance of the display panel. In the embodiments of the present disclosure, the width of the gate line refers to the size of the gate line in a direction perpendicular to the gate line.

[0084] In the exemplary embodiment, the gate electrodes 11 in the first, second, and third subpixels are all rectangular, with the longer sides of the gate electrodes 11 in the first and second subpixels extending in the row direction and the longer side of the gate electrode 11 in the third subpixel extending in the column direction. In a direction perpendicular to the gate line, the distance between the upper edge of the gate electrode 11 in the third subpixel and the gate line 4 is greater than the distance between the upper edges of the gate electrodes 11 in the first and second subpixels and the gate line 4. In a direction parallel to the gate line, the distance between the two edges of the gate electrode 11 in the third subpixel is smaller than the distance between the two edges of the gate electrode 11 in the first and second subpixels. Because a second common electrode protrusion extending toward the gate line 4 is disposed on the common electrode 9 in the third subpixel, the gate electrode 11 in the third subpixel is designed to have a rectangular shape extending toward the common electrode 9, thereby ensuring the area of ​​the gate electrode 11 in the third subpixel.

[0085] (3) Forming a semiconductor layer pattern. In an exemplary embodiment, forming the semiconductor layer pattern may include sequentially depositing a first insulating thin film and a semiconductor layer thin film on the first base substrate on which the aforementioned pattern has been formed, and patterning the semiconductor layer thin film through a patterning process to form a first insulating layer 12 covering the first metal layer pattern and the first conductive layer pattern, and a semiconductor layer pattern disposed on the first insulating layer 12, as shown in Figures 6A, 6B, and 6C. The semiconductor layer pattern includes at least an active layer 13 disposed in each subpixel, and the position of each active layer 13 corresponds to the position of the gate electrode 11 in the subpixel in which it is located. Figure 6B is a cross-sectional view taken along the AA direction in Figure 6A, and Figure 6C is a cross-sectional view taken along the BB direction in Figure 6A.

[0086] In an exemplary embodiment, the shape of the active layer 13 in each subpixel may be the same, and the position of the active layer 13 in each subpixel in the kth display row is different from the position of the active layer 13 in each subpixel in the k+1th display row.

[0087] In an exemplary embodiment, the kth display row is an odd-numbered row, and the thin film transistors in the first, second, and third subpixels are connected to the first data line located to the left of the subpixels. Therefore, the active layer 13 in the kth display row is located closer to the first data line (left side), thereby simplifying the structure of the source electrode of the thin film transistor, reducing parasitic capacitance between the source electrode and the gate electrode, and improving the electrical performance of the thin film transistor. The k+1th display row is an even-numbered row, and the thin film transistors in the first, second, and third subpixels are connected to the second data line located to the right of the subpixels. Therefore, the active layer 13 in the k+1th display row is located closer to the second data line (right side), thereby simplifying the structure of the source electrode of the thin film transistor, reducing parasitic capacitance between the source electrode and the gate electrode, and improving the electrical performance of the thin film transistor.

[0088] (4) forming a second metal layer pattern. In an exemplary embodiment, Second metal layer pattern As shown in FIGS. 7A, 7B, and 7C, the second metal thin film is deposited on the first base substrate on which the above-mentioned pattern is formed, and the second metal thin film is patterned by a patterning process, and then disposed on the first insulating layer 12. Second metal layer pattern Forming Second metal layer pattern may include at least a first data line 6 and a second data line 7 extending in the vertical direction, and a source electrode 14 and a drain electrode 15 arranged in each sub-pixel, FIG. 7B is a cross-sectional view taken along the AA direction in FIG. 7A, and FIG. 7C is a cross-sectional view taken along the BB direction in FIG. 7A.

[0089] In an exemplary embodiment, the first data line 6 and the second data line 7 in each display column form a dual data line, where the first data line 6 is disposed on the left side of each display column and is used to provide data signals to the sub-pixels in the kth display row (odd-numbered row), and the second data line 7 is disposed on the right side of each display column and is used to provide data signals to the sub-pixels in the k+1th display row (even-numbered row). In the kth display row, the source electrode 14 of each sub-pixel is connected to the first data line 6, and in the k+1th display row, the source electrode 14 of each sub-pixel is connected to the second data line 7. In each sub-pixel, one end of the source electrode 14 and one end of the drain electrode 15 are disposed on the active layer 13, respectively, and a conductive channel is formed between the source electrode 14 and the drain electrode 15.

[0090] In an exemplary embodiment, in each display row, the source electrodes 14 and drain electrodes 15 of the first and second subpixels are the same in shape, size, and position, while the third subpixel has a different shape, size, and position from the first and second subpixels. The source electrodes 14 and drain electrodes 15 of the first subpixel in the kth display row and the first subpixel in the k+1th display row are the same in shape and size, and their positions are mirror symmetrical about the vertical center line. The source electrodes 14 and drain electrodes 15 of the second subpixel in the kth display row and the second subpixel in the k+1th display row are the same in shape and size, and their positions are mirror symmetrical about the vertical center line. The source electrodes 14 and drain electrodes 15 of the third subpixel in the kth display row and the third subpixel in the k+1th display row are the same in shape and size, and their positions are mirror symmetrical about the vertical center line. The vertical center line is the center line between the first data line 6 and the second data line 7 in each display column.

[0091] In some possible implementations, the formation of the semiconductor layer pattern and the formation of the second metal layer pattern may be patterned in a single patterning process, by first sequentially depositing a first insulating thin film, a semiconductor layer thin film, and a second metal thin film, coating a layer of photoresist on the second metal thin film, exposing and developing the photoresist with a half-tone or gray-tone mask plate, and then using a secondary etching process and a primary ashing process to form patterns of the active layer, the first data line, the second data line, the source electrode, and the drain electrode, with the semiconductor layer thin film retained under the patterns of the first data line, the second data line, the source electrode, and the drain electrode.

[0092] (5) Forming a second insulating layer pattern. In an exemplary embodiment, forming a second insulating layer pattern includes depositing a second insulating thin film on the first base substrate on which the above-mentioned pattern has been formed, and patterning the second insulating thin film through a patterning process, as shown in Figures 8A, 8B, and 8C; Second metal layer pattern 8B is a cross-sectional view in the AA direction in FIG. 8A, and FIG. 8C is a cross-sectional view in the BB direction in FIG. 8A.

[0093] In an exemplary embodiment, the through holes may include a first through hole K1 arranged at a position where the drain electrode 15 of each subpixel is located, a second through hole K2 arranged at a position where the first connection electrode 31 of the third subpixel is located, and a third through hole K3 arranged at a position where the common electrode line 5 of the third subpixel is located, wherein the second insulating layer 16 in the first through hole K1 is etched and removed to expose the surface of the drain electrode 15, the second insulating layer 16 and the first insulating layer 12 in the second through hole K2 are etched and removed to expose the surface of the first connection electrode 31, and the second insulating layer 16 and the first insulating layer 12 in the third through hole K3 are etched and removed to expose the surface of the common electrode line 5. The position of the third through hole K3 in the third subpixel of the kth display row is different from the position of the third through hole K3 in the third subpixel of the k+1th display row.

[0094] (6) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include depositing a second transparent conductive thin film on the first base substrate on which the aforementioned pattern has been formed, and patterning the second transparent conductive thin film through a patterning process to form a second conductive layer pattern, as shown in FIGS. 9A, 9B, and 9C. The second conductive layer pattern may include at least a pixel electrode 8 disposed in each subpixel and a second connection electrode 32 disposed in the third subpixel. FIG. 9B is a cross-sectional view taken along the AA direction in FIG. 9A, and FIG. 9C is a cross-sectional view taken along the BB direction in FIG. 9A. In an exemplary embodiment, in each subpixel, the pixel electrode 8 is a slit electrode and is connected to the drain electrode 15 of the corresponding subpixel by a first through-hole K1. In the third subpixel, one end of the second connection electrode 32 is connected to the first connection electrode 31 by a second through-hole K2, and the other end is connected to the common electrode line 5 of the next display row by a third through-hole K3, thereby realizing interconnection of the common electrodes 9 in each third subpixel in the display column direction. In an exemplary embodiment, in each display row, the pixel electrodes 8 of the first and second subpixels have the same shape and size, while the pixel electrode 8 of the third subpixel is different from those of the first and second subpixels. The pixel electrodes 8 of the first subpixel in the kth display row are different from those of the first subpixel in the k+1th display row, the pixel electrodes 8 of the second subpixel in the kth display row are different from those of the second subpixel in the k+1th display row, and the pixel electrodes 8 of the third subpixel in the kth display row are different from those of the third subpixel in the k+1th display row. In an exemplary embodiment, the common electrodes 9 of each third subpixel are interconnected via the second common electrode protrusion, the first connecting electrode 31, the second connecting electrode 32, and the common electrode line 5 in the display column direction, and the common electrodes 9 of each subpixel are interconnected via the common electrode line 5 in the display row direction, thereby realizing the interconnection of the common electrodes 9 of all subpixels, so that the common electrodes 9 of all subpixels have the same potential and improving the display effect of the display panel.

[0095] In an exemplary embodiment, the first base substrate may be a glass base substrate, a quartz base substrate, or a plastic base substrate. The first and second metal thin films may be made of metal materials and deposited by magnetron sputtering. The metal materials may include one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They may have a single-layer structure or a multilayer composite structure, such as Ti / Al / Ti. The first and second insulating thin films may be made of one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). They may have a single-layer structure or a multilayer composite structure and are deposited by chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD). The first insulating layer is referred to as a gate insulating (GI) layer, and the second insulating layer is referred to as a passivation (PVX) layer. The first transparent conductive thin film and the second transparent conductive thin film may be made of indium tin oxide (ITO) or indium zinc oxide (IZO). The semiconductor thin film may be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, polythiophene, etc. That is, the embodiments of the present disclosure are applicable to transistors fabricated based on oxide technology, silicon technology, or organic technology.

[0096] In this way, the array substrate is fabricated, and the gate electrode 11, active layer 13, source electrode 14, and drain electrode 15 in each subpixel form a thin film transistor, the common electrode 9 in each subpixel is a plate electrode, and the pixel electrode 8 is a slit electrode. The common electrode 9 is configured to provide a common voltage, and the pixel electrode 8 is configured to provide a pixel voltage for display, and a multi-dimensional electric field generated between the slit electrode and the plate electrode deflects the liquid crystal. In a display row, the common electrodes 9 in the first, second, and third subpixels are interconnected by the same common electrode line 5, and in a display column, the common electrode 9 in the kth display row and the common electrode 9 in the k+1th display row are interconnected by a first connecting electrode 31 and a second connecting electrode 32.

[0097] In some possible implementations, the first conductive layer pattern may include a pixel electrode, the second conductive layer pattern may include a common electrode, the pixel electrode is a plate electrode, and the common electrode is a slit electrode. In some possible implementations, the manufacturing method of the array substrate may further include forming a planar layer and an alignment film, and performing processing such as alignment on the alignment film.

[0098] 2. Part 1: Fabrication of color filter substrate 10A to 11C show a manufacturing process of a color filter substrate, illustrating the structure of six filter units in two display rows and three display columns on the color filter substrate. In an exemplary embodiment, the kth display row may be an odd-numbered row, and the k+1th display row may be an even-numbered row. Each display row includes a first filter unit, a second filter unit, and a third filter unit, which correspond to the first sub-pixel, the second sub-pixel, and the third sub-pixel of the array substrate, respectively. In an exemplary embodiment, the first filter unit may be a red filter unit, the second filter unit may be a green filter unit, and the third filter unit may be a blue filter unit.

[0099] (1) Forming a black matrix pattern. In an exemplary embodiment, forming a black matrix pattern may include coating a black matrix thin film on the second base substrate 20, exposing the black matrix thin film with a mask plate, and forming a black matrix 21 pattern on the second base substrate 20 after development, as shown in Figures 10A, 10B, and 10C. Figure 10B is a cross-sectional view taken along the CC direction in Figure 10A, and Figure 10C is a cross-sectional view taken along the DD direction in Figure 10A.

[0100] In an exemplary embodiment, the black matrix 21 pattern on the color filter substrate includes shielding rows 211 extending in the gate line extending direction X and shielding columns 212 extending in the data line extending direction Y, and the shielding rows 211 and the shielding columns 212 intersect with each other to form a plurality of opening regions, which correspond to the positions of the plurality of pixel electrodes 8 on the array substrate. Common electrode wire 5 , corresponding to the positions of the thin film transistors, the shielding row 211 is arranged to shield the gate lines, common electrode lines and thin film transistors on the array substrate, the position of the shielding column 212 corresponds to the positions of the first and second data lines on the array substrate, and the shielding column 212 is arranged to shield the first and second data lines on the array substrate.

[0101] In an exemplary embodiment, in the vertical direction Y, the masking row 211 located between the filter unit of the kth display row and the filter unit of the k+1th display row has a first width, and the masking row 211 located between the filter unit of the k+1th display row and the filter unit of the k+2th display row has a second width, and the first width is not equal to the second width. In the embodiment of the present disclosure, the vertical direction Y is a direction parallel to the data lines.

[0102] In an exemplary embodiment, the masking row 211 located between the filter unit of the kth display row and the filter unit of the k+1th display row includes an upper edge located within the kth display row and a lower edge located within the k+1th display row, The upper edge located within the kth display row includes a first upper edge 101 located within the first filter unit of the kth display row, a second upper edge 201 located within the second filter unit of the kth display row, and a third upper edge 301 located within the third filter unit of the kth display row.

[0103] In the exemplary embodiment, the bottom edges located in the k+1th display row include a first bottom edge 102 located in the first filter unit of the k+1th display row, a second bottom edge 202 located in the second filter unit of the k+1th display row, and a third bottom edge 302 located in the third filter unit of the k+1th display row. The distance between the first top edge 101 and the first bottom edge 102 is a first distance L1, the distance between the second top edge 201 and the second bottom edge 202 is a second distance L2, and the distance between the third top edge 301 and the third bottom edge 302 is a third distance L3.

[0104] In the exemplary embodiment, the masking row 211 located between the filter unit of the k+1th display row and the filter unit of the k+2th display row includes an upper edge located within the k+1th display row and a lower edge located within the k+2th display row. The upper edge located within the k+1th display row includes a fourth upper edge 401 located within the first filter unit of the k+1th display row, a fifth upper edge 501 located within the second filter unit of the k+1th display row, and a sixth upper edge 601 located within the third filter unit of the k+1th display row. The lower edge located within the k+2th display row includes a fourth lower edge 402 located within the first filter unit of the k+2th display row, a fifth lower edge 502 located within the second filter unit of the k+2th display row, and a sixth lower edge 602 located within the third filter unit of the k+2th display row. The distance between the fourth upper edge 401 and the fourth lower edge 402 is a fourth distance L4, the distance between the fifth upper edge 501 and the fifth lower edge 502 is a fifth distance L5, and the distance between the sixth upper edge 601 and the sixth lower edge 602 is a sixth distance L6.

[0105] In an exemplary embodiment, the first width not being equal to the second width includes one or more of: the first distance L1 being less than the fourth distance L4; the second distance L2 being less than the fifth distance L5; and the third distance L3 being greater than the sixth distance L6.

[0106] In an exemplary embodiment, the difference between the first distance L1 and the fourth distance L4 is approximately 10 μm to 20 μm, the difference between the second distance L2 and the fifth distance L5 is approximately 10 μm to 20 μm, and the difference between the third distance L3 and the sixth distance L6 is approximately 1 μm to 5 μm. In some possible implementations, the difference between the first distance L1 and the fourth distance L4 is approximately 13 μm to 15 μm, the difference between the second distance L2 and the fifth distance L5 is approximately 13 μm to 15 μm, and the difference between the third distance L3 and the sixth distance L6 is approximately 2.5 μm to 3.5 μm.

[0107] In the exemplary embodiment, the third distance L3 is greater than the first distance L1, the third distance L3 is greater than the second distance L2, and the first distance L1 is equal to the second distance L2.

[0108] In some possible implementations, the difference between the third distance L3 and the first distance L1 is about 10 μm to 35 μm, and the difference between the third distance L3 and the second distance L2 is about 10 μm to 35 μm.

[0109] In the exemplary embodiment, the sixth distance L6 is greater than the fourth distance L4, the sixth distance L6 is greater than the fifth distance L5, and the fourth distance L4 is equal to the fifth distance L5.

[0110] In some possible implementations, the difference between the sixth distance L6 and the fourth distance L4 is about 10 μm to 20 μm, and the difference between the sixth distance L6 and the fifth distance L5 is about 10 μm to 20 μm.

[0111] In the exemplary embodiment, a first protrusion 103 is disposed in a masked row located in a first filter unit of the kth display row, and a second protrusion 203 is disposed in a masked row located in a second filter unit of the kth display row. The first protrusion 103 is disposed on a first upper edge 101 and extends away from a first lower edge 102, and the second protrusion 203 is disposed on a second upper edge 201 and extends away from a second lower edge 202.

[0112] In an exemplary embodiment, the position of the first protrusion 103 corresponds to the position of the thin film transistor on the array substrate in the horizontal direction X. In the embodiment of the present disclosure, the horizontal direction X is a direction parallel to the gate line.

[0113] In an exemplary embodiment, in a plane parallel to the color filter substrate, the shape of the first protrusions 103 and the second protrusions 203 may include a rectangle or a trapezoid.

[0114] In the exemplary embodiment, the first protrusion 103 includes a first protrusion upper edge, and the second protrusion 203 includes a second protrusion upper edge, and in the vertical direction Y, the distance L7 between the first protrusion upper edge and the first upper edge 101 is about 10 μm to 20 μm, and the distance L8 between the second protrusion upper edge and the second upper edge 201 is about 10 μm to 20 μm. In the horizontal direction X, the width of the first protrusion 103 and the second protrusion 203 is 1 / 3 to 1 / 2 of the width of the filter unit in which they are located.

[0115] In an exemplary embodiment, the masking row located between the first filter unit of the kth display row and the first filter unit of the k+1th display row includes a first upper edge 101 having a first protrusion 103 disposed thereon and a first flat lower edge 102, where the first upper edge 101 and the first lower edge 102 extend in the horizontal direction X. The masking row located between the first filter unit of the k+1th display row and the first filter unit of the k+2th display row includes a fourth flat upper edge 401 and a fourth lower edge 402 having two protruding blocks disposed thereon, where the two protruding blocks are respectively disposed adjacent to the masking columns on both sides of the fourth lower edge 402. In an exemplary embodiment, the protruding blocks may be right-angled triangles, where first right-angled sides of the two right-angled triangles are respectively disposed at the fourth lower edge 402, and second right-angled sides of the two right-angled triangles are respectively disposed at the masking columns on both sides of the fourth lower edge 402.

[0116] In an exemplary embodiment, the shielding row located between the second filter unit of the kth display row and the second filter unit of the k+1th display row includes a second upper edge 201 on which the second protrusion 203 is arranged and a straight second lower edge 202, where the second upper edge 201 and the straight second lower edge 202 extend in the horizontal direction X. The shielding row located between the second filter unit of the k+1th display row and the second filter unit of the k+2th display row includes a straight fifth upper edge 501 and a fifth lower edge 502 on which two protruding blocks are arranged, where the two protruding blocks are respectively arranged at positions adjacent to the shielding columns on both sides of the fifth lower edge 502. In an exemplary embodiment, the protruding blocks may be right-angled triangles, where first right-angled sides of the two right-angled triangles are respectively arranged on the fifth lower edge 502, and second right-angled sides of the two right-angled triangles are respectively arranged on the shielding columns on both sides of the fifth lower edge 502.

[0117] In an exemplary embodiment, the occluding row located between the third filter unit of the kth display row and the third filter unit of the k+1th display row includes a flat third upper edge 301 and a flat third lower edge 302, where the third upper edge 301 and the third lower edge 302 extend in the horizontal direction X. The occluding row located between the third filter unit of the k+1th display row and the third filter unit of the k+2th display row includes a flat sixth upper edge 601 and a sixth lower edge 602 on which two protruding blocks are arranged, where the two protruding blocks are arranged at positions adjacent to the occluding columns on both sides of the sixth lower edge 602. In an exemplary embodiment, the protruding blocks may be right-angled triangles, where first right-angled sides of the two right-angled triangles are respectively arranged at the sixth lower edge 602, and second right-angled sides of the two right-angled triangles are respectively arranged in the occluding columns on both sides of the sixth lower edge 602. Taking the protruding block on the fourth lower edge as an example, if the protruding block includes one right-angled triangle, the first right-angled side of the right-angled triangle is positioned closely adjacent to the fourth lower edge, and the second right-angled side of the right-angled triangle is positioned in a shielding row adjacent to one side (left or right) of the fourth lower edge. If the protruding block includes two right-angled triangles, the first right-angled side of the first right-angled triangle is positioned closely adjacent to the fourth lower edge, and the second right-angled side of the first right-angled triangle is positioned in a shielding row adjacent to the left (or right) side of the fourth lower edge. The first right-angled side of the second right-angled triangle is positioned closely adjacent to the fourth lower edge, and the second right-angled side of the second right-angled triangle is positioned in a shielding row adjacent to the right (or left) side of the fourth lower edge.

[0118] In an exemplary embodiment, in the vertical direction Y, the distance between the third upper edge 301 and the first upper edge 101 is greater than the distance L7 between the first protrusion upper edge and the first upper edge 101, and the distance between the third upper edge 301 and the second upper edge 201 is greater than the distance L8 between the second protrusion upper edge and the second upper edge 201.

[0119] In the exemplary embodiment, for the occluded rows between the kth display row and the k+1th display row, the distance between the top edge of the first protrusion 103 and the first center line is greater than the distance between the first top edge 101 and the first center line, the distance between the top edge of the second protrusion 203 and the first center line is greater than the distance between the second top edge 201 and the first center line, the distance between the third top edge 301 and the first center line is greater than the distance between the top edge of the first protrusion 103 and the first center line, and the distance between the third top edge 301 and the first center line is greater than the distance between the top edge of the second protrusion 203 and the first center line. The distance between the third bottom edge 302 and the first center line is greater than the distance between the first bottom edge 102 and the first center line, and the distance between the third bottom edge 302 and the first center line is greater than the distance between the second bottom edge 202 and the first center line. In the embodiment of the present disclosure, the first centerline is a centerline extending in the horizontal direction X between the top edge located in the kth display row and the bottom edge located in the k+1th display row.

[0120] In some possible implementations, the distance between the upper edge of the first protrusion 103 and the first center line is equal to the distance between the upper edge of the second protrusion 203 and the first center line, the distance between the first upper edge 101 and the first center line is equal to the distance between the second upper edge 201 and the first center line, and the distance between the first lower edge 102 and the first center line is equal to the distance between the second lower edge 202 and the first center line.

[0121] In an exemplary embodiment, for an obscured row between the k+1th display row and the k+2nd display row, the distance between the sixth top edge 601 and the second center line is greater than the distance between the fourth top edge 401 and the second center line, the distance between the sixth top edge 601 and the second center line is greater than the distance between the fifth top edge 501 and the second center line, the distance between the sixth bottom edge 602 and the second center line is equal to the distance between the fourth bottom edge 402 and the second center line, and the distance between the sixth bottom edge 602 and the second center line is equal to the distance between the fifth bottom edge 502 and the second center line. In an embodiment of the present disclosure, the second center line is a center line extending in the horizontal direction X between the top edge located in the k+1th display row and the bottom edge located in the k+2nd display row.

[0122] In some possible implementations, the distance between the fourth upper edge 401 and the second centerline is equal to the distance between the fifth upper edge 501 and the second centerline.

[0123] (2) Forming a filter unit pattern. In an exemplary embodiment, forming the filter unit pattern may include sequentially forming three filter unit patterns on a second base substrate 20 on which a black matrix 21 pattern has been formed, where the three filter unit patterns include a red filter unit 23, a green filter unit 24, and a blue filter unit 25, and the three filter units are respectively disposed between the black matrices 21 and periodically arranged according to a predetermined rule, as shown in Figures 11A, 11B, and 11C. Figure 11B is a cross-sectional view taken along the CC direction in Figure 11A, and Figure 11C is a cross-sectional view taken along the DD direction in Figure 11A.

[0124] 3. Part 2 In an exemplary embodiment, the cell alignment process may include first inverting the color filter substrate so that the color filter layer of the color filter substrate faces the array substrate, as shown in FIG. 12 , then coating a sealing body on the non-display area of ​​the array substrate, drop-coating liquid crystal on the display area of ​​the array substrate, bringing the color filter substrate and the array substrate close to each other under vacuum conditions for alignment and compression bonding, and curing the frame sealant by ultraviolet curing and / or thermal curing to complete the cell alignment process and form a display panel.

[0125] In an exemplary embodiment, the shielding rows of the black matrix provide shielding for a plurality of gate lines, a plurality of common electrode lines, and a plurality of thin film transistors on the first substrate, the shielding columns of the black matrix provide shielding for a plurality of first data lines and a plurality of second data lines on the first substrate, and the plurality of opening areas formed by the intersections of the shielding rows and the shielding columns expose the plurality of pixel electrodes on the first substrate.

[0126] In an exemplary embodiment, in each subpixel on the first substrate, the connection area between the pixel electrode and the drain electrode overlaps with the black matrix, whereby the black matrix can provide shielding for the first through-hole, thereby ensuring good display quality.

[0127] In an exemplary embodiment, in each sub-pixel on the first substrate, the edge region of the pixel electrode overlaps with the black matrix, so that the black matrix can shield the edge region and ensure good display quality.

[0128] In some possible implementations, an array substrate inversion method may be adopted, the frame sealant may be coated on the array substrate or on the color filter substrate, and the liquid crystal may be drop coated on the array substrate or on the color filter substrate, and the present disclosure is not limited thereto.

[0129] In some possible implementations, the array substrate and the color filter substrate may be fabricated in other ways, and other film layers may be formed on the array substrate and the color filter substrate, and the present disclosure is not limited thereto.

[0130] In an exemplary embodiment, the thin film transistors of the subpixels in the odd rows are connected to the first data line, and the thin film transistors of the subpixels in the even rows are connected to the second data line, so that the electrode shapes of the subpixels in the odd and even rows are different, resulting in a difference in pixel aperture ratio. When forming the black matrix in the embodiment of the present disclosure, the shielding rows of the odd and even display rows are configured to have different widths, so that the pixel aperture ratios of the first subpixels in the odd and even rows are the same, the pixel aperture ratios of the second subpixels in the odd and even rows are the same, and the pixel aperture ratios of the third subpixels in the odd and even rows are the same, thereby reducing the difference between the pixel aperture ratios of the odd and even display rows and effectively avoiding horizontal stripe defects and light leakage defects in the dark state. By disposing protrusions on the shielding rows adjacent to the thin film transistors in the first and second sub-pixels of the odd display rows, the width of the shielding rows adjacent to the thin film transistors is increased, thereby effectively avoiding light leakage defects in the dark state that may occur when the array substrate and the color filter substrate are misaligned, and improving product quality.

[0131] 13 is an equivalent circuit diagram of another first substrate according to an exemplary embodiment of the present disclosure. As shown in FIG. 13, the first substrate includes M gate lines 4, M common electrode lines 5, and N pairs of data lines, each pair of data lines including a first data line 6 and a second data line 7. The gate lines 4 and the common electrode lines 5 extending horizontally and arranged in parallel define M display rows, and the first data lines 6 and the second data lines 7 extending vertically and arranged in parallel define N display columns. Thus, the M gate lines 4, the M common electrode lines 5, the N first data lines 6, and the N second data lines 7 intersect vertically to define M*N subpixels arranged in an array, where M and N are positive integers greater than or equal to 1. Each subpixel includes a thin film transistor 3 and a pixel electrode 8. The source electrode of the thin film transistor 3 is connected to the first data line 6 or the second data line 7, and the drain electrode of the thin film transistor 3 is connected to the pixel electrode 8 of the corresponding subpixel. In one display row, the gate line 4 is arranged adjacent to the next display row, and the common electrode line 5 is arranged adjacent to the previous display row. That is, the gate line 4 is arranged below the subpixels of the current display row, and the common electrode line 5 is arranged above the subpixels of the current display row. In one display column, the first data line 6 is arranged adjacent to the previous display column, and the second data line 7 is arranged adjacent to the next display column. That is, the first data line 6 is arranged to the left of the subpixels of the current display column, between the current display column and the left display column, and the second data line 7 is arranged to the right of the subpixels of the current display column, between the current display column and the right display column. The M display rows include M / 2 odd display rows and M / 2 even display rows. The thin film transistors 3 of the subpixels in the M / 2 odd display rows are connected to the second data line 7, and the thin film transistors 3 of the subpixels in the M / 2 even display rows are connected to the first data line 6.

[0132] In an exemplary embodiment, the second substrate 2 includes M*N filter units arranged in an array, the M*N filter units 22 and the M*N sub-pixels have a one-to-one correspondence between their positions, and a black matrix 21 is disposed between two adjacent filter units 22. Since the thin film transistors of the sub-pixels in the even display rows are connected to a first data line and the thin film transistors of the sub-pixels in the odd display rows are connected to a second data line, the masked row between the kth (even) display row and the k+1th (odd) display row has a first width, and the masked row between the k+1th (odd) display row and the k+2th (even) display row has a second width, and the first width may be configured not to be equal to the second width.

[0133] The first width not being equal to the second width includes one or more of: the first distance being smaller than the fourth distance; the second distance being smaller than the fifth distance; and the third distance being larger than the sixth distance.

[0134] The first distance is the distance between a first upper edge located in a first subpixel of the kth display row and a first lower edge located in a first subpixel of the k+1th display row, the second distance is the distance between a second upper edge located in a second subpixel of the kth display row and a second lower edge located in a second subpixel of the k+1th display row, the third distance is the distance between a third upper edge located in a third subpixel of the kth display row and a third lower edge located in a third subpixel of the k+1th display row, the fourth distance is the distance between a fourth upper edge located in a first subpixel of the k+1th display row and a fourth lower edge located in a first subpixel of the k+2th display row, the fifth distance is the distance between a fifth upper edge located in a second subpixel of the k+1th display row and a fifth lower edge located in a second subpixel of the k+2th display row, and the sixth distance is the distance between a sixth upper edge located in a third subpixel of the k+1th display row and a sixth lower edge located in a third subpixel of the k+2th display row.

[0135] An embodiment of the present disclosure further provides a display device, comprising the above-mentioned display panel. The display device may be a product or component having a display function, such as a mobile phone, a tablet PC, a television, a monitor, a notebook PC, a digital photo frame, or a navigation system.

[0136] Although the embodiments disclosed in the present disclosure are as described above, the description is merely an embodiment adopted for understanding the present disclosure and is not intended to limit the present disclosure. Those skilled in the art may make modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present disclosure, but the patent protection scope of the present application shall comply with the scope described in the claims.

Claims

1. a display panel comprising a first substrate and a second substrate disposed opposite to each other, the first substrate including M*N sub-pixels defined by M gate lines and N pairs of data lines intersecting each other, each pair of data lines including a first data line and a second data line, the sub-pixels including a thin film transistor and a pixel electrode, the thin film transistors of all the sub-pixels in the m-th display row being connected to the m-th gate lines, the thin film transistors of the sub-pixels in the odd-numbered display rows in the n-th display column being connected to a first data line of the n-th pair of data lines and the thin film transistors of the sub-pixels in the even-numbered display rows being connected to a second data line of the n-th pair of data lines, or the thin film transistors of the sub-pixels in the even-numbered display rows in the n-th display column being connected to the first data line of the n-th pair of data lines and the thin film transistors of the sub-pixels in the odd-numbered display rows being connected to the second data line of the n-th pair of data lines, M and N are all positive integers equal to or greater than 1, m=1, 2, ..., M, n=1, 2, ..., N; the second substrate includes M*N filter units corresponding to the sub-pixels one-to-one, a black matrix is ​​disposed between adjacent filter units, and the black matrix includes a masking row disposed between adjacent display rows and a masking column disposed between adjacent display columns; In an extension direction of the data lines, a masked row located between the kth display row and the k+1th display row has a first width, and a masked row located between the k+1th display row and the k+2th display row has a second width, the first width being not equal to the second width; The plurality of sub-pixels in the m-th display row include first, second, and third sub-pixels that are periodically arranged, and a masked row located between the k-th display row and the k+1-th display row includes an upper edge located in the k-th display row and a lower edge located in the k+1-th display row, the upper edge including a first upper edge located in a first sub-pixel of the k-th display row, a second upper edge located in a second sub-pixel of the k-th display row, and a third upper edge located in a third sub-pixel of the k-th display row, and the lower edge including a first upper edge located in a first sub-pixel of the k-th display row, a second upper edge located in a second sub-pixel of the k-th display row, and a third upper edge located in a third sub-pixel of the k-th display row. a first lower edge located in the second sub-pixel of the k+1-th display row, a second lower edge located in the second sub-pixel of the k+1-th display row, and a third lower edge located in the third sub-pixel of the k+1-th display row; a masked row located between the k+1-th display row and the k+2-th display row includes an upper edge located in the k+1-th display row and a lower edge located in the k+2-th display row, and the upper edges include a fourth upper edge located in the first sub-pixel of the k+1-th display row, a fifth upper edge located in the second sub-pixel of the k+1-th display row, and a sixth upper edge located in the third sub-pixel of the k+1-th display row. the lower edges include a fourth lower edge located in a first sub-pixel of the k+2th display row, a fifth lower edge located in a second sub-pixel of the k+2th display row, and a sixth lower edge located in a third sub-pixel of the k+2th display row; in an extending direction of the data lines, a distance between the first upper edge and the first lower edge is a first distance, a distance between the second upper edge and the second lower edge is a second distance, a distance between the third upper edge and the third lower edge is a third distance, a distance between the fourth upper edge and the fourth lower edge is a fourth distance, and a distance between the fifth upper edge and the fifth lower edge is a a fifth distance, a distance between the sixth upper edge and the sixth lower edge is a sixth distance, the first width not being equal to the second width includes the first distance being smaller than the fourth distance, the second distance being smaller than the fifth distance, and the third distance being larger than the sixth distance, the first distance, the second distance, and the third distance all being distances between the kth display row and the k+1th display row, and the fourth distance, the fifth distance, and the sixth distance all being distances between the k+1th display row and the k+2th display row.

2. a difference between the first distance and the fourth distance is 10 μm to 20 μm, a difference between the second distance and the fifth distance is 10 μm to 20 μm, and a difference between the third distance and the sixth distance is 1 μm to 5 μm; Or, The display panel of claim 1 , wherein the third distance is greater than the first distance, and the third distance is greater than the second distance.

3. 3. The display panel of claim 2, wherein the difference between the third distance and the first distance is 10 μm to 35 μm, and the difference between the third distance and the second distance is 10 μm to 35 μm.

4. The display panel of claim 1 , wherein the sixth distance is greater than the fourth distance, and the sixth distance is greater than the fifth distance.

5. 5. The display panel of claim 4, wherein the difference between the sixth distance and the fourth distance is 10 μm to 20 μm, and the difference between the sixth distance and the fifth distance is 10 μm to 20 μm.

6. 2. The display panel of claim 1, wherein a first protrusion is disposed in a masked row located in a first sub-pixel of a kth display row, the first protrusion being disposed at the first upper edge and extending in a direction away from the first lower edge; and a second protrusion is disposed in a masked row located in a second sub-pixel of the kth display row, the second protrusion being disposed at the second upper edge and extending in a direction away from the second lower edge.

7. the first protrusion is located on a side of the first sub-pixel where a thin film transistor is disposed, and the second protrusion is located on a side of the second sub-pixel where a thin film transistor is disposed, in an extension direction of the gate line; Or, The first protrusion and the second protrusion have a shape including a rectangle or a trapezoid; Or, 7. The display panel of claim 6, wherein, in the extension direction of the data line, the first protrusion includes a first protrusion upper edge, the second protrusion includes a second protrusion upper edge, the distance between the first protrusion upper edge and the first upper edge is 10 μm to 20 μm, and the distance between the second protrusion upper edge and the second upper edge is 10 μm to 20 μm.

8. 8. The display panel of claim 7, wherein in the extension direction of the data lines, the distance between the third upper edge and the first upper edge is greater than the distance between the first protrusion upper edge and the first upper edge, and the distance between the third upper edge and the second upper edge is greater than the distance between the second protrusion upper edge and the second upper edge.

9. 2. The display panel of claim 1, wherein the first, second, and third lower edges are flat, straight edges extending in the direction of the gate lines; the fourth, fifth, and sixth upper edges are flat, straight edges extending in the direction of the gate lines; and the fourth, fifth, and sixth lower edges each have a protruding block disposed at each of the fourth, fifth, and sixth lower edges, the protruding block being disposed adjacent to a shielding row on both sides of the fourth, fifth, and sixth lower edges, respectively.

10. 10. The display panel of claim 9, wherein the protruding blocks include right-angled triangles, first right-angled sides of which are respectively located at the fourth lower edge, the fifth lower edge, and the sixth lower edge, and second right-angled sides of which are respectively located at the shielding rows on both sides of the fourth lower edge, the fifth lower edge, and the sixth lower edge.

11. The first substrate includes a first conductive layer, a first metal layer, a first insulating layer, a semiconductor layer, a second metal layer, a second insulating layer, and a second conductive layer, which are stacked together, the first conductive layer includes a common electrode arranged in each subpixel, the first metal layer includes a gate line, a common electrode line, a gate electrode arranged in each subpixel, and a first connection electrode arranged in the third subpixel, the gate line is connected to the gate electrode in each subpixel, the common electrode line is connected to the common electrode in each subpixel, and the first connection electrode is connected to the common electrode of the third subpixel, the semiconductor layer includes an active layer arranged in each subpixel, and the second metal layer includes a first data line, a second data line, and a first connection electrode arranged in each subpixel.

11. The display panel of claim 1, further comprising: a source electrode and a drain electrode arranged in a pixel; in a k-th display row, the source electrode of each sub-pixel is connected to the first data line; in a k+1-th display row, the source electrode of each sub-pixel is connected to the second data line, and a conductive channel is formed between the source electrode and the drain electrode; the second conductive layer includes a pixel electrode arranged in each sub-pixel and a second connection electrode arranged in the third sub-pixel; the pixel electrode is connected to the drain electrode of the sub-pixel in which it is located via a through-hole; and the second connection electrode is connected to the first connection electrode and the common electrode line via a through-hole, respectively.

12. In the k-th display row, a first common electrode protrusion is arranged on a common electrode in the first sub-pixel, the second sub-pixel, and the third sub-pixel, and the first common electrode protrusion of each sub-pixel is located on a side of the common electrode adjacent to the k-1-th display row; a second common electrode protrusion is arranged on a common electrode in the third sub-pixel, and the second common electrode protrusion is located on a side of the common electrode adjacent to the next display row; and the first connection electrode is arranged on the second common electrode protrusion; Or, In a first spacing region between adjacent common electrode lines, the common electrode lines have a third width, and in a second spacing region between adjacent first spacing regions, the common electrode lines have a fourth width, the third width being smaller than the fourth width; in the first spacing region, the gate lines have a fifth width, and in the second spacing region, the gate lines have a sixth width, the fifth width being smaller than the sixth width; Or, the gate electrodes of the first sub-pixel, the second sub-pixel, and the third sub-pixel are all rectangular, the long sides of the gate electrodes of the first sub-pixel and the second sub-pixel extend in a display row direction, and the long side of the gate electrode of the third sub-pixel extends in a display column direction; Or, one end of the second connection electrode is connected to the first connection electrode via a through hole provided in the first insulating layer and the second insulating layer, and the other end of the second connection electrode is connected to a common electrode line of a next display row via a through hole provided in the first insulating layer and the second insulating layer; Or, 12. The display panel according to claim 11, wherein in each sub-pixel, a connection area between the pixel electrode and the drain electrode overlaps with the black matrix, and a peripheral area of ​​the pixel electrode overlaps with the black matrix.

13. 11. The display panel of claim 1, wherein the plurality of filter units in the kth display row include a first filter unit, a second filter unit, and a third filter unit that are periodically arranged, the first filter unit corresponding to the first sub-pixel, the second filter unit corresponding to the second sub-pixel, and the third filter unit corresponding to the third sub-pixel, the first filter unit including a red filter unit, the second filter unit including a green filter unit, and the third filter unit including a blue filter unit.

14. A display device comprising a display panel according to any one of claims 1 to 10.

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