wiring board

Abstract

This wiring board has an insulating layer, a via conductor, and a conductor layer. The insulating layer is made of glass ceramics. The via conductor is arranged to penetrate the insulating layer. The conductor layer is positioned along the surface of the insulating layer. The via conductor and conductor layer are connected, and both are sintered bodies of a plurality of metal particles containing copper as a main component. The average particle size of the metal particles in the via conductor is larger than the average particle size of the metal particles in the conductor layer. The via conductor and conductor layer viewed in cross section contain a metal component at 70% or more per unit area.

Description

[Technical Field]

[0001] The disclosed embodiments relate to a wiring substrate. [Background technology]

[0002] A wiring board having a ceramic insulating layer, a copper-based conductor layer, and via conductors is known. Such a wiring board can be obtained, for example, by simultaneously firing a conductor layer material and a via conductor material, which are made of copper powder with a metal oxide added, and a glass ceramic insulating layer material. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-277852 [Patent Document 2] Japanese Patent Application Publication No. 2019-207977 Summary of the Invention

[0004] A wiring board according to one aspect of the embodiment includes an insulating layer, a via conductor, and a conductor layer. The insulating layer is made of glass ceramics. The via conductor is disposed so as to penetrate the insulating layer. The conductor layer is positioned in a direction along the surface of the insulating layer. The via conductor and the conductor layer are connected to each other and are both sintered bodies of a plurality of metal particles primarily composed of copper. The average particle size of the metal particles in the via conductor is larger than the average particle size of the metal particles in the conductor layer. When viewed in cross section, the via conductor and the conductor layer contain 70% or more metal components per unit area. [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1 is a cross-sectional view showing an example of a wiring board according to an embodiment. [Figure 2] FIG. 2 is an enlarged view of area A shown in FIG. [Figure 3]FIG. 3 is an explanatory diagram showing a method for evaluating crystallites. [Figure 4] FIG. 4 is an enlarged view of region B shown in FIG. [Figure 5] FIG. 5 is an enlarged view of region C shown in FIG. [Figure 6] FIG. 6 is a cross-sectional view showing an outline of a sample according to an example. [Figure 7] FIG. 7 is a diagram showing the evaluation results of the wiring board according to the example. DETAILED DESCRIPTION OF THE INVENTION

[0006] In the above-described wiring board, for example, there may be variations in the capacitance of the capacitor formed between the conductor layers overlapping in the stacking direction of the insulating layers, leaving room for improvement. Hereinafter, the capacitor formed between the conductor layers overlapping in the stacking direction of the insulating layers may be referred to as an embedded capacitor.

[0007] Therefore, there is a need to provide a wiring board in which the capacitance of the built-in capacitors varies little.

[0008] Hereinafter, embodiments of a wiring board disclosed in the present application will be described with reference to the accompanying drawings. Note that the present disclosure is not limited to the embodiments described below.

[0009] 1 is a cross-sectional view showing an example of a wiring board according to an embodiment. As shown in Fig. 1, the wiring board 1 according to the embodiment has an insulating layer 10, via conductors 20, and a conductor layer 30.

[0010] The insulating layer 10 is made of glass ceramics. This allows the wiring board 1 to be manufactured by simultaneously firing the green sheet that is the material for the insulating layer 10 and the conductive paste containing metal particles that is the material for the via conductors 20 and the conductive layer 30.

[0011] The via conductors 20 are electrically conductive and are arranged to penetrate the insulating layer 10 .

[0012] The via conductor 20 contains copper as a main component. Specifically, the via conductor 20 contains 50 mass % or more of copper. The via conductor 20 may contain 70 mass % or more of copper.

[0013] The via conductor 20 is a sintered body of multiple metal particles mainly composed of copper. The via conductor 20 includes polygonal crystallites 2 in a cross-sectional view. The state in which the via conductor 20 includes polygonal crystallites 2 can be confirmed by analysis using an electron backscattered diffraction (EBSD) method.

[0014] FIG. 2 is an enlarged view of region A shown in FIG. 1. The via conductor 20 has a structure of a group of crystallites 2 as shown schematically in FIG. 2. In this case, adjacent crystallites 2 in the via conductor 20 may be in contact with each other along the linear sides of the crystallites 2 as grain boundaries. The via conductor 20 has a crystalline structure in which the linear sides of the crystallites 2 are in contact with each other. The crystallites 2 included in the via conductor 20 have a larger contact area with each other than when the crystallites 2 are spherical or particulate in shape. This increases the interfacial conductivity at high frequencies, thereby enabling the production of a wiring board with high interfacial conductivity at high frequencies.

[0015] Here, a method for evaluating the "linear sides" of the crystallite 2 will be described with reference to FIG. 3. FIG. 3 is an explanatory diagram showing a method for evaluating a crystallite. As shown in FIG. 3, the crystallite 2 has a polygonal cross section. For example, the crystallite 2 shown in FIG. 3 has an octagonal outline with sides S01 to S08. For an image of a via conductor 20 including such a cross section, for example, a scale (or ruler) 40 is prepared and positioned along the side S01. The length of the part of the side S01 that is along the scale (or ruler) 40 is calculated as the longest diameter d of the crystallite 2. MAXIf the length of the edge S01 is equal to or greater than 1 / 2 of the length L01, it is defined as a "straight edge". In addition, the other edges S02 to S08 are also evaluated as to whether they are "straight edges" in the same manner as edge S01. In the example shown in FIG. 3, edge S01 having a length L01 and edge S07 having a length L07 are evaluated as "straight edges". In other words, the crystallite 2 shown in FIG. 3 has two "straight edges". The longest diameter d of the crystallite 2 MAX It is preferable that the thickness is 1 μm or more and 10 μm or less.

[0016] For example, for the via conductor 20 according to the embodiment, the above-described evaluation is repeated for each side of each of the plurality of crystallites 2. In such a case, 50% or more of the plurality of crystallites 2 may have two or more straight sides. In this way, in a wiring board 1 having via conductors 20 in which 50% or more of the crystallites 2 have two or more straight sides, it is possible to reduce the decrease in interfacial conductivity at frequencies of, for example, 1 GHz to 49 GHz. This allows for an increase in interfacial conductivity at high frequencies.

[0017] In this case, wiring board 1 is cut at a location where the cross section of via conductor 20 is visible, and the cut surface is polished to prepare a sample for cross-section observation.

[0018] Next, the polished surface is analyzed using the EBSD method. The photographing range of the sample in the thickness direction and length direction of the via conductor 20 is set, for example, as follows. The number of crystallites 2 included in the photographing range is set, for example, to 50 or more and 100 or less.

[0019] The image is taken over a range of about 20 μm in the thickness and width directions of the via conductor 20. Alternatively, the range may be 10 μm or more and 20 μm or less.

[0020] Returning to FIG. 1 , further explanation will be given. The conductor layers 30 are conductive and are arranged in a predetermined pattern on the surfaces of the insulating layers 10 and between adjacent insulating layers 10. That is, in the wiring board 1, the conductor layers 30 are positioned in a direction along the surfaces of the insulating layers 10. The conductor layers 30 are positioned at a predetermined interval, sandwiching the insulating layer 10 therebetween. When two conductor layers 30 are arranged in positions sandwiching one insulating layer 10, the overlapping portion of the two conductor layers 30 arranged with one insulating layer 10 in between functions as a capacitor. In other words, in the wiring board 1, the portion that functions as a capacitor is the overlapping portion of the two conductor layers 30 sandwiching one insulating layer 10 therebetween.

[0021] The conductor layer 30 contains copper as a main component. Specifically, the conductor layer 30 contains 50 mass % or more of copper. The conductor layer 30 may contain 70 mass % or more of copper.

[0022] Similar to the via conductor 20, the conductor layer 30 is a sintered body of a plurality of metal particles containing copper as a main component. Fig. 4 is an enlarged view of region B shown in Fig. 1. The conductor layer 30 may also include crystallites 3 that are polygonal in cross section, as shown in Fig. 4.

[0023] In this case, the conductor layer 30 may include a plurality of adjacent crystallites 3 that are in contact with each other along the linear sides of the crystallites 3 as grain boundaries. 50% or more of the plurality of crystallites 3 may have two or more linear sides. This increases the interfacial conductivity at high frequencies, thereby enabling the production of a wiring board that exhibits high interfacial conductivity at high frequencies.

[0024] Furthermore, in the wiring board 1 according to the embodiment, the average particle size of the metal particles in the via conductors 20 may be larger than the average particle size of the metal particles in the conductor layer 30. Specifically, for example, by setting the ratio of the average particle size of the metal particles in the via conductors 20 to the average particle size of the metal particles in the conductor layer 30 to be 6.6:1 to 1.4:1, particularly 5:1 to 1.3:1, a high-performance wiring board 1 can be obtained. In other words, when the average particle size of the crystallites 2 contained in the conductor layer 30 is taken as 1, the average particle size of the crystallites 2 contained in the via conductors 20 should be, for example, in the range of 1.4 to 6.6 times, particularly in the range of 1.3 to 5 times.

[0025] Here, a method for determining the average grain size of the crystallites 2 contained in the via conductors 20 will be described. First, the obtained wiring substrate 1 is cut or polished to prepare a sample in which the cross section of the via conductors 20 is exposed. The cross section of the wiring substrate 1, including the cross section of the via conductors 20, is preferably finished to a mirror finish. Next, the cross section of the via conductors 20 is observed using the EBSD method, and a photograph of the cross section is taken. The following measurements are performed using the photograph. In the cross section of the via conductor 20, an area containing, for example, 20 to 30 crystallites 2 is designated. The shape of the designated area is preferably circular or rectangular. Next, image analysis is performed on each crystallite 2 present in the designated location to determine the area of ​​each crystallite 2. Next, the determined area is converted into a circle to determine the area. Next, the diameter is calculated from the converted circle area. The diameter thus determined is used as the grain size of each crystallite 2. These measurements are performed on the crystallites 2 present in the designated location to determine the average grain size. The specified location may contain not only polygonal crystallites 2 but also other, for example, spherical crystallites 2. The average grain size of the crystallites 2 in the conductor layer 30 and the connecting portion between the via conductor 20 and the conductor layer 30 is also determined by the same method. When a voltage is applied to the wiring board 1, the via conductor 20 and the conductor layer 30 become electrically connected portions.

[0026] Furthermore, the via conductors 20 and the conductor layer 30 viewed in cross section may contain 70% or more of the metal component per unit area. This allows the metal components in the via conductors 20 and the conductor layer 30 to be densified, resulting in a high-performance wiring board 1. The proportion of the metal component contained in the via conductors 20 and the conductor layer 30 can also be evaluated by observing and photographing the same locations as those in the cross-sectional photographs used to determine the average particle size of the crystallites 2 using an electron microscope. The area A1 of the voids is determined by image analysis from the photographs of the cross sections of the via conductors 20 and the conductor layer 30, and when the area of ​​the specified range is taken as the total area A0, the ratio (A0-A1) / A0 is calculated.

[0027] The via conductors 20 and the conductor layer 30 may also contain silica. The silica may have an average particle size of, for example, 10 nm or more and 30 nm or less. The silica may be contained in an amount of 0.3 parts by mass or more and 0.8 parts by mass or less per 100 parts by mass of Cu. When the via conductors 20, the conductor layer 30, and the conductor paste for forming them contain glass components other than silica, it is preferable that the silica content be less than the content of the glass components other than silica.

[0028] The via conductors 20 and the conductor layers 30 may also contain borosilicate glass. The silica may have an average particle size of 50 nm or more and 200 nm or less. The borosilicate glass may be contained in an amount of about 1 part by mass per 100 parts by mass of Cu.

[0029] Furthermore, as shown in FIG. 1, the wiring board 1 may have a connecting portion 25. The connecting portion 25 refers to the portion where the end of the via conductor 20 and the conductor layer 30 come into contact. FIG. 5 is an enlarged view of region C shown in FIG. 1. As shown in FIG. 5, the connecting portion 25 may have crystallites 4 whose grain size is smaller than the average grain size of the crystallites 2, 3 of the via conductor 20 and the conductor layer 30. This makes the connecting portion 25 denser, and improves the adhesion between the via conductor 20 and the conductor layer 30. The connecting portion 25 may have one or more such crystallites 4.

[0030] [Example] Samples Nos. 1 to 24 simulating wiring board 1 according to the embodiment were fabricated and evaluated for the deviation of the capacitor capacitance.

[0031] First, a mixture of 40 wt% alumina particles and 60 wt% borosilicate glass was prepared as the material for insulating layer 10. This mixture is a glass ceramic raw material with a firing temperature of 900°C to 1000°C. In addition, 20 parts by mass of isobutyl methacrylate resin and dibutyl phthalate per 100 parts by mass of the glass ceramic raw material was used as an organic binder, and a green sheet with a thickness of 100 μm was produced by doctor blade molding.

[0032] The raw materials for the via conductors 20 and conductor layers 30 were copper powder with different average particle sizes for each sample, silica particles with an average particle size of 20 nm, and borosilicate glass particles with an average particle size of 100 nm. The silica particles had a cumulative ratio of 70% or more between a lower limit of 10 nm and an upper limit of 30 nm. The organic binder used was isobutyl methacrylate resin and a mixed solvent of butyl carbitol acetate and dibutyl phthalate. Five parts by weight of isobutyl methacrylate resin was added to 100 parts by weight of copper powder, followed by a mixed solvent of butyl carbitol acetate and dibutyl phthalate to prepare a conductor paste containing 100 parts by weight of copper powder, 0.3 parts by weight of silica particles, and 1 part by weight of borosilicate glass particles. For samples 6, 12, 18, and 24, a conductor paste containing 100 parts by weight of copper powder and 1 part by weight of borosilicate glass particles was prepared.

[0033] Then, a roughly cylindrical conductor paste was printed so as to penetrate the prepared green sheet, and the conductor paste was printed in a predetermined area on both surfaces of the green sheet to prepare a laminate, which was then fired. The firing was carried out in a reducing atmosphere using a hydrogen-nitrogen mixed gas, with a maximum temperature of 930°C and a holding time of 2 hours. The laminate used was a 15-layer laminate consisting of two 35 μm-thick insulating layers 10 and 13 25 μm-thick insulating layers 10 stacked together.

[0034] FIG. 6 is a cross-sectional view showing an outline of a sample according to the example. The wiring board 1 used as the sample according to the example was a laminate of 15 layers, consisting of two 35 μm-thick insulating layers 10 and 13 25 μm-thick insulating layers 10. The evaluation layer, corresponding to the distance between the conductor layer 31 electrically connected to the via conductor 21 and the conductor layer 32 electrically connected to the via conductor 22, was set to 25 μm. A predetermined voltage was applied between the via conductor 21 and the via conductor 22, and the capacitance (capacitor capacitance) between the conductor layers 31 and 32 was measured. This measurement was performed at 30 locations, and the deviation (coefficient of variation 3CV: 3 × standard deviation (σ) / average value (x)) was calculated. The results are shown in FIG. 7.

[0035] Figure 7 shows the evaluation results of the wiring board according to the example. Figure 7 shows the average particle size (raw material particle size) of the copper powder used as the raw material for via conductor 20 and conductor layer 30, the ratio of the average particle size (particle size ratio) of the copper powder used as the raw material for via conductor 20 and conductor layer 30, the presence or absence of silica particles in the conductor paste, the content of metal components per unit area (area ratio of metal components) in cross-sectional views of via conductor 20 and conductor layer 30, a comparison of the average particle size of crystallites in via conductor 20 and conductor layer 30, and the deviation of capacitor capacitance (3CV). When analyzed using EBSD, the average particle size of the crystallites was found to be equivalent to the raw material particle size, except for sample No. 19.

[0036] 7, the wiring boards according to Samples 1 to 4, 7 to 10, 13 to 17, and 20 to 23 had high performance and a small 3CV of 7 or less. In particular, the wiring boards according to Samples 1 to 3, 7 to 10, 14 to 17, and 21 to 23 had high performance and a small 3CV of 5 or less.

[0037] On the other hand, the wiring boards of Samples Nos. 5 and 11 had a 3CV exceeding 7, resulting in poor performance. One reason for this is thought to be that the raw material particle size in via conductor 20 was equal to or smaller than the raw material particle size in conductor layer 30.

[0038] Furthermore, the wiring board of sample No. 19 also had a 3CV exceeding 7, resulting in a wiring board with poor performance. This is thought to be due in part to the fact that the raw material particle size in the via conductor 20 was larger than that in the conductor layer 30, and that the average crystallite size in the via conductor 20 and the conductor layer 30 became similar due to grain growth. Because the grain size difference was large in sample No. 19, the smaller copper particles grew to a size equivalent to the larger copper particles. Furthermore, in sample No. 19, there were areas where the coverage of the conductor layer 30 was low, and the capacitance was about 30% of that of the other samples.

[0039] Furthermore, the wiring boards of Samples Nos. 6, 12, 18, and 24 also had a capacitance deviation (3 CV) of more than 7, and thus had poor performance. One reason for this is thought to be that they did not contain silica particles, which have an average particle size smaller than that of borosilicate glass particles.

[0040] Among the samples prepared, the via conductors and conductor layers to which silica particles were added all contained polygonal crystallites in the range of 50% to 80%. Furthermore, in all of these samples, crystallites with a diameter smaller than the average diameter of the crystallites in the via conductors and conductor layers were observed at the connection points where the ends of the via conductors and the conductor layers met.

[0041] Further advantages and other aspects may readily occur to those skilled in the art. Therefore, the disclosure in its broader aspects is not limited to the specific details and representative embodiments shown and described above. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. [Explanation of symbols]

[0042] 1. Wiring board 2-4 crystallites 10 Insulating layer 20 Via conductor 30 Conductor Layer

Claims

1. an insulating layer; a via conductor; a conductor layer; the insulating layer is made of glass ceramics, the via conductor is arranged to penetrate the insulating layer, the conductor layer is located in a direction along the surface of the insulating layer, the via conductor and the conductor layer are connected to each other, and each is a sintered body of a plurality of metal particles containing copper as a main component; the average particle size of the metal particles in the via conductor is larger than the average particle size of the metal particles in the conductor layer; the via conductor and the conductor layer, when viewed in cross section, contain 70% or more of a metal component per unit area; the metal particles of the via conductor and the conductor layer have a plurality of crystallites; The plurality of crystallites include polygonal crystallites having straight sides, and the sides are in contact with each other as grain boundaries. Wiring board.

2. The plurality of crystallites have two or more straight sides, and the number ratio of the crystallites per unit area is 50% or more. The wiring board according to claim 1 .

3. A connecting portion where an end of the via conductor and the conductor layer are in contact has crystallites whose grain size is smaller than the average grain size of the crystallites of the via conductor and the conductor layer. The wiring board according to claim 1 .

4. An insulating layer; a via conductor; a conductor layer; the insulating layer is made of glass ceramics, the via conductor is arranged to penetrate the insulating layer, the conductor layer is located in a direction along the surface of the insulating layer, the via conductor and the conductor layer are connected to each other, and each is a sintered body of a plurality of metal particles containing copper as a main component; the average particle size of the metal particles in the via conductor is larger than the average particle size of the metal particles in the conductor layer; the via conductor and the conductor layer, when viewed in cross section, contain 70% or more of a metal component per unit area; A connecting portion where an end of the via conductor and the conductor layer are in contact has crystallites whose grain size is smaller than the average grain size of the crystallites of the via conductor and the conductor layer. Wiring board.

5. The via conductor and the conductor layer contain silica. The wiring board according to any one of claims 1 to 4.

Images