Information processing device and control method

Abstract

To speed up access to data by the BIOS. [Solution] The information processing device comprises a processor that executes BIOS processing and a memory that temporarily stores multiple pieces of data accessed by BIOS processing, and the processor performs the following processes: storing data location information indicating the location in memory of some of the multiple pieces of data stored in the memory by BIOS processing in an area separate from the area in the memory where the multiple pieces of data are stored; and when accessing any of the multiple pieces of data stored in the memory by BIOS processing, if the data location information of the data to be accessed is not stored in the memory, the processor accesses the data by searching the multiple pieces of data stored in the memory in a predetermined order, and if the data location information of the data to be accessed is stored in the memory, the processor accesses the data based on the data location information.

Description

[Technical Field]

[0001] The present invention relates to an information processing device and a control method. [Background technology]

[0002] Conventionally, in an information processing device such as a personal computer (PC), when powered on, the BIOS (Basic Input Output System) executes a POST (Power On Self Test) process, and then executes an OS (Operating System) boot process. The POST process is a process for detecting each piece of hardware in the information processing device and initializing each piece of hardware (see, for example, Patent Document 1).

[0003] For such information processing devices, shortening the time required for computer startup is required to improve user convenience, and there is a constant demand for reducing POST time. For example, BIOS data is accessed tens of thousands of times during POST processing, so faster access is required. Conventionally, speed has been improved by copying data stored in non-volatile storage to RAM (Random Access Memory) and caching it. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-10492 Summary of the Invention [Problem to be solved by the invention]

[0005] The data accessed by the BIOS during POST processing contains multiple variables, each with its own identifier. To access a variable with a certain identifier, the BIOS searches through the multiple variables copied to RAM, searching from the top for the variable with the matching identifier. This means that accessing variables stored later in the program takes time, and the access time increases as the number of variables increases. If tens of thousands of accesses occur during POST processing, the POST time becomes longer, and the conventional method of caching data in RAM alone is insufficient to speed up access to BIOS data.

[0006] The present invention has been made in view of the above circumstances, and one of its objects is to provide an information processing device and a control method that can speed up access to data by the BIOS. [Means for solving the problem]

[0007] The present invention has been made to solve the above-mentioned problems, and an information processing device according to a first aspect of the present invention comprises a processor that executes BIOS (Basic Input Output System) processing, and a memory that temporarily stores multiple pieces of data accessed by the BIOS processing, and the processor performs the following processing: storing data location information indicating the location in the memory of some of the multiple pieces of data stored in the memory by the BIOS processing in an area separate from the area in the memory in which the multiple pieces of data are stored; and when accessing any of the multiple pieces of data stored in the memory by the BIOS processing, if the data location information of the data to be accessed is not stored in the memory, the processor accesses the multiple pieces of data stored in the memory by searching in a predetermined order, and if the data location information of the data to be accessed is stored in the memory, the processor accesses the data based on the data location information.

[0008] In the information processing device, the processor may store the data location information of the accessed data in the memory in response to accessing any of the multiple data stored in the memory through processing of the BIOS.

[0009] In the above-mentioned information processing device, each of the plurality of data is stored in the memory in association with the respective identification information of the data, and the processor may, in response to accessing any of the plurality of data, associate the identification information of the accessed data with the data location information and store them in the memory.

[0010] In the above information processing device, when the processor reads any of the plurality of data by processing the BIOS, if the data location information of the data to be read is not stored in the memory, the processor may access and read the plurality of data stored in the memory by searching in a predetermined order, and if the data location information of the data to be read is stored in the memory, the processor may access and read the data based on the data location information.

[0011] In the above information processing device, the plurality of data include first data to which writing may occur during POST (Power On Self Test) processing by the BIOS but no writing occurs after the POST processing, and second data to which writing may occur both during the POST processing and after the POST processing, and when storing the data location information in the memory, the processor may store the data location information of the first data and the data location information of the second data in a first area and a second area in the memory separately.

[0012] In the above-mentioned information processing device, when the processor writes to any of the multiple pieces of data through BIOS processing, it may invalidate the data before writing and write the data to another location in the memory, and when it accesses and writes the data based on the data location information stored in the first area or the second area, it may update the data location information based on the location of the data in the memory after writing.

[0013] In the above information processing device, when the processor accesses and writes the data based on the data location information stored in the first area, it may erase all of the data location information currently stored in the first area and then store the data location information indicating the location of the data in the memory after writing in the first area when updating the data location information; and when the processor accesses and writes the data based on the data location information stored in the second area, it may erase all of the data location information currently stored in the second area and then store the data location information indicating the location of the data in the memory after writing in the second area when updating the data location information.

[0014] In the information processing device, the processor may prohibit erasure of the data location information stored in the first area after the POST processing.

[0015] In the information processing device, the processor may be initialized to a state in which the data location information is not stored in the first area and the second area at the start of the POST process.

[0016] In the information processing device, the memory may be a volatile memory that temporarily stores a copy of BIOS data stored in a nonvolatile memory.

[0017] In addition, according to a second aspect of the present invention, a control method for an information processing device having a processor that executes BIOS (Basic Input Output System) processing and a memory that temporarily stores multiple pieces of data accessed by the BIOS processing includes the steps of: causing the processor to store data location information indicating the location in the memory of some of the multiple pieces of data stored in the memory by the BIOS processing in an area separate from the area in the memory in which the multiple pieces of data are stored; and when accessing any of the multiple pieces of data stored in the memory by the BIOS processing, if the data location information of the data to be accessed is not stored in the memory, accessing the multiple pieces of data stored in the memory by searching in a predetermined order, and if the data location information of the data to be accessed is stored in the memory, accessing the data based on the data location information. [Effects of the Invention]

[0018] According to the above aspect of the present invention, it is possible to speed up access to data by the BIOS. [Brief explanation of the drawings]

[0019] [Figure 1] FIG. 1 is a block diagram showing an example of a hardware configuration of an information processing apparatus according to an embodiment. [Figure 2] FIG. 2 is a schematic diagram illustrating the BIOS data according to the embodiment when it is loaded from ROM to RAM. [Figure 3] FIG. 10 is a schematic diagram showing an example of processing for searching for a variable at the time of access according to the embodiment. [Figure 4] FIG. 2 is a block diagram showing an example of the functional configuration of an information processing device according to the embodiment that performs data access using a predictive pointer cache. [Figure 5] FIG. 1 is a schematic diagram showing an overview of a data access method using a predictive pointer cache according to an embodiment. [Figure 6]10A and 10B are schematic diagrams showing an example of processing when a variable pointer of a variable to be read accessed is registered according to the embodiment; [Figure 7] FIG. 10 is a schematic diagram showing an example of processing when a variable pointer for a variable to be read accessed is not registered according to the embodiment. [Figure 8] FIG. 4 is a schematic diagram showing an example of write access processing during POST processing according to the embodiment. [Figure 9] FIG. 10 is a schematic diagram showing an example of control of a protection prediction pointer cache according to the embodiment. [Figure 10] FIG. 4 is a schematic diagram showing an example of a write access process after a POST process according to the embodiment. [Figure 11] FIG. 1 is a schematic diagram showing an example of speeding up data access according to an embodiment. [Figure 12] FIG. 10 is a diagram showing an example of the effect of speeding up data access according to the embodiment. [Figure 13] 10 is a flowchart showing an example of a data access process during a read access according to the embodiment. [Figure 14] 10 is a flowchart showing an example of data access processing at the time of write access during POST processing according to the embodiment. [Figure 15] 10 is a flowchart showing an example of a data access process during a write access after a POST process according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0020] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The information processing device 10 according to this embodiment is a computer device such as a clamshell (notebook) personal computer, a desktop personal computer, a tablet terminal, a smartphone, etc. First, an example of the hardware configuration of the information processing device according to this embodiment will be described with reference to FIG.

[0021] 1 is a block diagram showing an example of the hardware configuration of an information processing device 10 according to this embodiment. The information processing device 10 includes a CPU 11, a main memory 12, a video subsystem 13, a display unit 14, a chipset 21, a BIOS memory 22, a storage medium 23, an audio system 24, a WLAN card 25, a USB connector 26, an embedded controller 31, an input unit 32, a power supply circuit 33, and a battery 34.

[0022] The CPU 11 executes various arithmetic processes under program control and controls the entire information processing device 10. For example, the CPU 11 executes processes based on programs of an OS (Operating System) and a BIOS (Basic Input Output System). The CPU 11 is an example of a processor.

[0023] The main memory 12 is a volatile memory that includes, for example, RAM (Random Access Memory) and is used as a read area for the programs executed by the CPU 11 or as a work area for writing data processed by the programs. For example, the main memory 12 may be configured with multiple DRAM (Dynamic Random Access Memory) chips. The programs include an OS, various drivers for operating peripheral devices, various services / utilities, application programs, etc.

[0024] Video subsystem 13 is a subsystem for realizing functions related to image display, and includes a video controller. The video controller processes drawing commands from CPU 11, writes the processed drawing information to a video memory, and also reads the drawing information from the video memory and outputs it to display unit 14 as drawing data (display data).

[0025] The display unit 14 is, for example, a liquid crystal display or an organic EL display, and displays a display screen based on the drawing data (display data) output from the video subsystem 13.

[0026] The chipset 21 includes controllers for a Universal Serial Bus (USB), a Serial AT Attachment (Serial ATA), a Serial Peripheral Interface (SPI) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express bus, and a Low Pin Count (LPC) bus, and is connected to a plurality of devices, such as a BIOS memory 22 (described later), a storage medium 23, an audio system 24, a WLAN card 25, a USB connector 26, and an embedded controller 31.

[0027] The BIOS memory 22 includes a nonvolatile memory (nonvolatile storage) that stores BIOS data, such as a flash ROM (Read Only Memory) or an EEPROM (Electrically Erasable Programmable Read Only Memory). The BIOS memory 22 stores the BIOS, system firmware (programs) for controlling the embedded controller 31, and other components, as well as data.

[0028] The storage medium 23 includes a hard disk drive (HDD), a solid state drive (SSD), etc. For example, the storage medium 23 stores an OS, various drivers, various services / utilities, application programs, and various data.

[0029] The audio system 24 is connected to a microphone and a speaker (not shown) and records, plays back, and outputs sound data. The microphone and the speaker are built into the information processing device 10, for example.

[0030] The WLAN (Wireless Local Area Network) card 25 connects to a network via a wireless LAN to perform data communication. For example, when the WLAN card 25 receives data from the network, it generates an event trigger indicating that the data has been received. The USB connector 26 is a connector for connecting peripheral devices that use USB.

[0031] The input unit 32 collectively refers to input devices (input equipment) provided in the information processing device 10. The input unit 32 includes a keyboard, a mouse, etc. The input unit 32 outputs input information input by a user operation to the embedded controller 31.

[0032] The power supply circuit 33 includes, for example, a DC / DC converter, a charge / discharge unit, an AC / DC adapter, etc. For example, the power supply circuit 33 converts a DC voltage supplied from an external power source such as an AC adapter (not shown) or a battery 34 into a plurality of voltages required to operate the information processing device 10. The power supply circuit 33 also supplies power to each unit of the information processing device 10 based on control from the embedded controller 31.

[0033] The battery 34 is, for example, a secondary battery such as a lithium ion battery. When power is supplied to the information processing device 10 from an external power source, the battery 34 is charged via the power supply circuit 33. When power is not supplied to the information processing device 10 from an external power source, the battery 34 outputs the stored power via the power supply circuit 33 as operating power for the information processing device 10.

[0034] The embedded controller 31 is a one-chip microcomputer that monitors and controls various devices (peripheral devices, sensors, etc.) regardless of the system state of the information processing device 10. The embedded controller 31 includes a CPU, ROM, RAM, A / D input terminals for multiple channels, D / A output terminals, a timer, and digital input / output terminals (not shown). The digital input / output terminals of the embedded controller 31 are connected to an input unit 32, a power supply circuit 33, etc., and the embedded controller 31 controls the operations of these devices.

[0035] Next, the BIOS data access method will be described. BIOS data is stored in the BIOS memory 22 (ROM). At startup, this data is copied to the main memory 12 (RAM) and expanded, and the copy (cache) in RAM is accessed, which is faster than accessing the ROM.

[0036] FIG. 2 is a schematic diagram of BIOS data when it is expanded from ROM to RAM. For example, in a UEFI BIOS that employs UEFI (Unified Extensible Firmware Interface), multiple UEFI variables are stored as BIOS data. Each UEFI variable has an identifier for identifying it. The identifier may include, for example, two identifiers: a variable name and a vendor GUID (Vendor Globally Unique Identifier). In the following description, "UEFI variable" will be simply referred to as "variable."

[0037] Variables that are expanded (copied) to RAM are saved as a set of an identifier and a variable value. When accessed (read / write), the corresponding variable is searched for by the identifier. In this way, expanding BIOS data from ROM to RAM and caching it has traditionally been used to speed up access.

[0038] However, to access a variable with a certain identifier, variables with a matching identifier must be searched for one by one from the top of the RAM, which slows down access to variables stored at the back.

[0039] Figure 3 is a schematic diagram showing an example of the process of searching for variables during access (read / write). As shown in the figure, if the variable to be accessed (read / write) is stored at the end of the RAM, it must be searched one by one from the beginning, which increases the access time (for example, in the current POST process, it takes up to 60 μs). As the number of variables increases, the access time also increases. In addition, when tens of thousands of accesses occur, as in the current POST process, the overall POST process time increases depending on the number of accesses, so there is a demand for further speed improvements.

[0040] Therefore, in this embodiment, a predictive pointer cache is used to directly access variables (cache) expanded in RAM, thereby achieving high speed. The predictive pointer cache is data in which address (offset) information (hereinafter referred to as "variable pointer") indicating the position in RAM of a variable that is predicted to be accessed is registered, and is stored in an area in RAM separate from the area in which multiple variable data are stored.

[0041] 4 is a block diagram showing an example of a functional configuration in which an information processing device 10 according to this embodiment accesses data using a predictive pointer cache. The information processing device 10 includes a processing unit 100 and a RAM 110. The processing unit 100 has a functional configuration in which a processor such as a CPU 11 executes BIOS processing based on a BIOS program. The RAM 110 is a volatile memory such as the main memory 12, to which BIOS data is copied at startup and expanded as cache data. The processing unit 100 accesses the cache data expanded in the RAM 110 using the predictive pointer cache.

[0042] (Data access method overview) 5 is a schematic diagram showing an overview of a data access method using a predictive pointer cache according to this embodiment. Some variables require write protection to prevent writing, while others do not require write protection. Therefore, the predictive pointer cache is divided into a protection predictive pointer cache that registers variable pointers for variables that require write protection, and a general-use predictive pointer cache that registers variable pointers for variables that do not require write protection, and these are stored in different areas within the RAM 110.

[0043] A variable that needs to be write-protected is a variable that may be written to during the BIOS POST (Power On Self Test) process, but that will not be written to after the POST process (during runtime). To protect the BIOS data configuration (settings), variable pointers of variables that are restricted from being written to and cannot be changed after the POST process (during runtime) are registered in a protective predicted pointer cache. The protective predicted pointer cache is maintained after the POST process (during runtime). On the other hand, a variable that does not need to be write-protected is a variable that may be written to both during and after the POST process.

[0044] When the processing unit 100 accesses (reads / writes) a variable (cache) expanded in RAM 110, if the variable pointer of the corresponding variable is not registered in the prediction pointer cache, it accesses it by searching the multiple variables stored in RAM 110 in order from the beginning (see Figure 3).

[0045] On the other hand, when the processing unit 100 accesses (reads / writes) a variable (cache) expanded in the RAM 110, if the variable pointer of the corresponding variable is registered in the prediction pointer cache (protected or general), the processing unit 100 directly accesses the variable at the address indicated by the variable pointer. As a result, if the variable to be accessed is a variable whose variable pointer is registered in the prediction pointer cache, the time required to search the RAM 110 from the beginning is eliminated, thereby shortening the access time.

[0046] Next, the processes at the time of read access and write access will be described in detail for the data access using the predictive pointer cache described with reference to FIG.

[0047] (read access) First, read access will be described. 6 and 7 are schematic diagrams showing an example of read access using a predictive pointer cache according to this embodiment. During read access, no writing occurs during or after POST processing, and the handling of the predictive pointer cache is the same for protection and general use. Therefore, in these Figures 6 and 7, the predictive pointer cache is illustrated without distinguishing between protection and general use. Although there is no distinction between protection and general use, variable pointers that need to be write-protected after POST processing (during runtime) are registered in the protection predictive pointer cache, and variable pointers that do not need to be write-protected either during or after POST processing (during runtime) are registered in the general predictive pointer cache.

[0048] 6 is a schematic diagram showing an example of processing when a variable pointer of a variable to be read-accessed is registered. When performing read access to a variable expanded in RAM 110, the processing unit 100 checks all variable pointers registered in both the protection and general prediction pointer caches using the identifier of the variable (the variable to be read-accessed). If a variable pointer matching the identifier of the variable is registered in the prediction pointer cache, the processing unit 100 accesses the address indicated by the matching variable pointer and reads the value (data) of the variable.

[0049] 7 is a schematic diagram showing an example of processing when a variable pointer for a variable to be read accessed is not registered. When performing read access to a variable expanded in RAM 110, the processing unit 100 checks all variable pointers registered in both the protection and general prediction pointer caches using the identifier of the variable (the variable to be read accessed). If a variable pointer matching the identifier of the variable is not registered in the prediction pointer cache, the processing unit 100 accesses the multiple variables stored in RAM 110 by searching sequentially from the top, and reads the value (data) of the variable with the matching identifier.

[0050] Furthermore, the processing unit 100 registers the variable pointer of the accessed variable in a prediction pointer cache in the RAM 110. For example, if the accessed variable is a variable that needs to be write-protected, the processing unit 100 registers the variable pointer in a protection prediction pointer cache, and if the accessed variable is a variable that does not need to be write-protected, the processing unit 100 registers the variable pointer in a general prediction pointer cache.

[0051] (Write access during POST processing) Next, write access during POST processing will be described. FIG. 8 is a schematic diagram showing an example of write access processing during POST processing. During write access during POST processing, there are no variables that are write-protected, so the handling of the protection and general-use predictive pointer caches is the same. For this reason, FIG. 8 illustrates the protection and general-use predictive pointer caches without distinguishing between protection and general-use. Although there is no distinction between protection and general-use, variable pointers of variables that need to be write-protected after POST processing (during Runtime) are registered in the protection predictive pointer cache, and variable pointers of variables that do not need to be write-protected either during POST processing or after POST processing (during Runtime) are registered in the general-use predictive pointer cache.

[0052] When the processing unit 100 performs a write access to a variable expanded in the RAM 110, it checks all variable pointers registered in both the protection and general prediction pointer caches using the identifier of the variable (the variable to be write-accessed). If a variable pointer matching the identifier of the variable is registered in the prediction pointer cache, the processing unit 100 accesses the address indicated by the matching variable pointer, writes a value (data) to the variable, writes it back to the BIOS memory 22 (non-volatile storage), and synchronizes (updates) the data stored in the BIOS memory 22.

[0053] Although not shown in the figure, if a variable pointer matching the identifier of the variable in question is not registered in the predicted pointer cache, the processing unit 100 searches the multiple variables stored in the RAM 110 sequentially from the beginning, similar to the read access shown in Fig. 7. Then, by searching sequentially from the beginning, the processing unit 100 accesses the variable in question with the matching identifier, writes a value (data), writes it back to the BIOS memory 22 (non-volatile storage), and synchronizes (updates) the data stored in the BIOS memory 22.

[0054] Furthermore, the processing unit 100 registers the variable pointer of the accessed variable in a prediction pointer cache in the RAM 110. For example, if the accessed variable is a variable that needs to be write-protected, the processing unit 100 registers the variable pointer in a protection prediction pointer cache, and if the accessed variable is a variable that does not need to be write-protected, the processing unit 100 registers the variable pointer in a general prediction pointer cache.

[0055] Here, when data is written during a write access, the address of the corresponding variable (the written variable) changes. Specifically, during a write access, the processing unit 100 invalidates the variable before writing and writes the corresponding variable to a different address in the RAM 110. Therefore, when registering the variable pointer of the corresponding variable into which data has been written, the processing unit 100 flushes (erases) the prediction pointer cache on the registration side, regardless of whether the variable pointer is registered in a protection or general prediction pointer cache, and then registers the variable pointer indicating the address after writing. The prediction pointer cache shown in this figure shows a flushed (erased) state (NULL) due to the writing of data. After that, the variable pointer is registered.

[0056] (Protection prediction pointer cache switching) Next, switching of the protection prediction pointer cache will be described. 9 is a schematic diagram showing an example of control of a protection prediction pointer cache. Variables that need to be write-protected are also written to during POST processing. Therefore, when a variable is written to by a write access during POST processing, both the protection prediction pointer cache and the general-use prediction pointer cache are flushed (erased) before the variable pointer is registered.

[0057] On the other hand, after the POST process (during runtime), writing to variables that need to be write-protected is restricted, and no changes are made to the protective prediction pointer cache. For example, to protect the BIOS data configuration (settings), writing is restricted and no changes are made to the protective prediction pointer cache after the POST process (during runtime). For example, the processing unit 100 may prohibit flushing (erasing) of the protective prediction pointer cache by using the "UEFI Exit Boot Service" that is executed when BIOS boot is terminated as a trigger. This allows the processing unit 100 to use the variable pointers registered in the protective prediction pointer cache even when accessing after the POST process (during runtime).

[0058] (Write access after POST processing) Next, a write access after the POST process to which the switching control of the protection prediction pointer cache described above is applied will be described. Note that, if the write request is to a variable that needs to be write-protected, the processing unit 100 does not process the write access and returns an error. FIG. 10 is a schematic diagram showing an example of processing of a write access to a variable that does not need to be write-protected after the POST processing (during runtime).

[0059] When the processing unit 100 performs a write access to a variable expanded in the RAM 110, it checks all variable pointers registered in both general prediction pointer caches using the identifier of the variable (the variable to be write-accessed). If a variable pointer matching the identifier of the variable is registered in the prediction pointer cache, the processing unit 100 accesses the address indicated by the matching variable pointer and writes a value (data) to the variable.

[0060] Although not shown, if a variable pointer matching the identifier of the variable is not registered in the prediction pointer cache, the processing unit 100 searches the multiple variables stored in the RAM 110 sequentially from the beginning, similar to the read access shown in Fig. 7. Then, by searching sequentially from the beginning, the processing unit 100 accesses the variable with the matching identifier and writes a value (data).

[0061] Furthermore, the processing unit 100 registers the variable pointer of the accessed variable in a prediction pointer cache in the RAM 110. At this time, the processing unit 100 registers the variable pointer in the general prediction pointer cache (after flushing), but the protection prediction pointer cache is maintained.

[0062] (Example of speeding up data access) Next, an example will be described in which the data access method using the predictive pointer cache described with reference to FIGS. 5 to 10 speeds up access to data.

[0063] FIG. 11 is a schematic diagram showing an example of speeding up data access according to this embodiment. In this diagram, the processing unit 100 shows a series of processes when changing the value (data) of a variable, reading the value (data) of the variable and writing the modified value to the variable. For example, if the processing unit 100 registers the variable pointer of the variable accessed during a read access in the predictive pointer cache, when writing the modified value, the registered variable pointer can be used to directly access the address indicated by the variable pointer without searching from the beginning. When changing the value (data) of a variable, the process of reading the variable and writing to that variable is performed each time, thereby reducing access time.

[0064] Although FIG. 11 shows an example of a process in which a variable is read and written to, the access time can also be reduced by using the registered variable pointer when a read variable is read again.

[0065] 12 is a diagram showing an example of the effect of speeding up data access according to this embodiment. In an experiment in which a predictive pointer cache capable of registering three variable pointers each for protection and general use for approximately 500 variables was provided and variable pointers of matching variables were registered, there were 20,259 matches between the variable pointers out of a total of 34,256 accesses, resulting in a reduction of approximately 600 ms.

[0066] (Data access processing using predictive pointer cache) Next, a description will be given of the operation of the processing in which the processing unit 100 accesses the variable (cache data) expanded in the RAM 110 using the predictive pointer cache through BIOS processing. Fig. 13 is a flowchart showing an example of data access processing during read access according to this embodiment.

[0067] (Step S101) The processing unit 100 checks the identifier of the variable to be read-accessed against the identifier of the variable pointer registered in the prediction pointer cache, and then proceeds to the processing of step S103.

[0068] (Step S103) The processing unit 100 determines whether or not the variable pointer of the variable to be read-accessed is registered in the prediction pointer cache based on the collation result in step S101. If the processing unit 100 determines that the variable pointer of the variable to be read-accessed is registered in the prediction pointer cache (step S103: YES), the processing unit 100 proceeds to the processing of step S105. On the other hand, if the processing unit 100 determines that the variable pointer of the variable to be read-accessed is not registered in the prediction pointer cache (step S103: NO), the processing unit 100 proceeds to the processing of step S107.

[0069] (Step S105) The processing unit 100 accesses the variable (the variable to be read-accessed) using the variable pointer determined to be registered in step S103, and reads (reads) the value (data) of the variable. This ends the read access process.

[0070] (Step S107) The processing unit 100 accesses the multiple variables stored in the RAM 110 by searching them sequentially from the top, and reads (reads) the value (data) of the corresponding variable (variable to be read-accessed) whose identifier matches. Then, the processing proceeds to step S109.

[0071] (Step S109) The processing unit 100 determines whether the variable read-accessed in step S107 is a variable that needs to be write-protected. Here, a variable that needs to be write-protected is a variable that needs to be write-protected after the POST process (during runtime). If the processing unit 100 determines that the variable needs to be write-protected (step S109: YES), the processing proceeds to step S111. On the other hand, if the processing unit 100 determines that the variable does not need to be write-protected (step S109: NO), the processing proceeds to step S113.

[0072] (Step S111) The processing unit 100 registers the variable pointer of the variable read-accessed in step S107 in the protection prediction pointer cache, and ends the read access process.

[0073] (Step S113) The processing unit 100 registers the variable pointer of the variable read-accessed in step S107 in the general-use prediction pointer cache, and ends the read access process.

[0074] FIG. 14 is a flowchart showing an example of data access processing at the time of write access during POST processing according to this embodiment.

[0075] (Step S201) The processing unit 100 checks the identifier of the variable to be write-accessed against the identifier of the variable pointer registered in the prediction pointer cache, and then proceeds to the processing of step S203.

[0076] (Step S203) The processing unit 100 determines whether or not the variable pointer of the variable to be write-accessed is registered in the prediction pointer cache based on the collation result in step S201. If the processing unit 100 determines that the variable pointer of the variable to be write-accessed is registered in the prediction pointer cache (step S203: YES), the processing unit 100 proceeds to the processing of step S205. On the other hand, if the processing unit 100 determines that the variable pointer of the variable to be write-accessed is not registered in the prediction pointer cache (step S203: NO), the processing unit 100 proceeds to the processing of step S207.

[0077] (Step S205) The processing unit 100 accesses the variable (the variable to be write-accessed) using the variable pointer determined to be registered in step S203, and writes (writes) a value (data) to the variable. Specifically, the processing unit 100 invalidates the variable before writing, writes the variable to another address in RAM 110, writes it back to the BIOS memory 22 (non-volatile storage), and synchronizes (updates) the data stored in the BIOS memory 22. This ends the write access process.

[0078] (Step S207) The processing unit 100 accesses the multiple variables stored in the RAM 110 by searching them sequentially from the top, and writes a value (data) to the variable with a matching identifier (the variable to be write-accessed). Specifically, the processing unit 100 invalidates the variable before writing, and writes the variable to another address in the RAM 110. Then, the processing proceeds to step S209.

[0079] (Step S209) The processing unit 100 determines whether the variable write-accessed in step S207 is a variable that needs to be write-protected. Here, a variable that needs to be write-protected is a variable that needs to be write-protected after the POST process (during runtime). If the processing unit 100 determines that the variable needs to be write-protected (step S209: YES), the processing proceeds to step S211. On the other hand, if the processing unit 100 determines that the variable does not need to be write-protected (step S209: NO), the processing proceeds to step S213.

[0080] (Step S211) The processing unit 100 registers a variable pointer indicating the address after writing of the variable write-accessed in step S207. Specifically, the processing unit 100 flushes (deletes) the protection prediction pointer cache, then registers the variable pointer, and ends the write access process.

[0081] (Step S113) The processing unit 100 registers a variable pointer indicating the address after writing of the variable write-accessed in step S207. Specifically, the processing unit 100 flushes (erases) the general-use prediction pointer cache, then registers the variable pointer and ends the write access process.

[0082] FIG. 15 is a flowchart showing an example of data access processing at the time of write access after POST processing (during runtime) according to this embodiment.

[0083] (Step S300) The processing unit 100 determines whether the request is to write to a variable that needs to be write-protected. If the processing unit 100 determines that the request is to write to a variable that needs to be write-protected (YES), it returns an error and ends the process. On the other hand, if the processing unit 100 determines that the request is to write to a variable that does not need to be write-protected (NO), it proceeds to the process of step S301.

[0084] (Step S301) The processing unit 100 checks the identifier of the variable to be write-accessed against the identifier of the variable pointer registered in the prediction pointer cache, and then proceeds to the processing of step S303.

[0085] (Step S303) The processing unit 100 determines whether or not the variable pointer of the variable to be write-accessed is registered in the prediction pointer cache based on the collation result in step S301. If the processing unit 100 determines that the variable pointer of the variable to be write-accessed is registered in the prediction pointer cache (step S303: YES), the processing unit 100 proceeds to the processing of step S305. On the other hand, if the processing unit 100 determines that the variable pointer of the variable to be write-accessed is not registered in the prediction pointer cache (step S303: NO), the processing unit 100 proceeds to the processing of step S307.

[0086] (Step S305) The processing unit 100 accesses the variable (the variable to be write-accessed) using the variable pointer determined to be registered in step S303, and writes (writes) a value (data) to the variable. Specifically, the processing unit 100 invalidates the variable before writing, writes the variable to another address in RAM 110, writes it back to the BIOS memory 22 (non-volatile storage), and synchronizes (updates) the data stored in the BIOS memory 22. This ends the write access process.

[0087] (Step S307) The processing unit 100 accesses the multiple variables stored in the RAM 110 by searching them sequentially from the top, and writes (writes) a value (data) to the variable with a matching identifier (the variable to be write-accessed). Specifically, the processing unit 100 invalidates the variable before writing, writes the variable to another address in the RAM 110, writes it back to the BIOS memory 22 (non-volatile storage), and synchronizes (updates) the data stored in the BIOS memory 22. Then, the processing proceeds to step S309.

[0088] (Step S309) The processing unit 100 registers the variable pointer of the variable write-accessed in step S307. Specifically, the processing unit 100 flushes (erases) the general-use prediction pointer cache, then registers the variable pointer indicating the address after writing, and ends the write access process. Note that the processing unit 100 holds the protection prediction pointer cache after the POST process (during runtime).

[0089] As described above, the information processing device 10 according to this embodiment includes a processing unit 100 (e.g., a processor such as the CPU 11) that executes BIOS processing, and a RAM 110 (e.g., a memory such as the main memory 12) that temporarily stores multiple pieces of data accessed by the BIOS processing. The processing unit 100 performs processing to store variable pointers (data location information) that indicate addresses (locations) in the RAM 110 of some of the multiple variables (examples of data) stored in the RAM 110 by the BIOS processing in an area (e.g., a predicted pointer cache) separate from the area in the RAM 110 where the multiple variables are stored. Furthermore, when accessing one of the multiple variables stored in the RAM 110 by the BIOS processing, if the variable pointer of the variable to be accessed is not stored in the RAM 110, the processing unit 100 accesses the variable by searching the multiple variables stored in the RAM 110 in a predetermined order, and if the variable pointer of the variable to be accessed is stored in the RAM 110, the processing unit 100 accesses the variable based on the variable pointer.

[0090] This allows the information processing device 10 to directly access the variables (data) expanded in RAM 110 using the variable pointers registered in the predicted pointer cache, thereby speeding up access to data by the BIOS.

[0091] For example, when the processing unit 100 accesses one of a plurality of variables stored in the RAM 110 through BIOS processing, the processing unit 100 registers (stores) in the RAM 110 a variable pointer of the accessed variable.

[0092] As a result, when the information processing device 10 accesses a variable that it has already accessed, it can access it directly using the variable pointer registered in the predicted pointer cache, thereby speeding up access to data by the BIOS.

[0093] Each of the multiple variables is associated with its respective identifier (identification information) and stored in RAM 110. Then, in response to accessing any of the multiple variables, processing unit 100 associates the identifier of the accessed variable with a variable pointer and registers (stores) them in RAM 110.

[0094] This allows the information processing device 10 to use the variable pointer by checking the identifier when accessing the variable.

[0095] Furthermore, when the processing unit 100 reads one of a plurality of variables through BIOS processing, if the variable pointer of the variable to be read is not stored in RAM 110, it accesses and reads the variable by searching the plurality of variables stored in RAM 110 in a predetermined order (for example, from the beginning), and if the variable pointer of the variable to be read is stored in RAM 110, it accesses and reads the variable based on the variable pointer.

[0096] This allows the information processing device 10 to directly access and read the variables (data) expanded in RAM 110 using the variable pointers registered in the predicted pointer cache, thereby speeding up access to data by the BIOS.

[0097] The multiple variables include variables (first data) that may be written during POST processing by the BIOS but not after the POST processing (during Runtime), and variables (second data) that may be written both during and after the POST processing (during Runtime). Here, the variables that may be written during POST processing by the BIOS but not after the POST processing (during Runtime) correspond to variables that need to be write-protected. Furthermore, the variables that may be written both during and after the POST processing (during Runtime) correspond to variables that do not need to be write-protected. When storing variable pointers in the RAM 110, the processing unit 100 registers (stores) the variable pointers of variables that need to be write-protected and the variable pointers of variables that do not need to be write-protected in a protection prediction pointer cache (first area) and a general-use prediction pointer cache (second area) of the RAM 110, respectively.

[0098] This allows the information processing device 10 to retain and use the variable pointer of the variable that needs to be write-protected after the POST process (during runtime).

[0099] Furthermore, when the processing unit 100 writes to one of a plurality of variables through BIOS processing, it invalidates the variable before writing and writes the variable to another address (location) in the RAM 110. When the processing unit 100 accesses and writes to a variable based on a variable pointer stored in a protection prediction pointer cache or a general prediction pointer cache, it updates the variable pointer based on the address (location) in the RAM 110 of the variable after writing.

[0100] As a result, when the information processing device 10 writes to a variable by write access, the variable pointer changes, so the variable pointer stored in the prediction pointer cache can be appropriately updated and used during subsequent accesses.

[0101] When the processing unit 100 accesses and writes to a variable based on a variable pointer stored in the protection prediction pointer cache, it erases all of the variable pointers currently stored in the protection prediction pointer cache when updating the variable pointer, and then stores in the protection prediction pointer cache a variable pointer indicating the address (position) of the variable in RAM 110 after writing. Also, when the processing unit 100 accesses and writes to a variable based on a variable pointer stored in the general prediction pointer cache, it erases all of the variable pointers currently stored in the general prediction pointer cache when updating the variable pointer, and then stores in the general prediction pointer cache a variable pointer indicating the address (position) of the variable in RAM 110 after writing.

[0102] This allows the information processing device 10 to easily and quickly update the variable pointers stored in the predictive pointer cache.

[0103] Furthermore, the processing unit 100 prohibits the deletion of the variable pointers stored in the protective predicted pointer cache after the POST process (during runtime).

[0104] As a result, the information processing device 10 can speed up access after the POST process (during runtime) by using the variable pointer stored in the protective predicted pointer cache.

[0105] Furthermore, the processing unit 100 initializes the protection prediction pointer cache and the general prediction pointer cache so that no variable pointers are stored in them at the start of the POST process.

[0106] This allows the information processing device 10 to start the POST process in a state where no invalid variable pointers remain in the predictive pointer cache, thereby speeding up access during the POST process.

[0107] In addition, the memory (e.g., RAM 110) that temporarily stores multiple data items accessed by BIOS processing is a volatile memory that copies and temporarily stores BIOS data stored in a non-volatile memory (e.g., BIOS memory 22).

[0108] As a result, the information processing device 10 can speed up access by expanding and caching data (variable data, etc.) accessed by BIOS processing from the nonvolatile memory to the volatile memory.

[0109] In addition, the control method in the information processing device 10 of this embodiment includes the steps of: the processing unit 100 storing a variable pointer (data location information) indicating the address (location) in RAM 110 of some of the multiple variables (an example of data) stored in RAM 110 by BIOS processing in an area (e.g., a predicted pointer cache) separate from the area in RAM 110 in which the multiple variables are stored; and when accessing one of the multiple variables stored in RAM 110 by BIOS processing, if the variable pointer of the variable to be accessed is not stored in RAM 110, accessing the variable by searching the multiple variables stored in RAM 110 in a predetermined order, and if the variable pointer of the variable to be accessed is stored in RAM 110, accessing the variable based on the variable pointer.

[0110] As a result, the control method in the information processing device 10 can directly access variables (data) expanded in RAM 110 using variable pointers registered in the predicted pointer cache, thereby speeding up access to data by the BIOS.

[0111] In this embodiment, an example is shown in which three variable pointers can be registered in each of the protection prediction pointer cache and the general prediction pointer cache, but the number of variable pointers that can be registered can be set arbitrarily. However, if the number of variable pointers in the prediction pointer cache becomes too large, the time required to search within the prediction pointer cache increases, so it is desirable to keep the number of variable pointers to a minimum (for example, about several). Furthermore, the number of variable pointers that can be registered in each of the protection prediction pointer cache and the general prediction pointer cache may differ.

[0112] In addition, in this embodiment, the variable pointers of variables that have been accessed once are registered in the prediction pointer cache, but registration in the prediction pointer cache is not limited to this. For example, at least some of the variable pointers registered in the prediction pointer cache may be variable pointers of specific variables.

[0113] Although each embodiment of the present invention has been described above in detail with reference to the drawings, the specific configuration is not limited to the above-described embodiments, and the present invention also includes designs that do not deviate from the gist of the present invention. For example, the configurations described in the above-described embodiments can be combined in any manner.

[0114] The information processing device 10 described above includes an internal computer system. A program for implementing the functions of each component of the information processing device 10 may be recorded on a computer-readable recording medium, and the program may be loaded into a computer system and executed to perform processing in each component of the information processing device 10. Here, "loading a program recorded on a recording medium into a computer system and executing it" includes installing the program into a computer system. The term "computer system" here includes hardware such as an OS and peripheral devices. The term "computer system" may also include multiple computers connected via a network, including the Internet, a WAN, a LAN, a dedicated line, or other communication lines. The term "computer-readable recording medium" refers to portable media such as a flexible disk, a magneto-optical disk, a ROM, a CD-ROM, or a storage device such as a hard disk built into a computer system. The recording medium storing the program may also be a non-transitory recording medium such as a CD-ROM.

[0115] The recording medium also includes internal or external recording media accessible from a distribution server for distributing the program. The program may be divided into multiple parts, downloaded at different times, and then combined by each component of the information processing device 10, or each divided program may be distributed by a different distribution server. Furthermore, the term "computer-readable recording medium" also includes a medium that stores a program for a certain period of time, such as volatile memory (RAM) within a computer system that serves as a server or client when a program is transmitted over a network. The program may also be a medium that realizes part of the above-described functions. Furthermore, the program may be a so-called differential file (differential program) that can realize the above-described functions in combination with a program already stored in the computer system.

[0116] Furthermore, some or all of the functions of the information processing device 10 in the above-described embodiment may be realized as an integrated circuit such as an LSI (Large Scale Integration). Each function may be individually implemented as a processor, or some or all of the functions may be integrated into a processor. The integrated circuit method is not limited to LSI, and may be implemented using a dedicated circuit or a general-purpose processor. Furthermore, if an integrated circuit technology that can replace LSI emerges due to advances in semiconductor technology, an integrated circuit based on that technology may be used. [Explanation of symbols]

[0117] 10 information processing device, 11 CPU, 12 main memory, 13 video subsystem, 14 display unit, 21 chipset, 22 BIOS memory, 23 storage medium, 24 audio system, 25 WLAN card, 25 WLAN card, 26 USB connector, 31 embedded controller, 32 input unit, 33 power supply circuit, 34 battery, 100 processing unit, 110 RAM

Claims

1. a processor that executes BIOS (Basic Input Output System) processing; a memory for temporarily storing a plurality of data items accessed by the BIOS processing; Equipped with The processor: a process of storing data location information indicating locations in the memory of some of the plurality of data stored in the memory by processing of the BIOS in an area in the memory different from an area in which the plurality of data are stored; a process of, when accessing any of the plurality of data stored in the memory by processing of the BIOS, if the data location information of the data to be accessed is not stored in the memory, accessing the data by searching the plurality of data stored in the memory in a predetermined order, and if the data location information of the data to be accessed is stored in the memory, accessing the data based on the data location information; An information processing device that performs the above.

2. The processor: In response to an access to any one of the plurality of data stored in the memory by the processing of the BIOS, the data location information of the accessed data is stored in the memory. The information processing device according to claim 1 .

3. each of the plurality of data is stored in the memory in association with identification information of the data; The processor: In response to an access to any one of the plurality of data, identification information of the accessed data and the data location information are stored in the memory in association with each other. The information processing device according to claim 2 .

4. The processor: When reading any of the plurality of data by processing of the BIOS, if the data location information of the data to be read is not stored in the memory, the plurality of data stored in the memory are accessed and read by searching in a predetermined order, and if the data location information of the data to be read is stored in the memory, the data is accessed and read based on the data location information. The information processing device according to claim 1 .

5. The plurality of data include first data that may be written during a POST (Power On Self Test) process by the BIOS but not after the POST process, and second data that may be written both during the POST process and after the POST process, The processor: When storing the data location information in the memory, the data location information of the first data and the data location information of the second data are stored in a first area and a second area in the memory, respectively. The information processing device according to claim 1 .

6. The processor: When writing to any of the plurality of data by the processing of the BIOS, the data before writing is invalidated and the data is written to another location in the memory; when the data is accessed and written based on the data position information stored in the first area or the second area, the data position information is updated based on the position of the data in the memory after writing. The information processing device according to claim 5 .

7. The processor: When the data is accessed and written based on the data position information stored in the first area, all of the data position information currently stored in the first area is erased when updating the data position information, and then the data position information indicating the position in the memory of the data after writing is stored in the first area; When the data is accessed and written based on the data position information stored in the second area, all of the data position information currently stored in the second area is erased when updating the data position information, and then the data position information indicating the position in the memory of the data after writing is stored in the second area. The information processing device according to claim 6 .

8. The processor: prohibiting erasure of the data location information stored in the first area after the POST process; The information processing device according to claim 7 .

9. The processor: initializing the first area and the second area to a state in which the data position information is not stored at the start of the POST process; The information processing device according to any one of claims 5 to 8.

10. The memory is a volatile memory that temporarily stores a copy of BIOS data stored in a nonvolatile memory. The information processing device according to claim 1 .

11. A control method for an information processing device including a processor that executes a BIOS (Basic Input Output System) process and a memory that temporarily stores a plurality of data items accessed by the BIOS process, comprising: the processor: storing data location information indicating locations in the memory of some of the plurality of data stored in the memory by processing of the BIOS in an area in the memory different from an area in which the plurality of data are stored; a step of, when accessing any of the plurality of data stored in the memory by processing of the BIOS, if the data location information of the data to be accessed is not stored in the memory, accessing the data by searching the plurality of data stored in the memory in a predetermined order, and if the data location information of the data to be accessed is stored in the memory, accessing the data based on the data location information; A control method comprising:

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