Control circuits and switching power supplies

Abstract

To preferably suppress power supply noise in a switching power supply.SOLUTION: A control circuit for controlling a switching power supply including a capacitor for generating an output voltage and a switching element for switching charging and discharging of the capacitor through a current flowing in a transformer includes: a burst control unit for comparing a feedback voltage in accordance with an output voltage with a reference voltage to output a burst signal for causing the switching element to perform burst operation based on comparison results; and a jitter superimposition unit for superposing a jitter on the reference voltage to input it to the burst control unit.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a control circuit and a switching power supply. [Background technology]

[0002] BACKGROUND ART Power supply systems that perform burst operations to reduce power consumption have been disclosed (see, for example, Patent Document 1). Patent Document 1: JP 2011-139626 A Summary of the Invention [Problem to be solved by the invention]

[0003] In a switching power supply, it is preferable to suppress power supply noise. [Means for solving the problem]

[0004] In order to solve the above problems, a first aspect of the present invention provides a control circuit. The control circuit may control a switching power supply. The switching power supply may include a capacitor that generates an output voltage and a switching element that switches between charging and discharging the capacitor through a current flowing through a transformer. The control circuit may include a burst control unit. The burst control unit may compare a feedback voltage corresponding to the output voltage with a reference voltage and output a burst signal that causes the switching element to perform a burst operation based on the comparison result. The control circuit may include a jitter superimposition unit. The jitter superimposition unit may superimpose jitter on the reference voltage and input the reference voltage to the burst control unit.

[0005] The jitter incorporating section may incorporate jitter into the burst signal output by the burst control section.

[0006] The jitter applying section may generate jitter that repeatedly transitions between an upper limit voltage and a lower limit voltage.

[0007] The jitter applying section may generate jitter that transitions between an upper limit voltage and a lower limit voltage at a predetermined repetition period.

[0008] The repetition period may be a period in which a first period and a second period different from the first period are alternately repeated.

[0009] The burst operation may be performed by causing the switching element to repeat switching when the burst signal is at a first level, and by causing the switching element to stop switching when the burst signal is at a second level.

[0010] A second aspect of the present invention provides a switching power supply. The switching power supply may include a capacitor. The capacitor may generate an output voltage. The switching power supply may include a switching element. The switching element may switch between charging and discharging the capacitor. The switching power supply may include a control circuit. The control circuit may control the switching element. The control circuit may include a burst control unit. The burst control unit may compare a feedback voltage corresponding to the output voltage with a reference voltage, and output a burst signal that causes the switching element to perform a burst operation based on the comparison result. The control circuit may include a jitter superimposition unit. The jitter superimposition unit may superimpose jitter on the reference voltage and input the reference voltage to the burst control unit.

[0011] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a diagram illustrating an example of the configuration of a switching power supply 10. FIG. [Figure 2] FIG. 2 is a diagram illustrating a control circuit 22 according to a comparative example. [Figure 3] FIG. 10 is a diagram showing an example of a timing chart of a control circuit 22 according to a comparative example. [Figure 4] FIG. 10 is a diagram showing an example of a timing chart of a control circuit 22 according to a comparative example. [Figure 5] FIG. 2 is a diagram illustrating a control circuit 22 according to the embodiment. [Figure 6] FIG. 3 is a diagram showing an example of a timing chart of the control circuit 22 according to the embodiment. [Figure 7] FIG. 10 is a diagram illustrating the relationship between frequency and noise level. [Figure 8] FIG. 4 is a diagram illustrating another example of the control circuit 22. [Figure 9] FIG. 10 illustrates an example of a jitter superimposing unit 63. [Figure 10] 10 is a diagram showing an example of a timing chart of the jitter superimposing unit 63. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0013] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0014] FIG. 1 shows an example of the configuration of a switching power supply 10. In this example, the switching power supply 10 is an AC-DC converter. The switching power supply 10 in this example is a flyback power supply circuit that generates an output voltage Vout at a target level from an AC voltage Vac of a commercial power supply. The switching power supply 10 outputs the output voltage Vout to a load 11.

[0015] The switching power supply 10 includes a full-wave rectifier circuit 20, a capacitor 21, a capacitor 31, a capacitor 33, a capacitor 41, a control circuit 22, a switching element 23, a transformer 24, a resistor 28, a diode 30, a diode 40, a phototransistor 32, a constant voltage circuit 42, and a light-emitting diode 43.

[0016] The full-wave rectifier circuit 20 performs full-wave rectification on the input AC voltage Vac and outputs the result. The capacitor 21 smoothes the output from the full-wave rectifier circuit 20. The capacitor 21 generates the voltage Vrec.

[0017] The control circuit 22 controls the switching power supply 10. The control circuit 22 is an integrated circuit that controls the switching of the switching element 23 so that the level of the output voltage Vout becomes a target level. The control circuit 22 is, for example, a switching control IC. The control circuit 22 drives the switching element 23 based on the current IL1 flowing through the primary coil L1 of the transformer 24 and the output voltage Vout. Details of the control circuit 22 will be described with reference to FIG. 2.

[0018] In this specification, the switching element 23 is an NMOS transistor for controlling the output voltage Vout of the switching power supply 10. The switching element 23 switches between charging and discharging the capacitor 41. In this example, the switching element 23 switches between charging and discharging the capacitor 41 through a current flowing through the transformer 24. The output voltage Vout can be controlled by adjusting the ratio between the charging period and the discharging period of the capacitor 41. Note that the switching element 23 is not limited to a MOS (Metal Oxide Semiconductor) transistor, and may be a bipolar transistor or the like. A voltage Vdr is input to the gate electrode of the switching element 23. The switching operation of the switching element 23 can be controlled by the voltage Vdr.

[0019] The transformer 24 includes a primary coil L1, a secondary coil L2, and an auxiliary coil L3. The primary coil L1 and the auxiliary coil L3 are magnetically coupled to and electrically insulated from the secondary coil L2. In this example, the polarity of the primary coil L1 and the auxiliary coil L3 is opposite to that of the secondary coil L2. In this example, a voltage Vrec is applied to one end of the primary coil L1, and the other end is connected to the drain electrode of the switching element 23. In this specification, the voltage at the connection point between the primary coil L1 and the switching element 23 is referred to as Vds. When the switching element 23 is turned on, a current IL1 flows through the primary coil L1 of the transformer 24. Furthermore, a current corresponding to the winding ratio of the primary coil L1 flows through the auxiliary coil L3. The primary coil L1 stores energy due to the current IL1 while the switching element 23 is on. When the switching element 23 is turned off, the energy stored in the primary coil L1 is transferred to the secondary coil L2, causing a current IL2 to flow.

[0020] The diode 40 rectifies the current IL2 from the secondary coil L2 of the transformer 24 and supplies the rectified current to the capacitor 41. The capacitor 41 is charged by the current IL2 from the diode 40, and an output voltage Vout is generated across the terminals of the capacitor 41. In other words, the capacitor 41 generates the output voltage Vout. If the time that the switching element 23 is turned on becomes longer, the time that the capacitor 41 is charged becomes longer, and the output voltage Vout becomes higher.

[0021] Resistor 28 is a resistor provided between the source electrode of switching element 23 and ground. That is, one end of resistor 28 is connected to the source electrode of switching element 23, and the other end of resistor 28 is connected to ground. In this specification, "connected" includes being directly connected and being indirectly connected via a circuit element. By detecting voltage Vcs across resistor 28, it is possible to detect current IL1 flowing through primary coil L1 of transformer 24 and switching element 23.

[0022] The diode 30 rectifies the current from the auxiliary coil L3 of the transformer 24 and supplies it to the capacitor 31. When the switching element 23 performs a switching operation, a current flows through the auxiliary coil L3 and charges the capacitor 31. The capacitor 31 applies the power supply voltage Vcc to the control circuit 22.

[0023] The constant voltage circuit 42 is a circuit that generates a constant DC voltage. In this example, the constant voltage circuit 42 is configured using a shunt regulator.

[0024] The light-emitting diode 43 is an element that emits light with an intensity corresponding to the difference between the output voltage Vout and the output of the constant voltage circuit 42. The light-emitting diode 43, together with the phototransistor 32 described below, constitutes a photocoupler. In this example, as the level of the output voltage Vout increases, the intensity of the light emitted from the light-emitting diode 43 increases.

[0025] The phototransistor 32 receives light from the light-emitting diode 43. The phototransistor 32 generates a sink current I1 that corresponds to the intensity of the received light. The phototransistor 32 is connected to the terminal FB of the control circuit 22. The voltage Vfb at the terminal FB is determined by the internal resistance of the control circuit 22 and the sink current I1.

[0026] The capacitor 33 is connected in parallel with the phototransistor 32 between the terminal FB and ground potential. The capacitor 33 is a filter that removes high-frequency components from the voltage Vfb. When the output voltage Vout increases, the light-emitting diode 43 emits light with a stronger intensity, and the sink current I1 of the phototransistor 32 increases. As a result, the voltage drop across the internal resistance of the control circuit 22 increases, and the voltage Vfb decreases. Conversely, when the output voltage Vout falls below the target level, the voltage drop across the internal resistance of the control circuit 22 decreases, and the voltage Vfb increases.

[0027] 2 is a diagram showing a control circuit 22 according to a comparative example. The control circuit 22 is an integrated circuit that controls the driving of the switching element 23. The control circuit 22 has terminals VCC, FB, CS, OUT, and GND. The terminal GND is grounded. The terminal GND may provide a GND potential to each element of the control circuit 22. Note that connections between the terminal GND and each element are omitted in FIG. 2.

[0028] The terminal VCC is a terminal to which the power supply voltage Vcc is applied. The power supply voltage Vcc is generated by charging the current of the auxiliary coil L3 through the capacitor 31. The terminal CS is a terminal to which the voltage Vcs is applied. The terminal OUT is a terminal that outputs the voltage Vdr.

[0029] Terminal FB is a terminal where voltage Vfb is generated. Resistor 50 is connected to terminal FB. When current I1 shown in FIG. 1 flows through resistor 50, voltage Vfb is generated at terminal FB. When the load is light, the current flowing through the load decreases, so the charge accumulated in capacitor 41 increases and output voltage Vout rises. This increases the light emission intensity of light-emitting diode 43 and increases current I1 flowing through phototransistor 32. As a result, voltage Vfb decreases. On the other hand, when the load is heavy, the current flowing through the load increases, so the charge accumulated in capacitor 41 decreases and output voltage Vout decreases. This decreases the light emission intensity of light-emitting diode 43 and decreases current I1 flowing through phototransistor 32. As a result, voltage Vfb increases.

[0030] The control circuit 22 also includes a resistor 50, a comparator 51, an internal power supply 52, an oscillator 55, a one-shot circuit 56, an SR flip-flop 57, a voltage dividing circuit 58, a comparator 59, a logical sum circuit 61, and a logical product circuit 62.

[0031] The internal power supply 52 is a circuit that generates an internal voltage Vdd from the power supply voltage Vcc. The internal voltage Vdd is applied to one end of a resistor 50. It is preferable that the internal voltage Vdd be approximately constant regardless of the magnitude of the power supply voltage Vcc.

[0032] One end of the resistor 50 is connected to the internal power supply 52, and the other end of the resistor 50 is connected to the voltage dividing circuit 58. The other end of the resistor 50 is connected to the terminal FB and the comparator 51.

[0033] The comparator 51 is a circuit that compares the voltage Vfb with a reference voltage Vfb-off and outputs a burst signal FBcomp. The burst signal is a signal that causes the switching element 23 to perform burst operation. The burst operation will be described with reference to FIG. 4. The reference voltage Vfb-off is a threshold voltage for comparison with the voltage Vfb. The reference voltage Vfb-off may be generated based on an internal voltage Vdd or the like. The magnitude of the reference voltage Vfb-off may be set in advance by a user or the like. The comparator 51 causes the switching element 23 to perform burst operation based on the comparison result between the voltage Vfb and the reference voltage Vfb-off. In this example, a signal for controlling the switching element 23 and the burst signal FBcomp output by the comparator 51 are input to a logical product circuit 62. The logical product of these signals is input to the switching element 23 as voltage Vdr. For example, when the voltage Vfb falls below the reference voltage Vfb-off under light load conditions, the comparator 51 outputs a low-level burst signal FBcomp. As a result, the voltage Vdr output by the AND circuit 62 is fixed to a low level, and the switching operation of the switching element 23 is stopped. Also, when the voltage Vfb rises above the reference voltage Vfb-off under heavy load conditions, the comparator 51 outputs a high-level burst signal FBcomp. As a result, the AND circuit 62 passes a signal for controlling the switching element 23, causing the switching element 23 to operate. The comparator 51 is an example of a burst control unit. In this specification, a "signal" refers to a voltage signal. The comparator 51 may compare a "voltage" with a "signal."

[0034] The oscillator 55 is a circuit that outputs a signal Vpwm. For example, the signal Vpwm is a pulse waveform having a predetermined frequency. The one-shot circuit 56 is a circuit that generates a one-shot pulse (1 shot-out). The one-shot circuit 56 is a circuit that outputs one pulse (1 shot-out) every time the oscillator 55 outputs a predetermined number of pulses.

[0035] The SR flip-flop 57 receives the one-shot pulse 1shot-out at its set input and the signal PWMcomp (described later) at its reset input, and generates the signal rs-out. Therefore, when the one-shot pulse 1shot-out goes high, the SR flip-flop 57 generates the signal rs-out at a high level. Also, when the signal PWMcomp goes high, the SR flip-flop 57 generates the signal rs-out at a low level.

[0036] A voltage divider circuit 58 generates a voltage PWM-off by dividing the voltage Vfb generated at the terminal FB by a predetermined voltage division ratio. The comparator 59 is a circuit that compares the voltage Vcs from the terminal CS with the voltage PWM-off and generates a signal PWMcomp. As described above, the voltage Vcs corresponds to the current L1 flowing through the primary coil L1, and the voltage PWM-off corresponds to the output voltage Vout. In this example, the comparator 59 outputs a low-level signal PWMcomp when the voltage Vcs is lower than the voltage PWM-off. On the other hand, the comparator 59 outputs a high-level signal PWMcomp when the voltage Vcs is higher than the voltage PWM-off.

[0037] The logical AND circuit 61 outputs the logical OR of the one-shot pulse 1shot-out and the signal rs-out. The burst signal FBcomp and the output of the logical AND circuit 61 are input to the logical AND circuit 62. As described above, when the burst signal FBcomp is at a low level, the logical AND circuit 62 outputs a low-level signal regardless of the output of the logical OR circuit 61, and when the burst signal FBcomp is at a high level, it passes the output of the logical OR circuit 61. By providing the logical AND circuit 62, it is possible to cause the switching element 23 to perform burst operation in accordance with the burst signal FBcomp.

[0038] FIG. 3 is a diagram showing an example of a timing chart of the control circuit 22 according to the comparative example. The example in FIG. 3 shows operation under heavy load. In the example in FIG. 3, since the load 11 is heavy, the output voltage Vout decreases and the voltage Vfb increases. Therefore, the comparator 51 outputs a high-level signal FBcomp. Therefore, the AND circuit 62 passes the output of the OR circuit 61. Note that the operation in FIG. 3 also corresponds to the operation under heavy load in an embodiment described later.

[0039] FIG. 3 shows a timing chart of the one-shot pulse 1shot-out, signal rs-out, voltage Vcs, signal PWMcomp, and voltage Vdr. The horizontal axis represents times t1, t2, t3, and t4. Times t1 and t3 are the times when the one-shot pulse 1shot-out goes high. Times t2 and t4 are the times when the voltage Vcs becomes higher than the voltage PWM-off.

[0040] At time t1, the one-shot pulse 1shot-out goes high. When the one-shot pulse 1shot-out goes high, the SR flip-flop 57 generates a high-level signal rs-out. Also, at time t1, the voltage Vdr also goes high. When the voltage Vdr goes high, the switching element 23 is turned on, and the voltage Vcs, which is the current value of the current flowing through the primary coil L1, increases.

[0041] At time t2, voltage Vcs becomes higher than voltage PWM-off (shown by the dashed line). Therefore, at time t2, PWMcomp goes high, and SR flip-flop 57 generates a low-level signal rs-out. Also, at time t2, voltage Vdr similarly goes low. When voltage Vdr goes low, switching element 23 goes into the off state, and voltage Vcs, which is the current value of the current flowing through primary coil L1, decreases. Then, at time t3, one-shot pulse 1shot-out goes high again, and the same operation is repeated.

[0042] The PWM-off voltage is generated from the voltage Vfb. Therefore, the pulse widths of the rs-out and Vdr signals change depending on the voltage Vfb. The pulse widths of the rs-out and Vdr signals are the durations during which these voltages or signals are at a high level, e.g., time T1 in FIG. 3 . Time T1 may be the time from time t1 to time t2. For example, when the output voltage Vout decreases, such as during a heavy load, the Vfb and PWM-off voltages increase. In this case, the time T1 required for the Vcs voltage to exceed the PWM-off voltage increases. This lengthens the on-time T1 of the switching element 23, increasing the output voltage Vout. Furthermore, when the output voltage Vout increases, such as during a light load, the Vfb and PWM-off voltages decrease. This shortens the on-time T1 of the switching element 23, reducing the output voltage Vout. This control reduces fluctuations in the output voltage Vout.

[0043] FIG. 4 is a diagram showing an example of a timing chart of the control circuit 22 according to the comparative example. The example in FIG. 4 illustrates an operation of transitioning from a heavy load to a light load. FIG. 4 shows a timing chart of the voltage Vfb and the voltage Vds. The horizontal axis represents times t10, t11, t12, t13, t14, t15, t16, t17, and t18. Times t11, t13, t15, and t17 are times when the voltage Vfb becomes lower than the reference voltage Vfb-off (shown by the dashed-dotted line). Times t12, t14, t16, and t18 are times when the voltage Vfb becomes higher than the reference voltage Vfb-off. Furthermore, time t10 is the time when the load 11 is changed from a heavy load to a light load.

[0044] At time t10, the load 11 changes from a heavy load to a light load. When the load 11 becomes a light load, the output voltage Vout increases and the voltage Vfb monotonically decreases. Furthermore, as the voltage Vfb monotonically decreases, the voltage PWM-off also decreases. Therefore, the pulse width of the voltage Vds may also gradually decrease.

[0045] At time t11, the voltage Vfb becomes lower than the reference voltage Vfb-off. In this case, the comparator 51 outputs a low-level burst signal FBcomp to stop the switching operation of the switching element 23 and fix it in the OFF state. Fixing the switching element 23 in the OFF state reduces the output voltage Vout and increases the voltage Vfb. In this example, because the constant voltage circuit 42 is configured using a shunt regulator, the response of the voltage Vfb after the switching element 23 is turned OFF is slow. Therefore, the voltage Vfb increases with a delay from time t11.

[0046] At time t12, the voltage Vfb becomes higher than the reference voltage Vfb-off. In this case, the comparator 51 outputs a high-level burst signal FBcomp, causing the switching element 23 to perform a switching operation in response to the output of the OR circuit 61. As shown in FIG. 4, burst operation refers to an operation in which the switching element 23 repeatedly performs a switching period (when the voltage Vfb is higher than the reference voltage Vfb-off) and a non-switching period (when the voltage Vfb is lower than the reference voltage Vfb-off). When the switching element 23 is turned on, the output voltage Vout increases and the voltage Vfb decreases. In this example, because the constant voltage circuit 42 is configured using a shunt regulator, the response of the voltage Vfb after the switching element 23 is turned on is slow. Therefore, the voltage Vfb decreases with a delay from time t12. From time t13 onward, the switching element 23 is repeatedly stopped and activated.

[0047] In this example, the switching element 23 is stopped from time t11 to time t12, from time t13 to time t14, from time t15 to time t16, and from time t17 to time t18. The switching element 23 is operated from time t12 to time t13, from time t14 to time t15, from time t16 to time t17, and from time t18 onward. Repeatedly stopping and operating the switching element 23 can reduce the number of switching operations when the load 11 is lightly loaded. Under light load conditions, the power supplied to the load is reduced. Therefore, there are cases where the switching loss is not negligible compared to the power supplied to the load. In response to this, reducing the number of switching operations under light load conditions can improve power conversion efficiency.

[0048] In this specification, the period (time) from when the switching element 23 is stopped until the next time the switching element 23 is stopped is defined as the burst period. The burst period T11 is the time from time t11 to time t13. The burst period T12 is the time from time t13 to time t15. The burst period T13 is the time from time t15 to time t17. In the conventional example, since the reference voltage Vfb-off is constant, the burst period under light load is approximately constant if the load under light load is constant. In other words, the burst period T11, burst period T12, and burst period T13 are approximately equal. This burst period falls within a specific audible frequency band (approximately several kHz), and may cause power supply noise due to the transformer 24 or each capacitor. Note that, as in this comparative example and the example described later, under light load conditions, burst operation is performed by the voltage Vfb repeatedly fluctuating above and below the reference voltage Vfb-off. In a heavy load state, the voltage Vfb is above (larger than) the reference voltage Vfb-off, so that the switching operation is always performed.

[0049] Fig. 5 is a diagram showing a control circuit 22 according to an embodiment. The control circuit 22 in Fig. 5 differs from the control circuit 22 in Fig. 2 in that it includes a jitter superimposing unit 63. Other configurations of the control circuit 22 in Fig. 5 may be the same as those of the control circuit 22 in Fig. 2.

[0050] In this example, the jitter superimposing unit 63 superimposes jitter on the reference voltage Vfb-off and inputs the result to the comparator 51. In this example, jitter refers to signal variations (fluctuations), such as components that cause voltage to fluctuate over time. By superimposing jitter on the reference voltage Vfb-off, the reference voltage Vfb-off fluctuates over time, unlike the example in FIG. 4. This causes variations in the timing at which the voltage Vfb becomes greater than the reference voltage Vfb-off.

[0051] FIG. 6 is a diagram illustrating an example of a timing chart of the control circuit 22 according to the embodiment. FIG. 6 illustrates operation during a light load. FIG. 6 illustrates a timing chart of the voltages Vfb and Vds. The horizontal axis represents times t20, t21, t22, t23, t24, t25, t26, t27, t28, t29, t30, t31, and t32. At times t21, t23, t25, t27, t29, and t31, the voltage Vfb becomes lower than the reference voltage Vfb-off (shown by the dashed-dotted line). At times t22, t24, t26, t28, t30, and t32, the voltage Vfb becomes higher than the reference voltage Vfb-off. Furthermore, time t20 is the time when the load 11 is changed from a heavy load to a light load. Furthermore, in this example, jitter is superimposed on the reference voltage Vfb-off, so the reference voltage Vfb-off changes over time.

[0052] In this example, the reference voltage Vfb-off repeatedly transitions between an upper limit voltage Vfb-off1 and a lower limit voltage Vfb-off2. That is, the jitter superimposing unit 63 generates jitter whose voltage fluctuates with a constant amplitude so that the reference voltage Vfb-off repeatedly transitions between the upper limit voltage Vfb-off1 and the lower limit voltage Vfb-off2. In this example, the reference voltage Vfb-off repeatedly transitions between the upper limit voltage Vfb-off1 and the lower limit voltage Vfb-off2 at a constant cycle. That is, the jitter repeatedly transitions between the upper limit voltage Max-jitter and the lower limit voltage Min-jitter at a constant cycle (see FIG. 10).

[0053] At time t20, the load 11 changes from a heavy load to a light load. In this case, the voltage Vfb decreases monotonically, as in FIG. 4. Furthermore, as the voltage Vfb decreases monotonically, the voltage PWM-off also decreases. Therefore, the pulse width of the voltage Vds may also decrease.

[0054] At time t21, the voltage Vfb becomes lower than the reference voltage Vfb-off. In this case, the comparator 51 outputs a low-level burst signal FBcomp to stop the switching operation of the switching element 23 and fix it in the OFF state. Fixing the switching element 23 in the OFF state reduces the output voltage Vout and increases the voltage Vfb. In this example, since the constant voltage circuit 42 is configured using a shunt regulator, the response of the voltage Vfb after the switching element 23 is turned OFF may be slow. Therefore, the voltage Vfb may increase with a delay from time t21.

[0055] At time t22, the voltage Vfb becomes higher than the reference voltage Vfb-off. In this case, the comparator 51 outputs a high-level burst signal FBcomp to operate the switching element 23. When the switching element 23 turns on, the voltage Vfb decreases. In this example, the constant voltage circuit 42 is configured using a shunt regulator, so the response of the voltage Vfb after the switching element 23 turns on is slow. Therefore, the voltage Vfb decreases with a delay from time t22. After time t23, the switching element 23 repeatedly stops and starts operating.

[0056] 6, the switching element 23 is stopped from time t21 to time t22, from time t23 to time t24, from time t25 to time t26, from time t27 to time t28, from time t29 to time t30, and from time t31 to time t32. The switching element 23 is operated from time t22 to time t23, from time t24 to time t25, from time t26 to time t27, from time t28 to time t29, from time t30 to time t31, and from time t32 onwards.

[0057] Burst period T21 is the time from time t21 to time t23. Burst period T22 is the time from time t23 to time t25. Burst period T23 is the time from time t25 to time t27. Burst period T24 is the time from time t27 to time t29. Burst period T25 is the time from time t29 to time t31.

[0058] In this example, since the reference voltage Vfb-off is changed, the burst period T21, the burst period T22, the burst period T23, the burst period T24, and the burst period T25 are all different from one another. This makes it possible to suppress the generation of power supply noise due to the transformer 24 and each capacitor. This in turn improves the quality of the switching power supply 10.

[0059] The reference voltage Vfb-off may repeatedly transition between an upper limit voltage Vfb-off1 and a lower limit voltage Vfb-off2 at random timing. The random timing may be determined by random number generation. In this case, the jitter repeatedly transitions between the upper limit voltage and the lower limit voltage at random timing.

[0060] In this example, the reference voltage Vfb-off transitions between an upper limit voltage Vfb-off1 and a lower limit voltage Vfb-off2 in a predetermined cycle. That is, the jitter superimposing unit 63 generates jitter whose voltage fluctuates with a constant amplitude so that the reference voltage Vfb-off transitions between the upper limit voltage Vfb-off1 and the lower limit voltage Vfb-off2 in a predetermined cycle. That is, the jitter transitions between the upper limit voltage Max-jitter and the lower limit voltage Min-jitter in a predetermined cycle (see FIG. 10). By generating jitter that transitions in a predetermined cycle, it is possible to suppress power supply noise caused by the transformer 24 and each capacitor.

[0061] In this example, the repetition period alternates between a first period T31 and a second period T32 that is different from the first period. In this example, the first period T31 is three times the second period T32. Furthermore, if the first period T31 and the second period T32 are integer multiples of the burst period T21, for example, operation and stop will be repeated periodically, so it is preferable that the first period T31 and the second period T32 are not integer multiples of the burst period T21, for example.

[0062] Fig. 7 is a diagram showing the relationship between frequency and noise level, in which the comparative example is represented by a solid line and the working example is represented by a dotted line.

[0063] In the comparative example, the noise level is high at a specific burst frequency f. The burst frequency f is the frequency during the burst period. For example, the burst frequency f is expressed as f=1 / T11. In contrast, in the embodiment, the noise level is discretized. Therefore, even when the burst period falls within a specific audible frequency band, the noise level peak can be suppressed, and the generation of power supply noise due to the transformer 24 and each capacitor can be suppressed.

[0064] Fig. 8 is a diagram showing another example of the control circuit 22. The control circuit 22 in Fig. 8 differs from the control circuit 22 in Fig. 2 in that it includes a jitter superimposing unit 63. Other configurations of the control circuit 22 in Fig. 8 may be the same as those of the control circuit 22 in Fig. 2. Note that the position at which the jitter superimposing unit 63 is provided in Fig. 8 differs from that in Fig. 5.

[0065] In this example, the jitter superimposing unit 63 superimposes jitter on the burst signal FBcomp. By superimposing jitter on the burst signal FBcomp, variations occur in the burst signal FBcomp. Therefore, the timing at which the switching element 23 is activated or deactivated can be varied, and the occurrence of power supply noise due to the transformer 24 and each capacitor can be suppressed.

[0066] The jitter injection section 63 may randomly delay the burst signal FBcomp. By randomly delaying the burst signal FBcomp, the burst signal FBcomp can be varied.

[0067] 9 is a diagram showing an example of the jitter superimposing unit 63. The jitter superimposing unit 63 includes a PWM signal generating unit 70 and a triangular wave generating unit 80. In FIG. 9, GND is connected to the terminal GND. In other words, GND is grounded. Also in FIG. 9, the internal voltage Vdd of FIG. 2 is applied to Vdd.

[0068] The PWM signal generating unit 70 includes resistor 71, resistor 72, capacitor 73, resistor 74, comparator 75, resistor 76, comparator 77, resistor 78, and resistor 79. Comparator 75 is connected to resistor 71, resistor 72, capacitor 73, resistor 74, and resistor 76. Resistor 71, resistor 72, capacitor 73, resistor 74, comparator 75, and resistor 76 form a circuit that generates a triangular wave. Comparator 75 outputs a signal PWMInput to comparator 77. Comparator 77 receives the signal PWMInput and a voltage PWMInput-off. Comparator 77 outputs a signal PWMOutput.

[0069] The triangular wave generating unit 80 includes a resistor 81, a resistor 82, a capacitor 83, a switch 84, a resistor 85, a resistor 86, a comparator 87, and a resistor 88. The comparator 87 is connected to the resistors 81, 82, the capacitor 83, the switch 84, the resistors 85, 86, and the resistor 88. The resistors 81, 82, the capacitor 83, the switch 84, the resistors 85, 86, the comparator 87, and the resistor 88 form a circuit that generates a triangular wave. The comparator 87 outputs a signal Jitter to the reference voltage Vfb-off. Note that the signal Jitter may also be the reference voltage Vfb-off. In this example, the signal PWMOutput is applied to the switch 84 as the signal SW.

[0070] Fig. 10 is a diagram showing an example of a timing chart of the jitter superimposing unit 63. Fig. 10 shows a timing chart of the signal PWMInput, the voltage PWMInput-off, the signal PWMOutput, the signal SW, and the signal Jitter.

[0071] Comparator 77 compares signal PWMInput with voltage PWMInput-off. When signal PWMInput is higher than voltage PWMInput-off, comparator 77 outputs high-level signal PWMOutput. When signal PWMInput is lower than voltage PWMInput-off, comparator 77 outputs low-level signal PWMOutput. Therefore, by changing voltage PWMInput-off, it is possible to adjust the pulse width ratio of signal PWMOutput. The pulse width ratio of signal PWMOutput is the ratio of the length of the period during which the signal is at a high level to the length of the period during which the signal is at a low level. In other words, the pulse width ratio of signal PWMOutput is the ratio of the first period T31 to the second period T32. The pulse width ratio of signal PWMOutput can be adjusted by adjusting resistor 78 or resistor 79. Signal PWMOutput has the same waveform as signal SW.

[0072] When the signal SW is at a high level, the switch 84 is turned on. When the switch 84 is turned on, the resistor 85 is connected, and the combined resistance within the triangular wave generating unit 80 changes. When the signal SW is at a low level, the switch 84 is turned off. Therefore, by turning the switch 84 on and off, the combined resistance within the triangular wave generating unit 80 can be changed, and the time constant within the triangular wave generating unit 80 can be controlled. Therefore, the frequency of the signal Jitter can be controlled.

[0073] In this example, the signal Jitter repeatedly transitions between an upper limit voltage Max-jitter and a lower limit voltage Min-jitter at a constant cycle. The signal Jitter also transitions between the upper limit voltage Max-jitter and the lower limit voltage Min-jitter at a predetermined cycle. In Fig. 10, the cycle alternates between a first cycle T31 and a second cycle T32, which is different from the first cycle, as in Fig. 6.

[0074] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0075] It should be noted that the execution order of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order. [Explanation of symbols]

[0076] 10. Switching power supply, 11. Load, 20. Full-wave rectifier circuit, 21. Capacitor, 22. Control circuit, 23. Switching element, 24. Transformer, 28. Resistor, 30. Diode, 31. Capacitor, 32. Phototransistor, 33. Capacitor, 40. Diode, 41. Capacitor, 42. Constant voltage circuit, 43. Light-emitting diode, 50. Resistor, 51. Comparator, 52. Internal power supply, 55. Oscillator, 56. One-shot circuit, 57. SR free flip-flop, 58. voltage divider circuit, 59. comparator, 61. OR circuit, 62. AND circuit, 63. jitter superposition section, 70. PWM signal generation section, 71. resistor, 72. resistor, 73. capacitor, 74. resistor, 75. comparator, 76. resistor, 77. comparator, 78. resistor, 79. resistor, 80. triangular wave generation section, 81. resistor, 82. resistor, 83. capacitor, 84. switch, 85. resistor, 86. resistor, 87. comparator, 88. resistor

Claims

1. A control circuit for controlling a switching power supply including a capacitor that generates an output voltage and a switching element that switches between charging and discharging the capacitor through a current flowing through a transformer, a burst control unit that compares a feedback voltage corresponding to the output voltage with a reference voltage and outputs a burst signal that causes the switching element to perform a burst operation based on the comparison result; a jitter superimposing unit that superimposes jitter on the reference voltage and inputs the superimposed jitter to the burst control unit; Equipped with the jitter superimposing unit generates the jitter that repeatedly transitions between an upper limit voltage and a lower limit voltage; The jitter has a waveform that continuously changes between the upper limit voltage and the lower limit voltage. Control circuit.

2. A control circuit for controlling a switching power supply including a capacitor that generates an output voltage and a switching element that switches between charging and discharging the capacitor, a burst control unit that compares a feedback voltage corresponding to the output voltage with a reference voltage and outputs a burst signal that causes the switching element to perform a burst operation based on the comparison result; a jitter superimposing unit that superimposes jitter on the burst signal output by the burst control unit; Equipped with the jitter superimposing unit generates the jitter that repeatedly transitions between an upper limit voltage and a lower limit voltage; The jitter has a waveform that continuously changes between the upper limit voltage and the lower limit voltage. Control circuit.

3. The jitter superimposing unit generates jitter that transitions between the upper limit voltage and the lower limit voltage at a predetermined repetition period.

3. The control circuit according to claim 1 or 2.

4. The repeating period is A first period; a second period different from the first period; Repeat alternately 4. The control circuit of claim 3.

5. When the burst signal is at a first level, the switching element repeats switching, and when the burst signal is at a second level, the switching element stops switching, thereby performing the burst operation.

3. The control circuit according to claim 1 or 2.

6. a capacitor for generating an output voltage; a switching element for switching between charging and discharging the capacitor; a control circuit for controlling the switching element; Equipped with the control circuit comprises a burst control section that compares a feedback voltage corresponding to the output voltage with a reference voltage and outputs a burst signal that causes the switching element to perform a burst operation based on the comparison result; a jitter superimposing unit that superimposes jitter on the reference voltage and inputs the superimposed jitter to the burst control unit; Equipped with the jitter superimposing unit generates the jitter that repeatedly transitions between an upper limit voltage and a lower limit voltage; The jitter has a waveform that continuously changes between the upper limit voltage and the lower limit voltage. Switching power supply.

7. The jitter superimposing unit generates jitter that transitions between the upper limit voltage and the lower limit voltage at a predetermined repetition period.

7. The switching power supply according to claim 6.

8. The repeating period is A first period; a second period different from the first period; Repeat alternately 8. The switching power supply according to claim 7.

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