Switching control circuits, power supply circuits

Abstract

To provide a switching control circuit capable of accurately detecting a state of a load, and a power supply circuit.SOLUTION: A switching control circuit includes: a transformer including a primary coil and a secondary coil; a first and a second transistors for controlling a current of the primary coil; and a resonance circuit including the primary coil and a first capacitor, and controls switching of a first and a second transistors of a power supply circuit that generates an output voltage of a target level on a secondary side. The switching control circuit includes: an averaging circuit for averaging a first voltage Vis according to a resonance current flowing in a first period in the power supply circuit in a cycle based on a setting signal to output it as a second voltage Vca indicating a load current flowing in a load of the power supply circuit; a setting circuit for outputting a setting signal N for increasing a cycle when the load current increases based on the second voltage; and a drive signal output circuit for outputting drive signals Vdr1 and Vdr2 for driving the first and the second transistors based on a feedback voltage according to the output voltage, the second voltage, and the setting signal.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a switching control circuit and a power supply circuit. [Background technology]

[0002] A switching control circuit that controls an LLC current resonant converter may include a load detection circuit that detects the state of the load based on the resonant current (for example, Patent Documents 1 and 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6229804 [Patent Document 2] Japanese Patent Application Publication No. 2019-193447 Summary of the Invention [Problem to be solved by the invention]

[0004] The above-described load detection circuit generates a detection voltage that indicates the load state based on the resonant current. Generally, the load detection circuit generates the detection voltage by amplifying the resonant current with a predetermined gain. Therefore, if the gain is large, the detection voltage may become saturated. On the other hand, if the gain is small, it may become difficult to detect the detection voltage when the resonant current is small.

[0005] The present invention has been made in view of the above-mentioned problems in the prior art, and an object of the present invention is to provide a switching control circuit that can detect the state of a load with high accuracy. [Means for solving the problem]

[0006] The switching control circuit of the present invention, which solves the above-mentioned problems, is a switching control circuit that controls switching of the first and second transistors of a power supply circuit that includes a transformer including a primary coil and a secondary coil, first and second transistors that control the current of the primary coil, and a resonant circuit including the primary coil and a first capacitor, and generates an output voltage of a target level on the secondary side, and includes an averaging circuit that averages a first voltage corresponding to a resonant current flowing in the power supply circuit for a first period, over a period based on a setting signal, and outputs the averaged first voltage as a second voltage that indicates a load current flowing through a load of the power supply circuit, a setting circuit that outputs the setting signal based on the second voltage, which lengthens the period when the load current increases, and a drive signal output circuit that outputs a drive signal to drive the first and second transistors based on a feedback voltage corresponding to the output voltage, the second voltage, and the setting signal.

[0007] The power supply circuit of the present invention, which solves the above-mentioned problems, is a power supply circuit that generates an output voltage of a target level on the secondary side, and includes a transformer including a primary coil and a secondary coil, first and second transistors that control the current of the primary coil, a resonant circuit including the primary coil and a first capacitor, and a switching control circuit that controls the switching of the first and second transistors, wherein the switching control circuit includes an averaging circuit that averages a first voltage corresponding to a resonant current flowing in the power supply circuit for a first period, over a period based on a setting signal, and outputs the averaged first voltage as a second voltage that indicates a load current flowing through a load of the power supply circuit, a setting circuit that outputs the setting signal based on the second voltage, and lengthens the period when the load current increases, and a drive signal output circuit that outputs a drive signal to drive the first and second transistors based on a feedback voltage corresponding to the output voltage, the second voltage, and the setting signal. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a switching control circuit that can detect the load state with high accuracy. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram illustrating an example of a switching power supply circuit 10a. [Figure 2] FIG. 2 is a diagram illustrating an example of a control IC 40a. [Figure 3] FIG. 2 is a diagram illustrating an example of a setting circuit 62. [Figure 4] FIG. 10 is a diagram illustrating an example of an averaging circuit 65. [Figure 5] 10 is a flowchart showing an example of the operation of the output circuit 84. [Figure 6] FIG. 4 is a diagram illustrating an example of the operation of the control circuit 91. [Figure 7] FIG. 10 is a diagram showing the relationship between the voltage Vca and the voltage Vis in the control IC 40a. [Figure 8] FIG. 10 is a diagram showing the relationship between the number of thinning-out pixels N, the voltage Vca, and the signal Vload. [Figure 9] 10 is a diagram showing an example of drive signals Vdr1 and Vdr2 when the load 11 is in a heavy load state. FIG. [Figure 10] 10 is a diagram showing an example of drive signals Vdr1 and Vdr2 when the load 11 is in a light load state. FIG. [Figure 11] FIG. 10 is a diagram illustrating an example of the operation of the control IC 40a when N=0 (gain 1.0). [Figure 12] FIG. 10 is a diagram illustrating an example of the operation of the control IC 40a when N=1 (gain 0.5 times). [Figure 13] 10 is a diagram showing the relationship between the voltage Vca and the voltage Vis in the control IC 40a when a modified example of the setting circuit 62 is used. FIG. [Figure 14] 10 is a diagram showing the relationship between the voltage Vca and the voltage Vis in the control IC 40a when a modified example of the setting circuit 62 is used. FIG. [Figure 15] 10 is a diagram showing the relationship between the voltage Vca and the voltage Vis in the control IC 40a when a modified example of the setting circuit 62 is used. FIG. [Figure 16] FIG. 10 is a diagram illustrating an example of an averaging circuit 67. [Figure 17] FIG. 1 is a diagram illustrating an example of a switching power supply circuit 10b. [Figure 18] FIG. 2 is a diagram illustrating an example of a control IC 40b. DETAILED DESCRIPTION OF THE INVENTION

[0010] At least the following matters will become clear from the description of this specification and the accompanying drawings.

[0011] =====This embodiment===== <<<Outline of the Switching Power Supply Circuit 10a>>> 1 is a diagram showing an example of the configuration of a switching power supply circuit 10a according to one embodiment of the present invention. The switching power supply circuit 10a is an LLC current resonance type power supply circuit that generates an output voltage Vout of a target level to a load 11 from a predetermined input voltage Vin.

[0012] The switching power supply circuit 10a includes capacitors 20, 21, 22, and 32, a resistor 23, NMOS transistors 24 and 25, a transformer 26, a control block 27, diodes 30 and 31, a constant voltage circuit 33, and a light emitting diode .

[0013] Capacitor 20 stabilizes the voltage between the power supply line to which input voltage Vin is applied and the ground line on the ground side, and removes noise, etc. The input voltage Vin is a DC voltage of a predetermined level. Capacitor 21 is a so-called resonant capacitor that forms a resonant circuit with leakage inductance between the primary coil L1 and the secondary coils L2 and L3. Capacitor 21 corresponds to the "first capacitor."

[0014] The capacitor 22 and the resistor 23 constitute a detection circuit that divides and detects the resonant current Icr flowing through the capacitor 21, and the series-connected capacitor 22 and resistor 23 are connected in parallel to the capacitor 21.

[0015] Furthermore, the resistor 23 generates a voltage Vis based on a current obtained by dividing the resonant current Icr. Therefore, the voltage Vis corresponds to the resonant current Icr. When the resonant current Icr flows in the direction of the arrow shown in FIG. 1, the resonant current Icr is referred to as a positive resonant current Icr, and the voltage Vis in this case is a positive voltage. When the resonant current Icr flows in the direction of the arrow, i.e., the resonant current Icr flows through the primary coil L1, the capacitor 22, and the resistor 23 in this order, the direction of the resonant current Icr is positive. When the resonant current Icr flows in the opposite direction to the arrow, i.e., the resonant current Icr flows through the resistor 23, the capacitor 22, and the primary coil L1 in this order, the direction of the resonant current Icr is negative.

[0016] The NMOS transistor 24 is a high-side power transistor, and the NMOS transistor 25 is a low-side power transistor. Specifically, the NMOS transistors 24 and 25 are connected in series between a node to which the input voltage Vin is applied and a node to which the ground voltage is applied. In this embodiment, the NMOS transistors 24 and 25 are used as switching elements, but they may also be PMOS transistors or bipolar transistors, for example. The NMOS transistor 24 corresponds to a "first transistor," and the NMOS transistor 25 corresponds to a "second transistor."

[0017] The transformer 26 includes a primary coil L1, secondary coils L2 and L3, and an auxiliary coil La, and is insulated from the primary coil L1, the secondary coils L2 and L3, and the auxiliary coil La. In the transformer 26, a voltage is generated in the secondary coils L2 and L3 on the secondary side and in the auxiliary coil La in response to a change in voltage across the primary coil L1 on the primary side.

[0018] The primary coil L1 has one end connected to the source of the NMOS transistor 24 and the drain of the NMOS transistor 25, and the other end connected to the source of the NMOS transistor 25 via the capacitor 21.

[0019] Therefore, when switching of the NMOS transistors 24 and 25 starts, there is a change in the voltage of each of the secondary coils L2 and L3 and the auxiliary coil La. The primary coil L1 and the secondary coils L2 and L3 are electromagnetically coupled with opposite polarities, and the primary coil L1 and the auxiliary coil La are electromagnetically coupled with the same polarity.

[0020] The control block 27 is a circuit block for controlling the switching of the NMOS transistors 24 and 25, and will be described in detail later.

[0021] Diodes 30 and 31 rectify the voltages of the secondary coils L2 and L3, and capacitor 32 smoothes the rectified voltage. As a result, a smoothed output voltage Vout is generated in capacitor 32. The output voltage Vout becomes a DC voltage at a target level.

[0022] The constant voltage circuit 33 is a circuit that generates a constant DC voltage, and is configured using, for example, a shunt regulator.

[0023] The light-emitting diode 34 is an element that emits light with an intensity corresponding to the difference between the output voltage Vout and the output of the constant voltage circuit 33, and forms a photocoupler together with a phototransistor 52, which will be described later. In this embodiment, as the level of the output voltage Vout increases, the intensity of the light emitted from the light-emitting diode 34 increases.

[0024] <<<Control Block 27>>> The control block 27 includes a control IC 40a, a diode 50, capacitors 51, 53, and 54, a phototransistor 52, and a resistor 55. The control IC 40a corresponds to a "switching control circuit."

[0025] The control IC 40a is an integrated circuit that controls the switching of the NMOS transistors 24 and 25, and has terminals VCC, GND, FB, IS, CA, HO, LO, and VS.

[0026] A terminal VCC is a terminal to which a power supply voltage Vcc is applied to operate the control IC 40a. The terminal VCC is connected to the cathode of a diode 50 and a capacitor 51, one end of which is grounded. The capacitor 51 is charged with a voltage from the auxiliary coil La of the transformer 26, and the voltage becomes Vcc. The control IC 40a is started by applying a divided voltage of the input voltage Vin, which is obtained by rectifying an AC input, via a terminal not shown, and after starting up, it operates based on the power supply voltage Vcc.

[0027] The terminal GND is a terminal to which a ground voltage is applied, and is connected to, for example, the housing of a device in which the switching power supply circuit 10a is provided.

[0028] The terminal FB generates a feedback voltage Vfb corresponding to the output voltage Vout, and is connected to a phototransistor 52 and a capacitor 53. The phototransistor 52 passes a bias current I1, whose magnitude corresponds to the intensity of light from the light-emitting diode 34, from the terminal FB to ground, and the capacitor 53 is provided to remove noise between the terminal FB and ground. Therefore, the phototransistor 52 operates as a transistor that generates a sink current.

[0029] Terminal IS is a terminal for detecting the current value of the resonant current of the primary coil L1. Here, a voltage corresponding to the current value of the resonant current of the primary coil L1 is generated at the node where capacitor 22 and resistor 23 are connected. Therefore, a voltage Vis corresponding to the current value of the resonant current of the primary coil L1 is applied to terminal IS. Note that voltage Vis corresponds to the "first voltage."

[0030] Terminal CA is a terminal to which a voltage Vca, which is generated based on the resonant current of the primary coil L1 and corresponds to the input power of the switching power supply circuit 10a, is applied. Note that, as will be described in detail later, terminal CA is connected to a capacitor 54 and a resistor 55. Furthermore, voltage Vca corresponds to a "second voltage," and capacitor 54 corresponds to a "second capacitor."

[0031] The terminal HO is a terminal from which a drive signal Vdr1 for driving the NMOS transistor 24 is output, and the gate of the NMOS transistor 24 is connected.

[0032] The terminal LO is a terminal from which a drive signal Vdr2 that drives the NMOS transistor 25 is output, and the gate of the NMOS transistor 25 is connected.

[0033] The terminal VS is a terminal to which the voltage of the connection node connecting the source terminal of the NMOS transistor 24 and the drain terminal of the NMOS transistor 25 is applied, and when the NMOS transistor 24 is turned on, the input voltage Vin is applied, and when the NMOS transistor 25 is turned on, the ground voltage is applied. The terminal VS corresponds to the "first terminal."

[0034] Furthermore, the potential of the voltage Vs at the terminal VS becomes the reference potential of the output voltage of a bootstrap circuit (not shown) for turning on the NMOS transistor 24 when the input voltage Vin is applied to the terminal VS.

[0035] <<<Details of the control IC 40a>>> 2 is a diagram showing an example of a control IC 40a. The control IC 40a is an integrated circuit that switches NMOS transistors 24 and 25 based on the magnitude of the resonance current Icr. The control IC 40a includes resistors 60, 63, and 64, a drive signal output circuit 61, a setting circuit 62, an averaging circuit 65, and an overload detection circuit 66. Note that the terminal VCC is omitted here for convenience.

[0036] ==Resistance 60== The resistor 60 generates a feedback voltage Vfb based on the bias current I1 from the phototransistor 52. A predetermined voltage Vdd is applied to one end of the resistor 60, and the other end is connected to the terminal FB. Therefore, if the resistance value of the resistor 60 is "R", the feedback voltage Vfb generated at the terminal FB is expressed by equation (1).

[0037] Vfb=Vdd-R×I1 (1) As described above, in this embodiment, the current value of the bias current I1 increases in response to an increase in the output voltage Vout, so that when the output voltage Vout increases, the feedback voltage Vfb decreases.

[0038] ==Drive signal output circuit 61== The drive signal output circuit 61 outputs drive signals Vdr1 and Vdr2 for driving the NMOS transistors 24 and 25. Specifically, the drive signal output circuit 61 outputs the drive signals Vdr1 and Vdr2 based on the feedback voltage Vfb, the voltage Vca, and a thinning-out number N, which will be described later. The drive signal output circuit 61 is configured to include an oscillation circuit 70, a detection circuit 71, and a drive circuit 72.

[0039] ===Oscillator Circuit 70=== The oscillator circuit 70 is a voltage-controlled oscillator circuit that outputs an oscillation signal Vosc to the drive circuit 72 based on the input feedback voltage Vfb, for switching the NMOS transistors 24 and 25. The oscillation signal Vosc is, for example, a signal with a high-level (hereinafter referred to as "H" level) duty ratio of 50%. When the level of the voltage Vfb becomes low, the oscillator circuit 70 outputs an oscillation signal Vosc with a high frequency. The oscillation signal Vosc corresponds to a "second oscillation signal."

[0040] ===Detection circuit 71=== The detection circuit 71 outputs a signal Vload indicating the state of the load 11 based on the voltage Vca and the thinning number N to the drive circuit 72 and the overload detection circuit (OLP) 66. The signal Vload is a signal indicating a digital value of several bits calculated from the voltage Vca converted into a digital value by an analog-to-digital converter (not shown) and the thinning number N.

[0041] The details of the detection circuit 71 and the relationship between the voltage Vca, the thinning number N, and the signal Vload will be described later.

[0042] ===Driver Circuit 72=== The drive circuit 72 drives the NMOS transistors 24 and 25 based on the transmission signal Vosc and the signal Vload from the detection circuit 71. The drive circuit 72 will be described in detail later.

[0043] ==Setting Circuit 62== The setting circuit 62 outputs a thinning number N that controls the increase rate (or gain) of the voltage Vca relative to the voltage Vis based on the voltage Vca. Specifically, the setting circuit 62 causes an averaging circuit 65, described below, to average the voltage Vis over a period (hereinafter referred to as the period TA) based on the thinning number N and output the averaged voltage as the voltage Vca. When the load current Iout increases and the voltage Vca rises, the setting circuit 62 increases the thinning number N to lengthen the period TA. On the other hand, when the load current Iout decreases and the voltage Vca drops, the setting circuit 62 decreases the thinning number N to shorten the period TA.

[0044] 3, the setting circuit 62 includes comparators 80 and 82, reference voltage circuits 81 and 83, and an output circuit 84. The comparators 80 and 82 compare the level of the voltage Vca with a predetermined level Vca_h or a predetermined level Vca_l, and the output circuit 84, which will be described later, sets the thinning number N based on the comparison result.

[0045] ===Comparators 80, 82=== When the amplitude of voltage Vis increases and the level of voltage Vca exceeds a predetermined level Vca_h, comparator 80 outputs a comparison result of "H" level. On the other hand, when the level of voltage Vca is lower than the predetermined level Vca_h, comparator 80 outputs a comparison result of "L" level. The predetermined level Vca_h is output by a reference voltage circuit 81 that operates based on the power supply voltage Vdd.

[0046] Furthermore, when the amplitude of voltage Vis decreases and the level of voltage Vca falls below predetermined level Vca_l, comparator 82 outputs a comparison result of "H" level. On the other hand, when the level of voltage Vca is higher than predetermined level Vca_l, comparator 82 outputs a comparison result of "L" level. Note that predetermined level Vca_l is output by a reference voltage circuit 83 that operates based on power supply voltage Vdd. In this embodiment, predetermined level Vca_l is a level (e.g., 2.5 V) that is half of predetermined level Vca_h (e.g., 5 V).

[0047] Furthermore, comparator 80 corresponds to a "first comparison circuit," and comparator 82 corresponds to a "second comparison circuit." Furthermore, predetermined level Vca_h corresponds to a "first reference voltage," and predetermined level Vca_l corresponds to a "second reference voltage." Furthermore, reference voltage circuit 81 corresponds to a "first reference voltage output circuit," and reference voltage circuit 83 corresponds to a "second reference voltage output circuit."

[0048] ===Output Circuit 84=== The output circuit 84 is an up-down counter that changes its count value based on the comparison results of the comparators 80 and 82 and outputs the count value as the thinning-out number N. Specifically, when the comparator 80 outputs a comparison result of "H" level, the output circuit 84 increments the thinning-out number N. On the other hand, when the comparator 82 outputs a comparison result of "H" level, the output circuit 84 decrements the thinning-out number N. However, when the thinning-out number N is 0, the output circuit 84 does not decrement the thinning-out number N even if the comparator 82 outputs a comparison result of "H" level.

[0049] As will be described in detail later, when the thinning number N is incremented, the period (period TA) averaged by the averaging circuit 65 doubles. On the other hand, when the thinning number N is decremented, the period (period TA) averaged by the averaging circuit 65 halves. The thinning number N corresponds to a "setting signal."

[0050] ==Resistors 63, 64== Returning to FIG. 2, resistors 63 and 64 divide voltage Vs to generate voltage Vs_div at the connection point. When NMOS transistor 24 is turned on and NMOS transistor 25 is turned off, voltage Vs becomes the input voltage Vin, and when NMOS transistor 24 is turned off and NMOS transistor 25 is turned on, voltage Vs becomes the ground voltage. That is, depending on whether NMOS transistors 24 and 25 are turned on or off, voltage Vs becomes either the input voltage Vin or the ground voltage. Accordingly, depending on whether NMOS transistors 24 and 25 are turned on or off, voltage Vs_div changes between a voltage corresponding to input voltage Vin and the ground voltage.

[0051] ==Averaging circuit 65== The averaging circuit 65 averages the voltage Vis at a timing according to the voltage Vs_div and outputs the voltage Vca. Specifically, the averaging circuit 65 averages the positive voltage Vis generated when the resonance current Icr flows in the positive direction at a timing according to the voltage Vs_div and at a period TA based on the thinning number N. The averaging circuit 65 then outputs the averaged voltage as the voltage Vca indicating the load current Iout.

[0052] As shown in FIG. 4, the averaging circuit 65 includes a comparator 90, a control circuit 91, and a charge / discharge circuit 92.

[0053] ===Comparator 90=== The comparator 90 is a circuit that outputs a signal clk that changes in the same manner as the voltage Vs, which varies between the input voltage Vin and the ground voltage. Specifically, when the NMOS transistor 24 is turned on and the voltage Vs_div is higher than the reference voltage Vref, the comparator 90 outputs a signal clk at a high level. On the other hand, when the NMOS transistor 25 is turned on and the voltage Vs_div is lower than the reference voltage Vref, the comparator 90 outputs a signal clk at a low level.

[0054] As described above, when the NMOS transistor 24 is turned on, the resonant current Icr flows in the positive direction, and when the NMOS transistor 25 is turned on, the resonant current Icr flows in the negative direction. Therefore, when the resonant current Icr flows in the positive direction, the signal clk is at the "H" level, and when the resonant current Icr flows in the negative direction, the signal clk is at the "L" level. The comparator 90 corresponds to the "oscillation signal output circuit," and the signal clk corresponds to the "first oscillation signal."

[0055] Furthermore, the period during which the signal clk is output at "H" level corresponds to the "first period", and the period during which the signal clk is output at "L" level corresponds to the "second period".

[0056] ===Control circuit 91==== The control circuit 91 outputs the signal sw_ctrl based on the thinning number N and the signal clk. Specifically, the control circuit 91 thins out the “H” level signals included in the signal clk based on the thinning number N corresponding to the voltage Vca, and outputs the result as the signal sw_ctrl.

[0057] In other words, the control circuit 91 shortens or extends the period during which the control signal sw_ctrl is at the “H” level, based on the thinning-out number N. In addition, the signal sw_ctrl controls the rate of increase of the voltage Vca relative to the voltage Vis when the charging / discharging circuit 92, which will be described later, generates the voltage Vca.

[0058] How the control circuit 91 outputs the signal sw_ctrl based on the thinning number N will be described later. The control circuit 91 corresponds to a "control signal output circuit," and the signal sw_ctrl corresponds to a "control signal." The "H" level corresponds to a "first logic level," and the "L" level corresponds to a "second logic level."

[0059] ===Charging and discharging circuit 92=== The charge / discharge circuit 92 averages the voltage Vis, which is detected at the terminal IS and corresponds to the resonance current of the primary coil L1, using the capacitor 54 connected to the terminal CA, and outputs the averaged voltage as a voltage Vca indicating the load current Iout.

[0060] The charge / discharge circuit 92 averages the voltage Vis based on the positive resonance current Icr based on the signal sw_ctrl from the control circuit 91.

[0061] Specifically, the charge / discharge circuit 92 switches the voltage at node A between the voltage Vis at the terminal IS or the ground voltage based on the signal sw_ctrl. Then, the charge / discharge circuit 92 charges or discharges the capacitor 54 connected to the terminal CA via the resistor 103, and outputs the voltage Vca.

[0062] The current value of the resonant current Icr of the primary coil L1 increases in accordance with the input power of the switching power supply circuit 10a. The input power of the switching power supply circuit 10a also increases in accordance with the power consumed by the load 11. Therefore, the voltage Vca increases as the load 11 becomes heavier (i.e., as the load current Iout of the load 11 increases).

[0063] The charge / discharge circuit 92 includes switches 100 and 102 , an inverter 101 , and a resistor 103 .

[0064] The switch 100 is an element that is turned on when the control circuit 91 outputs a high-level signal sw_ctrl. When the switch 100 is turned on, the voltage Va of the node A to which the switches 100 and 102 are connected becomes the voltage Vis of the terminal IS.

[0065] The switch 102 is an element that is turned on when the control circuit 91 outputs a signal sw_ctrl of an “L” level and the inverter 101 outputs a signal of an “H” level. When the switch 102 is turned on, the voltage Va of the node A becomes the ground voltage.

[0066] Resistor 103 is connected between node A and terminal CA, and resistor 103, together with capacitor 54 connected to terminal CA, constitutes an RC integrator circuit that operates with a "time constant τ." If the resistance value of resistor 103 is R1 and the capacitance value of capacitor 54 is C1, then "time constant τ" = R1 × C1. Note that "time constant τ" is set to be sufficiently longer than the period of drive signals Vdr1 and Vdr2 that drive NMOS transistors 24 and 25.

[0067] Therefore, when the control circuit 91 outputs a signal sw_ctrl of “H” level, the charge / discharge circuit 92 charges the capacitor 54 via the resistor 103 with a voltage Vis based on a positive resonance current Icr corresponding to the power consumption of the load 11.

[0068] On the other hand, when the control circuit 91 outputs the signal sw_ctrl at the "L" level, the charge / discharge circuit 92 discharges the capacitor 54 via the resistor 103 at the ground voltage.

[0069] This allows the charge / discharge circuit 92 to average the voltage Vis and output the voltage Vca that indicates the load current Iout.

[0070] Furthermore, resistors 55 and 103 form a voltage divider circuit. Therefore, when the resistance value of resistor 55 is large, the voltage applied to capacitor 54 increases, and as a result, the rate of increase of voltage Vca relative to voltage Vis increases.

[0071] On the other hand, when the resistance value of resistor 55 is small, the voltage applied to capacitor 54 is relatively small compared to when the resistance value of resistor 55 is large, and as a result, the rate of increase of voltage Vca relative to voltage Vis is small. Note that resistor 55 does not necessarily have to be connected to terminal CA.

[0072] <<Operations of the Output Circuit 84 and the Averaging Circuit 65>> Fig. 5 is a flowchart showing an example of the operation of the output circuit 84. Fig. 6 is a diagram illustrating what kind of signal sw_ctrl the control circuit 91 outputs depending on the thinning number N. In Fig. 5, first, when the control IC 40a is started up, the output circuit 84 sets the thinning number N to 0 (S100).

[0073] When the thinning number N is 0, the control circuit 91 outputs the signal sw_ctrl as shown in (A) of Fig. 6. Specifically, when the thinning number N is 0, the control circuit 91 outputs the signal clk as the signal sw_ctrl.

[0074] At this time, the rate of increase of voltage Vca relative to voltage Vis is determined by resistor 55, and this rate of increase is set to a gain of 1.0. Then, output circuit 84 maintains the gain at 1.0 as shown in FIG. 7 until the level of voltage Vca reaches a predetermined level Vca_h.

[0075] When the gain is 1.0, the charge / discharge circuit 92 in Fig. 4 applies the voltage Vis to the terminal CA every time the resonant current Icr flows in the positive direction. Therefore, as the voltage Vis increases, the voltage Vca increases at an increasing rate determined by the resistor 55 as shown in Fig. 7.

[0076] Then, as shown in FIG. 5, the comparator 80 compares whether the level of the voltage Vca is lower than a predetermined level Vca_h (S110).

[0077] If the comparator 80 indicates that the level of the voltage Vca is lower than the predetermined level Vca_h (S110: Yes), the output circuit 84 leaves the thinning number N at 0.

[0078] On the other hand, if the comparator 80 indicates that the level of the voltage Vca is higher than the predetermined level Vca_h (S110: No), the output circuit 84 sets the thinning number N to 1 (S120).

[0079] When the thinning number N is 1, the control circuit 91 outputs the signal sw_ctrl as shown in (B) of Fig. 6. Specifically, when the thinning number N is 1, the control circuit 91 thins out one "H" level signal included in the signal clk and outputs one "H" level signal sw_ctrl while two "H" level signal clk are input. Therefore, the period TA is twice as long as the period when the thinning number N is 0.

[0080] At this time, the rate of increase of voltage Vca relative to voltage Vis is half the rate determined by resistor 55, and this rate of increase is set to a gain of 0.5. In other words, the gain is determined according to period TA. Then, output circuit 84 maintains the gain at 0.5 as shown in FIG. 7 until the level of voltage Vca reaches a predetermined level Vca_h.

[0081] When the gain is 0.5, every time the resonant current Icr flows in the positive direction twice, the charge / discharge circuit 92 in Fig. 4 applies the voltage Vis to the terminal CA. Therefore, as the voltage Vis increases, the voltage Vca increases at a rate that is 1 / 2 the rate determined by the resistor 55, as shown in Fig. 7.

[0082] In this case, the period TA is twice as long as when the thinning number N is 0, and the level of the voltage Vca drops to a predetermined level Vca_l as shown in Fig. 7. This is because the period TA is doubled and the number of times the positive voltage Vis is averaged during a predetermined period is halved.

[0083] Then, as shown in FIG. 5, the comparators 80 and 82 compare whether the level of the voltage Vca is lower than a predetermined level Vca_h and higher than a predetermined level Vca_l (S130).

[0084] If the comparators 80 and 82 indicate that the level of the voltage Vca is lower than the predetermined level Vca_h and higher than the predetermined level Vca_l (S130: Yes), the output circuit 84 leaves the thinning number N at one.

[0085] When the comparator 82 indicates that the level of the voltage Vca is lower than the predetermined level Vca_l, the output circuit 84 sets the thinning number N to 0 (S100).

[0086] In this case, the period TA is 1 / 2 of the period when the thinning number N is 1, and the level of the voltage Vca rises to the predetermined level Vca_h, as shown in Fig. 7. This is because the period TA is 1 / 2 and the number of times the positive voltage Vis is averaged during the predetermined period is doubled.

[0087] When the thinning-out number N becomes 0 (i.e., the gain is 1.0), the charge / discharge circuit 92 in FIG. 4 applies the voltage Vis to the terminal CA every time the resonant current Icr flows in the positive direction. Therefore, as the voltage Vis increases, the voltage Vca increases at an increasing rate determined by the resistor 55. Compared with the increasing rate when the thinning-out number N is 1 (i.e., the gain is 0.5), the increasing rate when the thinning-out number N is 0 (i.e., the gain is 1.0), as shown in FIG. 7, is twice as high.

[0088] Furthermore, as shown in FIG. 5, when the comparator 80 indicates that the level of the voltage Vca is higher than the predetermined level Vca_h, the output circuit 84 sets the thinning number N to 2 (S140).

[0089] When the thinning number N is 2, the control circuit 91 outputs the signal sw_ctrl as shown in (C) of Fig. 6. Specifically, when the thinning number N is 2, the control circuit 91 thins out the "H" level signal included in the signal clk three times while the "H" level signal clk is input four times, and outputs the "H" level signal sw_ctrl once. Therefore, the period TA is twice as long as the period when the thinning number N is 1.

[0090] At this time, the rate of increase of voltage Vca relative to voltage Vis is 1 / 4 of the rate determined by resistor 55, and this rate of increase is set to a gain of 0.25. Then, output circuit 84 maintains the gain at 0.25 as shown in FIG. 7 until the level of voltage Vca reaches a predetermined level Vca_h.

[0091] When the gain is 0.25, the charge / discharge circuit 92 in Fig. 4 applies the voltage Vis to the terminal CA every four times that the resonant current Icr flows in the positive direction. Therefore, as the voltage Vis increases, the voltage Vca increases at a rate that is 1 / 4 of the rate determined by the resistor 55, as shown in Fig. 7.

[0092] Then, as shown in FIG. 5, the comparator 82 compares whether the level of the voltage Vca is higher than a predetermined level Vca_l (S150).

[0093] If the comparator 82 indicates that the level of the voltage Vca is higher than the predetermined level Vca_l (S150: Yes), the output circuit 84 keeps the thinning number N at 2.

[0094] When the comparator 82 indicates that the level of the voltage Vca is lower than the predetermined level Vca_l (S150: No), the output circuit 84 sets the thinning number N to 1 (S120).

[0095] In this case, the period TA is half that when the thinning number N is 2, and therefore, as shown in FIG. 7, the level of the voltage Vca rises to a predetermined level Vca_h.

[0096] ===Detection circuit 71=== Returning to FIG. 2, as described above, the detection circuit 71 outputs a signal Vload indicating the state of the load 11 to the drive circuit 72 and the overload detection circuit (OLP) 66 based on the voltage Vca and the thinning number N.

[0097] Specifically, the detection circuit 71 detects the state of the load 11 based on the voltage Vca, which changes based on the thinning number N, and the thinning number N, and outputs the result to the drive circuit 72 and the overload detection circuit 66 as a signal Vload.

[0098] 8, the signal Vload is a signal indicating a digital value of several bits, and is a signal obtained by converting the voltage Vca, which is determined according to the voltage Vis and the thinning-out number N, according to the thinning-out number N. In other words, the signal Vload is a signal obtained by converting the voltage Vca, whose rate of increase with respect to the voltage Vis changes depending on the thinning-out number N, into a voltage value (shown by the dashed line, for example) at which the rate of increase with respect to the voltage Vis is constant.

[0099] Furthermore, when the load 11 is in a heavy load state, the detection circuit 71 outputs a signal Vload indicating that the load 11 is in a heavy load state. On the other hand, when the load 11 is in a light load state, the detection circuit 71 outputs a signal Vload indicating that the load 11 is in a light load state. The signal Vload corresponds to the "detection result."

[0100] Note that "the load 11 is in a heavy load state" refers to, for example, a state in which the load current Iout flowing through the load 11 is equal to or greater than a predetermined value (e.g., 1 A). Also, "the load 11 is in a light load state" refers to, for example, a state in which the load current Iout flowing through the load 11 is smaller than a predetermined value (e.g., 1 A). Also, "the load 11 is in a no-load state" refers to a state in which the load current Iout flowing through the load 11 is extremely small or 0 (zero) A. Also, although the current value of the load current Iout used to determine whether the load 11 is in a heavy load state or a light load state has been described as, for example, 1 A, this current value can be set in various ways. This setting can be varied by the drive circuit 72 receiving the signal Vload setting a digital threshold for determining the signal Vload. The drive circuit 72 determines whether the load is heavy or light using the signal Vload.

[0101] ===Driver Circuit 72=== 1 based on the transmission signal Vosc and the signal Vload from the detection circuit 71. Specifically, the drive circuit 72 switches the NMOS transistors 24 and 25 in a continuous switching operation in which the drive signals Vdr1 and Vdr2 alternately go high in response to the transmission signal Vosc, as shown in FIG. 9, based on the signal Vload indicating that the load 11 is in a heavy load state. In this case, the drive circuit 72 does not intermittently stop its switching operation.

[0102] Furthermore, based on the signal Vload indicating that the load 11 is in a light load state, the drive circuit 72 switches the NMOS transistors 24 and 25 in response to the transmission signal Vosc so that continuous switching operation and stopping operation in which the switching operation is intermittently stopped are repeated as shown in FIG. 10.

[0103] 9 and 10, the drive circuit 72 is depicted as outputting drive signals Vdr1 and Vdr2 that are generated with a 50% duty cycle according to the transmission signal Vosc and alternately go to the "H" level. However, in reality, the drive circuit 72 has a dead time and outputs drive signals Vdr1 and Vdr2 that are generated with a duty cycle of approximately 50% according to the transmission signal Vosc and alternately go to the "H" level. Note that while FIG. 10 shows the drive signals Vdrv1 and Vdrv2 to have the same number of pulses during switching operation, this is merely an example, and the number of pulses may be different.

[0104] Here, "dead time" refers to the period from when the drive signal Vdr1, which is at "H" level, becomes low level (hereinafter referred to as "L" level) until the drive signal Vdr2 becomes "H" level, and is the period during which both the drive signals Vdr1 and Vdr2 are at "L" level.

[0105] ==Overload Detection Circuit (OLP) 66== The overload detection circuit (OLP) 66 detects (i.e., determines) whether the load 11 is in an overload state based on the signal Vload from the detection circuit 71. Specifically, the overload detection circuit 66 detects whether the load 11 is in an overload state based on whether the value of the signal Vload indicating the state of the load 11, i.e., the value of the load current Iout, is equal to or greater than a predetermined value. The threshold value for detecting whether the load 11 is in an overload state can be set in various ways. This setting can be varied by the overload detection circuit 66 receiving the signal Vload setting a digital threshold value for determining the signal Vload. The overload detection circuit 66 determines whether the load 11 is in an overload state using the signal Vload.

[0106] When it is detected that the load 11 is in an overload state, the overload detection circuit 66 outputs a signal OLP to the drive circuit 72 to turn off the NMOS transistors 24 and 25. The overload detection circuit 66 corresponds to a "determination circuit."

[0107] <<Operation of control IC 40a>> ==When the thinning number N is 0== FIG. 11 is a diagram showing an example of the operation of the control IC 40a when the thinning number N is 0.

[0108] At time t0, the drive circuit 72 of the control IC 40a outputs the drive signal Vdr2 at the "L" level, and the NMOS transistor 25 is turned off.

[0109] Thereafter, the negative resonant current Icr causes the voltage Vs at the terminal VS to rise and reach half the input voltage Vin at time t1. Accordingly, the resistors 63 and 64 in FIG. 2 generate a voltage Vs_div corresponding to the voltage Vs, and the comparator 90 in FIG. 4 outputs a high-level signal clk. Furthermore, because the thinning-out number N is 0, the control circuit 91 outputs the signal clk as the signal sw_ctrl.

[0110] At this time, the switch 100 in FIG. 4 is turned on based on the signal sw_ctrl at the "H" level, and the voltage Va at the node A becomes the voltage Vis.

[0111] At time t2, when the dead time has elapsed since time t0, the drive circuit 72 outputs the drive signal Vdr1 at the “H” level, turning on the NMOS transistor 24. Then, the voltage Vis corresponding to the resonance current Icr flowing in the positive direction becomes positive.

[0112] At time t3 after the drive circuit 72 outputs the drive signal Vdr1 at the "L" level, the positive resonant current Icr causes the voltage Vs at the terminal VS to drop to half the voltage of the input voltage Vin. Accordingly, the resistors 63 and 64 in Fig. 2 generate a voltage Vs_div corresponding to the voltage Vs, and the comparator 90 in Fig. 4 outputs the signal clk at the "L" level.

[0113] At this time, the switch 102 in FIG. 4 is turned on based on the "L" level signal sw_ctrl, and the voltage Va at node A becomes the ground voltage. Then, from time t4 onwards, the same operation is repeated. Therefore, the period TA is the period from time t1 to time t4, and the charge / discharge circuit 92 outputs the voltage Vca based on the voltage Vis. As a result, as described above, the voltage Vca is output with a gain of 1.0 times the magnitude of the voltage Vis.

[0114] ==When the thinning number N is 1== FIG. 12 is a diagram showing an example of the operation of the control IC 40a when the thinning number N is 1.

[0115] The operation from time t10 to time t13 is the same as the operation from time t0 to time t3 in Fig. 11. Note that the voltage Vis is assumed to be twice as high as in Fig. 11.

[0116] At time t14, the negative resonant current Icr causes the voltage Vs at the terminal VS to rise to half the voltage of the input voltage Vin. Accordingly, the resistors 63 and 64 in FIG. 2 generate a voltage Vs_div corresponding to the voltage Vs, and the comparator 90 in FIG. 4 outputs a high-level signal clk. However, because the thinning-out number N is 1, the control circuit 91 does not output the signal clk as the signal sw_ctrl. Therefore, the voltage Va at the node A remains at ground voltage.

[0117] At time t15 after the drive circuit 72 of the control IC 40a outputs the drive signal Vdr1 at the "L" level, the positive resonant current Icr causes the voltage Vs at the terminal VS to drop to half the voltage of the input voltage Vin. Accordingly, the resistors 63 and 64 in Fig. 2 generate the voltage Vs_div corresponding to the voltage Vs, and the comparator 90 in Fig. 4 outputs the signal clk at the "L" level.

[0118] At this time, switch 102 in FIG. 4 is turned on based on the "L" level signal sw_ctrl, and voltage Va at node A remains at ground voltage. Similar operations are then repeated from time t16 onwards. Therefore, cycle TA is the period from time t11 to time t16, and charge / discharge circuit 92 outputs voltage Vca based on voltage Vis. As a result, as described above, voltage Vca is output with a gain of 0.5 times the magnitude of voltage Vis.

[0119] <<Modification of Setting Circuit 62>> In the above-described embodiment, the period TA doubles each time the level of the voltage Vca exceeds the predetermined level Vca_h and the thinning number N is incremented. Then, by doubling the period TA, the level of the voltage Vca becomes a predetermined level Vca_l, which is half the level of the predetermined level Vca_h.

[0120] In such a case, if the voltage Vca is affected by noise and fluctuates, there is a possibility that the thinning number N will be incremented or decremented frequently. Therefore, in order to suppress the influence of noise, a predetermined level Vca_l_delta, which is lower than the predetermined level Vca_l, may be used instead of the predetermined level Vca_l. The operation of the setting circuit 62 when the predetermined level Vca_l_delta is used will be described below as a modified example of the setting circuit 62.

[0121] 13 to 15 are diagrams showing the relationship between the voltage Vca and the voltage Vis in the control IC 40a when a modified example of the setting circuit 62 is used.

[0122] 3, the reference voltage circuit 83 outputs a level that is half the predetermined level Vca_h (e.g., 5 V) as the predetermined level Vca_l (e.g., 2.5 V). However, in a modified example of the setting circuit 62, the reference voltage circuit 83 outputs a level that is lower than half the predetermined level Vca_h as the predetermined level Vca_l_delta (e.g., 2.4 V).

[0123] The following describes how the control IC 40a outputs the voltage Vca in such a case. Fig. 13 shows the operation when the state of the load 11 changes from no load to a heavy load, and Fig. 14 shows the operation when the state of the load 11 changes from a heavy load to no load. Fig. 15 is a diagram combining Figs. 13 and 14.

[0124] First, a case where the state of the load 11 changes from no load to a heavy load will be described with reference to Fig. 13. If the voltage Vis increases while the setting circuit 62 is outputting the thinning number N of "0", the averaging circuit 65 outputs a gradually increasing voltage Vca. Then, the setting circuit 62 outputs the thinning number N of "0" until the level of the voltage Vca reaches a predetermined level Vca_h.

[0125] Thereafter, when the voltage Vis increases further, the averaging circuit 65 outputs an even larger voltage Vca, so the setting circuit 62 outputs the thinning number N of "1." As a result, the level of the voltage Vca drops to the predetermined level Vca_l.

[0126] As the voltage Vis increases, the setting circuit 62 increases the thinning number N. Each time the thinning number N increases, the level of the voltage Vca decreases to a predetermined level Vca_l.

[0127] Next, a case where the state of the load 11 changes from a heavy load to no load will be described with reference to Fig. 14. If the voltage Vis decreases while the setting circuit 62 is outputting, for example, a thinning-out number N of "2," the averaging circuit 65 outputs a gradually decreasing voltage Vca. Then, the setting circuit 62 outputs a thinning-out number N of "2" until the level of the voltage Vca reaches a predetermined level Vca_l_delta.

[0128] Thereafter, when the voltage Vis decreases further, the averaging circuit 65 outputs an even smaller voltage Vca, so the setting circuit 62 outputs the thinning number N of "1." As a result, the level of the voltage Vca rises to a level Vca_x below the predetermined level Vca_h.

[0129] As the voltage Vis decreases, the setting circuit 62 decreases the thinning number N. Each time the thinning number N decreases, the level of the voltage Vca rises to a level Vca_x below the predetermined level Vca_h. This prevents the setting circuit 62 from outputting the original thinning number N again immediately after switching the thinning number N. This prevents the setting circuit 62 from frequently incrementing or decrementing the thinning number N, thereby suppressing the effects of noise on the voltage Vca.

[0130] 15, in the modified example of the setting circuit 62, when the voltage Vis increases, that is, when the load 11 becomes heavier, the level of the voltage Vca reaches a predetermined level Vca_h, and the thinning-out number N changes. Then, when the thinning-out number N changes, the level of the voltage Vca drops to a predetermined level Vca_l.

[0131] 15, when the voltage Vis decreases, that is, when the load 11 becomes lighter, the level of the voltage Vca reaches a predetermined level Vca_l_delta, and the thinning-out number N changes. When the thinning-out number N changes, the level of the voltage Vca rises to a level Vca_x.

[0132] From the above, the level of voltage Vca when the thinning-out number N changes and the level that voltage Vca reaches when the thinning-out number N changes differ depending on whether the state of load 11 is moving toward a heavy load or a light load. Therefore, even if voltage Vis fluctuates due to noise, it is possible to prevent frequent fluctuations in thinning-out number N and similar fluctuations in voltage Vca.

[0133] <<Modification of the averaging circuit 65>> Fig. 16 is a diagram showing an example of an averaging circuit 67 which is a modified example of the averaging circuit 65. In Fig. 16, the same components as those in Fig. 4 are denoted by the same reference numerals.

[0134] The averaging circuit 67 further includes a level shift circuit (LS) 110, a bias circuit (BIAS) 111, and a buffer circuit 112. The level shift circuit 110 is provided between the terminal IS and the switch 100, and shifts the level of the voltage Va, which varies around 0 V (zero volts).

[0135] The level shift circuit 110 shifts the voltage Vis so that the central level of the voltage Vis is at a predetermined level, where the "predetermined level" is, for example, half the level of the power supply voltage Vdd (e.g., 5 V) (Vdd / 2=2.5 V).

[0136] The level shift circuit 110 is, for example, a voltage divider circuit in which a power supply voltage Vdd is applied to the high voltage side and a voltage Vis is applied to the low voltage side.

[0137] The bias circuit 111 is provided between the terminal GND and the switch 102, and applies a predetermined voltage (for example, 1 V) to the level of the ground voltage. The bias circuit 111 is, for example, a voltage source that generates the predetermined voltage.

[0138] The buffer circuit 112 amplifies the voltage Va at the node A and outputs it as a voltage Vca via a resistor 103. The buffer circuit 112 is an arithmetic circuit configured, for example, with a plurality of operational amplifiers. This allows the averaging circuit 67 to average the voltage from the level shift circuit 110, which corresponds to the voltage Vis, and a predetermined voltage from the bias circuit 111, and to output the level of the voltage Vca within a desired range.

[0139] =====Other embodiments===== <<<Outline of the switching power supply circuit 10b>>> Fig. 17 is a diagram showing an example of a switching power supply circuit 10b, which is a modified example of the switching power supply circuit 10a. In Fig. 17, the same reference numerals are used for the same components as those in Fig. 1. Therefore, the same components will not be described.

[0140] The switching power supply circuit 10b further includes resistors 56 and 57 that divide the voltage generated in the auxiliary winding La. A voltage Vvw is generated at the connection point between the resistors 56 and 57. The control IC 40b further includes a terminal VW, and the voltage Vvw is applied to the terminal VW of the control IC 40b. The control IC 40b uses the voltage Vvw applied to the terminal VW to suppress so-called off-resonance.

[0141] Here, the primary coil L1 and the auxiliary coil La are electromagnetically coupled with the same polarity. Therefore, when a positive resonance current Icr flows through the primary coil L1, a positive voltage is generated in the auxiliary coil La. As a result, when the NMOS transistor 24 is turned on and the voltage Vs becomes the input voltage Vin, the auxiliary coil La also generates a positive voltage. Therefore, the voltage Vvw changes with the same polarity and phase as the voltage Vs.

[0142] <<<Details of Control IC 40b>>> Fig. 18 is a diagram showing an example of a control IC 40b. In Fig. 18, the same reference numerals are used to designate the same components as in Fig. 2, and the same components will not be described again.

[0143] The averaging circuit 65 in FIG. 18 uses the voltage Vvw instead of the voltage Vs to generate the signal sw_ctrl. The other circuits of the control IC 40b operate in the same manner as the circuits of the control IC 40a. This allows the control IC 40b to achieve the same operation as the control IC 40a by using the voltage Vvw instead of the voltage Vs. The terminal VW corresponds to the "second terminal."

[0144] ===Summary=== The switching power supply circuit 10a of this embodiment has been described above. The control IC 40a includes an averaging circuit 65, a setting circuit 62, and a drive signal output circuit 61. The control IC 40a changes the increase rate of the voltage Vca as the voltage Vis increases, i.e., as the load current Iout increases. When the load 11 is in a state close to no load, the control IC 40a outputs the voltage Vca at the largest increase rate, so that the state of the load 11 can be detected accurately even when the voltage Vis is small. Therefore, the control IC 40a can detect the state of the load with high accuracy.

[0145] The setting circuit 62 also includes comparators 80 and 82 and an output circuit 84. This allows the control IC 40a to determine the thinning number N in accordance with changes in the voltage Vca, and to change the rate of increase of the voltage Vca.

[0146] Furthermore, the output circuit 84 outputs the thinning number N so as to change the period TA based on the voltage Vca, thereby enabling the control IC 40a to change the rate of increase of the voltage Vca based on the voltage Vca.

[0147] The setting circuit 62 further includes reference voltage circuits 81 and 83. This allows the control IC 40a to change the thinning number N with high precision.

[0148] The output circuit 84 is an up-down counter, which allows the output circuit 84 to output the thinning number N using a simple circuit.

[0149] The averaging circuit 65 also includes a comparator 90, a control circuit 91, and a charge / discharge circuit 92. The averaging circuit 65 generates a signal sw_ctrl based on the thinning number N, thereby changing the period TA and changing the rate of increase of the voltage Vca.

[0150] The control IC 40a also has a terminal VS. The averaging circuit 65 of the control IC 40a generates a signal sw_ctrl based on the voltage VS, thereby outputting the voltage Vca from the voltage Vis, which is a positive voltage.

[0151] The control IC 40b also has a terminal VW that receives the voltage from the auxiliary coil La. The averaging circuit 65 of the control IC 40b can output a voltage Vca from the voltage Vis, which is a positive voltage, based on the voltage Vvw, similar to the averaging circuit 65 of the control IC 40a.

[0152] The drive signal output circuit 61 also includes an oscillation circuit 70, a detection circuit 71, and a drive circuit 72. The detection circuit 71 outputs a signal Vload based on the thinning number N and the voltage Vca. This allows the drive circuit 72 to switch the NMOS transistors 24 and 25 according to the state of the load 11.

[0153] The control IC 40a also includes an overload detection circuit 66. When the overload detection circuit 66 outputs a signal OLP indicating that the load 11 is in an overload state, the drive circuit 72 turns off the NMOS transistors 24 and 25. This allows the control IC 40a to protect the load 11.

[0154] The above-described embodiments are intended to facilitate understanding of the present invention and are not intended to limit the present invention. Furthermore, the present invention may be modified or improved without departing from the spirit thereof, and the present invention includes equivalents thereof. [Explanation of symbols]

[0155] 10a, 10b Switching power supply circuit 11 Load 20, 21, 22, 32, 51, 53, 54 capacitors 23,55~57,60,63,64,103 Resistance 24,25 NMOS transistor 26 Transformer 27 Control Blocks 30, 31, 50 Diodes 33 Constant voltage circuit 34 Light-emitting diode 52 Phototransistor 61 Drive signal output circuit 62 Setting circuit 65 Averaging circuit 66 Overload detection circuit 67 Averaging circuit 70 Oscillator Circuit 71 Detection circuit 72 Drive circuit 80, 82, 90 Comparator 81,83 Reference voltage circuit 84 Output circuit 91 Control circuit 92 Charge / discharge circuit 100,102 Switch 101 Inverter 110 Level shift circuit 111 Bias circuit 112 Buffer Circuit

Claims

1. A switching control circuit for controlling switching of the first and second transistors of a power supply circuit including a transformer including a primary coil and a secondary coil, first and second transistors for controlling a current in the primary coil, and a resonant circuit including the primary coil and a first capacitor, the power supply circuit generating an output voltage of a target level on a secondary side, an averaging circuit that averages a first voltage corresponding to a resonance current flowing in the power supply circuit for a first period, over a period based on a setting signal, and outputs the averaged first voltage as a second voltage indicating a load current flowing in a load of the power supply circuit; a setting circuit that outputs the setting signal based on the second voltage, which lengthens the period when the load current increases; a drive signal output circuit that outputs a drive signal for driving the first and second transistors based on a feedback voltage corresponding to the output voltage, the second voltage, and the setting signal; a switching control circuit including:

2. 2. The switching control circuit according to claim 1, The setting circuit a first comparison circuit that compares the second voltage with a first reference voltage; a second comparison circuit that compares the second voltage with a second reference voltage that is lower than the first reference voltage; an output circuit that outputs the setting signal to lengthen the period when the second voltage becomes the first reference voltage, and outputs the setting signal to shorten the period when the second voltage becomes the second reference voltage; a switching control circuit including:

3. 3. The switching control circuit according to claim 2, The output circuit When the second voltage reaches the first reference voltage, the setting signal for doubling the period is output, and when the second voltage reaches the second reference voltage, the setting signal for halving the period is output. Switching control circuit.

4. 4. The switching control circuit according to claim 3, a first reference voltage output circuit that outputs the first reference voltage; a second reference voltage output circuit that outputs the second reference voltage at a level that is lower than half the level of the first reference voltage; a switching control circuit including:

5. The switching control circuit according to any one of claims 2 to 4, The output circuit an up-down counter that changes a count value indicating the period when the second voltage becomes the first reference voltage or when the second voltage becomes the second reference voltage, and outputs the count value as the setting signal; Switching control circuit.

6. The switching control circuit according to any one of claims 1 to 5, The averaging circuit an oscillation signal output circuit that outputs a first oscillation signal whose logic level changes between the first period and the second period; a control signal output circuit that outputs a control signal that is at a first logic level during the first period in the cycle based on the first oscillation signal and the setting signal; a charge / discharge circuit that charges a second capacitor, on which the second voltage is generated, with the first voltage based on the control signal of the first logic level, and discharges the second capacitor based on the control signal of a second logic level; a switching control circuit including:

7. 7. A switching control circuit according to claim 6, the switching control circuit is an integrated circuit having a first terminal connected to a connection node between the first transistor and the second transistor, the oscillation signal output circuit outputs the first oscillation signal based on the voltage of the first terminal. Switching control circuit.

8. 7. A switching control circuit according to claim 6, the transformer includes an auxiliary coil electromagnetically coupled to the primary coil or the secondary coil, the switching control circuit is an integrated circuit having a second terminal to which a voltage from the auxiliary coil is applied, the oscillation signal output circuit outputs the first oscillation signal based on the voltage of the second terminal. Switching control circuit.

9. The switching control circuit according to any one of claims 1 to 8, The drive signal output circuit an oscillation circuit that outputs a second oscillation signal having a frequency corresponding to the feedback voltage; a detection circuit that detects a state of the load based on the second voltage and the setting signal; a drive circuit that drives the first and second transistors based on the detection result of the detection circuit and the second oscillation signal; a switching control circuit including:

10. 10. The switching control circuit of claim 9, a determination circuit that determines whether the load current is equal to or greater than a predetermined value based on the detection result of the detection circuit; The drive circuit When the determination circuit determines that the load current is equal to or greater than the predetermined value, the first and second transistors are turned off. Switching control circuit.

11. a transformer including a primary coil and a secondary coil; first and second transistors for controlling the current in the primary coil; a resonant circuit including the primary coil and a first capacitor; a switching control circuit for controlling switching of the first and second transistors; A power supply circuit that generates an output voltage of a target level on a secondary side, The switching control circuit an averaging circuit that averages a first voltage corresponding to a resonance current flowing in the power supply circuit for a first period, over a period based on a setting signal, and outputs the averaged first voltage as a second voltage indicating a load current flowing in a load of the power supply circuit; a setting circuit that outputs the setting signal based on the second voltage, which lengthens the period when the load current increases; a drive signal output circuit that outputs a drive signal for driving the first and second transistors based on a feedback voltage corresponding to the output voltage, the second voltage, and the setting signal; A power supply circuit including:

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