Semiconductor Devices

Abstract

To provide a semiconductor device in which the increase in sheet resistance can be suppressed even with a thinner barrier layer.SOLUTION: A semiconductor device has a channel layer, a barrier layer provided above the channel layer, a protection layer provided above the barrier layer, and an insulating layer provided above the protection layer, and the composition of the barrier layer is Inx1Alx2Ga1-x1-x2N (0.00≤x1≤0.20 and 0.10≤x2≤1.00), and the composition of the protection layer is Iny1Aly2Ga1-y1-y2N (0.00≤y1≤0.20, 0.10≤y2≤1.00, x2<y2) and the protection layer is an amorphous layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Many reports have been published on field-effect transistors, particularly high electron mobility transistors (HEMTs), which use nitride semiconductors as semiconductor devices. Known nitride semiconductor HEMTs use a GaN layer as the channel layer and an AlGaN or InAlGaN layer as the barrier layer. An InAlGaN layer is easier to lattice match with a GaN layer than an AlGaN layer, even when the Al composition is high, and is therefore preferred for achieving a high concentration of two-dimensional electron gas (2DEG).

[0003] The current gain cutoff frequency f, which is an index of the high-frequency characteristics of a HEMT T is expressed by the following formula (1). C in formula (1) gs is the gate-source capacitance, and g m is the mutual conductance. Also, the mutual conductance g m is expressed by the following formula (2). ε in formula (2) s is the dielectric constant, and W g is the gate width, and ν s is the saturated drift velocity, d is the thickness of the barrier layer, and Δd is the thickness of the 2DEG.

[0004]

number

[0005]

number

[0006] As can be seen from equation (1), the mutual conductance g m By increasing the current gain cutoff frequency f TBy thinning the barrier layer, the transconductance g m That is, by making the barrier layer thinner, high frequency characteristics can be improved. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-34201 [Patent Document 2] Japanese Patent Application Laid-Open No. 2017-147320 [Patent Document 3] US Patent Application Publication No. 2006 / 0011915 [Non-patent literature]

[0008] [Non-Patent Document 1] H. Wang, FJ Lumbantoruan, T. Hsieh, C. Wu, Y. Lin and EY Chang, "High-Performance LPCVD-SiNx / InAlGaN / GaN MIS-HEMTs with 850-V 0.98-mΩ·cm2 for Power Device Applications," in IEEE Journal of the Electron Devices Society, 6, 1136-1141, (2018) Summary of the Invention [Problem to be solved by the invention]

[0009] However, an insulating layer such as a SiN layer is formed on the barrier layer by plasma chemical vapor deposition (CVD). The InAlGaN layer is more susceptible to plasma damage on the surface than the AlGaN layer. If there are defects due to damage on the surface of the barrier layer, the electron mobility of the 2DEG may decrease, and the sheet resistance may increase. As described above, thinning the barrier layer is effective for improving high-frequency characteristics. However, the thinner the barrier layer, the smaller the distance between the surface of the barrier layer and the 2DEG. Therefore, when the barrier layer is thinned, in particular, the 2DEG is easily affected by the defects on the surface of the barrier layer, and the sheet resistance is likely to increase. Although it has been proposed to form the insulating layer by thermal CVD to suppress damage, the InAlGaN layer is also susceptible to thermal damage, and the sheet resistance increases.

[0010] An object of the present disclosure is to provide a semiconductor device capable of suppressing an increase in sheet resistance even when the barrier layer is thinned.

Means for Solving the Problems

[0011] [[ID= (10]] According to one embodiment of the present disclosure, a channel layer, a barrier layer provided above the channel layer, and provided on the barrier layer , in contact with the barrier layer a protective layer, and provided on the protective layer , in contact with the protective layer an insulating layer, a gate electrode, a source electrode, and a drain electrode provided above the barrier layer; having, the composition of the barrier layer is In x1 Al x2 Ga 1-x1-x2 N (0.00 ≦ x1 ≦ 0.20, 0.10 ≦ x2 ≦ 1.00), the composition of the protective layer is In y1 Al y2 Ga 1-y1-y2 N (0.00 ≦ y1 ≦ 0.20, 0.10 ≦ y2 ≦ 1.00, x2 < y2), a two-dimensional electron gas exists in the channel layer below the gate electrode when no voltage is applied to the gate electrode; A semiconductor device is provided in which the protective layer is an amorphous layer.

Effects of the Invention

[0012] According to the present disclosure, even if the barrier layer is thin, an increase in sheet resistance can be suppressed. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a cross-sectional view showing a semiconductor device according to a first embodiment. [Figure 2] 1A to 1C are cross-sectional views (part 1) illustrating a method for manufacturing a semiconductor device according to a first embodiment. [Figure 3] 5A and 5B are cross-sectional views (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 4] 5A to 5C are cross-sectional views (part 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 5] 4A and 4B are cross-sectional views (part 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] 5 is a cross-sectional view (part 5) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] 6 is a cross-sectional view (part 6) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] 10 is a cross-sectional view (part 7) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 9] 8 is a cross-sectional view (part 8) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 10] FIG. 10 is a diagram showing changes in sheet resistance. [Figure 11] FIG. 10 is a cross-sectional view showing a semiconductor device according to a modified example of the first embodiment. [Figure 12] FIG. 4 is a cross-sectional view showing a semiconductor device according to a second embodiment. [Figure 13] 5A to 5C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a second embodiment. [Figure 14] FIG. 10 is a diagram showing a discrete package according to a third embodiment. [Figure 15] FIG. 10 is a wiring diagram showing a PFC circuit according to a fourth embodiment. [Figure 16] FIG. 10 is a wiring diagram showing a power supply device according to a fifth embodiment. [Figure 17] FIG. 10 is a wiring diagram showing an amplifier according to a sixth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In this specification and drawings, components having substantially the same functional configurations are designated by the same reference numerals, and redundant description may be omitted.

[0015] (First embodiment) A first embodiment will be described. The first embodiment relates to a semiconductor device including a high electron mobility transistor (HEMT). Fig. 1 is a cross-sectional view showing the semiconductor device according to the first embodiment.

[0016] In the semiconductor device 100 according to the first embodiment, as shown in FIG. 1 , a nitride semiconductor stacked structure 107 is formed above a substrate 101. The nitride semiconductor stacked structure 107 includes a nucleation layer 102, a channel layer 103, a spacer layer 104, a barrier layer 105, and a protective layer 106. The nucleation layer 102 is formed on the substrate 101. The channel layer 103 is formed on the nucleation layer 102. The spacer layer 104 is formed on the channel layer 103. The barrier layer 105 is formed on the spacer layer 104. The protective layer 106 is formed on the barrier layer 105.

[0017] The substrate 101 is, for example, a semi-insulating SiC substrate. The nucleation layer 102 is, for example, an AlN layer having a thickness of 5 nm to 150 nm. The channel layer 103 is, for example, a GaN layer having a thickness of 1 μm to 5 μm. The spacer layer 104 is, for example, an AlN layer having a thickness of 0.5 nm to 3 nm. z Ga 1-z The spacer layer 104 is, for example, an AlGaN layer having a thickness of 0.5 nm or more and 3 nm or less, and an Al composition z of 0.40 or more and 1.00 or less. The barrier layer 105 is, for example, an InGaN layer having a thickness of 4 nm to 10 nm. x1 Al x2 Ga 1-x1-x2It is an N-layer (0.00≦x1≦0.20, 0.10≦x2≦1.00). That is, the barrier layer 105 is, for example, an InAlGaN layer with a thickness of 4 nm or more and 10 nm or less, an In composition x1 of 0.00 or more and 0.20 or less, and an Al composition x2 of 0.10 or more and 1.00 or less.

[0018] The protective layer 106 is, for example, an amorphous In y1 Al y2 Ga 1-y1-y2 N-layer (0.00≦y1≦0.20, 0.10≦y2≦1.00, x2<y2). That is, the protective layer 106 is, for example, an amorphous InAlGaN layer with a thickness of 2 nm or more and 6 nm or less, an In composition y1 of 0.00 or more and 0.20 or less, and an Al composition y2 of 0.10 or more and 1.00 or less. The Al composition y2 of the protective layer 106 is larger than the Al composition x2 of the barrier layer 105.

[0019] The channel layer 103, the spacer layer 104, and the barrier layer 105 have an a-axis in a direction parallel to the main surface of the channel layer 103 and a c-axis in a direction perpendicular to the main surface of the channel layer 103. On the other hand, since the protective layer 106 is an amorphous layer, it does not have a polarization aligned in the direction parallel to the c-axis of the channel layer 103.

[0020] An element isolation region that defines an element region is formed in the nitride semiconductor layer structure 107. In the element region, an opening 106s for a source and an opening 106d for a drain are formed in the protective layer 106. A source electrode 108 is formed in the opening 106s, and a drain electrode 109 is formed in the opening 106d. An insulating layer 110 that covers the source electrode 108 and the drain electrode 109 is formed on the protective layer 106. An opening 110g is formed in the insulating layer 110 at a position between the source electrode 108 and the drain electrode 109 in plan view, and a gate electrode 111 that contacts the protective layer 106 through the opening 110g is formed on the insulating layer 110.

[0021] The source electrode 108 and the drain electrode 109 include, for example, a Ta film having a thickness of 10 nm to 50 nm and an Al film having a thickness of 100 nm to 500 nm thereon, and are in ohmic contact with the nitride semiconductor stacked structure 107. The gate electrode 111 includes, for example, a Ni film having a thickness of 10 nm to 50 nm and an Au film having a thickness of 300 nm to 500 nm thereon. The insulating layer 110 includes, for example, a layer of a nitride of Si, Al, Hf, Zr, Ti, Ta, or W, and is preferably a Si nitride (SiN) layer. The thickness of the insulating layer 110 is, for example, 2 nm to 500 nm, and preferably about 100 nm.

[0022] In the semiconductor device 100, when no voltage is applied to the gate electrode 111, a 2DEG exists in the channel layer 103 below the gate electrode 111. In other words, the semiconductor device 100 operates normally on.

[0023] Next, a method for manufacturing the semiconductor device 100 according to the first embodiment will be described. Figures 2 to 9 are cross-sectional views showing the method for manufacturing the semiconductor device 100 according to the first embodiment.

[0024] First, as shown in FIG. 2, a nitride semiconductor stacked structure 107 is formed on a substrate 101. In forming the nitride semiconductor stacked structure 107, a nucleation layer 102, a channel layer 103, a spacer layer 104, a barrier layer 105, and a protective layer 106 are formed by, for example, metal organic vapor phase epitaxy (MOVPE). When growing the nitride semiconductor stacked structure 107, a mixed gas of trimethylgallium (TMGa) gas, which is a Ga source, and ammonia (NH) gas, which is an N source, is used as the source gas for growing the GaN layer. A mixed gas of trimethylaluminum (TMAl) gas, which is an Al source, and NH is used as the source gas for growing the AlN layer. A mixed gas of TMAl gas, TMGa gas, and NH is used as the source gas for growing the AlGaN layer. A mixed gas of TMAl gas, TMGa gas, and NH is used as the source gas for growing the InAlGaN layer. The supply and flow rates of TMAl gas, TMGa gas, and TMIn gas are appropriately determined depending on the composition of the nitride semiconductor layer to be grown. Hydrogen (H2) gas or nitrogen (N2) gas is used as the carrier gas. For example, the growth pressure is approximately 1 kPa to 100 kPa, and the growth temperature is approximately 300°C to 1200°C. However, the growth temperature of the protective layer 106 is lower than the growth temperatures of the nucleation layer 102, channel layer 103, spacer layer 104, and barrier layer 105, and the protective layer 106 is an amorphous layer. The growth temperature of the protective layer 106 is, for example, 350°C.

[0025] Next, an isolation region that defines an element region is formed in the nitride semiconductor laminate structure 107. In forming the isolation region, for example, a photoresist pattern that exposes the region where the isolation region is to be formed is formed on the nitride semiconductor laminate structure 107, and ions such as Ar are implanted using this pattern as a mask. Dry etching using a chlorine-based gas may also be performed using this pattern as an etching mask.

[0026] 3, a surface protective film 121 is formed on the protective layer 106. The surface protective film 121 includes a layer of an oxide, nitride, or oxynitride of, for example, Si, Al, Hf, Zr, Ti, Ta, or W, and is preferably a Si oxide (SiO2) layer. The surface protective film 121 can be formed by, for example, a plasma CVD method. The surface protective film 121 may also be formed by an atomic layer deposition (ALD) method or a sputtering method.

[0027] 4, openings 121s and 121d are formed in the surface protective film 121, and openings 106s and 106d are formed in the protective layer 106. In forming the openings 121s, 121d, 106s, and 106d, for example, a photoresist pattern exposing regions where the openings 106s and 106d are to be formed is formed on the surface protective film 121 by photolithography. Then, using this pattern as an etching mask, dry etching is performed using a fluorine-based gas or a chlorine-based gas.

[0028] Next, as shown in FIG. 5, the surface protection film 121 is removed.

[0029] Thereafter, as shown in FIG. 6, a source electrode 108 is formed in the opening 106s, and a drain electrode 109 is formed in the opening 106d. The source electrode 108 and the drain electrode 109 can be formed by, for example, a lift-off method. That is, a photoresist pattern exposing the regions where the source electrode 108 and the drain electrode 109 are to be formed is formed, and a metal film is formed by evaporation using this pattern as a growth mask, and this pattern is then removed together with the metal film thereon. To form the metal film, for example, a Ta film is formed, and then an Al film is formed thereon. Next, for example, a heat treatment is performed in a nitrogen atmosphere at 400°C to 1000°C (for example, 550°C) to establish ohmic characteristics.

[0030] 7, an insulating layer 110 is formed on the protective layer 106 to cover the source electrode 108 and the drain electrode 109. The insulating layer 110 is formed by, for example, a plasma CVD method. The insulating layer 110 may also be formed by an ALD method or a sputtering method. The formation of the insulating layer 110 increases the concentration of the 2DEG 150 near the top surface of the channel layer 103 below the region between the source electrode 108 and the drain electrode 109.

[0031] 8, openings 110g are formed in the insulating layer 110. In forming the openings 110g, for example, a photoresist pattern exposing the region where the openings 110g are to be formed is formed on the insulating layer 110 by photolithography, and then dry etching is performed using a fluorine-based gas or a chlorine-based gas with this pattern as an etching mask. Instead of dry etching, wet etching using hydrofluoric acid or buffered hydrofluoric acid may be performed.

[0032] 9, a gate electrode 111 is formed on the insulating layer 110, contacting the protective layer 106 through the opening 110g. The gate electrode 111 can be formed by, for example, a lift-off method. That is, a photoresist pattern exposing the region where the gate electrode 111 is to be formed is formed, and a metal film is formed by evaporation using this pattern as a growth mask, and this pattern is then removed together with the metal film on top. To form the metal film, for example, a Ni film is formed, and then an Au film is formed on top of that.

[0033] In this manner, the semiconductor device 100 according to the first embodiment can be manufactured.

[0034] Here, the function and effect of the protective layer 106 will be described with reference to a reference example. In the reference example, the formation of the protective layer 106 is omitted, and the insulating layer 110 is formed on the barrier layer 105 by plasma CVD so as to be in direct contact with the barrier layer 105. Here, a 6-nm-thick InAlGaN layer is used as the barrier layer 105, a 4-nm-thick amorphous AlN layer is used as the protective layer 106, and a SiN layer is used as the insulating layer 110.

[0035] FIG. 10 shows the change in sheet resistance in the first embodiment and the reference example. FIG. 10 shows the sheet resistance before and after the formation of the insulating layer 110. As shown in FIG. 10, in the first embodiment (dashed line), the sheet resistance decreases as the insulating layer 110 is formed. This is because the formation of the insulating layer 110 changes the band structure of the nitride semiconductor stacked structure 107, increasing the concentration of the 2DEG. On the other hand, in the reference example (solid line), the sheet resistance increases as the insulating layer 110 is formed. This is because the formation of the insulating layer 110 changes the band structure of the nitride semiconductor stacked structure 107, increasing the concentration of the 2DEG, but because plasma-induced defects occur on the surface of the barrier layer 105 during the formation of the insulating layer 110, reducing electron mobility.

[0036] Furthermore, in the reference example, since the insulating layer 110 is in direct contact with the barrier layer 105, interdiffusion occurs between the Si contained in the insulating layer 110 and the Ga contained in the barrier layer 105. The Si diffused into the barrier layer 105 functions as an n-type impurity and can become an electron trap for the 2DEG. On the other hand, in the first embodiment, the protective layer 106 is provided between the insulating layer 110 and the barrier layer 105, so that interdiffusion such as that in the reference example can be suppressed.

[0037] 10, before the formation of the insulating layer 110, the sheet resistance of the first embodiment is lower than that of the reference example, which is due to a change in the band structure caused by the formation of the protective layer 106. Thus, according to the first embodiment, the change in the band structure caused by the formation of the protective layer 106 also increases the concentration of the 2DEG, thereby making it possible to keep the sheet resistance low.

[0038] The composition of the barrier layer 105 is In. x1 Al x2 Ga 1-x1-x2It is represented by N(0.00≦x1≦0.20, 0.10≦x2≦1.00), and it is preferable that the Al composition x2 is 0.10 or more and 0.70 or less, and the barrier layer 105 contains Ga. Also, the Al composition x2 may be 0.15 or more and 1.00 or less, or 0.15 or more and 0.70 or less.

[0039] If the thickness of the barrier layer 105 exceeds 10 nm, the mutual conductance may increase and the high-frequency characteristics may deteriorate. Therefore, the thickness of the barrier layer 105 is preferably 10 nm or less. That is, the distance between the upper surface of the channel layer 103 and the lower surface of the protective layer 106 is preferably 10 nm or less. The thickness of the barrier layer 105 is more preferably 9 nm or less, and still more preferably 8 nm or less. Also, if the thickness of the barrier layer 105 is less than 4 nm, there is a possibility that a sufficient concentration of 2DEG cannot be obtained. Therefore, the thickness of the barrier layer 105 is preferably 4 nm or more.

[0040] The composition of the protective layer 106 is In y1 Al y2 Ga 1-y1-y2 It is represented by N(0.00≦y1≦0.20, 0.10≦y2≦1.00, x2<y2), and the In composition y1 is 0.00, the Al composition y2 is 1.00, and the protective layer 106 may be an AlN layer.

[0041] If the thickness of the protective layer 106 exceeds 6 nm, the mutual conductance may increase and the high-frequency characteristics may deteriorate. Therefore, the thickness of the protective layer 106 is preferably 6 nm or less. The thickness of the protective layer 106 is more preferably 5 nm or less, and still more preferably 4 nm or less.

[0042] The composition of the spacer layer 104 is Al z Ga 1-z It is represented by N(0.40≦z≦1.00), and the Al composition z is 1.00, and the spacer layer 104 may be an AlN layer.

[0043] The spacer layer 104 may not be formed, and the barrier layer 105 may be in direct contact with the channel layer 103. This also applies to the following embodiments.

[0044] (Modification of the first embodiment) A modification of the first embodiment will be described. The modification of the first embodiment differs from the first embodiment mainly in the configuration of the nitride semiconductor stacked structure. Fig. 11 is a cross-sectional view showing a semiconductor device according to the modification of the first embodiment.

[0045] 11, in the semiconductor device 100A according to the modification of the first embodiment, the nitride semiconductor stack structure 107 has a cap layer 120 between the barrier layer 105 and the protective layer 106. The cap layer 120 is, for example, a GaN layer having a thickness of 8 nm to 12 nm.

[0046] The other configurations are the same as those in the first embodiment.

[0047] (Second embodiment) A second embodiment will be described. The second embodiment differs from the first embodiment mainly in the configuration of the insulating layer. Fig. 12 is a cross-sectional view showing a semiconductor device according to the second embodiment.

[0048] 12, the semiconductor device 200 according to the second embodiment has an insulating layer 210 instead of the insulating layer 110. Like the insulating layer 110, the insulating layer 210 includes a layer of a nitride of, for example, Si, Al, Hf, Zr, Ti, Ta, or W, and is preferably a Si nitride (SiN) layer. The thickness of the insulating layer 210 is, for example, 2 nm to 500 nm, and preferably about 100 nm. However, the insulating layer 210 does not have an opening corresponding to the opening 110g, and the entire lower surface of the gate electrode 111 is in contact with the insulating layer 210. The gate electrode 111 is not in contact with the protective layer 106.

[0049] The other configurations are the same as those in the first embodiment.

[0050] Next, a method for manufacturing the semiconductor device 200 according to the second embodiment will be described. Figure 13 is a cross-sectional view showing the method for manufacturing the semiconductor device 200 according to the second embodiment.

[0051] First, similarly to the first embodiment, processing up to the formation of the source electrode 108 and the drain electrode 109 is performed (see FIG. 6). Next, as shown in FIG. 13, an insulating layer 210 covering the source electrode 108 and the drain electrode 109 is formed on the protective layer 106. The insulating layer 210 is formed by, for example, a plasma CVD method. The insulating layer 210 may also be formed by an ALD method or a sputtering method. The formation of the insulating layer 210 increases the concentration of the 2DEG 150 near the top surface of the channel layer 103 below the region between the source electrode 108 and the drain electrode 109.

[0052] Thereafter, the gate electrode 111 is formed on the insulating layer 210. The gate electrode 111 can be formed by, for example, a lift-off method, as in the first embodiment.

[0053] In this manner, the semiconductor device 200 according to the second embodiment can be manufactured.

[0054] The semiconductor device 200 according to the second embodiment employs a metal-insulator-semiconductor (MIS) gate structure. As in the first embodiment, the semiconductor device 200 can also suppress an increase in sheet resistance even if the barrier layer 105 is thinned.

[0055] (Third embodiment) Next, a third embodiment will be described. The third embodiment relates to a discrete package of a HEMT. Fig. 14 is a diagram showing the discrete package according to the third embodiment.

[0056] 14 , the back surface of a semiconductor device 1210 having a structure similar to that of the first or second embodiment is fixed to a land (die pad) 1233 using a die attach adhesive 1234 such as solder. A wire 1235d such as an Al wire is connected to a drain pad 1226d connected to a drain electrode 109, and the other end of the wire 1235d is connected to a drain lead 1232d integrated with the land 1233. A wire 1235s such as an Al wire is connected to a source pad 1226s connected to a source electrode 108, and the other end of the wire 1235s is connected to a source lead 1232s independent from the land 1233. A wire 1235g such as an Al wire is connected to a gate pad 1226g connected to a gate electrode 111, and the other end of the wire 1235g is connected to a gate lead 1232g independent from the land 1233. The land 1233, the semiconductor device 1210, and the like are packaged in a molding resin 1231 so that a part of the gate lead 1232g, a part of the drain lead 1232d, and a part of the source lead 1232s protrude.

[0057] Such a discrete package can be manufactured, for example, as follows. First, the semiconductor device 1210 is fixed to the land 1233 of the lead frame using a die attach adhesive 1234 such as solder. Next, by bonding using wires 1235g, 1235d, and 1235s, the gate pad 1226g is connected to the gate lead 1232g of the lead frame, the drain pad 1226d is connected to the drain lead 1232d of the lead frame, and the source pad 1226s is connected to the source lead 1232s of the lead frame. After that, sealing is performed using mold resin 1231 by a transfer molding method. Next, the lead frame is separated.

[0058] (Fourth embodiment) Next, a fourth embodiment will be described. The fourth embodiment relates to a PFC (Power Factor Correction) circuit equipped with a HEMT. Fig. 15 is a wiring diagram showing a PFC circuit according to the fourth embodiment.

[0059] The PFC circuit 1250 includes a switch element (transistor) 1251, a diode 1252, a choke coil 1253, capacitors 1254 and 1255, a diode bridge 1256, and an AC power supply (AC) 1257. The drain electrode of the switch element 1251 is connected to the anode terminal of the diode 1252 and one terminal of the choke coil 1253. The source electrode of the switch element 1251 is connected to one terminal of the capacitor 1254 and one terminal of the capacitor 1255. The other terminal of the capacitor 1254 is connected to the other terminal of the choke coil 1253. The other terminal of the capacitor 1255 is connected to the cathode terminal of the diode 1252. A gate driver is connected to the gate electrode of the switch element 1251. The AC 1257 is connected between both terminals of the capacitor 1254 via the diode bridge 1256. A DC power supply (DC) is connected between both terminals of the capacitor 1255. In this embodiment, a semiconductor device having the same structure as that of the first or second embodiment is used as the switch element 1251.

[0060] When manufacturing the PFC circuit 1250, the switch element 1251 is connected to the diode 1252 and the choke coil 1253, etc., using, for example, solder or the like.

[0061] (Fifth embodiment) Next, a fifth embodiment will be described. The fifth embodiment relates to a power supply device equipped with a HEMT, suitable for use as a server power supply. Fig. 16 is a wiring diagram showing the power supply device according to the fifth embodiment.

[0062] The power supply device is provided with a high-voltage primary circuit 1261 , a low-voltage secondary circuit 1262 , and a transformer 1263 disposed between the primary circuit 1261 and the secondary circuit 1262 .

[0063] The primary side circuit 1261 is provided with a PFC circuit 1250 according to the fourth embodiment and an inverter circuit, for example, a full-bridge inverter circuit 1260, connected between both terminals of a capacitor 1255 of the PFC circuit 1250. The full-bridge inverter circuit 1260 is provided with a plurality of (four in this case) switch elements 1264a, 1264b, 1264c, and 1264d.

[0064] The secondary side circuit 1262 is provided with a plurality of (three in this case) switch elements 1265a, 1265b, and 1265c.

[0065] In this embodiment, semiconductor devices having the same structure as in the first or second embodiment are used for the switch element 1251 of the PFC circuit 1250 constituting the primary side circuit 1261 and the switch elements 1264a, 1264b, 1264c, and 1264d of the full-bridge inverter circuit 1260. On the other hand, ordinary MIS type FETs (field effect transistors) using silicon are used for the switch elements 1265a, 1265b, and 1265c of the secondary side circuit 1262.

[0066] (Sixth embodiment) Next, a sixth embodiment will be described. The sixth embodiment relates to an amplifier including a HEMT. Fig. 17 is a wiring diagram showing the amplifier according to the sixth embodiment.

[0067] The amplifier includes a digital predistortion circuit 1271, mixers 1272a and 1272b, and a power amplifier 1273.

[0068] The digital predistortion circuit 1271 compensates for nonlinear distortion in the input signal. The mixer 1272a mixes the input signal, for which nonlinear distortion has been compensated, with an AC signal. The power amplifier 1273 includes a semiconductor device having a structure similar to that of the first or second embodiment, and amplifies the input signal mixed with the AC signal. Note that in this embodiment, for example, by switching a switch, the output signal can be mixed with the AC signal by the mixer 1272b and sent to the digital predistortion circuit 1271. This amplifier can be used as a high-frequency amplifier or a high-power amplifier. The high-frequency amplifier can be used, for example, in a transmitter / receiver for a mobile phone base station, a radar device, and a microwave generator.

[0069] The substrate may be a silicon carbide (SiC) substrate, a sapphire substrate, a silicon substrate, an AlN substrate, a GaN substrate, or a diamond substrate, and may be conductive, semi-insulating, or insulating.

[0070] The structures of the gate electrode, source electrode, and drain electrode are not limited to those in the above-described embodiments. For example, they may be composed of a single layer. Furthermore, the method for forming them is not limited to the lift-off method. Furthermore, if ohmic characteristics can be obtained, the heat treatment after forming the source electrode and drain electrode may be omitted. Heat treatment may also be performed after forming the gate electrode.

[0071] Furthermore, an n-type GaN region may be formed directly below the source and drain electrodes of the nitride semiconductor multilayer structure, which may be formed by, for example, ion implantation or regrowth.

[0072] The above describes in detail preferred embodiments, but the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims.

[0073] Various aspects of the present disclosure are summarized below as appendices.

[0074] (Appendix 1) a channel layer, a barrier layer provided above the channel layer, a protective layer provided on the barrier layer, an insulating layer provided on the protective layer, and having the composition of the barrier layer is represented by In x1 [[ID=1十六]]Al x2 Ga 1-x1-x2 N (0.00 ≦ x1 ≦ 0.20, 0.10 ≦ x2 ≦ 1.00), the composition of the protective layer is represented by In y1 Al y2 Ga 1-y1-y2 N (0.00 ≦ y1 ≦ 0.20, 0.10 ≦ y2 ≦ 1.00, x2 < y2), The semiconductor device, wherein the protective layer is an amorphous layer. (Appendix 2) The semiconductor device according to Appendix 1, wherein the protective layer does not contain Si, Ge, Sn, and O. (Appendix 3) The semiconductor device according to Appendix 1 or 2, wherein the protective layer does not have polarization aligned in a direction parallel to the c-axis of the channel layer. (Appendix 4)<​​​​​​​​​​​​​​​​8. The semiconductor device according to claim 1, wherein the thickness of the protective layer is 6 nm or less. (Appendix 9) 9. The semiconductor device according to claim 1, further comprising a spacer layer between the channel layer and the barrier layer. (Appendix 10) 10. The semiconductor device according to any one of claims 1 to 9, further comprising a cap layer between the barrier layer and the protective layer. (Appendix 11) a gate electrode, a source electrode, and a drain electrode provided above the barrier layer; 11. The semiconductor device according to any one of claims 1 to 10, wherein two-dimensional electron gas exists in the channel layer below the gate electrode when no voltage is applied to the gate electrode. (Appendix 12) An amplifier comprising the semiconductor device according to any one of claims 1 to 11. (Appendix 13) A power supply device comprising the semiconductor device according to any one of claims 1 to 11. [Explanation of symbols]

[0075] 100, 100A, 200: Semiconductor device 101: Circuit board 102: Nucleation layer 103: Channel layer 104: Spacer layer 105: Barrier layer 106:Protective layer 108: Source electrode 109: Drain electrode 110, 210: insulating layer 120: Cap layer

Claims

1. a channel layer; a barrier layer provided above the channel layer; a protective layer provided on the barrier layer and in contact with the barrier layer; an insulating layer provided on the protective layer and in contact with the protective layer; a gate electrode, a source electrode, and a drain electrode provided above the barrier layer; and The composition of the barrier layer is In ｘ１ Al ｘ２ Ga １－ｘ１－ｘ２ N (0.00≦x1≦0.20, 0.10≦x2≦1.00), The protective layer has a composition of In ｙ１ Al ｙ２ Ga １－ｙ１－ｙ２ N (0.00≦y1≦0.20, 0.10≦y2≦1.00, x2<y2), a two-dimensional electron gas exists in the channel layer below the gate electrode when no voltage is applied to the gate electrode; The semiconductor device is characterized in that the protective layer is an amorphous layer.

2. 2. The semiconductor device according to claim 1, wherein the protective layer does not contain Si, Ge, Sn, or O.

3. 3. The semiconductor device according to claim 1, wherein the protective layer does not have polarization aligned in a direction parallel to the c-axis of the channel layer.

4. 4. The semiconductor device according to claim 1, wherein the protective layer is an AlN layer.

5. 5. The semiconductor device according to claim 1, wherein the barrier layer contains Ga.

6. 6. The semiconductor device according to claim 1, wherein the distance between the upper surface of the channel layer and the lower surface of the protection layer is 10 nm or less.

7. 7. The semiconductor device according to claim 1, wherein the protective layer has a thickness of 6 nm or less.

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