SiC substrates and SiC epitaxial wafers

Abstract

To provide an SiC substrate and an SiC epitaxial wafer, which are difficult to cause defects.SOLUTION: In an SiC substrate according to this embodiment, when an inner periphery is supported by an inner periphery supporting face at a position overlapping with a circumference with 17.5 mm radius from a center, a face of a top face for connecting a first point overlapping with the inner periphery supporting face seen from a thickness direction serves as a first reference face. When a part upper than the first reference face is positive, BOW is less than 40 μm.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a SiC substrate and a SiC epitaxial wafer. [Background technology]

[0002] Silicon carbide (SiC) has a dielectric breakdown field that is one order of magnitude larger than that of silicon (Si) and a band gap that is three times larger. Silicon carbide (SiC) also has properties such as a thermal conductivity that is about three times higher than that of silicon (Si). Therefore, silicon carbide (SiC) is expected to be applied to power devices, high-frequency devices, high-temperature operating devices, etc. For this reason, SiC epitaxial wafers have recently come to be used in these types of semiconductor devices.

[0003] SiC epitaxial wafers are obtained by laminating an SiC epitaxial layer on the surface of a SiC substrate cut from a SiC ingot. Hereinafter, the substrate before laminating the SiC epitaxial layer will be referred to as the SiC substrate, and the substrate after laminating the SiC epitaxial layer will be referred to as the SiC epitaxial wafer.

[0004] SiC substrates and SiC epitaxial wafers may warp during processes such as transportation. Warping can cause defects such as sensor detection failure and suction failure. For example, Patent Document 1 describes a method of suppressing warping during transportation by supporting a warped SiC substrate on the periphery so that the center is higher than the outside. Patent Document 2 describes a method of supporting the wafer flatly with a support to prevent warping in order to suppress unevenness during heat treatment. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] U.S. Patent Application Publication No. 2021 / 0198804 [Patent Document 2] Japanese Patent Application Laid-Open No. 2012-182234 Summary of the Invention [Problem to be solved by the invention]

[0006] There are various wafer support methods, and some methods are restricted by other configurations. The methods described in Patent Documents 1 and 2 can suppress the occurrence of defects when a specific wafer support method is used, but they cannot sufficiently reduce defects when the wafer is supported by inner peripheral support, for example.

[0007] The present invention has been made in view of the above problems, and has an object to provide a SiC substrate and a SiC epitaxial wafer that are less likely to produce defects. [Means for solving the problem]

[0008] The present inventors have fabricated a SiC substrate in which the bow and warp, which determine the shape and warp of the wafer, fall within a predetermined range, and have found that defects during transportation can be reduced by using the SiC substrate. That is, in order to solve the above problems, the present invention provides the following means.

[0009] (1) In the SiC substrate according to the first aspect, when the substrate is supported on the inner periphery by an inner periphery support surface located at a position overlapping the circumference of a circle with a radius of 17.5 mm from the center, the BOW is less than 40 μm when the plane connecting the first point on the upper surface that overlaps with the inner periphery support surface as viewed from the thickness direction is defined as a first reference plane and the direction above the first reference plane is defined as positive.

[0010] (2) The SiC substrate according to the above aspect may have a warp of less than 60 μm when supported by the inner peripheral support surface.

[0011] (3) When the SiC substrate according to the above aspect is supported on its periphery by a peripheral support surface located at a position overlapping the circumference 7.5 mm inward from the outermost periphery, the BOW may be larger than −40 μm when a plane connecting a second point on the upper surface that overlaps with the peripheral support surface as viewed from the thickness direction is defined as a second reference plane and the direction above the second reference plane is defined as positive.

[0012] (4) In the SiC substrate according to the above aspect, when the outer periphery is supported by the outer periphery support surface, the BOW relative to the second reference plane may be 0 μm or less.

[0013] (5) The SiC substrate according to the above aspect may have a warp of less than 60 μm when supported by the outer peripheral support surface.

[0014] (6) The SiC substrate according to the above aspect may have a diameter of 145 mm or more.

[0015] (7) The SiC substrate according to the above aspect may have a diameter of 195 mm or more.

[0016] (8) A SiC epitaxial wafer according to a second aspect includes the SiC substrate according to the above aspect and an SiC epitaxial layer stacked on one surface of the SiC substrate. [Effects of the Invention]

[0017] The SiC substrate and SiC epitaxial wafer according to the above aspects are less likely to produce defects. [Brief explanation of the drawings]

[0018] [Figure 1] FIG. 1 is a plan view of a SiC substrate according to the present embodiment. [Figure 2] FIG. 10 is a cross-sectional view for explaining a method for evaluating a BOW when the SiC substrate according to the present embodiment is supported on its inner periphery. [Figure 3] FIG. 10 is a cross-sectional view for explaining a method for evaluating WARP when the SiC substrate according to the present embodiment is supported from the inner periphery. [Figure 4] FIG. 10 is a cross-sectional view for explaining a method for evaluating a BOW when the SiC substrate according to the present embodiment is peripherally supported. [Figure 5] FIG. 10 is a cross-sectional view for explaining a method for evaluating WARP when the SiC substrate according to the present embodiment is peripherally supported. [Figure 6] FIG. 1 is a schematic diagram illustrating a sublimation method, which is an example of an apparatus for manufacturing a SiC ingot. [Figure 7] FIG. 1 is a cross-sectional view of a SiC epitaxial wafer according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0019] The SiC substrate and the like according to this embodiment will be described in detail below with reference to the drawings as appropriate. The drawings used in the following description may show characteristic portions enlarged for the sake of convenience in order to make the features of this embodiment easier to understand, and the dimensional ratios of each component may differ from the actual ones. The materials, dimensions, and the like exemplified in the following description are merely examples, and the present invention is not limited thereto and can be appropriately modified and implemented within the scope that does not change the gist of the present invention.

[0020] "First embodiment" 1 is a plan view of a SiC substrate 10 according to this embodiment, viewed from the thickness direction of the SiC substrate 10. The SiC substrate 10 is made of SiC. The polytype of the SiC substrate 10 is not particularly limited and may be any of 2H, 3C, 4H, and 6H. The SiC substrate 10 is, for example, 4H—SiC.

[0021] The SiC substrate 10 has a substantially circular shape in plan view. The SiC substrate 10 may have an orientation flat OF or a notch for determining the direction of the crystal axis. The diameter of the SiC substrate 10 is, for example, 145 mm or more, preferably 195 mm or more. The larger the diameter of the SiC substrate 10, the larger the absolute amount of warping will be even with the same curvature. SiC epitaxial wafers with large warping have a significant impact on subsequent processes, and therefore warping must be suppressed. In other words, the larger the diameter of the SiC substrate 10 satisfying the configuration of the present invention, the more useful it is.

[0022] The SiC substrate 10 may be supported on its inner periphery or its outer periphery during, for example, a process such as transportation. The inner periphery support is a method of supporting the SiC substrate 10 on an inner periphery support surface 1 near the center C of the SiC substrate 10, while the outer periphery support is a method of supporting the SiC substrate 10 on an outer periphery support surface 2 near the outermost periphery E of the SiC substrate 10.

[0023] The position of the inner peripheral support surface 1 is not limited to one, but for example, it is located at a position overlapping with the circumference of a circle with a radius of 17.5 mm from the center C. The inner peripheral support surface 1 may be an annular support surface located at a position overlapping with the circumference of a circle with a radius of 17.5 mm from the center C, or it may be a plurality of support surfaces scattered along the circle. The inner peripheral support surface 1 is the upper surface of the support body.

[0024] The position of the outer peripheral support surface 2 is not limited to one, but may be, for example, a position overlapping with a circumference 7.5 mm inward from the outermost periphery E. The outer peripheral support surface 2 may be an annular support surface overlapping with a circumference 7.5 mm inward from the outermost periphery E, or may be a plurality of support surfaces scattered along the circle. The outer peripheral support surface 2 is the upper surface of the support. For example, when the diameter of the SiC substrate 10 is 150 mm, the outer peripheral support surface 2 is positioned overlapping with a circumference with a radius of 67.5 mm from the center C. For example, when the diameter of the SiC substrate 10 is 200 mm, the outer peripheral support surface 2 is positioned overlapping with a circumference with a radius of 92.5 mm from the center C. For example, when the diameter of the SiC substrate 10 is 300 mm, the outer peripheral support surface 2 is positioned overlapping with a circumference with a radius of 142.5 mm from the center C. For example, when the diameter of the SiC substrate 10 is 450 mm, the outer peripheral support surface 2 is located at a position overlapping with the circumference of a circle having a radius of 217.5 mm from the center C.

[0025] When the SiC substrate 10 according to this embodiment is supported on the inner peripheral support surface 1 located at a position overlapping the circumference of a circle with a radius of 17.5 mm from the center C, the bow is less than 40 μm, preferably 20 μm or less, and more preferably 10 μm or less. When the bow of the inner peripheral support satisfies the above range, transfer errors can be reduced. Transfer errors include, for example, poor sensor detection, poor suction, contact with other components, etc.

[0026] 2 is a cross-sectional view illustrating a method for evaluating a bow when the SiC substrate 10 according to this embodiment is supported on its inner periphery. As shown in FIG. 2, when the SiC substrate 10 is supported on its inner periphery by the inner periphery support surface 1, the center C of the SiC substrate 10 is located farther from the flat surface F than the outermost periphery. That is, the SiC substrate 10 bends upward in a convex manner when supported on its inner periphery.

[0027] The BOW measures the height of the center C of the wafer, and this height is specified as a signed distance from a three-point reference plane. If it is above the three-point reference plane, it is positive, and if it is below, it is negative. The reference plane for inner peripheral support is called the first reference plane Sr1. The first reference plane Sr1 is a plane connecting first points p1 on the top surface 10a that overlap with the inner peripheral support surface 1 when viewed from the thickness direction. The first points p1 are, for example, the portions that overlap with the inner peripheral support surface 1 when viewed from the thickness direction. When there are multiple inner peripheral support surfaces 1, there are multiple first points p1. For example, the first reference plane Sr1 is a plane connecting multiple first points p1. The BOW for inner peripheral support is determined as the height position of the center C of the top surface 10a relative to the first reference plane Sr1. The absolute value of the BOW in the case of inner peripheral support is determined as the distance between the first surface S1 that passes through the center C and is parallel to the first reference surface Sr1 (flat surface F) and the three-point reference plane (first reference surface Sr1).

[0028] In the SiC substrate 10 according to this embodiment, when supported from the inner periphery, the warp is preferably 60 μm or less, more preferably 30 μm or less, and even more preferably 20 μm or less.

[0029] FIG. 3 is a cross-sectional view for explaining a method for evaluating WARP when the SiC substrate 10 according to this embodiment is supported from the inner periphery.

[0030] WARP is the sum of the distances from the three-point reference plane to the highest point hp and the lowest point lp of the upper surface 10a, and is always a positive value. WARP can be calculated, for example, as the distance between a second surface S2 that passes through the highest point hp and is parallel to the three-point reference plane (first reference plane Sr1) (flat surface F), and a third surface S3 that passes through the lowest point lp and is parallel to the three-point reference plane (first reference plane Sr1) (flat surface F). In the case of inner peripheral support, the highest point hp may coincide with the center C, in which case the first surface S1 and the second surface S2 coincide. The larger the WARP, the more deformed the SiC substrate 10 is determined to be.

[0031] Furthermore, in the SiC substrate 10 according to this embodiment, when supported at the periphery, the BOW is preferably larger than −40 μm, more preferably 0 μm or less, and further preferably −20 μm or more and −5 μm or less. A BOW larger than −40 μm means that the absolute value is smaller than 40 μm.

[0032] If the bow is within the above range when the SiC substrate 10 is supported from the outer periphery, transfer errors can be reduced whether the SiC substrate 10 is supported from the inner periphery or the outer periphery. That is, whether the SiC substrate is supported from the inner periphery or the outer periphery, a bow within the specified range is highly versatile and less likely to cause transfer errors, even when passing through a transfer process that requires a change in the support method during transfer. Furthermore, in an automatic transfer system, a wafer is transferred from a stage by lifting it up using a push-up pin or the like, and a robot hand enters the gap to lift it up. If the bow is not within the specified range, the robot hand may collide with the wafer, or the wafer may not be within the stroke range of the robot hand, resulting in transfer failure.

[0033] 4 is a cross-sectional view illustrating a method for evaluating a bow when the SiC substrate 10 according to this embodiment is peripherally supported. As shown in FIG. 4, when the SiC substrate 10 is peripherally supported by the peripheral support surface 2, the center C of the SiC substrate 10 is located, for example, closer to the flat surface F than the outermost periphery. That is, the SiC substrate 10 bends downward convexly when supported on the periphery.

[0034] The reference plane for peripheral support is referred to as the second reference plane Sr2. The second reference plane Sr2 is a plane connecting second points p2 on the upper surface 10a that overlap with the peripheral support surface 2 when viewed from the thickness direction. The second point p2 is, for example, a portion that overlaps with the radial center of the peripheral support surface 2 when viewed from the thickness direction. When there are multiple peripheral support surfaces 2, there will be multiple second points p2. The second reference plane Sr2 is, for example, a plane connecting multiple second points p2. The bow in the case of peripheral support is determined as the height direction position of the center C of the upper surface 10a relative to the three-point reference plane (second reference plane Sr2). The absolute value of the bow in the case of peripheral support is determined as the distance between the first surface S1, which passes through the center C and is parallel to the second reference plane Sr2 (flat surface F), and the three-point reference plane (second reference plane Sr2).

[0035] FIG. 5 is a cross-sectional view for explaining a method for evaluating WARP when the SiC substrate 10 according to this embodiment is supported on its periphery.

[0036] As described above, WARP is the sum of the distances from the three-point reference plane to the highest point hp and the lowest point lp of the upper surface 10a. WARP can be calculated, for example, as the distance between the second surface S2 that passes through the highest point hp and is parallel to the three-point reference plane (second reference surface Sr2) (flat surface F), and the third surface S3 that passes through the lowest point lp and is parallel to the three-point reference plane (second reference surface Sr2) (flat surface F). In the case of peripheral support, the lowest point lp may coincide with the center C, in which case the first surface S1 and the third surface S3 coincide.

[0037] The bow and warp of the SiC substrate 10 in the case of inner peripheral support and outer peripheral support are affected by strain generated in the SiC substrate 10 itself and bending of the SiC substrate 10 due to gravity. The strain generated in the SiC substrate 10 itself is caused by, for example, internal stress. The strain generated in the SiC substrate 10 itself can be controlled during the manufacturing process.

[0038] Next, an example of a method for manufacturing the SiC substrate 10 according to this embodiment will be described. The SiC substrate 10 is obtained by slicing an SiC ingot. The SiC ingot is obtained by, for example, sublimation deposition.

[0039] 6 is a schematic diagram illustrating a sublimation method, which is an example of an SiC ingot manufacturing apparatus 30. In FIG. 6, the direction perpendicular to the surface of pedestal 32 is the z-direction, one direction perpendicular to the z-direction is the x-direction, and the direction perpendicular to the z-direction and the x-direction is the y-direction.

[0040] The sublimation method involves placing a seed crystal 33 made of a SiC single crystal on a pedestal 32 placed in a graphite crucible 31, heating the crucible 31 to supply sublimation gas sublimated from a raw material powder 34 in the crucible 31 to the seed crystal 33, and growing the seed crystal 33 into a larger SiC ingot 35. The crucible 31 is heated using, for example, a coil 36.

[0041] By controlling the crystal growth conditions in the sublimation method, the bow and warp of the SiC substrate 10 obtained from the SiC ingot 35 can be controlled.

[0042] For example, when growing the SiC ingot 35 in the c-plane, the temperature of the center and the temperature of the peripheral part of the crystal growth surface are controlled. The crystal growth surface is the surface during the crystal growth process. For example, when growing the SiC ingot 35 in the c-plane, the temperature of the peripheral part of the crystal growth surface is made lower than the temperature of the center. Furthermore, crystal growth is performed so that the difference in growth rate between the center and the periphery in the xy plane is 0.001 mm / h or more and 0.05 mm / h or less. Here, the growth rate of the center in the xy plane is made slower than the growth rate of the periphery. The growth rate can be changed by changing the temperature of the crystal growth surface.

[0043] The temperature of the crystal growth surface can be adjusted by controlling the z-direction position of the heating center of crucible 31 by coil 36. The z-direction position of the heating center of crucible 31 can be changed by changing the z-direction position of coil 36. The z-direction position of the heating center of crucible 31 and the z-direction position of the crystal growth surface are controlled so that they move apart at a rate of 0.5 mm / h. Here, the z-direction position of the heating center of crucible 31 is controlled so that it is below (on the raw material powder 34 side) the z-direction position of the crystal growth surface.

[0044] Next, the SiC ingot 35 produced under these conditions is processed into a SiC substrate 10. In typical processing methods, the stress applied to the single crystal differs between the SiC ingot 35 and the SiC substrate 10. For example, in the molding process, the diameter must be reduced when processing a 180 mm diameter SiC ingot 35 into a 150 mm diameter SiC substrate 10. Furthermore, for example, the multi-wire cutting process generates surface waviness that must be removed. By undergoing these processes, for example, high-stress portions of the SiC ingot 35 may be removed or the shape of the crystal lattice plane may change, which may release the stress in the SiC ingot 35 when it is in the SiC substrate 10 state. The SiC substrate 10 is processed so that it inherits the stress applied to the single crystal in the SiC ingot 35 state. The stress applied to the SiC substrate 10 is one of the factors that causes the SiC substrate 10 to warp, and adjusting the stress can adjust the warp of the SiC substrate. As a result, it is possible to utilize the stress inherited by the SiC substrate 10 to suppress bending of the SiC substrate 10.

[0045] For example, after one side of the SiC ingot 35 is subjected to damage-free processing, it is cut with a single wire saw, and the surface that has been subjected to the damage-free processing is sucked and further damage-free processing is performed on the cut surface. By performing damage-free processing on both sides of the SiC substrate 10, some of the stress generated in the SiC ingot state is also inherited by the SiC substrate 10. An example of the damage-free processing is CMP processing. By processing the substrate in this way so as to retain the lattice plane shape of the SiC ingot 35, the stress of the SiC ingot 35 is inherited by the SiC substrate 10. Then, a molding process for adjusting the diameter is performed, thereby adjusting the deflection of the SiC substrate 10.

[0046] In this way, by using the above manufacturing method to fabricate the SiC substrate 10, it is possible to reduce the bow and warp in the case of inner peripheral support. Also, by using the above manufacturing method to fabricate the SiC substrate 10, it is possible to reduce the bow and warp in the case of outer peripheral support.

[0047] The SiC substrate 10 according to this embodiment is manufactured to satisfy predetermined conditions, and therefore has small bow and warp when supported from the inner periphery. Therefore, even when supported from the inner periphery, transfer errors are unlikely to occur. Furthermore, the SiC substrate 10, which also has small bow and warp when supported from the outer periphery, is unlikely to cause transfer errors in either the inner periphery or outer periphery support, and is therefore highly versatile in processes.

[0048] "Second embodiment" 7 is a cross-sectional view of a SiC epitaxial wafer 20 according to the second embodiment. The SiC epitaxial wafer 20 includes a SiC substrate 10 and a SiC epitaxial layer 11. The SiC epitaxial layer 11 is stacked on one surface of the SiC substrate 10. The SiC epitaxial layer 11 is stacked on, for example, the upper surface 10a of the SiC substrate 10.

[0049] To obtain high-quality SiC that can operate devices, an SiC epitaxial layer 11 is laminated on an SiC substrate 10. Furthermore, before laminating the SiC epitaxial layer 11, mechanical processing such as polishing is often performed. In this case, a processing-affected layer is formed on the upper surface 10a of the SiC substrate 10. When the SiC epitaxial layer 11 is laminated or a processing-affected layer is formed on one surface of the SiC substrate 10, the SiC epitaxial wafer 20 may warp.

[0050] The surface of the SiC substrate 10 is often ground. The surface roughness (Ra) of the upper surface 10a of the SiC substrate 10 is preferably, for example, 1 nm or less. The upper surface 10a is, for example, the surface on which the SiC epitaxial layer 11 is stacked.

[0051] Both the upper surface 10a and the lower surface 10b of the SiC substrate 10 may be ground. The upper surface 10a is, for example, a Si surface, and the lower surface 10b is, for example, a C surface. The relationship between the upper surface 10a and the lower surface 10b may be reversed. The upper surface 10a and the lower surface 10b may both be mirror-polished mirror surfaces with residual scratches or the like, or both be CMP-treated surfaces with chemical mechanical polishing (CMP), and the degree of polishing may differ between the upper surface 10a and the lower surface 10b. A processing-affected layer is formed on the mirror surface with residual scratches or the like, while almost no processing-affected layer is formed on the CMP-treated surface. The processing-affected layer is a portion damaged by processing and where the crystal structure is destroyed.

[0052] For example, if the upper surface 10a is a mirror-ground surface and the lower surface 10b is a CMP-treated surface, the difference in the surface conditions of the two surfaces will cause the Twyman effect in the SiC substrate 10. The Twyman effect is a phenomenon in which, when a difference in residual stress occurs between the two surfaces of a substrate, a force acts to compensate for the difference in stress between the two surfaces. The Twyman effect can cause warping of the SiC epitaxial wafer 20.

[0053] Furthermore, the SiC epitaxial wafer 20 after the SiC epitaxial layer 11 is deposited preferably has a WARP of 50 μm or less, more preferably 30 μm or less. Furthermore, the SiC epitaxial wafer 20 after the SiC epitaxial layer 11 is deposited preferably has a BOW of 30 μm or less, more preferably 10 μm or less, when supported from the inner periphery. Furthermore, the BOW of the SiC epitaxial wafer 20 after the SiC epitaxial layer 11 is deposited is preferably -30 μm or more, when supported from the outer periphery.

[0054] The SiC epitaxial wafer 20 according to the second embodiment has a warp and bow within a predetermined range of the SiC substrate 10, and therefore is less likely to warp even after the SiC epitaxial layer 11 is stacked. Therefore, the SiC epitaxial wafer 20 is also less likely to suffer from transfer errors.

[0055] Although the preferred embodiments of the present invention have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the gist of the present invention as set forth in the claims. [Example]

[0056] Example 1 SiC ingot 35 was produced by sublimation. When producing SiC ingot 35, the z-direction position of the heating center of crucible 31 and the z-direction position of the crystal growth surface were controlled so as to separate at a rate of 0.5 mm / h. Crystal growth was performed by lowering the temperature of the periphery of the crystal growth surface relative to the temperature at the center, and ensuring that the difference in growth rate between the center and periphery in the xy plane was 0.001 mm / h or more and 0.05 mm / h or less.

[0057] The fabricated SiC ingot 35 was then cut with a multi-wire saw and both surfaces were polished by CMP. Through the above steps, a SiC substrate 10 having a thickness of 348.15 μm and a diameter of 150 mm was prepared.

[0058] The fabricated SiC substrate 10 was supported by a plurality of inner peripheral support surfaces 1 arranged on a circumference with a radius of 17.5 mm from the center C, and the bow and warp were measured. The bow was 9.468 μm. The warp was 18.416 μm.

[0059] Then, this SiC substrate 10 was transported along a predetermined transport path. The height of the transport path was set to 2 mm. The thickness of the robot hand along the transport path was set to 1.5 mm, the stroke width was set to 50 μm, and the upper limit of the thickness of the transported wafer was set to 375 μm. When a plurality of SiC substrates 10 of Example 1 were transported under these conditions, the transport error rate of the SiC substrates 10 of Example 1 was 0%.

[0060] Example 2 In Example 2, the growth conditions for producing SiC ingot 35 were the same as those in Example 1, but the thickness of the cut SiC substrate 10 was different. When producing SiC substrate 10 in Example 2, the temperature of the outer periphery of the crystal growth surface was also set lower than the temperature of the center of the crystal growth surface, the difference in growth rate between the center and the periphery in the xy plane was set to 0.001 mm / h or more and 0.05 mm / h or less, and the distance between the position of the heating center of crucible 31 in the z direction and the position of the crystal growth surface in the z direction was controlled to be 0.5 mm / h.

[0061] Similarly to Example 1, SiC substrate 10 of Example 2 was supported by inner peripheral support surface 1, and the BOW and WARP were measured. When supported by inner peripheral support surface 1, the BOW was 35.744 μm and the WARP was 51.174 μm. The transfer error rate when SiC substrate 10 of Example 2 was transferred under the same conditions as Example 1 was 20%.

[0062] (Comparative Example 1, Comparative Example 2) Comparative Examples 1 and 2 differ from Example 1 in that the growth conditions for producing the SiC ingot 35 were changed. In Comparative Examples 1 and 2, the temperature conditions during crystal growth were not particularly controlled.

[0063] Similarly to Example 1, the bow and warp were measured when the SiC substrates 10 of Comparative Examples 1 and 2 were supported by the inner peripheral support surface 1.

[0064] The BOW was 74.027 μm and the WARP was 103.705 μm when the SiC substrate 10 of Comparative Example 1 was supported by the inner peripheral support surface 1. The transfer error rate when the SiC substrate 10 of Comparative Example 1 was transferred under the same conditions as in Example 1 was 100%.

[0065] The BOW was −30.164 μm and the WARP was 282.608 μm when the SiC substrate 10 of Comparative Example 2 was supported by the inner peripheral support surface 1. The transfer error rate when the SiC substrate 10 of Comparative Example 2 was transferred under the same conditions as in Example 1 was 100%.

[0066] The results of Examples 1 and 2 and Comparative Examples 1 and 2 are summarized in Table 1 below.

[0067] [Table 1]

[0068] In Examples 1 and 2, in which the temperature during manufacturing was precisely controlled, the bow and warp were small even when the substrate was supported from the inner periphery. Furthermore, the SiC substrates of Examples 1 and 2, which had small bow and warp, had a lower transfer error rate than the SiC substrates of Comparative Examples 1 and 2. Furthermore, the bow and warp of Example 1 were each smaller than the bow and warp of Example 2. Example 1 had a thicker SiC substrate 10 than Example 2. By increasing the thickness, the bow and warp can be reduced. [Explanation of symbols]

[0069] 1...inner peripheral support surface, 2...outer peripheral support surface, 10...SiC substrate, 10a...upper surface, 10b...lower surface, 11...SiC epitaxial layer, 20...SiC epitaxial wafer, 30...manufacturing apparatus, 31...crucible, 32...pedestal, 33...seed crystal, 34...raw material powder, 35...SiC ingot, 36...coil, C...center, F...flat surface, hp...highest point, lp...lowest point, p1...first point, p2...second point, S1...first surface, S2...second surface, S3...third surface, Sr1...first reference surface, Sr2...second reference surface

Claims

1. A SiC epitaxial wafer having a SiC substrate and a SiC epitaxial layer stacked on one surface of the SiC substrate, when the SiC epitaxial wafer is inner-circumferentially supported by an inner-circumferential support surface located at a position overlapping with a circumference having a radius of 17.5 mm from the center of the SiC epitaxial wafer, a plane connecting a first point on the upper surface of the SiC epitaxial wafer that overlaps with the inner-circumferential support surface as viewed from the thickness direction is defined as a first reference plane, and a direction above the first reference plane is defined as positive, the BOW of the SiC epitaxial wafer is 30 μm or less; The SiC epitaxial wafer, wherein the SiC substrate has a diameter of 145 mm or more.

2. 2. The SiC epitaxial wafer according to claim 1, wherein a bow of the SiC epitaxial wafer when supported by the inner peripheral support surface is 10 μm or less.

3. 2. The SiC epitaxial wafer according to claim 1, wherein the WARP is 50 μm or less.

4. 2. The SiC epitaxial wafer according to claim 1, wherein the WARP is 30 μm or less.

5. The SiC epitaxial wafer according to claim 1 , wherein the SiC substrate bends upwardly convexly when supported on the inner peripheral support surface.

6. 2. The SiC epitaxial wafer according to claim 1, wherein, when the SiC substrate is inner-circumferentially supported by an inner peripheral support surface located at a position overlapping a circumference having a radius of 17.5 mm from the center of the SiC substrate, a plane connecting a first point on the upper surface of the SiC substrate that overlaps with the inner peripheral support surface as viewed from the thickness direction is defined as a first reference plane, and a direction above the first reference plane is defined as positive.

7. The SiC epitaxial wafer according to claim 1 , wherein the SiC substrate is made of a single crystal.

8. The SiC epitaxial wafer according to claim 1 , wherein the SiC epitaxial layer is made of a single crystal.

9. 2. The SiC epitaxial wafer according to claim 1, wherein the SiC substrate has a thickness of 375 μm or less.

10. The SiC epitaxial wafer according to any one of claims 1 to 9, wherein the SiC substrate has a diameter of 195 mm or more.

11. When the outer periphery is supported by the outer periphery support surface located at a position overlapping with the circumference 7.5 mm inward from the outermost periphery, 10. The SiC epitaxial wafer according to claim 1, wherein a plane connecting a second point on the upper surface that overlaps with the outer peripheral support surface when viewed from the thickness direction is defined as a second reference plane, and when a direction above the second reference plane is defined as positive, the BOW of the SiC epitaxial wafer is −30 μm or more.

12. The SiC epitaxial wafer according to claim 11 , wherein the SiC substrate bends downwardly convexly when supported on the outer periphery by the outer periphery support surface.

13. 13. The SiC epitaxial wafer according to claim 12, wherein the SiC substrate has a diameter of 195 mm or more.

Images