Power amplifier

The power amplifier design addresses cost and performance issues by using separate package structures for carrier and balance amplifiers with equal electrical lengths, ensuring efficient and cost-effective operation with minimal phase shifts.

JP7740601B2Active Publication Date: 2025-09-17MITSUBISHI ELECTRIC CORP
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Patent Information

Application Number
JP2025513503
Authority / Receiving Office
JP · JP
Patent Type
Patents
Current Assignee / Owner
Filing Date
2023-04-10
Publication Date
2025-09-17
Estimated Expiration
2043-04-10

AI Technical Summary

Technical Problem

Existing power amplifiers for wireless communication using LMBA circuits face challenges in cost reduction due to the need for separate packages with low thermal resistance for the carrier amplifier and high thermal resistance for the balance amplifier, leading to increased costs and potential phase shift issues in module connections, which degrade high-frequency characteristics.

Method used

A power amplifier design comprising a carrier amplifier module, a balanced amplifier module, and delay lines with equal electrical lengths, using different package structures for each to optimize thermal resistance and minimize phase shifts, allowing easy module connection and reducing costs.

Benefits of technology

The design achieves high-performance, low-cost power amplifiers with improved high-frequency characteristics by optimizing package structures and equalizing electrical lengths, facilitating easy module connection without degrading performance.

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Patent Text Reader

Abstract

A power amplifier according to the present disclosure comprises a carrier amplifier module (5), a balance amplifier module (4), a first delay line (80), and a second delay line (81). The thermal resistance from an active element (12) of a first amplifier (10) to a package rear surface is smaller than the thermal resistance from an active element (22) of a second amplifier (20) and from an active element (32) of a third amplifier (30) to the package rear surface. The sum of the electrical length from an input terminal (2) to a first internal output terminal (90) and the electrical length from a first internal input terminal (91) to an output terminal (3) is equal to the sum of the electrical length from the input terminal (2) to a second internal output terminal (92) and the electrical length from a second internal input terminal (93) to the output terminal (3). The electrical lengths of the first delay line (80) and the second delay line (81) are equal to each other.
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Citation Information

Patent Citations

  • High power Doherty amplifier using multistage modules

    JP2008535321A

  • Semiconductor amplification element and semiconductor amplification device

    JP2019092009A

  • High frequency power amplification device

    WO2022176947A1