Substrate with built-in electronic components and method for manufacturing the same

Abstract

To provide a substrate with a built-in electronic component and a method for manufacturing the substrate with the built-in electronic component capable of easily filling resin between the back surface of a semiconductor chip and a substrate facing it.SOLUTION: A substrate with a built-in electronic component includes: a first substrate; a semiconductor chip mounted on the first substrate; a second substrate provided on the first substrate with the semiconductor chip interposed therebetween; a first resin filled between the semiconductor chip and the first substrate and having a covering portion covering the side surface of the semiconductor chip; and a second resin filled between the first substrate and the second substrate and sealing the semiconductor chip and the first resin, the first resin having a projecting portion projecting from the covering portion toward the second substrate.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a substrate with built-in electronic components and a method for manufacturing a substrate with built-in electronic components. [Background technology]

[0002] In recent years, in order to achieve thinner designs and space saving, electronic component built-in substrates in which semiconductor chips are embedded have been proposed.

[0003] An example of such an electronic component-embedded substrate is a structure in which a second substrate is stacked on a first substrate on which a semiconductor chip is flip-chip mounted face-down via substrate connecting members such as solder balls, and the space between the first and second substrates is sealed with resin.

[0004] The electronic component-embedded substrate includes, for example, a step of fabricating a first substrate on which a semiconductor chip is mounted, a step of fabricating a second substrate on which a substrate connecting member is mounted, a step of stacking the second substrate on the first substrate with the substrate connecting member mounting surface facing the semiconductor chip mounting surface, and a step of filling the gap between the first substrate and the second substrate with resin. In the step of filling with resin, from the viewpoint of reliability, it is preferable to also fill the gap between the back surface of the semiconductor chip and the second substrate with resin. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2020-096018 [Patent Document 2] International Publication No. 2007 / 069606 Summary of the Invention [Problem to be solved by the invention]

[0006] However, due to the demand for thinner electronic component embedded substrates, it has become necessary to narrow the gap between the back surface of the semiconductor chip and the second substrate. Also, in the resin filling process, the structure to be filled is pressed from above and below by a mold, which further narrows the gap, making it difficult to fill the resin between the back surface of the semiconductor chip and the second substrate.

[0007] The present disclosure aims to provide a substrate with built-in electronic components that allows resin to be easily filled between the back surface of a semiconductor chip and a substrate facing it, and a method for manufacturing such a substrate. [Means for solving the problem]

[0008] According to one aspect of the present disclosure, there is provided a semiconductor device including a first substrate, a semiconductor chip mounted on the first substrate, a second substrate provided on the first substrate with the semiconductor chip sandwiched therebetween, a first resin filled between the semiconductor chip and the first substrate and having a covering portion covering a side surface of the semiconductor chip, and a second resin filled between the first substrate and the second substrate and sealing the semiconductor chip and the first resin, wherein the first resin protrudes from the covering portion toward the second substrate. Multiple With protrusions The semiconductor chip has a rectangular planar shape, and two of the plurality of protrusions are provided on the outer sides of two parallel side surfaces of the semiconductor chip in a plan view. A substrate with built-in electronic components is provided. [Effects of the Invention]

[0009] According to the disclosed technique, the resin can be easily filled between the back surface of the semiconductor chip and the substrate facing it. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a cross-sectional view illustrating an example of an electronic component built-in substrate according to a first embodiment. [Figure 2] FIG. 3 is a schematic plan view illustrating the arrangement of protrusions in the first embodiment. [Figure 3] 4A to 4C are cross-sectional views (part 1) illustrating a manufacturing process of the electronic component built-in substrate according to the first embodiment. [Figure 4]5A to 5C are cross-sectional views (part 2) illustrating the manufacturing process of the electronic component built-in substrate according to the first embodiment. [Figure 5] 5A to 5C are cross-sectional views (part 3) illustrating the manufacturing process of the electronic component built-in substrate according to the first embodiment. [Figure 6] 10A to 10C are cross-sectional views (part 4) illustrating the manufacturing process of the electronic component built-in substrate according to the first embodiment. [Figure 7] 5A to 5C are cross-sectional views illustrating the manufacturing process of the electronic component built-in substrate according to the first embodiment. [Figure 8] 10A to 10C are cross-sectional views (part 6) illustrating the manufacturing process of the electronic component built-in substrate according to the first embodiment. [Figure 9] 10A to 10C are cross-sectional views (part 7) illustrating the manufacturing process of the electronic component built-in substrate according to the first embodiment. [Figure 10] FIG. 4 is a cross-sectional view illustrating an electronic component built-in substrate according to a first modified example of the first embodiment. [Figure 11] FIG. 10 is a cross-sectional view illustrating an example of an electronic component built-in substrate according to a second embodiment. [Figure 12] 10A to 10C are diagrams illustrating a manufacturing process of the electronic component built-in substrate according to the second embodiment. [Figure 13] FIG. 10 is a cross-sectional view illustrating an example of an electronic component built-in substrate according to a third embodiment. [Figure 14] FIG. 10 is a schematic plan view illustrating the arrangement of protrusions in the fourth embodiment. [Figure 15] FIG. 10 is a cross-sectional view illustrating an electronic component built-in substrate according to a second modified example of the first embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. In this specification and drawings, components having substantially the same functional configurations are designated by the same reference numerals, and redundant explanations may be omitted.

[0012] (First embodiment) A first embodiment will be described. The first embodiment relates to a substrate with built-in electronic components.

[0013] [Structure of electronic component embedded board] First, the structure of the electronic component built-in substrate will be described. Fig. 1 is a cross-sectional view showing the structure of the electronic component built-in substrate according to the first embodiment.

[0014] 1, the electronic component built-in substrate 1 according to the first embodiment includes a substrate 10, a substrate connecting member 20, a substrate 30, a semiconductor chip 40, a conductive bonding material 43, an underfill resin 60, a molded resin 70, and an external connection terminal 90. In the electronic component built-in substrate 1, the substrates 10 and 30 are stacked via the substrate connecting member 20 that electrically connects the substrates 10 and 30.

[0015] In this embodiment, for convenience, the solder resist layer 13 side of the electronic component built-in substrate 1 is referred to as the upper side or one side, and the solder resist layer 37 side is referred to as the lower side or the other side. Furthermore, the surface of each portion facing the solder resist layer 13 is referred to as one side or upper side, and the surface facing the solder resist layer 37 is referred to as the other side or lower side. However, the electronic component built-in substrate 1 can be used upside down or positioned at any angle. Furthermore, a planar view refers to viewing an object from the normal direction of one side of the solder resist layer 13, and a planar shape refers to the shape of the object viewed from the normal direction of one side of the solder resist layer 13.

[0016] The substrate 10 has one surface 10a and the other surface 10b. The substrate 30 has one surface 30a and the other surface 30b. The one surface 30a of the substrate 30 and the other surface 10b of the substrate 10 face each other.

[0017] Substrate 10 is disposed on substrate 30 with semiconductor chip 40 sandwiched therebetween. Substrate 10 has an insulating layer 11, a wiring layer 12, a solder resist layer 13, a wiring layer 14, and a solder resist layer 15. The planar shape of substrate 10 is not particularly limited, but can be, for example, a rectangular shape of approximately 15 mm square.

[0018] In the substrate 10, the insulating layer 11 may be, for example, a so-called glass epoxy substrate in which glass cloth is impregnated with an insulating resin such as an epoxy resin. Alternatively, the insulating layer 11 may be a substrate in which a woven or nonwoven fabric such as glass fiber, carbon fiber, or aramid fiber is impregnated with an insulating resin such as an epoxy resin. The thickness of the insulating layer 11 may be, for example, approximately 60 μm to 200 μm. Note that the glass cloth and other components are not shown in the drawings.

[0019] The wiring layer 12 is formed on one side of the insulating layer 11. The wiring layer 12 is electrically connected to the wiring layer 14. The wiring layer 12 includes via wiring filled in a via hole 11x that penetrates the insulating layer 11 and exposes one surface of the wiring layer 14, and a wiring pattern formed on one surface of the insulating layer 11.

[0020] The via holes 11x may be recesses in the shape of inverted truncated cones, with the diameter of the openings on the solder resist layer 13 side being larger than the diameter of the bottom of the openings formed by the upper surface of the wiring layer 14. The diameter of the openings of the via holes 11x may be, for example, about 50 μm. The wiring layer 12 may be made of a material such as copper (Cu). The thickness of the wiring pattern constituting the wiring layer 12 may be, for example, about 10 μm to 20 μm.

[0021] The solder resist layer 13 is formed on one surface of the insulating layer 11 so as to cover the wiring layer 12. The solder resist layer 13 can be formed from, for example, a photosensitive resin. The thickness of the solder resist layer 13 can be, for example, about 15 μm to 35 μm. The solder resist layer 13 has openings 13x, and a portion of the wiring layer 12 is exposed in the openings 13x. The wiring layer 12 exposed in the openings 13x includes pads 12p. The pads 12p function as pads that are electrically connected to electronic components (not shown), such as a semiconductor chip or a semiconductor package.

[0022] If necessary, a metal layer may be formed on one surface of the pad 12p, or an anti-oxidation treatment such as an OSP (organic solderability preservative) treatment may be performed. Examples of the metal layer include an Au layer, a Ni / Au layer (a metal layer formed by laminating a Ni layer and a Au layer in this order), and a Ni / Pd / Au layer (a metal layer formed by laminating a Ni layer, a Pd layer, and a Au layer in this order). Furthermore, an external connection terminal such as a solder ball may be formed on one surface of the pad 12p.

[0023] The wiring layer 14 is formed on the other surface of the insulating layer 11. One surface of the wiring layer 14 is in contact with and electrically connected to the lower end of the via wiring filled in the via hole 11x of the wiring layer 12. The material and thickness of the wiring layer 14 can be the same as those of the wiring pattern constituting the wiring layer 12, for example.

[0024] The solder resist layer 15 is formed on the other surface of the insulating layer 11 so as to cover the wiring layer 14. The material and thickness of the solder resist layer 15 can be, for example, the same as those of the solder resist layer 13. The solder resist layer 15 has openings 15x, and a portion of the wiring layer 14 is exposed in the openings 15x. The wiring layer 14 exposed in the openings 15x includes pads 14p. The pads 14p function as pads electrically connected to the substrate connecting member 20.

[0025] If necessary, the other surface of the pad 14p may be formed with the aforementioned metal layer or subjected to an anti-oxidation treatment such as OSP treatment.

[0026] The substrate 30 has an insulating layer 31, a wiring layer 32, an insulating layer 33, a wiring layer 34, a solder resist layer 35, a wiring layer 36, and a solder resist layer 37. The planar shape of the substrate 30 is not particularly limited, but can be, for example, a rectangular shape of about 15 mm square.

[0027] In the substrate 30, the material and thickness of the insulating layer 31 can be, for example, the same as those of the insulating layer 11. The wiring layer 32 is formed on one surface of the insulating layer 31. The material and thickness of the wiring layer 32 can be, for example, the same as those of the wiring pattern that constitutes the wiring layer 12.

[0028] The insulating layer 33 is formed on one surface of the insulating layer 31 so as to cover the wiring layer 32. The insulating layer 33 may be made of an insulating resin such as a thermosetting epoxy resin. The insulating layer 33 may contain a filler such as silica (SiO2). The thickness of the insulating layer 33 may be, for example, about 15 μm to 35 μm.

[0029] The wiring layer 34 is formed on one side of the insulating layer 33. The wiring layer 34 includes via wiring filled in via holes 33x that penetrate the insulating layer 33 and expose one surface of the wiring layer 32, and a wiring pattern formed on one surface of the insulating layer 33.

[0030] The via hole 33x can be an inverted truncated cone-shaped recess that opens on the solder resist layer 35 side and has a bottom surface formed by one surface of the wiring layer 32. The material of the wiring layer 34 and the thickness of the wiring pattern that forms the wiring layer 34 can be the same as those of the wiring layer 12, for example.

[0031] The solder resist layer 35 is formed on one surface of the insulating layer 33 so as to cover the wiring layer 34. The material and thickness of the solder resist layer 35 may be the same as those of the solder resist layer 13, for example. The solder resist layer 35 has openings 35x, and a portion of the wiring layer 34 is exposed in the openings 35x. The wiring layer 34 exposed in the openings 35x includes pads 34p.

[0032] Some of the pads 34p function as pads electrically connected to the substrate connecting member 20. Other parts of the pads 34p function as pads electrically connected to the semiconductor chip 40. The diameters of the pads 34p electrically connected to the substrate connecting member 20 and the pads 34p electrically connected to the semiconductor chip 40 can be set independently.

[0033] If necessary, the above-mentioned metal layer may be formed on one surface of the pad 34p, or an anti-oxidation treatment such as OSP treatment may be performed.

[0034] The wiring layer 36 is formed on the other side of the insulating layer 31. The wiring layer 36 includes via wiring filled in via holes 31x that penetrate the insulating layer 31 and expose the other surface of the wiring layer 32, and a wiring pattern formed on the other surface of the insulating layer 31.

[0035] The via hole 31x can be a truncated cone-shaped recess that opens on the solder resist layer 37 side and has a bottom formed by the other surface of the wiring layer 32, with the diameter of the opening being larger than the diameter of the bottom. The upper end of the via wiring filled in the via hole 31x of the wiring layer 36 contacts and is conductive with the other surface of the wiring layer 32. The material of the wiring layer 36 and the thickness of the wiring pattern that constitutes the wiring layer 36 can be the same as, for example, the wiring layer 12.

[0036] The solder resist layer 37 is formed on the other surface of the insulating layer 31 so as to cover the wiring layer 36. The material and thickness of the solder resist layer 37 may be the same as those of the solder resist layer 13, for example. The solder resist layer 37 has openings 37x, and a portion of the wiring layer 36 is exposed in the openings 37x. The wiring layer 36 exposed in the openings 37x includes pads 36p.

[0037] If necessary, the other surface of the pad 36p may be provided with the aforementioned metal layer or subjected to an anti-oxidation treatment such as OSP treatment.

[0038] A semiconductor chip 40 is flip-chip mounted face-down (with the circuit-forming surface 40a facing the one surface of the substrate 30) on one surface 30a of the substrate 30. More specifically, the semiconductor chip 40 has a chip body 41 equipped with a semiconductor integrated circuit and protruding electrodes 42 serving as connection terminals, and the protruding electrodes 42 of the semiconductor chip 40 are electrically connected to pads 34p of the substrate 30 via conductive bonding material 43. For example, gold bumps or copper posts can be used as the protruding electrodes 42. For example, the conductive bonding material 43 can be a solder material such as an alloy containing Pb, an alloy of Sn and Cu, an alloy of Sn and Sb, an alloy of Sn and Ag, or an alloy of Sn, Ag, and Cu.

[0039] An underfill resin 60 is filled between the circuit formation surface 40a of the semiconductor chip 40 and one surface 30a of the substrate 30. The underfill resin 60 also extends to each side surface 40s of the semiconductor chip 40. The back surface 40b of the semiconductor chip 40 is exposed from the underfill resin 60.

[0040] In other words, the circuit formation surface 40a and the side surfaces 40s of the semiconductor chip 40 are continuously covered with the underfill resin 60. That is, the underfill resin 60 has a covering portion that covers the side surfaces 40s. The underfill resin 60 may be made of an insulating resin such as a thermosetting epoxy resin. The underfill resin 60 may contain a filler such as silica (SiO2). The planar shape of the semiconductor chip 40 is not particularly limited, but may be, for example, a rectangular shape of approximately 12 mm square.

[0041] The underfill resin 60 further has a protrusion 61 that protrudes from a portion (covering portion) extending on the side surface 40s of the semiconductor chip 40 toward the other surface 10b of the substrate 10. The protrusion 61 has an apex 61a that is located closer to the other surface 10b of the substrate 10 than the back surface 40b of the semiconductor chip 40. The height H of the protrusion 61 (the amount of protrusion from the back surface 40b of the semiconductor chip 40) can be, for example, approximately 15 μm to 20 μm. In other words, the height from the one surface 30a of the substrate 30 to the apex 61a of the protrusion 61 is greater than the height from the one surface 30a of the substrate 30 to the back surface 40b of the semiconductor chip 40.

[0042] 2, the protrusion 61 is provided in a straight line parallel to the two side surfaces 40s of the semiconductor chip 40, outside the two parallel side surfaces 40s of the semiconductor chip 40. The width W of the protrusion 61 can be set to, for example, about 250 μm to 350 μm on the same plane as the back surface 40b of the semiconductor chip 40.

[0043] 2 is a schematic plan view illustrating the arrangement of protrusions in the first embodiment, and only shows some of the components of the electronic component built-in substrate 1. The dimensions in FIG. 2 do not match those in FIG. 1. Region E in FIG. 2 indicates the region where the substrate connecting member 20 is arranged. Arrow F in FIG. 2 indicates an example of the flow direction of the molding resin in the manufacturing process of the electronic component built-in substrate.

[0044] The substrate connecting member 20 is disposed between the pad 14p of the substrate 10 and the pad 34p of the substrate 30. The substrate connecting member 20 electrically connects the substrates 10 and 30 and also has the function of ensuring a predetermined distance between the substrates 10 and 30.

[0045] In this embodiment, as an example, a solder ball with a core is used as the board connecting member 20. The board connecting member 20 includes a substantially spherical core 21 and a conductive material 22 that covers the outer peripheral surface of the core 21, and is arranged so that the core 21 contacts the pads 14p and 34p.

[0046] The core 21 may be, for example, a metal core made of a metal such as copper or a resin core made of a resin. The conductive material 22 may be, for example, a solder material such as an alloy containing Pb, an alloy of Sn and Cu, an alloy of Sn and Sb, an alloy of Sn and Ag, or an alloy of Sn, Ag, and Cu. The diameter of the core 21 may be determined appropriately taking into consideration the height (thickness) of the semiconductor chip 40. For example, the diameter of the core 21 may be approximately 160 μm, the thickness of the conductive material 22 may be approximately 20 μm, and the overall diameter of the board connecting member 20 may be approximately 200 μm.

[0047] 1, the substrate connecting members 20 are arranged in three rows on each side of the semiconductor chip 40, but this is not limiting, and the substrate connecting members 20 may be arranged in two rows or four or more rows on each side of the semiconductor chip 40. The substrate connecting members 20 may also be arranged peripherally on the periphery of the substrate 10. For example, if the diameter of the substrate connecting members 20 is about 200 μm, the pitch of the substrate connecting members 20 can be about 270 μm.

[0048] The substrate 10 does not need to be flat overall. For example, as shown in FIG. 1, the portion overlapping the semiconductor chip 40 in a plan view may bend more toward the substrate 30 than the surrounding portion to which the substrate connecting member 20 is connected. In this case, the top 61a of the protrusion 61 may be in direct contact with the other surface 10b of the substrate 10. Although the amount of bending is small, for ease of explanation, the bending of the substrate 10 is exaggerated in FIG. 1 and other figures. Even if the substrate 10 is bent, the amount of bending of the substrate 10 is small, so that it does not interfere with the mounting of electronic components such as semiconductor chips and semiconductor packages on the pads 12p.

[0049] The molding resin 70 seals the board connecting member 20, the semiconductor chip 40, and the underfill resin 60, and others Side 10 b and the substrate 30 one Side 30 aThe mold resin 70 is filled between the back surface 40b of the semiconductor chip 40 and the other surface 30b of the substrate 30. For example, an insulating resin such as a thermosetting epoxy resin containing a filler can be used as the mold resin 70. The mold resin 70 is also filled between the back surface 40b of the semiconductor chip 40 and the other surface 30b of the substrate 30.

[0050] The external connection terminals 90 are provided on the other surface of the pads 36p and protrude downward from the other surface of the solder resist layer 37 through the openings 37x. The external connection terminals 90 are, for example, solder bumps. The external connection terminals 90 may also include posts and bumps thereon. The external connection terminals 90 function as external connection terminals that are electrically connected to a mounting substrate (not shown), such as a motherboard.

[0051] [Method for manufacturing a substrate with built-in electronic components according to the first embodiment] Next, a method for manufacturing an electronic component built-in substrate according to the first embodiment will be described. Figures 3 to 9 are cross-sectional views illustrating the manufacturing process of an electronic component built-in substrate according to the first embodiment. Note that, here, only a portion that will become one electronic component built-in substrate is shown and each step will be explained, but in reality, a plurality of portions that will become electronic component built-in substrates are manufactured and then singulated to manufacture a plurality of electronic component built-in substrates.

[0052] 3(a), a substrate 30 is fabricated. Specifically, an insulating layer 31 is prepared using a so-called glass epoxy substrate or the like as described above, and a wiring layer 32 is formed on one surface of the insulating layer 31. Next, via holes 31x are formed in the insulating layer 31 to expose the other surface of the wiring layer 32, and a wiring layer 36 is further formed on the other surface of the insulating layer 31. The wiring layer 32 and the wiring layer 36 are electrically connected via via wiring in the via holes 31x.

[0053] After the via holes 31x are formed, it is preferable to perform a desmear process to remove resin residue adhering to the surface of the wiring layer 32 exposed at the bottom of the via holes 31x. The via holes 31x can be formed, for example, by a laser processing method using a CO2 laser or the like. The wiring layers 32 and 36 can be formed using various wiring formation methods, such as a semi-additive method or a subtractive method. For example, the wiring layers 32 and 36 can be formed by copper plating or the like.

[0054] Next, an insulating resin film such as a thermosetting epoxy resin is laminated on one surface of the insulating layer 31 so as to cover the wiring layer 32, thereby forming the insulating layer 33. Alternatively, instead of laminating an insulating resin film such as a thermosetting epoxy resin, the insulating layer 33 may be formed by applying an insulating resin such as a liquid or paste-like thermosetting epoxy resin and then curing it.

[0055] Next, via holes 33x are formed in the insulating layer 33, penetrating the insulating layer 33 and exposing one surface of the wiring layer 32. The via holes 33x can be formed by, for example, a laser processing method using a CO2 laser or the like. After the via holes 33x are formed, it is preferable to perform a desmear process to remove resin residue adhering to the surface of the wiring layer 32 exposed at the bottom of the via holes 33x.

[0056] Next, a wiring layer 34 is formed on one side of the insulating layer 33. The wiring layer 34 includes via wiring filled in the via holes 33x and a wiring pattern formed on one surface of the insulating layer 33. The wiring layer 34 is electrically connected to the wiring layer 32 exposed at the bottom of the via holes 33x. The wiring layer 34 can be formed using various wiring formation methods such as a semi-additive method or a subtractive method.

[0057] Next, a solder resist layer 35 that covers the wiring layer 34 is formed on one surface of the insulating layer 33, and a solder resist layer 37 that covers the wiring layer 36 is formed on the other surface of the insulating layer 31. The solder resist layer 35 can be formed by applying an insulating resin such as a liquid or paste-like photosensitive epoxy resin to one surface of the insulating layer 33 so as to cover the wiring layer 34 by screen printing, roll coating, spin coating, or the like.

[0058] Similarly, the solder resist layer 37 can be formed by applying an insulating resin, such as a liquid or paste-like photosensitive epoxy resin, in a similar manner to the other surface of the insulating layer 31 so as to cover the wiring layer 36. Alternatively, instead of applying a liquid or paste-like resin, for example, an insulating resin, such as a film-like photosensitive epoxy resin, may be laminated.

[0059] Then, the applied or laminated insulating resin is exposed to light and developed to form openings 35x and 37x in the solder resist layers 35 and 37, thereby forming pads 34p and 36p (photolithography). The openings 35x and 37x may also be formed by laser processing or blasting. The planar shape of each of the openings 35x and 37x may be, for example, circular. The diameter of each of the openings 35x and 37x can be freely designed to suit the connection target. This completes the substrate 30.

[0060] Next, as shown in FIG. 3(b), underfill resin 60 is applied (laminated) to one surface of the substrate 30 so as to cover the portions of the pads 34p of the substrate 30 that are to be connected to the semiconductor chip 40. As the underfill resin 60, for example, an insulating resin such as a film-like thermosetting epoxy resin can be used. At this stage, the underfill resin 60 is in a B-stage state (semi-cured state). Note that instead of a film-like resin, a liquid resin may be used as the underfill resin 60.

[0061] Next, as shown in Fig. 4, a semiconductor chip 40 is prepared, in which protruding electrodes 42 are formed on the circuit formation surface 40a side of a chip body 41 equipped with a semiconductor integrated circuit. A conductive bonding material 43 is provided on the tip of the protruding electrode 42. Then, the semiconductor chip 40 is attached to a bonding tool 80. As described above, the conductive bonding material 43 may be, for example, a solder material such as an alloy containing Pb, an alloy of Sn and Cu, an alloy of Sn and Sb, an alloy of Sn and Ag, or an alloy of Sn, Ag, and Cu.

[0062] A recess communicating with a suction hole (not shown) is formed on a surface 81 of the bonding tool 80 facing the back surface of the semiconductor chip 40. For example, a groove 82 is formed as the recess. The groove 82 is formed corresponding to the region where the protrusion 61 of the underfill resin 60 is to be formed. That is, the groove 82 is formed linearly in a plan view. For example, the depth of the groove 82 is about 150 μm to 250 μm, and the width is about 300 μm to 400 μm. The semiconductor chip 40 is mounted on the bonding tool 80 with the surface 81 of the bonding tool 80 covered with a film 83 such as a fluororesin film, and the film 83 in close contact with the surface 81 through the suction hole and the groove 82.

[0063] 5, the conductive bonding material 43 and underfill resin 60 are heated to a predetermined temperature, for example, about 250° C., and then pressed into the underfill resin 60 until the conductive bonding material 43 at the tip of the protruding electrode 42 contacts one surface of the pad 34p. Because the semi-cured underfill resin 60 has fluidity, part of the underfill resin 60 creeps up onto the side surface 40s of the semiconductor chip 40 and enters the inside of the groove 82.

[0064] After the conductive bonding material 43 and underfill resin 60 have hardened by cooling, the bonding tool 80 and film 83 are removed from the semiconductor chip 40, as shown in FIG. 6( a). The protruding electrodes 42 of the semiconductor chip 40 are electrically connected to the pads 34p of the substrate 30 via the conductive bonding material 43. The underfill resin 60 is filled between the circuit-forming surface 40a of the semiconductor chip 40 and one surface 30a of the substrate 30, and the underfill resin 60 also extends to each side surface 40s of the semiconductor chip 40. The underfill resin 60 further has protrusions 61 that protrude upward from the portions extending to the two side surfaces 40s of the semiconductor chip 40, and the protrusions 61 have apexes 61a located above the back surface 40b of the semiconductor chip 40. In other words, the underfill resin 60 is molded so as to expose the back surface 40b of the semiconductor chip 40, cover the circuit-forming surface 40a and the side surfaces 40s, and have the protrusions 61. The rear surface 40b of the semiconductor chip 40 and the upper surface of the underfill resin 60 covering the side surface 40s of the semiconductor chip 40, excluding the protruding portion 61, can be flush with each other, for example.

[0065] In this manner, the semiconductor chip 40 can be flip-chip mounted face-down on one surface 30a of the substrate 30.

[0066] The height H of the protrusion 61 is set to such an extent that, for example, when the substrate 10 on which the substrate connecting member 20 is mounted is stacked on the substrate 30 as described below, a gap is formed between the top 61a of the protrusion 61 and the other surface 10b of the substrate 10 (see FIG. 7(a)). This is to more reliably bond the substrates 10 and 30 via the substrate connecting member 20. If this does not impede the bonding of the substrates 10 and 30, the height H of the protrusion 61 may be set to such an extent that the top 61a of the protrusion 61 and the other surface 10b of the substrate 10 come into contact with each other.

[0067] Separately from the fabrication of the substrate 30 and the flip-mounting of the semiconductor chip 40, the substrate 10 is fabricated as shown in FIG. 6(b). Specifically, an insulating layer 11 is prepared using a so-called glass epoxy substrate or the like as described above, and a wiring layer 14 is formed on the other surface of the insulating layer 11. Next, via holes 11x are formed in the insulating layer 11 to expose one surface of the wiring layer 14, and a wiring layer 12 is further formed on one surface of the insulating layer 11. The wiring layer 12 and the wiring layer 14 are electrically connected via via wiring in the via holes 11x.

[0068] After the via holes 11x are formed, it is preferable to perform a desmear process to remove resin residue adhering to the surface of the wiring layer 14 exposed at the bottom of the via holes 11x. The via holes 11x can be formed, for example, by a laser processing method using a CO2 laser or the like. The wiring layers 12 and 14 can be formed using various wiring formation methods, such as a semi-additive method or a subtractive method. For example, the wiring layers 12 and 14 can be formed by copper plating or the like.

[0069] Next, in the same manner as the solder resist layer 35 of the substrate 30, a solder resist layer 13 is formed on one surface of the insulating layer 11 to cover the wiring layer 12, and a solder resist layer 15 is formed on the other surface of the insulating layer 11 to cover the wiring layer 14. Then, in the same manner as the openings 35x of the substrate 30, openings 13x and 15x are formed in the solder resist layers 13 and 15, and pads 12p and 14p are formed (photolithography method). This completes the substrate 10.

[0070] 6(c), the substrate connecting member 20 is placed on the pad 14p exposed in the opening 15x of the solder resist layer 15 of the substrate 10. Then, the substrate connecting member 20 is heated to a predetermined temperature to melt the conductive material 22 that constitutes the substrate connecting member 20, and then hardened to bond it to the pad 14p.

[0071] Next, as shown in Figure 7(a), the substrate 10 carrying the substrate connecting member 20 is turned upside down from the state shown in Figure 6(c), and is stacked on the substrate 30 so that the conductive material 22 of the substrate connecting member 20 carried on the substrate 10 contacts one side of the pad 34p.

[0072] Then, while the conductive material 22 is heated and melted, the substrate 10 is pressed against the substrate 30. As a result, the substrate connecting member 20 comes into contact with the pad 14p of the substrate 10 and the pad 34p of the substrate 30, and the substrates 10 and 30 are electrically connected via the substrate connecting member 20. In addition, the core 21 of the substrate connecting member 20 ensures a predetermined distance between the substrates 10 and 30.

[0073] Next, as shown in Fig. 7(b), the structure shown in Fig. 7(a) is sandwiched between a lower mold 500 having a frame portion 510 and a cavity portion 520, and an upper mold 600 having a frame portion 610 and a cavity portion 620. At this time, the structure shown in Fig. 7(a) is held between the lower mold 500 and the upper mold 600 in a state where the lower surface of the solder resist layer 37 is in contact with the bottom surface of the cavity portion 520, and the upper surface of the solder resist layer 13 is in contact with the bottom surface of the cavity portion 620 via the release film 400.

[0074] By providing release film 400 on the inner wall of cavity 620, it is possible to prevent mold resin 70 from coming into direct contact with the inner wall of cavity 620. As release film 400, a film that has heat resistance that can withstand the heating temperature of mold resin 70 and that can be easily peeled off from the inner wall of cavity 620 can be used. Furthermore, release film 400 preferably has flexibility and extensibility that allows it to easily deform to follow the shape of the inner wall of cavity 620. Specifically, as release film 400, for example, polytetrafluoroethylene (PTFE), ethylene tetrafluoroethylene (ETFE), polyethylene terephthalate (PET), fluorinated ethylene propylene (FEP) film, fluorine-impregnated glass cloth, polypropylene film, polyvinylidine chloride, etc. can be used.

[0075] The release film 400 may also be provided on the inner wall of the cavity portion 520. Furthermore, the release film 400 may be provided on the inner wall of the cavity portion 520 without providing the release film 400 on the inner wall of the cavity portion 620.

[0076] 7(b), the substrate 10 is pressed by being sandwiched between the lower mold 500 and the upper mold 600, causing the substrate 10 to bend and the other surface 10b of the substrate 10 to come into contact with the tops 61a of the protrusions 61. Between the two protrusions 61, the distance between the back surface 40b of the semiconductor chip 40 and the other surface 10b of the substrate 10 is equal to the height H of the protrusions 61. The distance between the back surface 40b of the semiconductor chip 40 and the other surface 10b of the substrate 10 can be, for example, approximately 15 μm to 20 μm.

[0077] Next, as shown in FIG. 8(a), a liquid insulating resin that becomes the mold resin 70 is injected into the cavities 520 and 620 through a resin injection port (not shown), filling the cavities 520 and 620 with the liquid insulating resin and then curing. This forms the mold resin 70 that seals the board connecting member 20, the semiconductor chip 40, and the underfill resin 60 between the substrates 10 and 30. For example, an insulating resin such as a thermosetting epoxy resin containing a filler can be used as the mold resin 70. The liquid insulating resin is injected so that it flows, for example, parallel to the extension direction of the protrusions 61 (see FIG. 2).

[0078] Next, as shown in FIG. 8(b), the structure shown in FIG. 8(a) is removed from the sealing mold having the lower mold 500 and the upper mold 600.

[0079] In this way, the molding resin 70 can be formed by, for example, a transfer molding method using a sealing mold.

[0080] As described above, in practice, a plurality of portions that will become the electronic component-embedded substrates are fabricated and then singulated to fabricate a plurality of electronic component-embedded substrates. That is, in the step of Fig. 8(a), molding resin 70 is simultaneously formed on a plurality of portions that will become the electronic component-embedded substrates. After the molding resin 70 is formed, the plurality of portions that will become the electronic component-embedded substrates are singulated.

[0081] Next, as shown in FIG. 9, external connection terminals 90 are formed on the other surface of the pads 36p so as to protrude downward from the other surface of the solder resist layer 37 through the openings 37x.

[0082] In this way, the electronic component built-in substrate 1 according to the first embodiment is completed.

[0083] As described above, in the electronic component built-in substrate 1 according to the first embodiment, the underfill resin 60 has a protrusion 61 that protrudes from a portion extending to the side surface 40s of the semiconductor chip 40 toward the other surface 10b of the substrate 10, and the protrusion 61 has an apex 61a that is located closer to the other surface 10b of the substrate 10 than the back surface 40b of the semiconductor chip 40. Therefore, even if pressure is applied from above and below to the structure of FIG. 7(b) filled with the mold resin 70 when forming the mold resin 70 (see FIG. 8(a)), the back surface 40b of the semiconductor chip 40 and the other surface 10b of the substrate 10 can be easily formed. b A gap can be secured between them.

[0084] As a result, the back surface 40b of the semiconductor chip 40 and the other surface 10 of the substrate 10 b As a result, the back surface 40b of the semiconductor chip 40 and the other surface 10 of the substrate 10 can be easily infused with the molding resin 70 into the area where the back surface 40b of the semiconductor chip 40 and the other surface 10 of the substrate 10 face each other. b This allows the opposing area to be filled with molding resin 70 reliably.

[0085] In addition, the back surface 40b of the semiconductor chip 40 and the other surface 10 of the substrate 10 b Therefore, the back surface 40b of the semiconductor chip 40 and the other surface 10 of the substrate 10 can be reliably filled with the molding resin 70. b This allows the design value of the gap between the electronic component built-in substrate 1 to be reduced, thereby making it possible to reduce the total height of the electronic component built-in substrate 1.

[0086] In particular, when molding resin 70 is filled in the gap between top 61a of protrusion 61 and the other surface 10b of substrate 10, protrusion 61 and substrate 10 are bonded together. Therefore, even if electronic component-embedded substrate 1 is used in an environment where high temperature and low temperature environments are alternately experienced, the vicinity of protrusion 61 can be prevented from becoming a starting point for peeling.

[0087] 8(a), a force acts between the substrate 10 and the substrate 30 in a direction that spreads them apart due to the injection pressure of the insulating resin. Therefore, depending on the height of the protrusion 61 and the magnitude of the injection pressure of the insulating resin, a gap may be formed between the top 61a of the protrusion 61 and the other surface 10b of the substrate 10, and the mold resin 70 may also fill the gap. Furthermore, if a release film 400 is provided on at least one inner wall of the cavity 520 or 620, deformation (contraction) of the release film 400 may also cause a gap to be formed between the top 61a of the protrusion 61 and the other surface 10b of the substrate 10.

[0088] When a gap occurs between the top 61a of the protrusion 61 and the other surface 10b of the substrate 10, the gap is filled with a molding resin 70, as shown in Fig. 10. As a result, the deflection of the substrate 10 is alleviated, and the top 61a of the protrusion 61 and the substrate 10 are bonded together by the molding resin 70. Therefore, even when the electronic component built-in substrate 1 is used in an environment where high temperature and low temperature environments are alternately experienced, for example, it is possible to prevent the vicinity of the protrusion 61 from becoming a starting point for peeling. Fig. 10 is a cross-sectional view illustrating an electronic component built-in substrate 1A according to a first modified example of the first embodiment.

[0089] However, it is not an essential requirement that the molding resin 70 fill the gap between the top 61a of the protrusion 61 and the other surface 10b of the substrate 10. For example, depending on the height of the protrusion 61 and the magnitude of the injection pressure of the insulating resin, the molding resin 70 may not fill the gap between the top 61a of the protrusion 61 and the other surface 10b of the substrate 10.

[0090] In addition, a protrusion 61 whose top 61a is in contact with the other surface 10b of the substrate 10 and a protrusion 61 whose top 61a is bonded to the other surface 10b of the substrate 10 with molded resin 70 may be mixed within a single electronic component-embedded substrate 1.

[0091] (Second embodiment) Next, a second embodiment will be described. The second embodiment differs from the first embodiment mainly in the configuration of the board connecting member.

[0092] [Structure of electronic component embedded board] First, the structure of the electronic component built-in substrate will be described. Fig. 11 is a cross-sectional view illustrating an example of an electronic component built-in substrate according to the second embodiment.

[0093] As shown in FIG. 11, in an electronic component built-in substrate 2 according to the second embodiment, a substrate connecting member 20 has a metal pillar (metal column) 23 and conductive materials 24 and 25 instead of a solder ball with a core.

[0094] The metal pillar 23 may be, for example, a copper pillar. The conductive materials 24 and 25 may be, for example, the same as the conductive material 22. The conductive material 24 joins the metal pillar 23 to the pad 14p of the substrate 10. The conductive material 25 joins the metal pillar 23 to the pad 34p of the substrate 30.

[0095] The other configurations are the same as those in the first embodiment.

[0096] [Method for manufacturing a substrate with built-in electronic components according to the second embodiment] Next, a description will be given of a method for manufacturing an electronic component built-in substrate according to the second embodiment. Figure 12 is a diagram illustrating an example of a manufacturing process for an electronic component built-in substrate according to the second embodiment.

[0097] First, similarly to the first embodiment, a substrate 30 is fabricated, and a semiconductor chip 40 is mounted on the substrate 30 (see FIGS. 3 to 6(a)). Further, similarly to the first embodiment, a substrate 10 is fabricated (see FIG. 6(b)). Next, as shown in FIG. 12, a metal pillar 23 is bonded to a pad 14p exposed in an opening 15x of a solder resist layer 15 of the substrate 10 using a conductive material 24.

[0098] Next, the substrate 10 with the metal pillars 23 mounted thereon is turned upside down from the state shown in FIG. 12 and stacked on the substrate 30. At this time, the conductive material 25 is interposed between the metal pillars 23 and the pads 34p. Then, while the conductive material 25 is heated, the substrate 10 is pressed toward the substrate 30. As a result, the substrates 10 and 30 are electrically connected via the substrate connecting member 20. In addition, the metal pillars 23 ensure a predetermined distance between the substrates 10 and 30.

[0099] Thereafter, similarly to the first embodiment, the processes from the formation of the molding resin 70 onwards are carried out.

[0100] In this way, the electronic component built-in substrate 2 according to the second embodiment is completed.

[0101] The second embodiment can also provide the same effects as the first embodiment.

[0102] (Third embodiment) Next, a third embodiment will be described. The third embodiment differs from the first embodiment mainly in the positions of the external connection terminals. Fig. 13 is a cross-sectional view illustrating an example of an electronic component built-in substrate according to the third embodiment.

[0103] As shown in FIG. 13 , the electronic component built-in substrate 3 according to the third embodiment has an external connection terminal 91 instead of the external connection terminal 90. The external connection terminal 91 is provided on one surface of the pad 12p and protrudes upward from one surface of the solder resist layer 13 through the opening 13x. The external connection terminal 91 may include a post and a bump thereon. The external connection terminal 91 functions as an external connection terminal electrically connected to, for example, a mounting substrate such as a motherboard (not shown). On the other hand, the pad 36p functions as a pad electrically connected to an electronic component (not shown) such as a semiconductor chip or semiconductor package.

[0104] The other configurations are the same as those in the first embodiment.

[0105] The third embodiment can also provide the same effects as the first embodiment.

[0106] (Fourth embodiment) Next, a fourth embodiment will be described. The fourth embodiment differs from the first embodiment mainly in the arrangement of the protrusions. FIG. 14 is a plan view schematic illustrating the arrangement of the protrusions in the fourth embodiment. As with FIG. 2, FIG. 14 schematically illustrates only some of the components of the electronic component built-in substrate. The dimensional relationship in FIG. 14 does not match that in FIG. 1. In addition, in FIG. 14, region E indicates the region where board connecting member 20 is arranged. Arrow F in FIG. 14 indicates an example of the flow direction of molding resin in the manufacturing process of the electronic component built-in substrate.

[0107] 14, in the electronic component built-in substrate according to the fourth embodiment, the underfill resin 60 has a protrusion 62 in addition to the protrusion 61. Like the protrusion 61, the protrusion 62 has an apex that is located closer to the other surface 10b of the substrate 10 than the back surface 40b of the semiconductor chip 40. The height H of the protrusion 62 (the amount of protrusion from the back surface 40b of the semiconductor chip 40) can be, for example, about 15 μm to 20 μm.

[0108] As shown in FIG. 14 , the protrusions 62 are provided in an island shape on the outer side of the two parallel side surfaces 40s of the semiconductor chip 40 different from the two side surfaces 40s on which the protrusions 61 are provided. The planar shape of the protrusions 62 may be, for example, circular. For example, if the semiconductor chip 40 is rectangular and approximately 12 mm square, the protrusions 62 having a circular planar shape with a diameter of approximately 1 mm can be arranged at the position shown in FIG. 14 . In this case, a recess having a circular shape in plan view together with the groove 82 is provided on the surface 81 of the bonding tool 80. When the planar shape of the protrusions 62 is circular, the shape of the protrusions 62 may be cylindrical or may be a truncated cone whose diameter decreases toward the other surface 10b of the substrate 10. The planar shape of the protrusions 62, the position at which the protrusions 62 are arranged, and the number of the protrusions 62 are not limited to the form shown in FIG. 14 and can be determined arbitrarily. For example, the planar shape of the protrusions 62 may be rectangular, elliptical, or the like, and the shape of the protrusions 62 may be a rectangular column, a truncated pyramid, an elliptical column, or a truncated elliptical cone. However, it is preferable that the protrusions 62 are arranged so as not to obstruct the flow of the molding resin 70.

[0109] The other configurations are the same as those in the first embodiment.

[0110] The fourth embodiment can also achieve the same effects as the first embodiment. Furthermore, according to the fourth embodiment, since the underfill resin 60 has the protrusions 61 and 62, the back surface 40b of the semiconductor chip 40 and the other surface 10 of the substrate 10 can be easily bonded to each other. b This makes it easier to ensure a gap between the

[0111] 1 and other figures, the top 61a of the protrusion 61 is flat, but the shape of the top 61a is not particularly limited. For example, as shown in FIG. 15, the top 61a of the protrusion 61 may be a curved surface that is convex toward the other surface 10b of the substrate 10. The same applies to the shape of the top of the protrusion 62. FIG. 15 is a cross-sectional view illustrating an electronic component-embedded substrate 1B according to a second modified example of the first embodiment.

[0112] The above describes in detail preferred embodiments, but the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims.

[0113] For example, a build-up substrate having more wiring layers and insulating layers formed thereon may be used as the substrate 10 or the substrate 30. In this case, a coreless build-up substrate may also be used. [Explanation of symbols]

[0114] 1, 1A, 1B, 2, 3 Electronic component embedded board 10, 30 board 10a, 10b, 30a, 30b side 20. Board connection member 21 cores 22, 24, 25 Conductive materials 23 Metal Pillar 40 Semiconductor Chips 60 Underfill resin 61, 62 Protrusion 61a Top 80 Bonding Tools 81 sides 82 Groove

Claims

1. a first substrate; a semiconductor chip mounted on the first substrate; a second substrate provided on the first substrate with the semiconductor chip sandwiched therebetween; a first resin that is filled between the semiconductor chip and the first substrate and has a covering portion that covers a side surface of the semiconductor chip; a second resin filled between the first substrate and the second substrate and sealing the semiconductor chip and the first resin; and the first resin has a plurality of protrusions protruding from the covering portion toward the second substrate, The semiconductor chip has a rectangular planar shape, An electronic component-embedded substrate, wherein two of the plurality of protrusions are provided on the outer sides of two parallel side surfaces of the semiconductor chip in a plan view.

2. The electronic component built-in substrate according to claim 1 , wherein the two protrusions are provided linearly in parallel to the two side surfaces in a plan view.

3. 3. The electronic component built-in substrate according to claim 2, wherein at least one other of the plurality of protrusions is provided in an island shape on the outside of a side surface of the semiconductor chip that is different from the two side surfaces.

4. A first substrate; a semiconductor chip mounted on the first substrate; a second substrate provided on the first substrate with the semiconductor chip sandwiched therebetween; a first resin that is filled between the semiconductor chip and the first substrate and has a covering portion that covers a side surface of the semiconductor chip; a second resin filled between the first substrate and the second substrate and sealing the semiconductor chip and the first resin; and the first resin has a plurality of protrusions protruding from the covering portion toward the second substrate, At least two of the plurality of protrusions are spaced apart from the semiconductor chip in a plan view and are arranged to sandwich the semiconductor chip therebetween.

5. a gap is formed between the protrusion and the second substrate; The electronic component built-in substrate according to claim 1 , wherein the gap is filled with the second resin.

6. The electronic component built-in substrate according to claim 1 , wherein the protrusion is in contact with the second substrate.

7. The electronic component built-in substrate according to claim 1 , further comprising a substrate connecting member provided between the first substrate and the second substrate, for electrically connecting the first substrate and the second substrate.

8. the first resin is an underfill resin, 8. The electronic component built-in substrate according to claim 1, wherein the second resin is a molding resin.

9. providing a first resin on a first substrate; mounting a semiconductor chip on the first substrate via the first resin; providing a second substrate on the first substrate with the semiconductor chip sandwiched therebetween; a step of filling a second resin between the first substrate and the second substrate to seal the semiconductor chip and the first resin; and In the step of mounting the semiconductor chip, the semiconductor chip is pressed into the first resin while being held by suction at the center of a bonding tool; a recess is formed in the peripheral edge of the bonding tool, A method for manufacturing a substrate with embedded electronic components, in which the peripheral portion of the first resin is pressed by the peripheral portion of the bonding tool and the first resin is forced into the recess, thereby forming a covering portion in the first resin that covers the side surface of the semiconductor chip and forming a protrusion portion in the covering portion that protrudes toward the second substrate.

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