Ceramic electronic component and manufacturing method thereof

Abstract

To provide a ceramic electronic component capable of suppressing exfoliation of an external electrode and a manufacturing method for the same.SOLUTION: The ceramic electronic component includes: a laminated chip formed so that each of multiple dielectric layers mainly composed of ceramics and each of multiple inner electrode layers are laminated alternately and, the laminated multiple inner electrode layers are exposed alternately from multiple portions; and external electrodes provided on the multiple portions, respectively. The external electrode includes, at least in a portion: a first metal layer provided in contact with the laminated chip; and a plated layer provided on the first metal layer. The first metal layer includes: a first metal; and a second metal having a Young's modulus lower than that of the first metal.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a ceramic electronic component and a method for manufacturing the same. [Background technology]

[0002] Ceramic electronic components such as multilayer ceramic capacitors have a structure that includes a laminated chip in which dielectric layers and internal electrode layers are alternately stacked, and the stacked internal electrode layers are alternately exposed at multiple locations, and external electrodes provided at the multiple locations (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-65394 Summary of the Invention [Problem to be solved by the invention]

[0004] However, the external electrodes may peel off from the stacked chip.

[0005] The present invention has been made in view of the above-mentioned problems, and has as its object to provide a ceramic electronic component that can suppress peeling of external electrodes, and a method for manufacturing the same. [Means for solving the problem]

[0006] The ceramic electronic component of the present invention comprises a laminated chip in which a plurality of dielectric layers primarily composed of ceramic and a plurality of internal electrode layers are alternately stacked, and the stacked internal electrode layers are alternately exposed at a plurality of locations; and an external electrode provided at each of the plurality of locations, wherein the external electrode at least partially comprises a first metal layer provided in contact with the laminated chip and a plating layer provided on the first metal layer, and the first metal layer includes a first metal and a second metal having a lower Young's modulus than the first metal.

[0007] In the above ceramic electronic component, the external electrode may have a structure in which the plating layer is provided on a base layer provided in contact with the multiple locations, and the first metal layer may be provided in contact with the laminated chip at an interruption in the base layer.

[0008] In the ceramic electronic component, the Young's modulus of the second metal may be equal to or less than two-thirds of the Young's modulus of the first metal.

[0009] In the first metal layer of the ceramic electronic component, the amount of the second metal may be 1 at % or less when the amount of the first metal is 100 at %.

[0010] In the ceramic electronic component, the first metal may be Ti or Cr.

[0011] In the ceramic electronic component, the second metal may be Sn or In.

[0012] In the ceramic electronic component, the first metal layer may have a thickness of 5 nm or more and 100 nm or less.

[0013] The ceramic electronic component may further include a second metal layer provided between the first metal layer and the plating layer.

[0014] In the ceramic electronic component, the dielectric layer may contain barium titanate as a main component.

[0015] The method for manufacturing a ceramic electronic component according to the present invention includes the steps of: preparing a laminated chip in which a plurality of dielectric layers, primarily composed of ceramic, and a plurality of internal electrode layers are alternately stacked, with the stacked internal electrode layers being alternately exposed at a plurality of locations; forming a metal layer by sputtering or vapor deposition, the metal layer being in contact with the laminated chip and electrically connected to the internal electrode layers exposed at the plurality of locations; and forming a plating layer on the metal layer, wherein the metal layer includes a first metal and a second metal having a lower Young's modulus than the first metal. [Effects of the Invention]

[0016] According to the present invention, it is possible to provide a ceramic electronic component that can suppress peeling of external electrodes, and a method for manufacturing the same. [Brief explanation of the drawings]

[0017] [Figure 1] FIG. 2 is a partial cross-sectional perspective view of a multilayer ceramic capacitor. [Figure 2] FIG. 2 is a cross-sectional view taken along line AA in FIG. [Figure 3] FIG. 2 is a cross-sectional view taken along line BB in FIG. [Figure 4] 2 is a cross-sectional view of an external electrode, and is a partial cross-sectional view taken along line AA in FIG. 1. [Figure 5] FIG. 5 is a partially enlarged view of FIG. [Figure 6] 1A to 1C are diagrams illustrating a flow of a method for manufacturing a multilayer ceramic capacitor. [Figure 7] 1(a) and 1(b) are diagrams illustrating the lamination process. [Figure 8] FIG. 1(a) is a diagram illustrating application of a metal paste, and FIG. 1(b) is a diagram illustrating a metal layer forming step. [Figure 9](a) is a trace of the SEM photograph of the cross section, (b) is an enlarged view of part A, and (c) is an enlarged view of part B. DETAILED DESCRIPTION OF THE INVENTION

[0018] Hereinafter, embodiments will be described with reference to the drawings.

[0019] (Embodiment) FIG. 1 is a partial cross-sectional perspective view of a multilayer ceramic capacitor 100 according to an embodiment. FIG. 2 is a cross-sectional view taken along line AA in FIG. 1. FIG. 3 is a cross-sectional view taken along line BB in FIG. 1. As illustrated in FIGS. 1 to 3, the multilayer ceramic capacitor 100 includes a laminated chip 10 having a substantially rectangular parallelepiped shape and external electrodes 20a, 20b provided on two opposing end faces of the laminated chip 10. Of the four faces of the laminated chip 10 other than the two end faces, the two faces other than the top and bottom faces in the stacking direction are referred to as side faces. The external electrodes 20a, 20b extend on the top, bottom and two side faces of the laminated chip 10 in the stacking direction. However, the external electrodes 20a, 20b are spaced apart from each other.

[0020] 1 to 3, the X-axis direction is the direction in which the two end faces of the laminated chip 10 face each other, and in which the external electrodes 20a and 20b face each other. The Y-axis direction is the direction in which the two side faces of the laminated chip 10 face each other. The Z-axis direction is the stacking direction, and in which the top and bottom faces of the laminated chip 10 face each other. The X-axis direction, Y-axis direction, and Z-axis direction are perpendicular to each other.

[0021] The multilayer chip 10 has a configuration in which dielectric layers 11 containing a ceramic material that functions as a dielectric and internal electrode layers 12 containing a base metal material are alternately stacked. The edges of each internal electrode layer 12 are alternately exposed at multiple locations on the multilayer chip 10. For example, the edges of each internal electrode layer 12 are alternately exposed at the end face of the multilayer chip 10 where the external electrode 20a is provided and the end face where the external electrode 20b is provided. As a result, each internal electrode layer 12 is alternately electrically connected to the external electrode 20a and the external electrode 20b. As a result, the multilayer ceramic capacitor 100 has a configuration in which multiple dielectric layers 11 are stacked with the internal electrode layers 12 interposed therebetween. In addition, in a laminate of the dielectric layers 11 and the internal electrode layers 12, the internal electrode layer 12 is arranged as the outermost layer in the stacking direction, and the upper and lower surfaces of the laminate are covered with a cover layer 13. The cover layer 13 is primarily composed of a ceramic material. For example, the material of the cover layer 13 may be made of the same main component ceramic material as that of the dielectric layer 11 .

[0022] The size of the multilayer ceramic capacitor 100 is, for example, a length of 1.0±0.05 mm in the X-axis direction, a width of 0.5±0.05 mm in the Y-axis direction, and a height of 0.0975±0.0125 mm in the Z-axis direction, or a length of 0.6 mm, a width of 0.3 mm, and a height of 0.110 mm, or a length of 1.0 mm, a width of 0.5 mm, and a height of 0.1 mm, but is not limited to these sizes.

[0023] The internal electrode layers 12 are mainly composed of base metals such as Ni (nickel), Cu (copper), and Sn (tin). Noble metals such as Pt (platinum), Pd (palladium), Ag (silver), and Au (gold), or alloys containing these metals, may also be used as the internal electrode layers 12. The thickness of the internal electrode layers 12 is, for example, 0.1 μm to 3 μm, 0.1 μm to 1 μm, or 0.1 μm to 0.5 μm.

[0024] The dielectric layer 11 has a main phase made of a ceramic material having a perovskite structure represented by the general formula ABO3. 3-αFor example, the ceramic material includes BaTiO3 (barium titanate), CaZrO3 (calcium zirconate), CaTiO3 (calcium titanate), SrTiO3 (strontium titanate), MgTiO3 (magnesium titanate), BaTiO3 (barium titanate) which forms a perovskite structure, 1-x-y Ca x Sr y Ti 1-z Zr z At least one of the following can be selected and used: O3 (0≦x≦1, 0≦y≦1, 0≦z≦1). 1-x-y Ca x Sr y Ti 1-z Zr z O3 is barium strontium titanate, barium calcium titanate, barium zirconate, barium titanate zirconate, calcium titanate zirconate, barium calcium titanate zirconate, etc. The thickness of each dielectric layer 11 is, for example, 0.05 μm or more and 5 μm or less, or 0.1 μm or more and 3 μm or less, or 0.2 μm or more and 1 μm or less.

[0025] 2, the region where the internal electrode layer 12 connected to the external electrode 20a and the internal electrode layer 12 connected to the external electrode 20b face each other is a region where capacitance is generated in the multilayer ceramic capacitor 100. Therefore, this region where capacitance is generated is referred to as a capacitance region 14. In other words, the capacitance region 14 is a region where adjacent internal electrode layers 12 connected to different external electrodes face each other.

[0026] The region where the internal electrode layers 12 connected to the external electrode 20a face each other without an internal electrode layer 12 connected to the external electrode 20b interposed therebetween is called the end margin 15. The region where the internal electrode layers 12 connected to the external electrode 20b face each other without an internal electrode layer 12 connected to the external electrode 20a interposed therebetween is also the end margin 15. In other words, the end margin 15 is the region where the internal electrode layers 12 connected to the same external electrode face each other without an internal electrode layer 12 connected to a different external electrode interposed therebetween. The end margin 15 is a region where no capacitance is generated.

[0027] 3, in the laminated chip 10, the regions extending from the two side surfaces of the laminated chip 10 to the internal electrode layers 12 are referred to as side margins 16. In other words, the side margins 16 are regions provided so as to cover the ends of the multiple internal electrode layers 12 stacked in the above-mentioned laminated structure, which extend to the two side surfaces. The side margins 16 are also regions that do not generate electrical capacitance.

[0028] Fig. 4 is a cross-sectional view of the external electrode 20b, and is a partial cross-sectional view taken along line AA in Fig. 1. Note that hatching representing the cross section has been omitted in Fig. 4. As illustrated in Fig. 4, the external electrode 20b has a structure in which a plating layer is formed on an underlayer 24. The plating layer includes, for example, a first plating layer 21 such as Cu, a second plating layer 22 such as Ni, and a third plating layer 23 such as Sn, in that order from the underlayer 24 side.

[0029] The underlayer 24 is provided in contact with and covers an end face of the laminated chip 10. The underlayer 24 may extend from the end face toward the opposing end face, covering the two side faces, top face, and bottom face of the laminated chip 10. The underlayer 24 is primarily composed of a metal such as Cu, Ni, Al (aluminum), or Zn (zinc), and may also contain a glass component for densifying the underlayer 24 or a co-material for controlling the sinterability of the underlayer 24. The underlayer 24 containing a large amount of these ceramic components has good adhesion to the dielectric layer 11 and cover layer 13, which are primarily composed of a ceramic material. The external electrode 20a also has a laminated structure similar to that of the external electrode 20b.

[0030] A first metal layer 25 is provided between the underlayer 24 and the plating layer. The first metal layer 25 covers the surface of the underlayer 24 facing the plating layer. The first metal layer 25 extends toward the opposing end faces and over the two side faces, top face, and bottom face of the laminated chip 10. The first metal layer 25 extends beyond the underlayer 24 toward the opposing end faces. In the region where the first metal layer 25 extends beyond the underlayer 24 toward the opposing end faces, the first metal layer 25 is provided in contact with the surface of the laminated chip 10, and the plating layer is provided in contact with the first metal layer 25. For example, in the region where the underlayer 24 is not provided, the first metal layer 25 is provided in contact with the surfaces of the cover layer 13 and the side margin 16. Note that the first metal layer 25 is in contact with the underlayer 24 and is therefore electrically connected to the internal electrode layers. The external electrode 20a also has a laminate structure similar to that of the external electrode 20b.

[0031] In the region where the underlayer 24 is not provided, the first metal layer 25 functions as a seed layer in the plating process. Therefore, by providing the first metal layer 25 in the region where the underlayer 24 is not provided, peeling of the plating layer can be suppressed.

[0032] Even in regions where the underlayer 24 is provided, discontinuous portions (such as holes) where the underlayer 24 is not formed may occur. For example, when the underlayer 24 is formed by firing a metal paste, the metal paste may not adhere to a portion of the surface of the laminated chip 10 due to repellency or the like. In this case, as illustrated in FIG. 5, the underlayer 24 may not be formed in the areas where the metal paste has not adhered. In areas where the underlayer 24 has not been formed, the plating layer may peel off from the laminated chip 10. However, in this embodiment, the first metal layer 25 is provided in the areas where the underlayer 24 has not been formed, thereby preventing peeling of the plating layer.

[0033] The first metal layer 25 is primarily composed of a first metal such as titanium (Ti). However, Ti has a large Young's modulus of approximately 106 GPa. Therefore, during the plating process and subsequent handling process, the first metal layer 25 may lack flexibility to withstand the impact of collisions between multilayer ceramic capacitors, potentially resulting in peeling of the external electrodes 20a, 20b. Therefore, in this embodiment, the first metal layer 25 includes a second metal having a smaller Young's modulus than the first metal. This reduces the Young's modulus of the entire first metal layer 25, thereby providing flexibility to the first metal layer 25. This prevents peeling of the external electrodes 20a, 20b. Table 1 shows examples of the Young's modulus of each metal. [Table 1]

[0034] The smaller the Young's modulus of the second metal, the better from the viewpoint of increasing the flexibility of the first metal layer 25. For example, the Young's modulus of the second metal is preferably 2 / 3 or less of the Young's modulus of the first metal, more preferably 1 / 2 or less, and even more preferably 1 / 3 or less.

[0035] If the amount of the second metal in the first metal layer 25 is too large, there is a risk of melting. Therefore, it is preferable to set an upper limit on the amount of the second metal in the first metal layer 25. For example, when (first metal + second metal) is taken as 100 at%, the amount of the second metal is preferably 20 at% or less, more preferably 5 at% or less, and even more preferably 1 at% or less.

[0036] For example, the resistance value of Ti is about 20 to 30 times that of Cu, so if first metal layer 25 is formed too thick, there is a risk of poor connection. Therefore, it is preferable to set an upper limit on the thickness of first metal layer 25. For example, the thickness of first metal layer 25 is preferably 100 nm or less, more preferably 75 nm or less, and even more preferably 50 nm or less.

[0037] On the other hand, if the first metal layer 25 is formed too thin, there is a risk of peeling. Therefore, it is preferable to set a lower limit to the thickness of the first metal layer 25. For example, the thickness of the first metal layer 25 is preferably 5 nm or more, more preferably 10 nm or more, and even more preferably 20 nm or more.

[0038] For example, it is preferable to use Ti as the first metal, because it forms a Ti-O bond with the underlying barium titanate, and when the first plating layer 21 is Cu, it forms a Ti-Cu bond, improving adhesion. Alternatively, it is preferable to use Cr or the like as the first metal, because it forms Cr-O and Cr-Cu bonds.

[0039] For example, it is preferable to use tin (Sn) as the second metal, because peeling is suppressed by using a material with a small Young's modulus. Alternatively, it is preferable to use In as the second metal, because In has a similar atomic number to Sn and similar mechanical and electrical properties to Sn.

[0040] As illustrated in Fig. 5, a second metal layer 26 or the like may be provided between the first metal layer 25 and the plating layer. For example, the second metal layer 26 may be provided so as to cover the first metal layer 25. The second metal layer 26 is provided from the viewpoint of the adhesion of the plating layer. For example, it is preferable to use the same metal as the first plating layer 21 for the second metal layer 26. Since Cu has the function of preventing the penetration of hydrogen, it is preferable that both the first plating layer 21 and the second metal layer 26 are Cu.

[0041] When the base layer 24 is thinned to reduce the thickness of the external electrodes 20a, 20b, discontinuities tend to occur in the base layer 24, which makes the effect of providing the first metal layer 25 more pronounced. For example, when the thickness of the base layer 24 is 0.1 μm to 10 μm, 0.2 μm to 5 μm, or 0.5 μm to 3 μm, the effect of providing the first metal layer 25 is more pronounced.

[0042] In each of the external electrodes 20a, 20b, the length in the X-axis direction of the area on the top, bottom, and two side surfaces of the laminated chip 10 where the base layer 24 is not provided and the first metal layer 25 is in contact with the laminated chip 10 is, for example, 1 / 10 or more and 4 / 10 or less of the length in the X-axis direction of the laminated ceramic capacitor 100.

[0043] Next, a description will be given of a method for manufacturing the multilayer ceramic capacitor 100. FIG.

[0044] (raw powder production process) First, a dielectric material for forming the dielectric layer 11 is prepared. The A-site elements and B-site elements contained in the dielectric layer 11 are typically contained in the dielectric layer 11 in the form of a sintered compact of ABO3 particles. For example, BaTiO3 is a tetragonal compound with a perovskite structure and exhibits a high dielectric constant. This BaTiO3 can generally be obtained by synthesizing barium titanate by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate. Various methods have been known for synthesizing the ceramic that is the main component of the dielectric layer 11, including the solid-phase method, the sol-gel method, and the hydrothermal method. Any of these methods can be used in this embodiment.

[0045] The resulting ceramic powder is then doped with a predetermined additive compound depending on the purpose, such as oxides of tin (Sn), magnesium (Mg), manganese (Mn), vanadium (V), chromium (Cr), rare earth elements (yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), and ytterbium (Yb)), or oxides containing cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K), or silicon (Si), or glasses containing cobalt, nickel, lithium, boron, sodium, potassium, or silicon.

[0046] For example, a ceramic material is prepared by wet-mixing a ceramic raw material powder with a compound containing an additive compound, followed by drying and pulverization. For example, the ceramic material obtained as described above may be pulverized as necessary to adjust the particle size, or may be combined with a classification process to adjust the particle size. A dielectric material is obtained by the above process.

[0047] (Lamination process) Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the obtained dielectric material and wet mixed. The obtained slurry is used to coat a dielectric green sheet 52 on a substrate 51 by, for example, a die coater method or a doctor blade method, and then dried. The substrate 51 is, for example, a PET (polyethylene terephthalate) film.

[0048] Next, as illustrated in Fig. 7(a), an internal electrode pattern 53 is formed on a dielectric green sheet 52. In Fig. 7(a), as an example, four layers of internal electrode patterns 53 are formed on the dielectric green sheet 52 at predetermined intervals. The film formation method is not particularly limited, but for example, an electrode paste containing the main component metal of the internal electrode layer 12 is used. Alternatively, vacuum film formation such as sputtering using a target of the main component metal of the internal electrode layer 12 may be used. The dielectric green sheet 52 on which the internal electrode pattern 53 is formed is defined as a lamination unit.

[0049] Next, while peeling the dielectric green sheet 52 from the substrate 51, the lamination units are stacked as shown in FIG. 7(b). Next, a predetermined number of cover sheets 55 (e.g., 2 to 10 layers) are stacked on top and bottom of the laminate obtained by stacking the lamination units, and are thermocompression bonded, and then cut to predetermined chip dimensions (e.g., 1.0 mm x 0.5 mm). In the example of FIG. 7(b), cutting is performed along the dotted lines. The cover sheet 55 may have the same components as the dielectric green sheet 52, or may contain a different additive compound.

[0050] (Firing process) The ceramic laminate thus obtained is subjected to binder removal treatment in an N2 atmosphere, and then, as shown in FIG. 8(a), a metal paste 54 that will become the underlayer 24 of the external electrodes 20a, 20b is applied to both end surfaces of the ceramic laminate by a dipping method, and the ceramic laminate is heated at an oxygen partial pressure of 10 -5 ~10 -8 The mixture is fired in a reducing atmosphere at 1100 to 1300°C for 10 minutes to 2 hours.

[0051] (Reoxidation treatment process) Thereafter, a re-oxidation treatment may be performed at 600°C to 1000°C in an N2 gas atmosphere.

[0052] (Metal layer formation process) Next, the surface is covered with a metal mask except for the regions where the external electrodes 20a and 20b are to be provided, and the first metal layer 25 is formed as shown in FIG. 8(b). Sputtering or vapor deposition can be used as the film formation method. Vapor deposition can be either chemical vapor deposition or physical vapor deposition. For example, the first metal layer 25 can be formed using an alloy of the first metal and the second metal contained in the first metal layer 25 as a target. Note that, as shown in FIG. 8(b), a second metal layer 26 may be formed so as to cover the first metal layer 25. The second metal layer 26 can also be formed using sputtering or vapor deposition.

[0053] (Plating process) Thereafter, the first plating layer 21, the second plating layer 22, and the third plating layer 23 are formed by plating using the first metal layer 25 as a seed layer. When the second metal layer 26 is provided, the second metal layer 26 is used as a seed layer. When the second metal layer 26 is provided, the second metal layer 26 is used as a seed layer.

[0054] According to the manufacturing method of this embodiment, the first metal layer 25 is formed by sputtering or vapor deposition, which allows for the formation of a denser, more pure film than when Ni paste is applied by a dipping method or other method. This improves the conductivity of the first metal layer 25 and accelerates the growth of the plating layer. Furthermore, because the first metal layer 25 is formed by sputtering or vapor deposition, it can be formed even in areas where the metal paste 54 did not adhere due to repellency or other reasons. This prevents peeling of the plating layer even in areas where the metal paste 54 is not applied. Furthermore, because the first metal layer 25 contains a second metal having a smaller Young's modulus than the first metal, the Young's modulus of the entire first metal layer 25 is reduced, allowing the first metal layer 25 to have flexibility. This prevents peeling of the external electrodes 20a, 20b.

[0055] The base layer 24 may be formed after the laminated chip 10 is obtained by firing. For example, a metal paste 54 for forming the base layer, which contains metal powder, glass frit, a binder, and a solvent, may be applied to both end surfaces of the laminated chip 10, dried, and then baked. The base layer 24 may be formed in this manner.

[0056] In the above embodiments, a multilayer ceramic capacitor has been described as an example of a ceramic electronic component, but the present invention is not limited to this. For example, other electronic components such as a varistor or a thermistor may also be used. [Example]

[0057] The multilayer ceramic capacitor according to the embodiment was fabricated as follows.

[0058] Additives were added to barium titanate powder, and the mixture was thoroughly wet mixed and pulverized in a ball mill to obtain a dielectric material. A butyral-based organic binder, toluene, and ethyl alcohol were added to the dielectric material, and a dielectric green sheet was applied to a PET substrate using the doctor blade method. Next, an internal electrode pattern was formed on the dielectric green sheet using a paste containing Ni powder.

[0059] Next, the dielectric green sheet was peeled off from the substrate, and the laminate units were stacked. Next, a predetermined number of cover sheets were stacked on the top and bottom of the laminate obtained by stacking the laminate units, and they were thermocompression bonded. After that, it was cut to the predetermined chip size.

[0060] The ceramic laminate thus obtained was subjected to a binder removal treatment in an N2 atmosphere, after which a metal paste that would become the base layer of the external electrodes was applied by dipping, and then fired in a reducing atmosphere.

[0061] After firing, the substrate was covered with a metal mask, leaving only the areas where the external electrodes would be formed, and a Ti metal layer was formed by sputtering. An alloy of Ti and Sn was used as the target. In this alloy, Ti was 100 at% and Sn was 20 at%. The Ti metal layer had a thickness of 0.05 μm. Then, a Cu layer was formed on the Ti metal layer by sputtering. The Cu layer had a thickness of 0.4 μm. Then, a Cu layer with a thickness of 5 μm, a Ni layer with a thickness of 3 μm, and a Sn layer with a thickness of 2 μm were formed in that order by plating.

[0062] FIG. 9(a) is a traced SEM photograph of the cross section. FIG. 9(b) is an enlarged view of portion A in FIG. 9(a). FIG. 9(c) is an enlarged view of portion B in FIG. 9(a). As shown in FIG. 9(b), a first metal layer 25 of Ti and a second metal layer 26 of Cu are formed on the underlayer 24, and a first plating layer 21 of Cu, a second plating layer 22 of Ni, and a third plating layer 23 of Sn are formed in this order on the second metal layer 26. Also, as shown in FIG. 9(c), the first metal layer 25 of Ti is formed in contact with the surface of the laminated chip in a location where the underlayer 24 should have been formed but was not. Thus, it was found that the first metal layer 25 can be formed by sputtering in a location where the underlayer 24 was not formed.

[0063] Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and variations are possible within the scope of the gist of the present invention as defined in the claims. [Explanation of symbols]

[0064] 10 stacked chips 11 Dielectric layer 12 Internal electrode layer 13 Cover Layer 14 Capacity area 15 End Margin 16 Side Margin 20a,20b external electrode 21 First plating layer 22 Second plating layer 23 Third plating layer 24 Base layer 25 1st metal layer 26 Second metal layer 51 Base material 52 Dielectric green sheet 53 Internal electrode pattern 54 Metal Paste 100 Multilayer ceramic capacitors

Claims

1. a laminated chip in which a plurality of dielectric layers mainly made of ceramic and a plurality of internal electrode layers are alternately laminated, and the laminated plurality of internal electrode layers are alternately exposed at a plurality of positions; an external electrode provided at each of the plurality of portions, the external electrode includes, at least in part, a first metal layer provided in contact with the laminated chip, and a plating layer provided on the first metal layer; the first metal layer includes a first metal and a second metal having a lower Young's modulus than the first metal; The ceramic electronic component is characterized in that the first metal is Ti or Cr.

2. the external electrode has a structure in which the plating layer is provided on a base layer provided in contact with the plurality of portions, 2. The ceramic electronic component according to claim 1, wherein the first metal layer is provided in contact with the laminated chip at the discontinuous portion of the base layer.

3. 3. The ceramic electronic component according to claim 1, wherein the Young's modulus of the second metal is not more than two-thirds of the Young's modulus of the first metal.

4. 4. The ceramic electronic component according to claim 1, wherein the amount of the second metal in the first metal layer is 1 at % or less when the amount of the first metal is 100 at %.

5. 5. The ceramic electronic component according to claim 1, wherein the second metal is Sn or In.

6. 6. The ceramic electronic component according to claim 1, wherein the first metal layer has a thickness of 5 nm or more and 100 nm or less.

7. 7. The ceramic electronic component according to claim 1, further comprising a second metal layer provided between the first metal layer and the plating layer.

8. 8. The ceramic electronic component according to claim 1, wherein the dielectric layer contains barium titanate as a main component.

9. A laminated chip in which a plurality of dielectric layers mainly composed of ceramic and a plurality of internal electrode layers are alternately laminated, and the laminated plurality of internal electrode layers are alternately exposed at a plurality of positions; an external electrode provided at each of the plurality of portions, the external electrode includes, at least in part, a first metal layer provided in contact with the laminated chip, and a plating layer provided on the first metal layer; the first metal layer includes a first metal and a second metal having a lower Young's modulus than the first metal; The ceramic electronic component is characterized in that the second metal is Sn or In.

10. preparing a laminated chip in which a plurality of dielectric layers mainly composed of ceramic and a plurality of internal electrode layers are alternately laminated, and the laminated plurality of internal electrode layers are alternately exposed at a plurality of positions; forming a metal layer by sputtering or vapor deposition, the metal layer being in contact with the laminated chip and electrically connected to the internal electrode layers exposed at the plurality of portions; forming a plating layer on the metal layer, the metal layer includes a first metal and a second metal having a lower Young's modulus than the first metal; 2. A method for manufacturing a ceramic electronic component, wherein the first metal is Ti or Cr.

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