Peripheral Component Interconnect (PCI) backplane connectivity System-on-Chip (SoC)

Abstract

To provide a PCI backplane integrated circuit (IC) that provides a cost-effective inter-SoC PCI communication device that supports the ability of SoCs to restrict access to a memory.SOLUTION: In a system (100), an integrated circuit (120) comprises an interconnect communication bus (130), and peripheral component interconnect (PCI) multi-function endpoints (MFN-EPs) (122, 124, 126, 128) coupled to the interconnect communication bus (130). Each PCI MFN-EP (122, 124, 126, 128) comprises a multiplexing device, a first address translation unit (ATU), and at least one PCI function circuit, each PCI function circuit comprising another ATU and base address registers (BARs).SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This application relates to peripheral component interconnects (PCI). Summary of the Invention

[0002] In at least one example, an integrated circuit includes an interconnect communication bus and peripheral component interconnect (PCI) multifunction endpoints (MFN-EPs) coupled to the interconnect communication bus, each MFN-EP including an output address translation unit (ATU) configured to translate addresses internal to the integrated circuit to PCI addresses, and at least one PCI functional circuit configured to route communications to one of the other MFN-EPs of the IC via the interconnect communication bus, and the at least one PCI functional circuit including an input ATU configured to translate PCI addresses to addresses internal to the integrated circuit.

[0003] In at least one example, a method of communicating between different peripheral component interconnect root complexes (PCI RCs) includes reading memory region configuration definitions by a processor of a backplane integrated circuit (IC), where each memory region configuration definition identifies a size of the memory region, identifies an IC communicatively coupled to the backplane IC in which the memory region is located, and identifies other ICs communicatively coupled to the backplane IC that are authorized to access the memory region, where each IC is communicatively coupled to a different multi-function endpoint (MFN-EP) of the backplane IC; and writing, by the processor, the size of the memory region to a base address register (BAR) of a peripheral component interconnect (PCI) functional circuit of the MFN-EP that is coupled to the IC, for each IC authorized to access one of the memory regions. The method further includes configuring, by the processor, for each IC in which the memory region is located, a translation register of an output address translation unit (ATU) in the MFN-EP coupled to the IC using a local address that is local to the backplane IC and using an address managed by the PCI RC of the IC, and configuring, by the processor, for each IC that is allowed access to one of the memory regions, a translation register of an input ATU in a PCI functional circuit of the MFN-EP coupled to the IC using a local address that is local to the backplane IC, the translation register of the input ATU being associated with a BAR of the PCI functional circuit of the MFN-EP.

[0004] In at least one example, an integrated circuit includes an interconnect communication bus and peripheral component interconnect (PCI) multi-function endpoints (MFN-EPs) coupled to the interconnect communication bus, each PCI MFN-EP including a multiplexing device, a first address translation unit (ATU), and at least one PCI function circuit, each PCI function circuit including another ATU and a base address register (BAR). [Brief explanation of the drawings]

[0005] [Figure 1]In various examples, a system is shown having a system-on-chip (SoC) interconnected by a peripheral component interconnect (PCI) backplane integrated circuit (IC).

[0006] [Figure 2] 1 illustrates a PCI backplane IC in various examples.

[0007] [Figure 3] 1 illustrates a base address register (BAR) structure in various examples.

[0008] [Figure 4] 1 illustrates an input address translation unit (ATU) in various examples.

[0009] [Figure 5] 1 shows an output ATU in various examples.

[0010] [Figure 6A] In various examples, another system is shown having SoCs interconnected by PCI backplane ICs.

[0011] [Figure 6B] 1 illustrates another PCI backplane IC in various examples.

[0012] [Figure 7A] In various examples, a flowchart of a method for configuring a PCI backplane IC is shown. [Figure 7B] In various examples, a flowchart of a method for configuring a PCI backplane IC is shown. DETAILED DESCRIPTION OF THE INVENTION

[0013] Peripheral Component Interconnect (PCI) is an increasingly important technology for facilitating communication between computing devices and peripheral devices. PCI Express (PCIe) systems are the successor to earlier PCI systems that relied on a serial communication interface, with one serial line going out from the PCIe host and one serial line going into the PCIe host. A PCI Root Complex (RC) generates transaction requests on behalf of the PCIe host, manages the PCI address space, and translates between the internal addressing used by the PCIe host and the PCI address space. To accomplish these translations, the PCI RC may build a memory map that defines the relationship between the PCIe host's internal addresses and addresses in the PCI address space.

[0014] Emerging automotive applications are designed to include multiple systems-on-chip (SoCs), which rely on high communication bandwidth and low latency. Peripheral Component Interconnect Express (PCIe) provides low-latency and high-throughput communication for connecting these SoCs. However, translating between each SoC's independent PCI address space presents a challenge. Some approaches for interconnecting SOCs with independent PCI address spaces involve switches, but these solutions have drawbacks. Simple switches use cascading, which increases latency when two or more SoCs are interconnected through a PCI backplane. Complex switches eliminate the need for cascading but can be very expensive. Additionally, both simple and complex switching solutions rely on non-transparent bridge (NTB) ports to translate from one SoC's PCI address space to another SoC's PCI address space. The use of such NTB ports prevents or prevents memory access restrictions between SoCs, such as allowing SoC2 to read from a predefined area of ​​SoC1's memory while prohibiting SoC3 from reading the same predefined area of ​​SoC1's memory.

[0015] This specification teaches a PCI backplane integrated circuit (IC) that provides a cost-effective inter-SoC PCI communication device that supports the SoC's ability to restrict access to memory. The PCI backplane IC models the SoC host as a separate function in a PCI multi-function endpoint (MFN-EP). For a first SoC to communicate with a second SoC via the PCI backplane IC, the first SoC communicates with a first PCI functional circuit of the first MFN-EP that models the second SoC. The first PCI functional circuit of the first MFN-EP communicates with the second MFN-EP via the PCI backplane IC's interconnect communication bus, and the second MFN-EP passes the communication to the second SoC. For a first SoC to communicate with a third SoC via the PCI backplane IC, the first SoC communicates with a second PCI functional circuit of the first MFN-EP that models the third SoC. The second PCI functional circuit of the first MFN-EP communicates with a third MFN-EP via an interconnection communication bus, and the third MFN-EP passes the communication to a third SoC. For the first SoC to communicate with a fourth SoC via a PCI backplane IC, the first SoC communicates with a third PCI functional circuit of the first MFN-EP that models the fourth SoC. The third PCI functional circuit communicates with the fourth MFN-EP via an interconnection communication bus, and the fourth MFN-EP passes the communication to the fourth SoC. For the second SoC to communicate with the first SoC via a PCI backplane IC, the second SoC communicates with a first PCI functional circuit of the second MFN-EP that models the first SoC. The first PCI functional circuit of the second MFN-EP communicates with the first MFN-EP via the interconnect communication bus, and the first MFN-EP passes the communication to the first SoC.

[0016] Each MFN-EP includes PCI functional circuitry. Each PCI functional circuit can be configured to indirectly map transactions from the PCI address space of an associated SoC to the PCI address space of the SoC modeled by that particular PCI functional circuit. The MFN-EP also includes an output address translation unit (ATU) for mapping transactions from other SoCs to the PCI address space of the SoC associated with that MFN-EP. These mappings provide the PCI backplane IC with the ability to restrict access to each of the SoC's PCI memory regions as configured by each of the SoCs.

[0017] This solution offers low latency, high throughput, and transparency, allowing the SoC to selectively restrict access to memory regions. Because the PCI backplane IC is a single device made by a single manufacturer, it can be more easily adapted for use in an automobile than a multi-device solution.

[0018] 1 , a system 100 includes a first system-on-chip (SoC) 102 having a first PCI root complex (RC) 104, a second SoC 106 having a second RC 108, a third SoC 110 having a third RC 112, a fourth SoC 114 having a fourth RC 116, and a peripheral component interconnect backplane integrated circuit (PCI backplane IC) 120. In one example, the PCI backplane IC 120 includes a first multifunction endpoint (MFN-EP) 122, a second MFN-EP 124, a third MFN-EP 126, a fourth MFN-EP 128, an interconnection communication bus 130, a processor 132, and a memory 134. Each of the MFN-EPs 122, 124, 126, and 128 is coupled to the interconnection communication bus 130 by a communication path 136. The first RC 104 is communicatively coupled to the first MFN-EP 122 by an input line 140 and an output line 142. The terms "input" and "output" are used relative to the PCI backplane IC 120. The second RC 108 is communicatively coupled to the second MFN-EP 124 by an input line 144 and an output line 146. The third RC 112 is communicatively coupled to the third MFN-EP 126 by an input line 148 and an output line 150. The fourth RC 116 is communicatively coupled to the fourth MFN-EP 128 by an input line 152 and an output line 154. In one example, each of the lines 140-154 is a serial communication line. In another example, each of the lines 140-154 includes parallel conductors.

[0019] In some contexts, the SoCs 102, 106, 110, and 114 may be referred to as remote SoCs or remote hosts. In some examples, one or more SoCs in the system 100 may be replaced with processors that are not system-on-chip. In some examples, the PCI backplane IC 120 may have three MFN-EPs rather than the four MFN-EPs shown. In some examples, the PCI backplane IC 120 may have five or more MFN-EPs rather than the four MFN-EPs shown. In some examples, the system 100 may be part of an automobile. For example, the SoCs 102, 106, 110, and 114 may be remote processors within the automobile that communicate with each other via the PCI backplane IC 120. One of the SoCs 102, 106, 110, and 114 may include a camera sensor to support the automobile's backup video function. One of the SoCs 102, 106, 110, 114 may include a radar processor and may support radar detection and ranging functionality for the automobile (e.g., to support proximity warning and / or autonomous driving features).

[0020] As described further below, each of the MFN-EPs 122, 124, 126, and 128 models a remote SoC and uses the model to provide a communication portal for the remote SoC it models. For example, the first MFN-EP 122 models each of the SoCs 106, 110, and 114 as PCI functional circuits and provides the first SoC 102 with a communication portal for accessing the other SoCs 106, 110, and 114. The modeling of the SoCs 102, 106, 110, and 114 provided by the MFN-EPs 122, 124, 126, and 128, as described further below, facilitates transparency to the SoCs and restricts access to memory based on the SoC attempting to access the memory. This transparency may be desirable in some applications, such as when it is desired to allow one or more specific other SoCs to access that memory while prohibiting other specific SoCs from accessing that memory.

[0021] The first SoC 102 may complete a transaction involving the second SoC 106 by sending a transaction to the first MFN-EP 122 via input lines 140, where the transaction identifies the PCI functional circuit embedded in the first MFN-EP 122 that corresponds to the second SoC 106. The transaction is multiplexed by the first MFN-EP 122 to the appropriate PCI functional circuit embedded in the first MFN-EP 122, which then transmits the transaction to the second MFN-EP 124 via the interconnect communication bus 130. The second MFN-EP 124 then completes the transaction with the second SoC 106 via output lines 146. The interconnect communication bus 130 may be referred to as an interconnect. In some cases, a response is returned from the SoC specified by the transaction to the SoC that issued the transaction. For example, an acknowledgment token or requested data may be returned.

[0022] The processor 132 executes computer-readable instructions stored in the memory 134. The memory 134 includes a non-transitory computer-readable storage medium for storing instructions. The instructions may be stored as software and / or data. The instructions may be stored as firmware. The processor 132 configures the MFN-EPs 122, 124, 126, and 128 during initialization of the system 100. For example, the processor 132 manages the configuration of the size of memory regions accessible by the SoCs 102, 106, 110, and 114 and the configuration of memory maps.

[0023] FIG. 2 shows further details of the MFN-EPs 122, 124, 126, and 128. The structure of the first MFN-EP 122 shown in FIG. 2 represents the structures of the MFN-EPs 124, 126, and 128. In one example, each of the MFN-EPs 122, 124, 126, and 128 is instantiated from the same intellectual property core (IP core). An IP core is a block of logic and / or data used in creating an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). The first MFN-EP 122 includes a multiplexing device 170, a first PCI functional circuit 172, a second PCI functional circuit 174, a third PCI functional circuit 176, and an output address translation unit (ATU) 178. In some contexts, the PCI functional circuits 172, 174, and 176 may be referred to as functional blocks.

[0024] PCI function circuits 172, 174, and 176 correspond to PCI functions that RC 104 can invoke. Each of PCI function circuits 172, 174, and 176 includes a base address register (BAR) and an input ATU. First PCI function circuit 172 includes a BAR 180 and an input ATU 182, second PCI function circuit 174 includes a BAR 184 and an input ATU 186, and third PCI function circuit 176 includes a BAR 188 and an input ATU 190. In another example, MFN-EP 122 includes two PCI function circuits. In another example, MFN-EP 122 includes four or more PCI function circuits. In one example, each MFN-EP of PCI backplane IC 120 includes one PCI function circuit less the total number of MFN-EPs in PCI backplane IC 120. A first PCI function circuit 172 is communicatively coupled to the interconnect communication bus 130 by communication path 136-1. A second PCI function circuit 174 is communicatively coupled to the interconnect communication bus by communication path 136-2. A third PCI function circuit 176 is communicatively coupled to the interconnect communication bus via communication path 136-3. An output ATU 178 is communicatively coupled to the interconnect communication bus by communication path 136-4.

[0025] Each PCI functional circuit 172-176 is associated with a particular SoC (e.g., each PCI functional circuit 172-176 models a particular SoC to the RC 104). For example, the first PCI functional circuit 172 is associated with SoC B, e.g., the second SoC 106, the second PCI functional circuit 174 is associated with SoC C, e.g., the third SoC 110, and the third PCI functional circuit 176 is associated with SoC D, e.g., the fourth SoC 114. Transactions received by the MFN-EP from the RC 104 via input lines 140 are analyzed by the multiplexing device 170 to identify which PCI functional circuit 172-176 the transaction is directed to (and thus which SoC the transaction is directed to) and direct the transaction to the identified one of the PCI functional circuits 172-176. PCI function circuits 172-176 use BARs 180, 184, 188 and input ATUs 182, 186, 190 to map PCI addresses associated with received transactions to address offsets and references to entries in the output ATUs of the specified MFN-EP. Only transactions that match one of the mappings or translations configured in BARs 180, 184, 188 and input ATUs 182, 186, 190 are routed by PCI function circuits 172, 174, 176 over the interconnect communication bus. Thus, SoCs 102, 106, 110, 114 can benefit from the transparency provided by PCI backplane IC 120 and restrict access to memory by not defining a mapping for that memory, or for specific regions of that memory, for a particular SoC.

[0026] For example, a transaction specifying a PCI address within the PCI address space managed by the first RC 104 is directed to the first PCI function circuit 172 (and therefore to SoC B or the second SoC 106). The first PCI function circuit 172 determines which of its BARs 180 is referenced by the PCI address associated with the received transaction and uses that one of its BARs 180 to index its input ATU 182 to find the corresponding local address associated with the output ATU 178 of the second MFN-EP 124. The first PCI function circuit 172 establishes a master-slave relationship with the second MFN-EP 124 via the interconnection communication bus 130 and sends the transaction, along with the local address, to the interconnection communication bus 130 via communication path 136-1 and to the output ATU 178 of the second MFN-EP 124 on the interconnection communication bus 130. In one example, the interconnection communication bus 130 may be an electronic crossbar switch or an electronic matrix switch, and a master-slave relationship may be established by configuring the switches within the interconnection communication bus 130. The second MFN-EP 124 uses the address offset and an index to the output ATU 178 to determine a PCI address within the PCI address space managed by the second RC 108 for routing the transaction to the second RC 108 of the second SoC 106. The second MFN-EP 124 also sends the transaction to the second RC 108 of the second SoC 106 via the multiplexing device 170 and via the output communication path 146. In this manner, the transaction from the RC 104 is sent to the SoC designated by the originating SoC. Further details regarding how transactions are interconnected between SoCs 102, 106, 110, 114 are provided below, along with expanded examples of the configuration of BARs 180, 184, 188, the configuration of input ATUs 182, 186, 190, and output ATU 178.

[0027] 3 shows further details of one of the BARs 180. While one of the BARs 180 is described here, the other BARs of the BARs 180, BAR 184 and BAR 188, have a similar structure. An instance of the BAR 180 includes a memory region size parameter 202 and a PCI address parameter 204. In one example, an instance of the BAR 180 includes the region size parameter 202, which may be configured by the processor 132 during initialization of the system 100 and includes the size of the region of memory exported or made accessible by the SoC associated with the BAR 180. (Note that the BAR 180 is included within a particular one of the PCI functional circuits 172-176, and the particular PCI functional circuit is associated with a particular one of the SoCs 102, 106, 110, 114.) In one embodiment, PCI backplane IC 120 supports SoCs 102, 106, 110, and 114, each of which can access up to 1 GB of memory. In one embodiment, PCI backplane IC 120 supports SoCs 102, 106, 110, and 114, each of which can access up to 2 GB of memory. In one embodiment, PCI backplane IC 120 supports SoCs 102, 106, 110, and 114, each of which can access up to 5 GB of memory. In one embodiment, PCI backplane IC 120 supports SoCs 102, 106, 110, and 114, each of which can access up to 10 GB of memory. In one embodiment, one of SoCs 102, 106, 110, and 114 includes one or more memory regions that it makes accessible to one or more other SoCs 102, 106, 110, and 114. The SoCs 102, 106, 110, 114 may have access to less than the maximum amount of memory.For example, if a PCI backplane IC 120 supports SoCs 102, 106, 110, and 114 that can each access up to 2 GB of memory, any one of these SoCs 102, 106, 110, and 114 may be able to access 10 kB of memory, 100 kB of memory, 1 MB of memory, or no memory.

[0028] In one embodiment, the MFN-EPs 122, 124, 126, and 128 are each configured to communicate with an external PCI address space that is a large outbound memory region containing one or more regions. In one embodiment, the MFN-EPs 122, 124, 126, and 128 are each configured to communicate with an external PCI address space of up to 1 GB of memory. In one embodiment, the MFN-EPs 122, 124, 126, and 128 are each configured to communicate with an external PCI address space of up to 2 GB of memory. In one embodiment, the MFN-EPs 122, 124, 126, and 128 are each configured to communicate with an external PCI address space of up to 5 GB of memory. In one embodiment, the MFN-EPs 122, 124, 126, and 128 are each configured to communicate with an external PCI address space of up to 10 GB of memory.

[0029] The PCI address parameters 204 may be configured during initialization of the system 100 to associate the PCI address with the PCI address space managed by the RCs 104, 108, 112, 116 of the SoCs 102, 106, 110, 114 to which the MFN-EPs 122, 124, 126, 128 containing the BAR 180 are coupled (note that the BAR 180 is contained within a particular one of the PCI functional circuits 172-176, which is itself contained within a particular one of the MFN-EPs 122, 124, 126, 128, and that a particular one of the MFN-EPs 122, 124, 126, 128 is coupled to the RCs 104, 108, 112, 116 of a particular one of the SoCs 102, 106, 110, 114). The PCI address may be provided and programmed into the BAR of the BAR 180 by the RC 104, 108, 112, 116 of the SoC 102, 106, 110, 114. The MFN-EP 122, 124, 126, 128 that contains the BAR 180 is coupled to the SoC 102, 106, 110, 114. If the memory region size parameter 202 of one of the BARs 180, 184, 188 has a null or zero value, the processor 132 may not allow a value to be provided for the PCI address parameter 204 of that BAR. In part, this is one way in which the SoC 102, 106, 110, 114 restricts access to its memory space. If a first SoC does not provide a value for the memory region size parameter 202 of any of the BARs of a PCI functional circuit associated with a second SoC, the second SoC is effectively prohibited from accessing any memory of the first SoC.

[0030] FIG. 4 shows further details of input ATU 182. While input ATU 182 is illustrated here, input ATUs 186 and 190 have a similar structure. Input ATU 182 includes translation registers 210. Each translation register 210 includes a local address parameter 214. In some examples, translation registers 210 also include a BAR identity. Local address parameter 214 identifies a local address of PCI backplane IC 120. A local address is an address that is unique within a localized address domain, such as within PCI backplane IC 120. A local address can be associated with a particular one of MFN-EPs 122, 124, 126, and 128 or with a PCI function block within PCI backplane IC 120 by interconnect communication bus 130 of PCI backplane IC 120. The local address parameter 214 may be configured by the processor 132 during initialization of the system 100 to associate a particular BAR among the BARs 180 of the PCI functional circuits of the MFN-EPs 122, 124, 126, 128 with a corresponding local address of the PCI backplane IC 120. In one example, one of the BARs 180 is associated with the translation register 210 by matching the BAR identification of that BAR to the BAR identification of the translation register 210. The BARs of the BARs 180 may be statically associated with the translation register 210 by hardware identification. For example, a first BAR of the BAR 180 may be predefined to be associated with a first translation register 210 in the input ATU 182, a second BAR of the BAR 180 may be predefined to be associated with a second translation register 210 in the input ATU 182, etc.

[0031] 5 shows further details of output ATU 178. Output ATU 178 includes translation registers 220. Each translation register 220 includes a local address parameter 222, a PCI address parameter 224, and a size parameter 226. Local address parameter 222 and PCI address parameter 224 may be configured by processor 132 during initialization of system 100 to associate a local address stored in local address parameter 222 with a PCI address value stored in PCI address parameter 224. Size parameter 226 may be configured by processor 132 during initialization of system 100 to identify the size of a memory region made accessible by SoC 102, 106, 110, 114 associated with output ATU 178.

[0032] In one example, the number of BARs 180 in each of the PCI functional circuits 172-176 is three. In one example, the number of translation registers 210 in each of the input ATUs 182 is three. In one example, the number of BARs 180 in each of the PCI functional circuits 172-176 is six. In one example, the number of translation registers 210 in each of the input ATUs 182 is six. In one example, the number of BARs 180 in each of the PCI functional circuits 172-176 is the same as the number of translation registers 210 in each of the input ATUs 182. In one example, the number of translation registers 220 in each of the output ATUs 178 is greater than 12 and less than 96. In one example, the number of translation registers 220 in each of the output ATUs 178 is 16. In one example, the number of translation registers 220 in each of the output ATUs 178 is 32. In one example, the number of conversion registers 220 in each output ATU 178 is at least 16. To make the use of BAR 180, input ATU 182, and output ATU 178 clearer, an extended example is provided below.

[0033] In one example, memory 134 of PCI backplane IC 120 is pre-configured with data defining the memory regions and sizes that will be made accessible to SoCs 102, 106, 110, and 114. The data also defines which regions of memory will be made accessible to which SoCs 102, 106, 110, and 114. As an example, memory 134 stores configuration data indicating that a first SoC 102 will make a first region of 25 Kbytes of memory accessible to a second SoC 106 and a third SoC 110, and a second region of 80 Kbytes of memory accessible to a fourth SoC 114. In this example, the configuration data stored in memory 134 also indicates that the fourth SoC 114 makes a third region of 100K bytes of memory accessible to the first SoC 102, a fourth region of 150K bytes of memory accessible to the first SoC 102, a fifth region of 75K bytes of memory accessible to the second SoC 106, and a sixth region of 125K bytes of memory accessible to the second SoC 106.

[0034] Defining translations 210 and 220 may allow a second SoC to access a particular memory region in a first SoC, while not defining translations 210 and 220 may prohibit a second SoC from accessing a particular memory region in a first SoC. The translations 210 of the input ATUs 182, 186, and 190 and the translation 220 of the output ATU 178 of the MFN-EPs 122, 124, 126, and 128 facilitate the benefit of transparency to the SoCs 102, 106, 110, and 114 and control access to those memory regions by other SoCs 102, 106, 110, and 114.

[0035] In one example, when PCI backplane IC 120 is powered on, and before a communication link is established between PCI backplane IC 120 and SoCs 102, 106, 110, 114, processor 132 reads memory access permissions from memory 134 and configures memory region size parameters 202 in the appropriate BARs 180, 184, 188 of the appropriate MFN-EPs 122, 124, 126, 128. In this example, a first PCI functional circuit 172 in each of MFN-EPs 124, 126, 128 models or is associated with the first SoC 102, and a third PCI functional circuit 176 in each of MFN-EPs 122, 124, 126 models or is associated with the fourth SoC 114. Considering the example configuration data described above, during power-on initialization of the PCI backplane IC 120, the memory region size parameter 202 of a BAR of a BAR 180 of a first PCI functional circuit 172 of the second MFN-EP 124 is allocated a value of 25K bytes, the memory region size parameter 202 of a certain BAR of a BAR 180 of a first PCI functional circuit 172 of the third MFN-EP 126 is allocated a value of 25K bytes, and the memory region size parameter 202 of a certain BAR of a BAR 180 of a first PCI functional circuit 172 of the fourth MFN-EP 128 is allocated a value of 80K bytes. Continuing with this example, the memory region size parameter 202 of one BAR of the BARs 188 of the third PCI functional circuit 176 of the first MFN-EP 122 is allocated a value of 100K bytes, another BAR of the BARs 188 of the third PCI functional circuit 176 of the first MFN-EP 122 is allocated a value of 150K bytes, the memory region size parameter 202 of one BAR of the BARs 188 of the third PCI functional circuit 176 of the second MFN-EP 124 is allocated a value of 75K bytes, and the memory region size parameter 202 of another BAR of the second MFN-EP 124 is allocated a value of 125K bytes.

[0036] After the PCI backplane IC 120 completes power-on during initialization, the first SoC 102 and / or the first RC 104 establish a communication link with the first MFN-EP 122, the second SoC 106 and / or the second RC 108 establish a communication link with the second MFN-EP 124, the third SoC 110 and / or the third RC 112 establish a communication link with the third MFN-EP 126, and the fourth SoC 114 and / or the fourth RC 116 establish a communication link with the fourth MFN-EP 128. During this process of establishing communication links, the MFN-EPs 122, 124, 126, 128 inform the RCs 104, 108, 112, 116 of the values ​​of the memory region size parameters 202 of the BARs 180, 184, 188. In this way, the RCs 104, 108, 112, and 116 learn the memory regions and sizes of those memory regions that are accessible to them from the other SoCs 102, 106, 110, and 114. In the above example, the first RC 104 learns that a 100-Kbyte memory region and a 150-Kbyte memory region of the fourth SoC 114 are accessible to it. The second RC 108 learns that a 25-Kbyte memory region of the first SoC 102, a 75-Kbyte memory region of the fourth SoC 114, and a 125-Kbyte memory region of the fourth SoC 114 are accessible to it. The third RC 112 learns that a 25-Kbyte memory region of the fourth SoC 114 is accessible to it. The fourth RC 116 learns that an 80-Kbyte memory region of the first SoC 102 is accessible to it.

[0037] Each of the RCs 104, 108, 112, 116, in response to learning which memory regions and the sizes of those memory regions have been made accessible to it, assigns a PCI address in its respective PCI address space corresponding to those regions of memory that have been made accessible and notifies the appropriate one of the PCI function circuits 172, 174, 176 of the MFN-EPs 122, 124, 126, 128 to which it is communicatively linked. This assigned PCI address is the first of a block of PCI addresses assigned by the RCs 104, 108, 112, 116 to communicate with the regions of memory that have been made accessible, where the number of PCI addresses in the block is equal to the corresponding memory region size parameter 202 of the corresponding BAR in BARs 180.

[0038] In the above example, the first RC 104 allocates the start of the third region of the PCI address space (made accessible to the first SoC 102 by the fourth RC 116) to PCI address 1000000H (this example value is in hexadecimal, as indicated by the "H" suffix) in the PCI address space managed by the first RC 104 and stores 1000000H in the PCI address parameter 204 of the first BAR of the BAR 188 of the third PCI functional circuit 176 of the first MFN-EP 122. The first RC 104 maps the start of the fourth region of PCI address space (made accessible to the first SoC 102 by the fourth RC 116) to PCI address 1020000H in the PCI address space managed by the first RC 104 and stores 1020000H in the PCI address parameter 204 of the second BAR of the BAR 188 of the third PCI functional circuit 176 of the first MFN-EP 122. In creating this mapping, the first RC 104 leaves enough PCI address space between the 1000000H and 1020000H addresses to accommodate the size of the third region of PCI address space (100 Kbytes).

[0039] The second RC 108 maps the start of the fifth region of the PCI address space (made accessible to the second SoC 106 by the fourth RC 116) to PCI address 1000000H in the PCI address space managed by the second RC 108 and stores 1000000H in the PCI address parameter 204 of the first BAR of the BAR 188 of the third PCI functional circuit 176 of the second MFN-EP 124. The second RC 108 maps the start of the sixth region of PCI address space (made accessible to the second SoC 106 by the fourth RC 116) to PCI address 1020000H in the PCI address space managed by the second RC 108 and stores 1020000H in the PCI address parameter 204 of the second BAR of the BAR 188 of the third PCI functional circuit 176 of the second MFN-EP 124. In creating this mapping, the second RC 108 leaves enough PCI address space between the 1000000H and 1020000H addresses to accommodate the size of the fifth region of PCI address space (75 Kbytes). The second RC 108 maps the start of the first region of the PCI address space (made accessible to the second SoC 106 and the third SoC 110 by the first RC 104) to PCI address 1040000H in the PCI address space managed by the second RC 108 and stores 1040000H in the PCI address parameter 204 of the first BAR of the BAR 180 of the first PCI functional circuit 172 of the second MFN-EP 124.

[0040] The third RC 112 maps the start of the first region of the PCI address space (made accessible to the third SoC 110 and the second SoC 106 by the first RC 104) to PCI address 1000000H in the PCI address space managed by the third RC 112 and stores 10000000H in the PCI address parameter 204 of the first BAR of the BAR 180 of the first PCI functional circuit 172 of the third MFN-EP 126. The fourth RC 116 maps the start of the second region of the PCI address space (made accessible to the fourth SoC 114 by the first RC 104) to PCI address 8000000H in the PCI address space managed by the fourth RC 116 and stores 8000000H in the PCI address parameter 204 of the first BAR of the BAR 180 of the first PCI functional circuit 172 of the fourth MFN-EP 128.

[0041] The above example addresses are arbitrary, and different addresses could be used in the example. Note that the PCI address parameter 204 value (1040000H) of the first BAR of the BAR 180 of the first PCI functional circuit 172 of the second MFN-EP 124 and the PCI address parameter 204 value (1000000H) of the first BAR of the BAR 180 of the first PCI functional circuit 172 of the third MFN-EP 126 are different even though they are associated with the same first region of the PCI address space controlled by the first RC 104. This illustrates the independence between the PCI address spaces managed by each of the individual RCs 104, 108, 112, and 116.

[0042] The memory 134 of the PCI backplane IC 120 may also be configured with addresses associated with memory regions that the RCs 104, 108, 112, 116 make accessible to other SoCs 102, 106, 110, 114. During power-on initialization of the PCI backplane IC 120, the processor 132 may read these addresses from the memory 134 and configure these addresses into the PCI address parameters 224 of the translation registers 220 in the output ATUs 178 of the target MFN-EPs 122, 124, 126, 128. A local address value of the PCI backplane IC 120 may be assigned by the processor 132 to the local address parameter 222 of this translation register 220 associated with the memory region, and the same local address value may be assigned by the processor 132 to the local address parameter 214 of the corresponding translation register 210 in a corresponding one of the input ATUs 182, 186, 190 of the PCI functional circuits 172, 174, 176 of the appropriate MFN-EP 122, 124, 126, 128 (e.g., the MFN-EP associated with the SoC 102, 106, 110, 114 that is granted access to the memory region). In an alternative example, the RC 104, 108, 112, 116 may notify the backplane IC 120 of the PCI address to be associated with the memory region made accessible by the SoC 102, 106, 110, 114 during communication link establishment, and the processor 132 may configure the translation register 220, 210 at that time.

[0043] Continuing with the above example, the PCI backplane IC 120 is pre-configured with data indicating that the first RC 104 associates PCI address 3000000H with a first memory region accessible to the second SoC 106 and the third SoC 110, and associates PCI address 3080000H with a second memory region accessible to the fourth SoC 114. The PCI backplane IC 120 is pre-configured with data indicating that the fourth RC 116 associates PCI address 3000000H with a third memory region accessible to the first SoC 102, PCI address 3040000H with a fourth memory region accessible to the first SoC 102, PCI address 3080000H with a fifth memory region accessible to the second SoC 106, and PCI address 30B0000H with a sixth memory region accessible to the second SoC 106. Note that both the first RC 104 and the fourth RC 116 are associated with memory that is made accessible to dual PCI addresses (3000000H and 3080000H are used by both the first RC 104 and the fourth RC 116), which is permitted because they are PCI addresses in the PCI address space that are controlled independently by each RC.

[0044] The PCI backplane IC 120 associates a local address of 183000000H with PCI address 3000000H, and associates a local address of 183080000H with PCI address 3080000H of the first RC 104. The PCI backplane IC 120 associates a local address of 303000000H with PCI address 3000000H, associates local address 303040000H with PCI address 3040000H, associates local address 303080000H with PCI address 3080000H, and associates local address 3030B0000H with PCI address 30B0000H of the fourth RC 116. Note that the PCI backplane IC 120 associates different local addresses with the PCI address 3000000H of the first RC 104 and the PCI address 3000000H of the fourth RC 116, and associates different local addresses with the PCI address 3080000H of the first RC 104 and the PCI address 3080000H of the fourth RC 116.

[0045] The PCI backplane IC 120 configures the first translation register 220 of the output ATU 178 of the first MFN-EP 122 to store 183000000H in its local address parameter 222 and 3000000H in its PCI address parameter 224. This first translation register 220 corresponds to the first memory region made accessible by the first SoC 102 to the second SoC 106 and the third SoC 110. The PCI backplane IC 120 configures the second translation register 220 of the output ATU 178 of the first MFN-EP 122 to store 183080000H in its local address parameter 222 and 3080000H in its PCI address parameter 224. This second translation register 220 corresponds to the second memory region made accessible by the first SoC 102 to the fourth SoC 114. The PCI backplane IC 120 configures the first translation register 210 of the input ATU 182 of the first PCI functional circuit 172 of the second MFN-EP 124 to store 183000000H in its local address parameter 214, and configures the first translation register 210 of the input ATU 182 of the first PCI functional circuit 172 of the third MFN-EP 126 to store 183000000H in its local address parameter 214. The first translation register 210 of the input ATU 182 of the first PCI functional circuit 172 of the second MFN-EP 124 is associated with the first BAR of the BAR 180 of the first PCI functional circuit 172 of the second MFN-EP 124. The first translation register 210 of the input ATU 182 of the first PCI functional circuit 172 of the third MFN-EP 126 is associated with the first BAR of the BAR 180 of the first PCI functional circuit 172 of the third MFN-EP 126. The PCI backplane IC 120 configures the first translation register 210 of the input ATU 182 of the first PCI functional circuit 172 of the fourth MFN-EP 128 to store 183080000H in its local address parameter 214. The first translation register 210 of the input ATU 182 of the first PCI functional circuit 172 of the fourth MFN-EP 128 is associated with the first BAR of the BAR 180 of the first PCI functional circuit 172 of the fourth MFN-EP 128.

[0046] The PCI backplane IC 120 may configure the interconnect communication bus 130 to route communications directed to local addresses ranging from 180000000H to 1FFFFFFFFH to the first MFN-EP 124. The PCI backplane IC 120 may configure the interconnect communication bus 130 to route communications directed to local addresses ranging from 200000000H to 27FFFFFFFH to the second MFN-EP 124. The PCI backplane IC 120 may configure the interconnect communication bus 130 to route communications directed to local addresses ranging from 280000000H to 2FFFFFFFFH to the third MFN-EP 126. The PCI backplane IC 120 may configure the interconnect communication bus 130 to route communications directed to local addresses ranging from 300000000H to 37FFFFFFFH to the fourth MFN-EP 128. In another example, PCI backplane IC 120 may configure interconnect communication bus 130 to route communications according to a different local address routing scheme than the example provided above.

[0047] The PCI backplane IC 120 configures the first translation register 220 of the output ATU 178 of the fourth MFN-EP 128 to store 303000000H in its local address parameter 222 and 3000000H in its PCI address parameter 224. The PCI backplane IC 120 configures the second translation register 220 of the output ATU 178 of the fourth MFN-EP 128 to store 303040000H in its local address parameter 222 and 3040000H in its PCI address parameter 224. The PCI backplane IC 120 configures the third translation register 220 of the output ATU 178 of the fourth MFN-EP 128 to store 303080000H in its local address parameter 222 and 3080000H in its PCI address parameter 224. The PCI backplane IC 120 configures the fourth translation register 220 of the output ATU 178 of the fourth MFN-EP 128 to store 3030B0000H in its local address parameter 222 and 30B0000H in its PCI address parameter 224 .

[0048] The PCI backplane IC 120 configures the first translation register 210 of the input ATU 190 of the third PCI functional circuit 176 of the first MFN-EP 122 to store 303000000H in its local address parameter 214, and configures the second translation register 210 of the input ATU 190 of the third PCI functional circuit 176 of the first MFN-EP 122 to store 303040000H in its local address parameter 214. The first translation register 210 of the input ATU 190 of the third PCI function circuit 176 of the first MFN-EP 122 is associated with the first BAR of the BAR 188 of the third PCI function circuit 176 of the first MFN-EP 122, and the second translation register 210 of the input ATU 190 of the third PCI function circuit 176 of the first MFN-EP 122 is associated with the second BAR of the BAR 188 of the third PCI function circuit 176 of the first MFN-EP 122.

[0049] The PCI backplane IC 120 configures the first translation register 210 of the input ATU 190 of the third PCI functional circuit 176 of the second MFN-EP 124 to store 303080000H in its local address parameter 214, and configures the second translation register 210 of the input ATU 190 of the third PCI functional circuit 176 of the second MFN-EP 124 to store 3030B0000H in its local address parameter 214. The first translation register 210 of the input ATU 190 of the third PCI function circuit 176 of the second MFN-EP 124 is associated with the first BAR of the BAR 188 of the third PCI function circuit 176 of the second MFN-EP 124, and the second translation register 210 of the input ATU 190 of the third PCI function circuit 176 of the second MFN-EP 124 is associated with the second BAR of the BAR 188 of the third PCI function circuit 176 of the second MFN-EP 124.

[0050] Once the BARs 180, 184, 188 of the MFN-EPs 122, 124, 126, 128, the translation registers 210 of the input ATUs 182, 186, 190, and the translation register 220 of the output ATU 178 have been initialized and configured as described above, the PCI backplane IC 120 is ready to route transactions between the SoCs 102, 106, 110, 114. Using the example configuration described above, an example of transaction routing will now be described.

[0051] During operation of the system 100, the SoC 102 sends a transaction to PCI address 1000000H via the first RC 104 over the input communication path 140 to the first MFN-EP 122. This PCI address 1000000H is associated with the first BAR of the BAR 188 of the third functional circuit 176 of the first MFN-EP 122 and is the first address in the associated block of PCI addresses. This PCI address is mapped to local address 303000000H by the input ATU 190 of the third functional circuit 176 of the first MFN-EP 122. The third functional circuit 176 of the first MFN-EP 122 sends the transaction onto the interconnect communication bus 130 directed to local address 303000000H. The interconnect communication bus 130 routes it to the fourth MFN-EP 128. The fourth MFN-EP 128 looks up the translation register 220 in its output ATU 178 that maps this local address 303000000H to PCI address 3000000H. The fourth MFN-EP 128 then sends the transaction to the fourth RC 116 directed to PCI address 30000000H.

[0052] The above example illustrates how SoCs 102, 106, 110, 114 can make regions of their memory accessible to specific other ones of the SoCs 102, 106, 110, 114, i.e., allow access to some of the SoCs 102, 106, 110, 114 and restrict access to other SoCs 102, 106, 110, 114. This example also illustrates how the PCI address space of one RC 104, 108, 112, 116 can be translated by the PCI backplane IC 120 to the PCI address space of a different RC 104, 108, 112, 116. This approach offers many advantages over alternative interconnect technologies that may not support the ability to restrict access to SoCs 102, 106, 110, 114 one at a time (e.g., granting a first SoC access to a first region of PCI address space, restricting access to the first region for a second SoC and other SoCs, granting access to a second region of PCI address space for the second SoC, and restricting access to the second region for the first SoC and other SoCs).

[0053] 6A and 6B illustrate another example of a PCI backplane IC 121 in the context of system 400. In one example, PCI backplane IC 121 includes a first multifunction endpoint (MFN-EP) 123, a second MFN-EP 125, a third MFN-EP 127, an interconnection communication bus 130, a processor 132, a memory 134, and a local functional circuit 135. PCI backplane IC 121 shares many of the same structures as PCI backplane IC 120, and these similar structures perform similar operations to corresponding structures in PCI backplane IC 120. Local functional circuit 135 provides some processing directly rather than forking transactions to SoCs 102, 106, and 110 for processing. Local functional circuit 135 may be an accelerator processing function. Local functional circuit 135 may be an on-chip peripheral. Local functional circuit 135 may be an IP block.

[0054] 6B, each MFN-EP 123, 125, 127 has a fourth PCI functional circuit 177 that receives transactions addressed to local functional circuit 135 by RC 104 and transmits the transactions to interconnect communication bus 130 via communication path 136-5 and via interconnect communication bus 130 to local functional circuit 135 for processing. In one example, PCI backplane IC 121 includes two or more local functional circuits 135 and two or more MFN-EPs, each of which includes a number of PCI functional circuits 177 matching the number of local functional circuits 135. Note that because PCI transactions inherently identify functions, no address translation is required for PCI backplane IC 121 to route transactions to local functional circuits 135.

[0055] 7A and 7B illustrate a method 300 for communicating between different peripheral component interconnect root complexes (PCI RCs). The sequence of steps of method 300 spans FIGS. 7A and 7B. Referring to FIG. 7A, at block 302, method 300 includes reading, by a processor of a backplane integrated circuit (IC) (e.g., processor 132 of PCI backplane ICs 120 and 121), a memory region configuration definition. Here, each memory region configuration definition identifies a size of the memory region, identifies an IC communicatively coupled to the backplane IC in which the memory region is located, and identifies other ICs communicatively coupled to the backplane IC that are granted access to the memory region. Here, each IC (e.g., SoCs 104, 106, 110, and 114) is communicatively coupled to a different multifunction endpoint (MFN-EP) (e.g., MFN-EPs 122, 124, 126, 128, 123, 125, and 127) of the backplane IC. In one example, the backplane ICs are PCI backplane ICs 120, 121. In one example, processor 132 reads the memory configuration definition from memory 134. In one example, processor 132 reads the memory configuration definition from memory external to the backplane ICs.

[0056] At block 304, the method 300 includes, for example, for each IC (e.g., SoC 104, 106, 110, 114) granted access to one of the memory regions, writing, by the processor, the size of the memory region to a base address register (BAR) of a peripheral component interconnect (PCI) functional circuit of the MFN-EP coupled to the IC. For all memory regions exported by the IC, the size of the memory region is programmed by the processor 132 into one or more BARs 180, 184, 188 of a corresponding one of the PCI functional circuits 172, 174, 176 that model the IC that makes the memory region accessible to the IC with which one of the PCI functional circuits 172, 174, 176 is associated.

[0057] In block 306, method 300 includes, for each IC in which a memory area (e.g., a memory area that SoC 102, 106, 110, 114 makes accessible to other SoCs) is located, configuring a translation register (e.g., translation register 120) of an output address translation unit (ATU) (e.g., ATU 178) in an MFN-EP (e.g., one of MFN-EPs 122, 124, 126, 128, 123, 125, 127) coupled to the IC by a processor (e.g., processor 132) using a local address local to the backplane IC (e.g., PCI backplane IC 120, 121) and using an address managed by the IC's PCI RC (e.g., one of RCs 104, 108, 112, 116). The processing of block 306 can be broken down into two parts: (A) assigning local addresses local to the backplane IC for memory areas made accessible by the IC, and (B) configuring the translation registers of the ATU in the MFN-EP coupled to the IC.

[0058] In block 308, the method 300 includes, for each IC that is allowed access to one of the memory areas (e.g., one of the memory areas that SoCs 102, 106, 110, 114 make accessible to other SoCs), configuring a translation register (e.g., translation register 210) of an input ATU (e.g., one of input ATUs 182, 186, 190) in a PCI functional circuit (e.g., one of PCI functional circuits 172, 174, 176, 177) of the MFN-EP that is coupled to the IC by the processor using a local address that is local to the backplane IC to which the translation register of the input ATU is associated with the BAR of the PCI functional circuit of the MFN-EP.

[0059] At block 310, the method 300 includes, for each IC that is permitted access to a memory region (e.g., a memory region that the SoC 102, 106, 110, 114 makes accessible to other SoCs), receiving by the MFN-EP coupled to the IC a PCI address managed by the IC's PCI RC (e.g., one of the PCI RCs 104, 108, 112, 116) and configuring the PCI address in a BAR of a PCI functional circuit of the MFN-EP coupled to the IC.

[0060] 7B, at block 312, the method 300 includes receiving a PCI transaction by the MFN-EP that specifies a PCI function circuit of the MFN-EP. The PCI transaction includes a PCI address in a PCI address space managed by a PCI RC of an IC coupled to the MFN-EP. The PCI function circuit is associated with an IC in which a memory region is located that the IC coupled to the MFN-EP is permitted to access.

[0061] At block 314, the method 300 includes retrieving, by the PCI functional circuit, a BAR of the PCI functional circuit based on the PCI address in the PCI transaction. At block 316, the method 300 includes reading, by the PCI functional circuit, a translation register associated with the retrieved BAR of the PCI functional circuit. At block 318, the method 300 includes determining, by the PCI functional circuit, a local address based on the translation register and the PCI address in the PCI transaction.

[0062] At block 320, method 300 includes sending, by a PCI functional circuit, the PCI transaction to a local address over an interconnect communication bus of a backplane IC. At block 322, method 300 includes routing, by an interconnect communication bus (e.g., interconnect communication bus 130), the PCI transaction to an MFN-EP coupled to the IC in which the memory region is located. At block 324, method 300 includes sending, by the MFN-EP coupled to the IC in which the memory region is located, the PCI transaction to a PCI RC of the IC in which the memory region is located.

[0063] Modifications are possible in the described embodiments and other embodiments are possible within the scope of the claims.

Claims

1. A circuit comprising: a first functional circuit including a first plurality of registers and a first input address translation unit, the first input address translation unit including a plurality of input translation registers, each corresponding to a respective register of the first plurality of registers; receiving a first transaction directed to the second circuit and including the first address; determining a first local address associated with the second circuit based on the first address, the first plurality of registers, and the first input address translation unit; sending the first transaction to the second circuit based on the first local address; a first functional circuit configured to:

2. 2. The circuit of claim 1, The circuitry, wherein the first functional circuitry is further configured to determine a reference register from the first plurality of registers, the reference register referencing the first address.

3. 3. The circuit of claim 2, The circuitry, wherein the first functional circuitry is further configured to index the first input address translation unit based on the reference register to determine the first local address.

4. 2. The circuit of claim 1, an interconnection communication bus coupling the circuit to the second circuit; a second functional circuit including a second plurality of registers and a second input address translation unit, receiving a second transaction associated with a second address directed to a third circuit; determining a second local address associated with the third circuit based on the second address, the second plurality of registers, and the second input address translation unit; sending the second transaction to the third circuit based on the second local address; the second functional circuit configured as follows: The circuit further comprises:

5. 5. The circuit of claim 4, The circuit, wherein the first functional circuit establishes a master-slave relationship with a second functional circuit of the second circuit via the interconnection communication bus.

6. 5. The circuit of claim 4, the circuit further comprising: an output address translation unit configured to receive output transactions directed to the circuit, the output address translation unit including a plurality of output translation registers, each of the plurality of output translation registers configured to store an output local address parameter and address and size parameters associated with the interconnect communication bus.

7. 7. The circuit of claim 6, A circuit wherein the size parameter identifies a memory size accessible by a device coupled to the circuit.

8. 8. The circuit of claim 7, The memory size is related to a memory area of ​​the second circuit.

9. 2. The circuit of claim 1, The circuitry, wherein each of the plurality of input translation registers is configured to store an input local address parameter and a register identifier.

10. 1. A method comprising: reading, by a processor, memory region configuration definitions for a memory region, each defining a size of the memory region, identifying the device in which the memory region is located, and identifying other devices authorized to access the memory region; for each device granted access by said processor to one of said memory regions, writing the size of said memory region in a base address register (BAR) of a functional circuit of an interface circuit coupled to said device, wherein each device is coupled to a different interface circuit; configuring, by said processor, for each device having one of said memory regions, with the local address a translation register of an output address translation unit (ATU) in functional circuitry of said interface circuit coupled to said device; configuring, for each device granted access by said processor to one of said memory regions, a translation register of an input ATU in a functional circuit of an interface circuit coupled to said device using said local address, said translation register of said input ATU being associated with a BAR of said functional circuit of said interface circuit; A method comprising:

11. 1. A method comprising: receiving, by a first functional circuit associated with a first circuit, a first transaction directed to a second circuit, the first transaction including a first address, the first functional circuit including a first plurality of registers and a first input address translation unit, the first input address translation unit including a plurality of input translation registers, each corresponding to a respective register of the first plurality of registers; determining, by the first functional circuit, a first local address based on the first address, the first plurality of registers, and the first input address translation unit; sending, by the first functional circuit, the first transaction to the second circuit based on the first local address; A method comprising:

12. 12. The method of claim 11, The method further comprising determining, by the first functional circuit, a reference register from the first plurality of registers, wherein the reference register references the first address.

13. 13. The method of claim 12, The method further comprising indexing, by the first functional circuit, the first input address translation unit based on the reference register to determine the first local address.

14. 12. The method of claim 11, The method, wherein the first circuit is coupled to the second circuit via an interconnection communication bus.

15. 15. The method of claim 14, receiving, by a second functional circuit associated with the second circuit, a second transaction directed to a third circuit, the second transaction including a second address; determining, by the second functional circuitry, a second local address based on the second address, a second plurality of registers, and a second input address translation unit; sending, by the second functional circuitry, the second transaction to the third circuitry using the second local address; The method further comprises:

16. 15. The method of claim 14, receiving, by an output address translation unit of the second circuit, the first transaction; The method, wherein the output address translation unit includes a plurality of output translation registers, each of the plurality of output translation registers storing an output local address parameter and an address parameter and a size parameter associated with the interconnect communication bus.

17. 17. The method of claim 16, The method, wherein the size parameter identifies a memory size accessible by a device coupled to the first circuit.

18. 18. The method of claim 17, The method, wherein the memory size is related to a memory area of ​​the second circuit.

19. 12. The method of claim 11, The method of claim 1, wherein each of the plurality of input translation registers stores an input local address parameter and a register identifier.

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