System on chip and method for manufacturing the same

Abstract

To provide a novel transistor with better structure and comprehensive performance to be used in a peripheral standard cell and an embedded memory cell of a system-on-chip that is desired in the industry.SOLUTION: A system-on-chip according to the present invention includes: an embedded memory module; and a peripheral digital module thereof. The embedded memory module includes at least one embed memory cell. The digital module includes: a first MOS transistor; and at least one standard cell. The standard cell includes a second MOS transistor. The embedded memory cell includes a third MOS transistor. Each of the first, the second, and the third MOS transistors includes one gate and gate oxide material layers below the gate. The second MOS transistor and the third MOS transistor have same thickness, are thinner than the gate oxide layer of the first MOS transistor. A transistor of an intermediate thickness data oxide layer in the peripheral standard cell and the memory cell in the system-on-chip of the present invention has: a smaller area; a lower operation voltage; and a smaller power consumption.SELECTED DRAWING: None

Description

[Technical Field]

[0001] The present invention relates to a system on a chip and a manufacturing method thereof, and more particularly to a system on a chip including a digital module and an embedded storage module and a manufacturing method thereof. [Background technology]

[0002] A system on a chip (SOC) includes a memory module and a peripheral digital module. The memory module includes an embedded memory module and a non-embedded memory module. The embedded memory module includes embedded memory cells, which include memory transistors. The peripheral digital module includes logic transistors (also called peripheral logic transistors) and standard cells, which also include logic transistors (also called peripheral logic transistors).

[0003] The peripheral logic transistors and memory transistors include different types of thick and thin gate oxide layers. Thick gate oxide transistors typically include 5v devices, and thin gate oxide transistors typically include 1.5v or 1.8v devices. Thick gate oxide transistor elements may be referred to as high voltage transistor elements, and thin gate oxide transistor elements may be referred to as low voltage transistor elements.

[0004] Peripheral standard cells and embedded memory cells usually select high-voltage transistors, such as 5V transistors, or low-voltage transistors, such as 1.5V transistors, which have the following drawbacks: high-voltage transistors have thick gate oxide layers, high threshold voltages, large areas, small unit capacitances, and are not suitable for low voltages, such as voltages below 5V; low-voltage transistors have low voltage resistance and are not suitable for high voltages, such as voltages above 1.5V. Summary of the Invention [Problem to be solved by the invention]

[0005] Therefore, there is a need in the industry for new transistors with better structure and integration for use in peripheral standard cells and embedded storage cells of systems-on-chip. [Means for solving the problem]

[0006] A system-on-chip according to a first aspect of the present invention includes a digital module including at least one first MOS transistor and at least one standard cell, and at least one embedded Included notes an embedded memory module including a standard cell, the standard cell including at least one second MOS transistor, and the embedded memory module including Included notes The memory cell includes at least one third MOS transistor, and each of the first MOS transistor, the second MOS transistor, and the third MOS transistor includes a gate and a gate oxide layer thereunder, and the gate oxide layers of the second MOS transistor and the third MOS transistor have the same thickness and are thinner than the gate oxide layer of the first MOS transistor.

[0007] In one preferred embodiment, the thickness of the gate oxide layer of the second MOS transistor and the third MOS transistor is Gate oxide layer At least 10 angstroms thick Small , more preferably at least 20 Angstroms small .

[0008] In another preferred embodiment, the gate oxide layers of the second MOS transistor and the third MOS transistor are formed in the same step in the same manufacturing process platform.

[0009] In another preferred embodiment, the digital module further includes a fourth MOS transistor including a gate and an underlying gate oxide layer, and the thickness of the gate oxide layer of the second MOS transistor is greater than the thickness of the gate oxide layer of the fourth MOS transistor. More preferably, the thickness of the gate oxide layer of the second MOS transistor is greater than the thickness of the gate oxide layer of the fourth MOS transistor. Gate oxide layer The thickness is at least 5 angstroms thicker than the thickness.

[0010] In another preferred embodiment, the thickness of the gate oxide layer of the second MOS transistor and the third MOS transistor is 30 to 190 angstroms.

[0011] In yet another preferred embodiment, said embedded storage cells are embedded non-volatile storage cells, more preferably embedded multiple-times programmable and erasable storage cells or embedded flash storage cells.

[0012] In another preferred embodiment, the standard cell is an inverter, a NAND gate, a NOR gate, a three-state buffer, a latch, a flip-flop, a register, a selector, or a full adder.

[0013] According to another aspect of the present invention, a method for manufacturing the above-described system-on-chip of the present invention includes the steps of forming a gate oxide layer for a first MOS transistor, and then thinning the formed gate oxide layer in regions where a second MOS transistor and a third MOS transistor are to be formed, while simultaneously forming gate oxide layers for the second MOS transistor and the third MOS transistor. DETAILED DESCRIPTION OF THE INVENTION

[0014] The system-on-chip includes multiple modules, each of which includes multiple semiconductor elements, such as transistors. A module further includes several cells, each of which is made up of semiconductor elements (such as transistors).

[0015] The system-on-chip of the present invention includes an embedded memory module and a peripheral digital module. The first and fourth MOS transistors included in the digital module and the second MOS transistor included in the standard cell may be referred to as thick-gate oxide and thin-gate oxide peripheral logic transistors and intermediate-thickness gate oxide peripheral logic transistors, respectively. The third MOS transistor included in the memory cell of the embedded memory module may be referred to as intermediate-thickness gate oxide memory transistor.

[0016] The first MOS transistor and the fourth MOS transistor in the digital module are preferably not included in a standard cell in the digital module.

[0017] In the system-on-chip of the present invention, the gate oxide thickness of the peripheral logic transistors with intermediate gate oxide layers is the same as that of the memory transistors with intermediate gate oxide layers but thinner than that of the peripheral logic transistors with thick gate oxide layers. If the digital module further includes peripheral logic transistors with intermediate gate oxide layers, the gate oxide thickness of the peripheral logic transistors with intermediate gate oxide layers is thinner than that of the peripheral logic transistors with thick gate oxide layers but thicker than that of the peripheral logic transistors with thin gate oxide layers, i.e., between the gate oxide thicknesses of the first and fourth MOS transistors in the digital module.

[0018] The intermediate gate oxide peripheral logic transistor of the present invention has a gate oxide thickness thinner than that of the thick gate oxide peripheral logic transistor in a digital module, and thus has higher performance than the thick gate oxide peripheral logic transistor (i.e., the high-voltage transistor commonly used in conventional peripheral standard cells), i.e., it can accommodate a smaller gate line width (transistor channel length), reduce area, have a lower threshold voltage, can meet the requirements of medium or low operating voltage, and has better device characteristics, such as a larger driving capability (driving current) and a higher unit capacitance.

[0019] In addition, the intermediate-thickness gate oxide peripheral logic transistors have a gate oxide thickness that is thicker than that of the thin-gate oxide peripheral logic transistors in the digital module, and thus have a higher breakdown voltage than the thin-gate oxide peripheral logic transistors (i.e., low-voltage transistors typically used in typical peripheral standard cells), and can meet the requirements for slightly higher or intermediate operating voltages.

[0020] Similarly, the memory transistor with intermediate gate oxide thickness of the present invention can reduce the operating voltage, area, and power consumption compared to the memory transistor with thick gate oxide layer, and has a higher breakdown voltage compared to the memory transistor with thin gate oxide layer, and can meet the requirements of slightly higher or intermediate operating voltage.

[0021] In the present invention, the thickness of the gate oxide layer of the peripheral logic transistor (second MOS transistor) with the intermediate gate oxide layer is preferably at least 10 angstroms less, more preferably at least 20 angstroms less, and even more preferably at least 30 angstroms less than the thickness of the gate oxide layer of the peripheral logic transistor (first MOS transistor) with the thick gate oxide layer.

[0022] When the digital module further includes a peripheral logic transistor (fourth MOS transistor) with a medium-thickness gate oxide layer, the thickness of the gate oxide layer of the peripheral logic transistor with a medium-thickness gate oxide layer is preferably at least 5 angstroms greater than the thickness of the gate oxide layer of the peripheral logic transistor with a thin gate oxide layer, more preferably at least 10 angstroms greater, even more preferably at least 20 angstroms greater, even more preferably at least 30 angstroms greater, and most preferably at least 50 angstroms greater.

[0023] The intermediate thickness gate oxide storage transistors have the preferred feature of having the same gate oxide thickness as the intermediate thickness gate oxide peripheral logic transistors.

[0024] In the present invention, the thickness of the gate oxide layer of the peripheral logic transistor and the memory transistor is not particularly limited to a specific dimension, and is set according to a specific application. Preferably, the thickness is as follows:

[0025] The thickness of the gate oxide layer of the peripheral logic transistor (first MOS transistor) with a thick gate oxide layer is >60 angstroms, preferably 70 to 300 angstroms, more preferably 80 to 260 angstroms, even more preferably 90 to 220 angstroms, and most preferably 100 to 180 angstroms.

[0026] The thickness of the gate oxide layer of the peripheral logic transistor (second MOS transistor) with an intermediate-thickness gate oxide layer and the memory transistor (third MOS transistor) with an intermediate-thickness gate oxide layer is preferably 30 to 190 angstroms, more preferably 40 to 150 angstroms, more preferably 50 to 110 angstroms, even more preferably 55 to 100 angstroms, and most preferably 60 to 90 angstroms.

[0027] The thickness of the thin gate oxide layer of the peripheral logic transistor (fourth MOS transistor) is preferably 10 to 40 angstroms, more preferably 12 to 38 angstroms, even more preferably 15 to 35 angstroms, and most preferably 18 to 32 angstroms.

[0028] In the present invention, the gate line width (channel length) of the peripheral logic transistors with intermediate gate oxide layers and the memory transistors with intermediate gate oxide layers is preferably smaller than that of the peripheral logic transistors with thick gate oxide layers. When the digital module includes two types of peripheral logic transistors with thick gate oxide layers and thin gate oxide layers, the gate line width (channel length) of the peripheral logic transistors with intermediate gate oxide layers is preferably not only smaller than that of the peripheral logic transistors with thick gate oxide layers but also larger than that of the peripheral logic transistors with thin gate oxide layers, and is between them.

[0029] In the present invention, the gate line width (channel length) of the peripheral logic transistor and memory transistor is not particularly limited to a specific dimension, and is set according to a specific application, and preferably has the following dimensions.

[0030] The gate line width (channel length) of the peripheral logic transistor with a thick gate oxide layer is preferably 0.11 to 12.00 μm, more preferably 0.15 to 7.00 μm, even more preferably 0.20 to 2.00 μm, and most preferably 0.30 to 0.8 μm.

[0031] The gate line width (channel length) of the peripheral logic transistor with the medium-thickness gate oxide layer and the memory transistor with the medium-thickness gate oxide layer is preferably 0.05 to 10.00 μm, more preferably 0.08 to 5.00 μm, even more preferably 0.11 to 1.00 μm, and most preferably 0.13 to 0.60 μm.

[0032] The gate line width (channel length) of the peripheral logic transistor of the thin gate oxide layer is preferably 0.01 to 5.00 μm, more preferably 0.03 to 1.00 μm, even more preferably 0.05 to 0.5 μm, and most preferably 0.07 to 0.20 μm.

[0033] In the system-on-chip of the present invention, the peripheral logic transistors in the digital module and the storage transistors in the storage module are fabricated and formed on the same manufacturing process platform. That is, the peripheral logic transistors with thick gate oxide layers, the peripheral logic transistors with medium-thickness gate oxide layers, and the storage transistors with medium-thickness gate oxide layers are fabricated and formed on the same manufacturing process platform. If the digital module further includes peripheral logic transistors with thin gate oxide layers, the peripheral logic transistors with thin gate oxide layers are also fabricated and formed on the same manufacturing process platform. For the peripheral logic transistors with medium-thickness gate oxide layers and the storage transistors with medium-thickness gate oxide layers, their gate oxide layers are formed together in the same manufacturing process, in the same steps. Furthermore, their well implantation, gate formation, and lightly and heavily doped source and drain doping steps are performed together with the corresponding steps for the peripheral logic transistors with thick gate oxide layers. However, if the types of these transistors are different, the well implantation and the types of ions doped into the source and drain are different. This manufacturing method is very convenient, improves efficiency, and reduces costs. Since the formation of new transistor elements in chips known in the industry typically requires additional gate oxide layer formation steps, additional well implantation and source-drain doping steps, the technical means of the present invention reduces process complexity and eliminates the photomask level.

[0034] That is, for an embedded memory module platform based on a logic process, the present invention utilizes the tunnel oxide in the memory cell as the gate oxide layer of the peripheral logic transistor with a medium-thickness gate oxide layer, and shares well implantation processes, lightly doped and heavily doped source / drain regions, etc. with standard logic devices with thick gate oxide layers in the process platform to form a novel transistor or transistor capacitor. The novel transistor has a thinner gate oxide layer, a lower threshold voltage, and can operate at a lower operating voltage. The device has a smaller design rule, and standard cells based on the process platform can use the novel device with a smaller area, significantly reducing customer product costs.

[0035] The system-on-chip of the present invention can be fabricated using a variety of standard logic process platforms common within the industry, such as 180nm, 150nm, 130nm, 110nm, 90nm, 55nm, or 40nm process platforms. The 180nm process can fabricate 5v or 3.3v transistor devices, or can fabricate 1.8v and 5v transistor devices simultaneously, or can fabricate 1.8v and 3.3v transistor devices simultaneously. The 110nm process can fabricate 5v transistor devices, or can fabricate 1.5v and 5v transistor devices simultaneously.

[0036] These processes generally include the following standard steps in sequence: forming a shallow trench isolation region; sequentially forming wells in which the thick gate oxide transistor and the thin gate oxide transistor will be located; forming a thick gate oxide layer; forming a thin gate oxide layer (specifically, covering the thin gate oxide transistor region other than the thin gate oxide transistor region with a mask, and then thinning the formed thick gate oxide layer in the thin gate oxide transistor region not covered by the mask to form a thin gate oxide layer); forming a gate; sequentially forming lightly doped source and drain regions of the thin gate oxide transistor and the thick gate oxide transistor; forming a gate sidewall protection layer; forming heavily doped source and drain regions of the thin gate oxide transistor and the thick gate oxide transistor; forming a metal silicide; and forming a rear metal wiring layer.

[0037] If the digital module does not include thin gate oxide peripheral logic transistors, the above steps do not include steps relating to thin gate oxide transistors.

[0038] More specifically, if the digital module in the system-on-chip does not include peripheral logic transistors with thin gate oxide layers, the steps for forming peripheral logic transistors with medium-thickness gate oxide layers and memory transistors with medium-thickness gate oxide layers in the present invention are as follows:

[0039] In the process for fabricating the system-on-chip of the present invention, the wells, gates, and source-drain regions of the intermediate-thickness gate oxide peripheral logic transistor and the intermediate-thickness gate oxide memory transistor are formed in the same step as the formation of the wells, gates, and source-drain regions of the thick-gate oxide peripheral logic transistor, respectively, except that the intermediate-thickness gate oxide peripheral logic transistor, if different in type from the intermediate-thickness gate oxide memory transistor or the thick-gate oxide peripheral logic transistor, has different ion types implanted into its well and different ion types implanted into its source-drain doped regions.

[0040] The gate oxide layer of the intermediate-thickness gate oxide peripheral logic transistor is the same as the gate oxide layer of the intermediate-thickness gate oxide storage transistor and is formed in the same step. However, it is different from the gate oxide layer of the thick-gate oxide peripheral logic transistor and is formed in a different order. That is, in the gate oxide layer formation step between the well formation step and the gate formation step, after forming the gate oxide layer of the thick-gate oxide peripheral logic transistor, regions other than the regions where the intermediate-thickness gate oxide peripheral logic transistor and the intermediate-thickness gate oxide storage transistor will be formed are covered with a mask, and then the formed thick gate oxide layer is thinned to a desired thickness in the regions of the intermediate-thickness gate oxide peripheral logic transistor and the intermediate-thickness gate oxide storage transistor that are not covered with the mask to form a new thin intermediate-thickness gate oxide layer.

[0041] A specific method for thinning the thick gate oxide layer formed in the area not covered by the mask and forming a new intermediate-thickness gate oxide layer includes irradiating the area not covered by the mask with optical radiation and etching it to reach the desired thickness of the new gate oxide layer, completely stripping the formed gate oxide layer, and then thermally oxidizing the area to form a new gate oxide layer. Alternatively, the specific method includes irradiating the area not covered by the mask with optical radiation and etching it to partially strip the formed gate oxide layer so that the remaining gate oxide layer reaches the desired thickness of the new gate oxide layer. The first method is preferred. In the second method, partially stripping the gate oxide layer leaves etching material in the remaining gate oxide layer, which affects the performance of the new gate oxide layer.

[0042] If the system-on-chip digital module further includes a thin-gate-oxide peripheral logic transistor, the manufacturing process involves forming the wells, gate oxide layers, gates, and source-drain doped regions of the intermediate-thickness gate-oxide peripheral logic transistor and the intermediate-thickness gate-oxide memory transistor as described above. The gate oxide layer of the thin-gate-oxide peripheral logic transistor is formed by forming the gate oxide layers for the thick-gate-oxide peripheral logic transistor and the intermediate-thickness gate-oxide peripheral logic transistor in the gate oxide layer formation step, then covering with a mask areas other than the area where the thin-gate-oxide peripheral logic transistor will be formed, and then thinning the gate oxide layer formed in the area of ​​the thin-gate-oxide peripheral logic transistor that is not covered with the mask to obtain the desired gate oxide thickness for the new thin-gate-oxide peripheral logic transistor. Then, gates are formed.

[0043] The specific method for thinning the formed gate oxide layer and forming a new gate oxide layer in the areas not covered by the mask is as described above.

[0044] The present invention Included notes The memory cells are preferably filled Not included A volatile memory cell, more preferably an embedded Complex A memory cell or filler that can be programmed and erased several times Including It is a rush memory cell.

[0045] The standard cells in the digital module of the present invention are preferably inverters, NAND gates, NOR gates, three-state buffers, latches, flip-flops, registers, selectors or full adders.

[0046] The following describes in detail the system-on-chip of the present invention, its manufacturing method, and the manufacturing methods of its intermediate gate oxide peripheral logic transistors and intermediate gate oxide memory transistors, as well as their structure and performance, by way of examples.

[0047] A 110-nm logic process is used to fabricate a system-on-chip (SOC). The SOC includes an embedded multiple-times programmable and erasable memory module and a peripheral digital module. The memory module includes at least one embedded multiple-times programmable and erasable memory cell, which includes a medium-thickness gate oxide memory transistor. The digital module includes at least one thick-gate oxide peripheral logic transistor, at least one thin-gate oxide peripheral logic transistor, and at least one standard cell. The at least one standard cell is an inverter. The inverter includes two medium-thickness gate oxide peripheral logic transistors that are essentially the same in structure and components but opposite in type: one NMOS medium-thickness gate oxide peripheral logic transistor and one PMOS medium-thickness gate oxide peripheral logic transistor.

[0048] The thick-gate-oxide peripheral logic transistor, thin-gate-oxide peripheral logic transistor, NMOS intermediate-thickness gate-oxide peripheral logic transistor in the inverter, and intermediate-thickness gate-oxide memory transistor are all NMOS transistors located in a P well, each having an N-type source and drain, each including one lightly N-doped region and one heavily N-doped region. The gate oxide thicknesses of these transistors are 139±5 Å, 25±5 Å, 85±5 Å, and 85±5 Å, respectively, and are applicable to 5V, 1.5V, 3.3V, and 3.3V operating voltages, and may also be referred to as 5V transistor elements, 1.5V transistor elements, 3.3V transistor elements, and 3.3V transistor elements. The PMOS intermediate-thickness gate oxide peripheral logic transistors in the inverter are located in an N-well and have P-type source and drain regions, each containing one lightly P-doped region and one heavily P-doped region. The gate oxide thickness is the same as that of the NMOS, 85±5 Å.

[0049] In contrast to the thick / thin gate oxide peripheral logic transistors (e.g., 5V / 1.5V transistor elements) commonly used in conventional peripheral standard cells, the gate oxide thickness of the NMOS and PMOS intermediate gate oxide peripheral logic transistors in this embodiment is thinner than that of the thick gate oxide peripheral logic transistors, resulting in a lower threshold voltage and allowing them to be used at operating voltages of 3.3V lower than 5V, thereby meeting the requirements for low operating voltages. At the same time, the gate oxide thickness of the NMOS and PMOS intermediate gate oxide peripheral logic transistors is thicker than that of the thin gate oxide peripheral logic transistors, resulting in improved voltage resistance and allowing them to be used at operating voltages of 3.3V higher than 1.5V.

[0050] In this embodiment, the gate line widths (channel lengths) of the thick gate oxide peripheral logic transistor, the thin gate oxide peripheral logic transistor, the NMOS and PMOS intermediate gate oxide peripheral logic transistors, and the intermediate gate oxide storage transistor are 0.6 μm, 0.11 μm, 0.35 μm, and 0.35 μm, respectively. The gate line width of the NMOS intermediate gate oxide peripheral logic transistor is the same as the gate line width of the PMOS intermediate gate oxide peripheral logic transistor. The gate line width (channel length) of the intermediate gate oxide peripheral logic transistor is smaller than the gate line width (channel length) of the thick gate oxide peripheral logic transistor. Compared to the thick gate oxide peripheral logic transistor commonly used in conventional peripheral standard cells, the intermediate gate oxide peripheral logic transistor of this embodiment allows for a reduced area size. The intermediate gate oxide storage transistor also allows for a reduced area size of the storage cell.

[0051] In this embodiment, the channel saturation currents of the thick gate oxide peripheral logic transistor, the thin gate oxide peripheral logic transistor, the NMOS and PMOS intermediate gate oxide peripheral logic transistors, and the intermediate gate oxide memory transistor are 570 μA / μm, 425 μA / μm, 530 μA / μm, −260 μA / μm, and 530 μA / μm, respectively. The channel saturation current of the intermediate gate oxide peripheral logic transistor is greater than that of the thin gate oxide peripheral logic transistor. Compared to the thin gate oxide peripheral logic transistor commonly used in conventional peripheral standard cells, the intermediate gate oxide peripheral logic transistor of this embodiment has a greater driving capability (driving current) under the same operating voltage.

[0052] The system-on-chip of this embodiment is fabricated using a conventional 110 nm logic process platform, and includes the steps of forming shallow trench isolation regions, forming N-wells in which peripheral logic transistors with PMOS intermediate-thickness gate oxide layers are located, forming P-wells in which peripheral logic transistors with thick gate oxide layers, peripheral logic transistors with NMOS intermediate-thickness gate oxide layers, and storage transistors with intermediate-thickness gate oxide layers are located, forming P-wells in which peripheral logic transistors with thin gate oxide layers are located, and forming gate oxide layers (gate oxide layers of peripheral logic transistors with thick gate oxide layers, gate oxide layers of peripheral logic transistors with PMOS and NMOS intermediate-thickness gate oxide layers and storage transistors with intermediate-thickness gate oxide layers, and gate oxide layers of peripheral logic transistors with thin gate oxide layers). forming gates of the four transistors; forming lightly doped N-type source / drain regions of the peripheral logic transistors with a thin gate oxide layer; forming lightly doped N-type source / drain regions of the peripheral logic transistors with a thick gate oxide layer, the peripheral logic transistors with an NMOS intermediate-thickness gate oxide layer, and the memory transistors with an intermediate-thickness gate oxide layer; and forming lightly doped P-type source / drain regions of the peripheral logic transistors with a PMOS intermediate-thickness gate oxide layer; forming a gate sidewall protection layer; forming heavily doped source / drain regions of the four transistors; forming a metal silicide; and forming a rear metal wiring layer.

[0053] The intermediate-thickness gate oxide peripheral logic transistor and the intermediate-thickness gate oxide memory transistor are basically formed together with the thick-gate oxide peripheral logic transistor (high-voltage transistor). The well, gate, and source / drain of the NMOS intermediate-thickness gate oxide peripheral logic transistor and the intermediate-thickness gate oxide memory transistor are respectively formed in the same step together with the well, gate, and source / drain of the thick-gate oxide peripheral logic transistor. The N-well of the PMOS intermediate-thickness gate oxide peripheral logic transistor is formed in preference to the P-well of the thick-gate oxide peripheral logic transistor, and its gate and source / drain are also respectively formed in the same step together with the thick-gate oxide peripheral logic transistor.

[0054] However, the gate oxide layers of the intermediate-thickness gate oxide peripheral logic transistors and the intermediate-thickness gate oxide memory transistors are formed differently from the gate oxide layers of the thick-thickness gate oxide peripheral logic transistors. The gate oxide layer formation steps for each transistor are specifically as follows:

[0055] Between the well formation step and the gate formation step, a gate oxide layer is first formed with a thickness of 139±5 angstroms for the thick gate oxide peripheral logic transistor. Next, areas other than the areas where the intermediate-thickness gate oxide peripheral logic transistor and the intermediate-thickness gate oxide memory transistor are to be formed are covered with a mask. Next, the areas of the intermediate-thickness gate oxide peripheral logic transistor and the intermediate-thickness gate oxide memory transistor that are not covered with the mask are irradiated with light and etched to completely remove the formed thick gate oxide layer, and then the areas are thermally oxidized to form new gate oxide layers with a thickness of 85±5 angstroms for the intermediate-thickness gate oxide peripheral logic transistor and the intermediate-thickness gate oxide memory transistor. Then, a gate oxide layer is directly formed for the thin gate oxide peripheral logic transistor. That is, areas of the thin gate oxide layer other than the area where the peripheral logic transistor area is to be formed are covered with a mask, and then the area of ​​the peripheral logic transistor of the thin gate oxide layer that is not covered with the mask is irradiated with optical radiation and etched to completely remove the gate oxide layer formed in that area, and then thermal oxidation is performed on that area to generate a new gate oxide layer of the peripheral logic transistor of the thin gate oxide layer having a thickness of 25±5 angstroms.

[0056] The present invention uses a simple, efficient, and low-cost method to simultaneously fabricate novel higher performance intermediate-thickness gate oxide peripheral logic transistors and intermediate-thickness gate oxide memory transistors, which are applied to peripheral digital modules and embedded memory modules of systems-on-chip, respectively.

Claims

1. a digital module including at least one first MOS transistor and at least one standard cell; and an embedded memory module including at least one embedded memory cell; the standard cell includes at least one second MOS transistor, the embedded memory cell includes at least one third MOS transistor, the first MOS transistor, the second MOS transistor, and the third MOS transistor each include a gate and an underlying gate oxide layer, the gate oxide layers of the second MOS transistor and the third MOS transistor have the same thickness and are both thinner than the thickness of the gate oxide layer of the first MOS transistor.

2. 2. The system-on-chip of claim 1, wherein the thickness of the gate oxide layer of the second MOS transistor and the third MOS transistor is at least 10 Angstroms less than the thickness of the gate oxide layer of the first MOS transistor.

3. 3. The system-on-chip of claim 1, wherein the digital module further includes a fourth MOS transistor including a gate and an underlying gate oxide layer, and wherein a thickness of the gate oxide layer of the second MOS transistor is greater than a thickness of the gate oxide layer of the fourth MOS transistor.

4. 4. The system on a chip of claim 3, wherein the thickness of the gate oxide layer of the second MOS transistor is at least 5 Angstroms thicker than the thickness of the gate oxide layer of the fourth MOS transistor.

5. 3. The system-on-chip according to claim 1, wherein the thickness of the gate oxide layer of the second MOS transistor and the third MOS transistor is 30 to 190 angstroms.

6. 3. The system-on-chip of claim 1, wherein the embedded storage cells are embedded non-volatile storage cells.

7. 7. The system-on-chip of claim 6, wherein the embedded non-volatile storage cells are embedded multiple-times programmable and erasable storage cells or embedded flash storage cells.

8. 3. The system-on-chip according to claim 1, wherein the standard cell is an inverter, a NAND gate, a NOR gate, a three-state buffer, a latch, a flip-flop, a register, a selector, or a full adder.

9. 2. The method for manufacturing a system on a chip according to claim 1, further comprising the step of: after forming a gate oxide layer of the first MOS transistor, thinning the formed gate oxide layer in regions where the second MOS transistor and the third MOS transistor are to be formed, thereby forming gate oxide layers of the second MOS transistor and the third MOS transistor.

10. 2. The method for manufacturing a system-on-chip of claim 1, wherein gate oxide layers of the second MOS transistor and the third MOS transistor are formed in the same step in the same manufacturing process platform.