Three-dimensional vertical NOR flash thin-film transistor strings

Abstract

A memory structure is provided that has low read latency, reduced susceptibility to read disturb and program disturb conditions, and a low cost per bit. The memory structure includes multiple active columns (430L, 430R, 431L, 431R) of semiconductor material formed on a semiconductor substrate. Each active column extends along a first direction perpendicular to the planar surface of the semiconductor substrate and includes a first heavily doped region, a second heavily doped region, and one or more lightly doped regions adjacent to both the first heavily doped region and the second heavily doped region. The active columns are arranged in a two-dimensional array and include charge trapping layers (432, 434) on one or more surfaces in each active column and multiple conductors each extending longitudinally along a third direction.

Description

[Technical Field]

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] This application is based on (i) co-pending U.S. Provisional Patent Application No. 62 / 260,137, filed November 25, 2015, entitled "3-D VERTICAL NOR FLASH THIN-FILM TRANSISTOR STRING" (co-pending U.S. Provisional Patent Application No. I), (ii) co-pending U.S. Provisional Patent Application No. 15 / 220,375, filed July 26, 2016, entitled "MULTIGATE NOR FLASH THIN-FILM TRANSISTOR STRING ORGANIZED IN STACKED HORIZONTAL ACTIVE STRIPS WITH VERTICAL CONTROL GATES" (co-pending U.S. Provisional Patent Application No. I), (iii) co-pending U.S. Provisional Patent Application No. 62 / 363,189, filed July 15, 2016, entitled "CAPACITIVELY COUPLED NON-VOLATILE THIN-FILM TRANSISTOR STRING" (co-pending U.S. Provisional Patent Application No. II), and (iv) Related to and claims the benefit of priority to co-pending U.S. patent application Ser. No. 15 / 248,420, entitled "Three-Dimensional Capacitively Coupled Nonvolatile Thin Film Transistor Strings," filed on August 26, 2016 (co-pending U.S. Patent Application II). The disclosures of co-pending U.S. Provisional Patent Application I, co-pending U.S. Provisional Patent Application II, co-pending U.S. Patent Application I, and co-pending U.S. Patent Application II are incorporated herein by reference in their entireties.

[0002] The present invention relates to high density memory structures, and more particularly to high density memory structures formed with interconnected thin film storage elements, such as thin films formed in vertical strips with horizontal word lines. [Background technology]

[0003] This disclosure describes several memory circuit structures. These structures can be fabricated on a planar semiconductor substrate (e.g., a silicon wafer) using conventional manufacturing processes. For clarity herein, the term "vertical" will refer to a direction perpendicular to the surface of the semiconductor substrate, and the term "horizontal" will refer to any direction parallel to the surface of the semiconductor substrate.

[0004] Many types of high-density nonvolatile memory structures, such as "three-dimensional vertical NAND strings," are known in the art. Many of these high-density memory structures are formed from deposited thin films (e.g., polysilicon thin films) and organized using thin-film storage transistors arranged as an array of "memory strings." One type of memory string is called a NAND memory string, or simply a "NAND string." A NAND string consists of many series-connected thin-film memory transistors ("TFTs"). Reading or programming the contents of any of the series-connected TFTs requires activation of all series-connected TFTs in the string. Thin-film NAND transistors have lower conductivity than NAND transistors formed in single-crystal silicon, so the low read currents required to conduct through long NAND strings result in slow read accesses (i.e., long latency).

[0005] Another type of high-density memory structure is called a NOR memory string or "NOR string." A NOR string contains multiple memory transistors, each connected to a shared source region and a shared drain region. Therefore, NOR strings are connected in parallel so that a read current through a NOR string is conducted with much less resistance than a read current through a NAND string. To read or program a memory transistor in a NOR string, only that memory transistor needs to be activated (i.e., "on" or conducting); all other memory transistors in the NOR string can be placed in a quiescent state (i.e., off or non-conducting). As a result, a NOR string allows for more rapid sensing of activated memory transistors to be read. Conventional NOR transistors are programmed by a channel hot electron injection technique, in which electrons are accelerated in the channel region by a voltage difference between the source and drain regions and injected into a charge trapping layer between the control gate and the channel region when an appropriate voltage is applied to the control gate. Channel hot electron injection programming requires a relatively large current (electron flow) through the channel region, limiting the number of transistors that can be programmed in parallel. Unlike transistors programmed by hot electron injection, transistors programmed by Fowler-Nordheim or direct tunneling inject electrons from the channel region into a charge trapping layer by a high electric field applied between the control gate and the source and drain regions. Fowler-Nordheim and direct tunneling are more efficient than channel hot electron injection and allow for massively parallel programming, but such tunneling is more susceptible to program disturb conditions.

[0006] A three-dimensional NOR memory array is disclosed in U.S. Patent No. 8,630,114 (Patent Document 1) by H.T. Lue, entitled "Memory Architecture for 3D NOR Array," filed March 11, 2011, and published January 14, 2014.

[0007] U.S. Patent Application Publication No. 2016 / 0086970 (Patent Document 2), by Haibing Peng, entitled "Memory Architecture for 3D NOR Array," filed on September 21, 2015, and published on March 24, 2016, discloses a non-volatile NOR flash memory device consisting of an array of basic NOR memory groups, in which individual memory cells are stacked along a horizontal direction parallel to a semiconductor substrate, with source and drain electrodes shared by all field-effect transistors located on one or both sides of a conductive channel.

[0008] Three-dimensional vertical memory structures are disclosed, for example, in U.S. Patent No. 8,878,278 (Patent Document 3) by Alsmeier et al., entitled "Compact 3D Vertical NAND and Method for Fabricating Same," filed January 30, 2013, and published November 4, 2014. U.S. Patent No. 8,878,278 (Alsmeier) discloses various types of high-density NAND memory structures, such as a "Terabit Cell Array Transistor" (TCAT) NAND array (FIG. 1A), a "Pipe-Shaped Bit-Cost Scalable (P-BiCS) Flash Memory" (FIG. 1B), and a "Vertical NAND" memory string structure. Similarly, U.S. Patent No. 7,005,350 (Patent Document 4) by Walker et al., entitled "Method for Fabricating a Programmable Memory Array Structure Incorporating Series-Connected Transistor Strings," filed December 31, 2002, and published February 28, 2006, also discloses numerous three-dimensional high-density NAND memory structures.

[0009] U.S. Pat. No. 7,612,411 (Patent Document 5) by Walker, entitled "Dual Gate Device and Method," filed August 3, 2005, and published November 3, 2009 (Walker II), discloses a "dual gate" memory structure in which a shared active area provides independently controlled storage elements in two NAND strings formed on opposite sides of the shared active area.

[0010] A three-dimensional NOR memory array is disclosed in US Pat. No. 8,630,114 (Patent Document 1).

[0011] A three-dimensional memory structure including horizontal NAND strings controlled by vertical polysilicon gates is disclosed in Kim et al., 2009. Another three-dimensional memory structure also including horizontal NAND strings with vertical polysilicon gates is disclosed in Lue et al., 2010.

[0012] FIG. 1A illustrates three-dimensional vertical NAND strings 101 and 102 according to the prior art. FIG. 1B illustrates a basic circuit representation 140 of a three-dimensional vertical NAND string according to the prior art. Specifically, the circuit representations of vertical NAND strings 101 and 102 of FIG. 1A and their counterparts, vertical NAND string 150, are essentially conventional horizontal NAND strings rotated 90 degrees so that each is perpendicular to the substrate (rather than each transistor connecting 32 or more transistors connected in series along the surface of the substrate). Vertical NAND strings 101 and 102 are thin-film transistors (TFTs) connected in series in a string configuration rising from the substrate like a skyscraper, with each TFT having a memory element and a control gate provided by one of the word line conductors in an adjacent stack of word line conductors. As shown in FIG. 1B, in the simplest embodiment of a vertical NAND string, TFTs 15 and 16 are the first and last memory transistors of NAND string 150, controlled by separate word lines WL0 and WL31, respectively. Bit line select transistor 11, activated by signal BLS, and ground select transistor 12, activated by signal SS, connect an addressed TFT in vertical NAND string 150 to a corresponding global bit line GBL at terminal 14 and to ground to a global source line (GSL) at terminal 13 during read, program, program inhibit, and erase operations. Reading or programming the contents of any one TFT (e.g., TFT 17) requires activating all 32 TFTs in vertical NAND string 150 and placing each TFT in a read inhibit and program inhibit state. This requirement limits the number of TFTs that can be included in a vertical NAND string to 64 or 128 TFTs or less. Furthermore, the polysilicon thin film from which vertical NAND strings are formed has significantly lower channel mobility and therefore higher resistivity than conventional NAND strings formed on single-crystal silicon substrates, resulting in a lower read current compared to that of conventional NAND strings.

[0013] U.S. Patent Application Publication No. 2011 / 0298013 (Patent Document 6) by Hwang, entitled "Vertical Structure Semiconductor Memory Device and Manufacturing Method Thereof," shows in FIG. 4D a block of three-dimensional vertical NAND strings addressed by wrap-around stacked word lines (reproduced here as 150 in FIG. 1C).

[0014] U.S. Patent No. 5,768,192 to Eitan, entitled "Memory Cell Utilizing Asymmetric Charge Traps," filed July 23, 1996, and published June 16, 1998, discloses an NROM-type memory transistor operation of the type employed in one embodiment of the present invention.

[0015] U.S. Patent No. 8,026,521 (Patent Document 8) by Zvi Or-Bach et al., entitled "Memory Cell Utilizing Asymmetric Charge Traps," filed October 11, 2010, and published September 27, 2011, discloses first and second layers of layer-transferred single crystal silicon, where the first and second layers include horizontally oriented transistors, in which the second layer of horizontally oriented transistors overlies the first layer of horizontally oriented transistors, and each group of horizontally oriented transistors has a side gate.

[0016] Transistors with conventional nonvolatile memory transistor structures but with shorter retention times can be called "quasi-volatile." A related point is that conventional nonvolatile memories have data retention times exceeding several decades. Planar quasi-volatile memory transistors on single-crystal silicon substrates are disclosed by H.C. Wann et al., 1995 (Non-Patent Document 3). Also, a quasi-volatile 3-D NOR array with quasi-volatile memory is disclosed in the aforementioned U.S. Patent No. 8,630,114 (Patent Document 6). [Prior art documents] [Patent documents]

[0017] [Patent Document 1] U.S. Patent No. 8,630,114 [Patent Document 2] US Patent Application Publication No. 2016 / 0086970 [Patent Document 3] U.S. Patent No. 8,878,278 [Patent Document 4] U.S. Patent No. 7,005,350 [Patent Document 5] U.S. Patent No. 7,612,411 [Patent Document 6] US Patent Application Publication No. 2011 / 0298013 [Patent Document 7] U.S. Patent No. 5,768,192 [Patent Document 8] U.S. Patent No. 8,026,521 [Non-patent literature]

[0018] [Non-Patent Document 1] W. Kim et al., "Multi-layered Vertical gate NAND Flash Overcoming Stacking Limit for Terabit Density Storage" ("Kim"), (2009) Symposium on VLSI Tech. Dig. of Technical Papers, pp 188-189 [Non-patent document 2] HT Lue et al., "A Highly Scalable 8- Layer 3D Vertical-gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device," 2010 Symposium on VLSI: Tech. Dig. Of Technical Papers, pp.131-13 [Non-patent document 3] HC Wann and C. Hu, "High-Endurance Ultra-Thin Tunnel Oxide in Monos Device Structure for Dynamic Memory Application", IEEE Electron Device letters, Vol. 16, No. 11, November 1995, pp 491-493 Summary of the Invention [Means for solving the problem]

[0019] According to one embodiment of the present invention, there is provided a memory structure including a plurality of memory cells formed on a planar surface of a semiconductor substrate having one or more voltage sources formed therein or on its surface and organized as a NOR string, each memory cell including a storage transistor having a channel region, a data storage region, a gate terminal, a first drain or source terminal, and a second drain or source terminal, the storage transistor having a variable threshold voltage indicative of a physical state of the data storage region, the memory structure including a word line connected to the gate terminal of one or more of the storage transistors and providing a control voltage during a read operation, and ... first drain or source terminal of each storage transistor. and a source line connected to the second drain or source terminal of each storage transistor; an insulating layer; and a conductor layer electrically connecting the channel region to one of the voltage sources in the semiconductor substrate to provide a bias voltage for the channel region, wherein the bit line and the source line each include a column of semiconductor material of a first conductivity type extending along a first direction that is substantially perpendicular to the planar surface, the insulating layer forming an isolation column between the bit line and the source line to electrically insulate the bit line and the source line from each other, and the conductor layer is made of semiconductor material of a second conductivity type opposite to the first conductivity type. In a row , extending along the first direction, the bit lines, the source lines, and the isolation columns The semiconductor row surroundingwherein the source line provides a capacitance sufficient to maintain at least a predetermined voltage difference between the second drain or source terminal and the gate terminal during a read operation, and the memory structure further comprises a precharge transistor for charging the capacitance to a predetermined voltage prior to the read operation. According to one embodiment of the present invention, there is provided a memory structure formed on a planar surface of a semiconductor substrate having one or more voltage sources formed therein or on the surface thereof, the memory structure comprising: (a) a plurality of word lines; (b) a plurality of source lines; (c) a plurality of bit lines, each bit line and each source line being a column of semiconductor material of a first conductivity type extending along a first direction that is substantially perpendicular to the planar surface; and (d) a plurality of insulating layers, each insulating layer adjacent one of the bit lines and one of the source lines. separation the insulating layer being a column and electrically insulating the adjacent bit lines and the adjacent source lines from each other; (e) a plurality of conductor layers, each conductor layer being made of a semiconductor material of a second conductivity type opposite to said first conductivity type; In a row , extending along the first direction and one of the isolation columns, the adjacent bit line, and the adjacent source line The semiconductorand (f) an array of NOR memory strings, each NOR memory string including a plurality of storage transistors, wherein (i) each storage transistor includes a channel region, a data storage region, a gate terminal, a first drain or source terminal, and a second drain or source terminal; (ii) each storage transistor has a variable threshold voltage indicative of a physical state of the data storage region; and (iii) each storage transistor is associated with (1) one of a word line connecting to a gate terminal for providing a control voltage during a read operation, (2) one of a bit line connecting the first drain or source terminal to a data detection circuit and one of a source line connected to the second drain or source terminal, and (3) one of the conductor layers electrically connecting the channel region to one of the voltage sources of the semiconductor substrate to provide a bias voltage for the channel region, the source line providing a capacitance sufficient to maintain at least a predetermined voltage difference between the second drain or source terminal and the gate terminal during a read operation; and the memory structure further comprises a precharge transistor for charging the capacitance to a predetermined voltage prior to the read operation. According to one embodiment of the present invention, a high-density memory structure called a three-dimensional vertical NOR flash memory string (a "multi-gate vertical NOR string" or simply a "vertical NOR string") is provided. A vertical NOR string includes multiple thin-film transistors ("TFTs") connected in parallel, each with a common source region and a common drain region extending generally vertically. Furthermore, the vertical NOR string includes multiple horizontal control gates that control each TFT in the vertical NOR string. When the TFTs in a vertical NOR string are connected in parallel, a read current in the vertical NOR string conducts with much less resistance than a read current through a NAND string with the same number of TFTs. To read or program any one TFT in the vertical NOR string, only that TFT needs to be activated; all other TFTs in the vertical NOR string can remain non-conductive. As a result, a vertical NOR string allows for faster sensing and can include many more TFTs (e.g., hundreds or more) while minimizing program disturb or read disturb conditions.

[0020] In one embodiment, the shared drain region of the vertical NOR strings is connected to a global bit line ("voltage V bl ”), and the shared source regions of the vertical NOR strings are connected to the global source line (“voltage V ss "). Alternatively, in a second embodiment, only the shared drain region is connected to a global bit line biased to a supply voltage, and the shared source region is precharged to a voltage determined by the amount of charge in the shared source region. To accomplish this, one or more dedicated TFTs can be provided to precharge the parasitic capacitance C of the shared source region.

[0021] According to one embodiment of the present invention, a multi-gate NOR flash thin-film transistor array ("multi-gate NOR string array") is organized as an array of vertical NOR strings extending perpendicular to the surface of a silicon substrate. Each multi-gate NOR string array includes a number of vertical active columns arranged in rows, each extending along a first horizontal direction. Each active column has two heavily doped vertical polysilicon regions of a first conductivity type separated by one or more vertical polysilicon regions that are undoped or lightly doped of a second conductivity type. The heavily doped regions each form a common source or drain region, and the lightly doped regions, together with a stack of one or more horizontal conductors, each perpendicular to the first horizontal direction, each form a plurality of channel regions. A charge trapping material forms storage elements overlying the channel regions of the TFTs in at least the active columns. The horizontal conductive lines in each stack are electrically insulated from one another and form control gates over the storage elements and channel regions of the active columns. In this manner, the multi-gate NOR string array forms a three-dimensional array of storage TFTs.

[0022] In one embodiment, support circuitry is formed in a semiconductor substrate to support the support circuitry and the plurality of multi-gate NOR string arrays formed on the semiconductor substrate. The support circuitry may include address encoders, address decoders, sense amplifiers, input / output drivers, shift registers, latches, compare cells, power lines, bias and reference voltage generators, inverters, NAND, NOR, exclusive-OR and other logic gates, other memory elements, sequencers, state machines, etc. The multi-gate NOR string arrays may be organized into multiple blocks of circuits having multiple multi-gate NOR string arrays.

[0023] According to embodiments of the present invention, variations in the threshold voltages of TFTs within a vertical NOR string can be compensated for by providing one or more electrically programmable reference vertical NOR strings within the same or another multi-gate vertical NOR string array. Background leakage current inherent in vertical NOR strings can be substantially neutralized during read operations by comparing the TFT results during read with those of a TFT simultaneously read in a programmable reference vertical NOR string. In some embodiments, each TFT in a vertical NOR string can amplify the capacitive coupling between each control gate and its corresponding channel region, thereby reducing charge injection from the control gate into the charge trapping material (i.e., the memory element) during erasure of the charge trapping material from the channel region. This advantageous capacitive coupling is particularly useful for storing more than one bit in each TFT in a vertical NOR string. In another embodiment, the charge trapping material in each TFT can have a modified structure to have a higher write / erase cycle endurance, but a lower retention time that requires refreshing of stored data. However, because a vertical NOR string array requires much less refresh than a conventional dynamic random access memory (DRAM), the multi-gate NOR string array of the present invention can also operate in some DRAM applications. The use of such vertical NOR strings allows for a substantially lower cost per bit to bit figure of merit compared to conventional DRAM, and significantly lower read latency compared to conventional NAND string arrays.

[0024] In another embodiment, the vertical NOR strings can be programmed, erased and read as NROM / mirror bit TFT strings.

[0025] Configuring the TFTs as vertical NOR strings rather than conventional vertical NAND strings offers the following benefits: (i) low read latency that approaches the latency of dynamic random access memory (DRAM) arrays, (ii) reduced susceptibility to read disturb and program disturb conditions associated with long NAND flash strings, and (iii) a lower cost per bit compared to NAND flash strings.

[0026] The present invention will be better understood from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0027] [Figure 1A] FIG. 1A is a diagram illustrating three-dimensional vertical NAND strings 101 and 102 in the prior art. [Figure 1B] FIG. 1B shows a basic circuit representation 140 of a three-dimensional vertical NAND string in the prior art. [Figure 1C] FIG. 1C is a diagram illustrating a three-dimensional representation of a block of three-dimensional vertical NAND strings addressed by wrap-around stacked word lines (150 in this diagram). [Figure 2] FIG. 2 is a diagram illustrating a conceptualized memory structure 100 showing a three-dimensional arrangement of memory cells according to one embodiment of the present invention, arranged in vertical NOR strings, each having memory cells controlled by one of a number of horizontal word lines. [Figure 3A] FIG. 3A shows a basic circuit representation in the ZY plane of a vertical NOR string 300 formed in an active column, where the vertical NOR string 300 represents a three-dimensional array of non-volatile storage TFTs, where each TFT sharing a local source line (LSL) 355 and a local bit line (LBL) 354 is accessed by a global bit line (GBL) 314 and a global source line (GSL) 313, respectively, according to one embodiment of the present invention. [Figure 3B] FIG. 3B shows a basic circuit representation in the ZY plane of a vertical NOR string 305 formed in an active column, which represents a three-dimensional array of non-volatile storage TFTs and includes a dedicated pre-charge TFT 370 for setting the voltage (“Vss”) on a shared local source line 355 with a parasitic capacitor C, according to one embodiment of the present invention. [Figure 3C] FIG. 3C shows a basic circuit representation of a dynamic non-volatile storage transistor 317 having one or more programmed threshold voltages and connected to a parasitic capacitor 360, which is precharged to temporarily hold a virtual voltage Vss at its source terminal (source line) 355, allowing the threshold voltage of transistor 317 to be dynamically sensed by discharging voltage Vss when the voltage at control gate 323p rises above the threshold voltage. [Figure 4A] FIG. 4A is a cross-sectional view in the ZY plane of one embodiment of the present invention, where each column may form a vertical NOR string having the basic circuit representation shown in either FIG. 3A or FIG. 3B. [Figure 4B] FIG. 4B is a cross-sectional view in the ZX plane of one embodiment of the present invention, showing active columns 430R, 430L, 431R and 431L, charge trapping layers 432 and 434, and word lines 423p-L and 423p-R. [Figure 4C] FIG. 4C is a diagram showing a basic circuit representation in the ZX plane of a pair of vertical NOR strings 491 and 492 according to one embodiment of the present invention. [Figure 5] FIG. 5 is a cross-sectional view in the ZY plane of one embodiment of the present invention, showing connections between the vertical NOR strings of active column 531, global bit line 514-1 (GBL1), global source line 507 (GSL1), and common body bias source 506 (Vbb). [Figure 6A]6A is a cross-sectional view in the XY plane of one embodiment of the present invention, showing the TFT 685(TL) of vertical NOR string 451a and the TFT 684(TR) of vertical NOR string 451b of vertical NOR string pair 491, as described in connection with FIG. 4C, in which global bit line 614-1 accesses every other local bit line LBL-1, and the predetermined curvature 675 of transistor channel region 656L amplifies the capacitive coupling between each control gate and the corresponding channel during programming. [Figure 6B] 6B is a cross-sectional view in the XY plane of one embodiment of the present invention, showing TFT 685 (TL) of vertical NOR string 451a sharing an active area with TFT 684 (TR) of vertical NOR string 451b of vertical NOR string pair 491, as described in connection with FIG. 4C. In FIG. 6B, global bit line 614-1 accesses every other (odd) bit of local bit line 654 (LBL-1), global bit line 614-2 addresses every other (even) bit of local bit line 657-2 (LBL-2), and local source lines LSL-1 and LSL-2 are precharged to supply the virtual power supply voltage Vss. [Figure 6C] FIG. 6C is a cross-sectional view in the XY plane of one embodiment of the present invention, showing dedicated word line stacks 623p each including a group of word lines, local vertical pillar bit lines 654 (extending along the Z direction) and local vertical pillar source lines 655 (extending along the Z direction), where each word line of the word line group in each word line stack extends to enclose (“wrap around”) the TFTs of the vertical NOR strings, and the local vertical pillar bit lines 654 and local vertical pillar source lines 655 are accessed by global horizontal bit lines 614 and global horizontal source lines 615, respectively; and in FIG. 6C, adjacent word line stacks 623p are insulated from each other by air gaps 610 or other dielectric isolation. [Figure 6D]FIG. 6D is a cross-sectional view in the XY plane of one embodiment of the present invention, showing closely staggered vertical NOR strings, similar to those shown in FIG. 6C, sharing word line stacks 623p and each pre-charged parasitic capacitor 660 providing a pre-charged virtual supply voltage Vss. [Figure 7A] FIG. 7A is a cross-sectional view of an intermediate structure formed in the fabrication process of a multi-gate NOR string array, according to one embodiment of the present invention. [Figure 7B] FIG. 7B is a cross-sectional view of an intermediate structure formed in the fabrication process of a multi-gate NOR string array, according to one embodiment of the present invention. [Figure 7C] FIG. 7C is a cross-sectional view of an intermediate structure formed in the fabrication process of a multi-gate NOR string array according to one embodiment of the present invention. [Figure 7D] FIG. 7D is a cross-sectional view of an intermediate structure formed in the fabrication process of a multi-gate NOR string array according to one embodiment of the present invention. [Figure 8A] FIG. 8A is a schematic diagram of a read operation of one embodiment of the present invention, where the local source lines (LSLs) of the vertical NOR strings are hardwired, and in FIG. 8A, "WLs" represents the voltage on the selected word line, and all unselected word lines ("WLNS") in the vertical NOR strings are set to 0V during the read operation. [Figure 8B] FIG. 8B is a schematic diagram of a read operation for an embodiment in which the local source line is floated at a precharge virtual voltage Vss, where "WLCHG" represents the gate voltage on a precharged transistor (e.g., precharged transistor 317 or 370 in FIG. 3C). DETAILED DESCRIPTION OF THE INVENTION

[0028] FIG. 2 illustrates a conceptualized memory structure 100 showing a three-dimensional arrangement of memory cells (or storage elements) arranged in vertical NOR strings. In the conceptualized memory structure 100, according to one embodiment of the present invention, each vertical NOR string includes a memory cell, each controlled by a corresponding horizontal word line. The substrate layer (101 in FIG. 2) may be, for example, a conventional silicon wafer used to manufacture integrated circuits, as is well known to those skilled in the art. In this detailed description, a Cartesian coordinate system (as shown in FIG. 2) is employed solely for ease of discussion. Under this coordinate system, the surface of the substrate layer (101 in FIG. 2) is considered a plane parallel to the XY plane. Therefore, as used herein, the term "horizontal" refers to any direction parallel to the XY plane, and "vertical" refers to the Z direction.

[0029] In FIG. 2 , each vertical column in the Z direction represents a storage element or TFT in a vertical NOR string (e.g., vertical NOR string 121). The vertical NOR strings are regularly arranged as rows aligned in the X direction. (Of course, a similar arrangement is also found for rows aligned in the Y direction.) The storage elements of a vertical NOR string share vertical local source lines and vertical local bit lines (not shown). A stack of horizontal word lines (e.g., WL 123) extends along the Y direction, with each word line serving as a control gate for the corresponding TFT in the vertical NOR string adjacent to the word line along the Y direction. Global source lines (e.g., GSL 122) and global bit lines (e.g., GBL 124) are generally provided extending along the X direction either below the bottom or above the top of the conceptualized memory structure 100. Alternatively, both signal lines GSL 122 and GBL 124 may be routed below or above the conceptualized memory structure 100, each of which may be selectively connected to the local source and bit lines of individual vertical NOR strings by access transistors (not shown). Unlike prior art vertical NAND strings, in the vertical NOR string of the present invention, writing to or reading from any one of its storage elements does not activate other storage elements in the vertical NOR string. As shown in FIG. 2, for illustrative purposes only, the conceptualized memory block (memory structure) 100 is a multi-gate vertical NOR string array consisting of a 4×5 array of vertical NOR strings, each NOR string typically having 32 or more storage elements and access select transistors. As a conceptual structure, the memory block (memory structure) 100 is merely an abstraction of certain salient features of the memory structure of the present invention. Although FIG. 2 shows a 4×5 configuration of vertical NOR strings, with each vertical NOR string having multiple storage elements, the memory structure of the present invention can have any number of vertical NOR strings in each row along either the X or Y direction, and any number of storage elements in each vertical NOR string.For example, there may be thousands of vertical NOR strings arranged in columns along both the X and Y directions, with each NOR string having, for example, 2, 4, 8, 16, 32, 64, 128 or more storage elements.

[0030] The number of storage elements in each vertical NOR string (e.g., vertical NOR string 121) in FIG. 2 corresponds to the number of word lines (e.g., WL123) that provide control gates to the vertical NOR string. The word lines are formed as elongated metal strips extending along the Y direction. The word lines are stacked on top of each other and electrically insulated from each other by dielectric insulating layers between them. The number of word lines in each stack can be any number but is preferably an integer power of 2 (i.e., 2n, where n is an integer). The selection of a power of 2 for the number of word lines follows conventional memory design practice. It is conventional to access each addressable memory unit by decoding a binary address. Whether or not to adopt this conventional practice is a matter of preference and need not be followed. For example, within the scope of the present invention, the conceptualized memory structure 100 can have M vertical NOR strings along each row in the X and Y directions, a number that is not necessarily a power of 2n, where n is any integer. In some embodiments described below, two vertical NOR strings can share a vertical local source line and a vertical local bit line, but the storage elements of each of the two vertical NOR strings are controlled by two separate word line stacks, which effectively doubles the storage density of the vertical NOR strings.

[0031] The conceptualized memory structure 100 of FIG. 2 is not drawn to any particular scale in any of the X, Y, or Z directions, as it is provided solely to illustrate the organization of memory cells.

[0032] FIG. 3A shows a basic circuit representation in the ZY plane of a vertical NOR string 300 formed in an active column. The vertical NOR string 300 represents a three-dimensional array of nonvolatile storage TFTs, each of which shares a local source line 355 and a local bit line 354, according to one embodiment of the present invention. In this detailed description, the terms “active area,” “active column,” or “active strip” refer to a region, column, or strip of one or more semiconductor materials on which an active device (e.g., a transistor or diode) may reside. As shown in FIG. 3A , the vertical NOR string 300 extends along the Z direction and includes TFTs 316 and 317 connected in parallel between a vertical local source line 355 and a vertical local drain or bit line 354. The bit line 354 and source line 355 are spaced apart, and the region between them (i.e., body region 356) provides the channel region of the TFTs in the vertical NOR string. A storage element is formed at the intersection of the channel region (in the body region 356) and each horizontal word line 323p, where p is the index of the word line in the word line stack, and in this example, p can be any value from 0 to 31. The word lines run along the Y direction. The local bit lines 354 are connected through bit line access select transistors 311 to horizontal global bit lines (GBLs) 314, which run along the X direction and connect the local bit lines 354 to an access bit line supply voltage V b1 The local source line 355 is connected to the source power supply voltage V through the horizontal global source line (GSL) 313. ss . An optional source select transistor (not shown in FIG. 3A ) can be provided to connect between local source line 355 and GSL 313. The optional source select transistor can be controlled by source decode circuitry, which can be implemented in the substrate (e.g., semiconductor substrate 101 of FIG. 2 ) or above the substrate and below memory structure 100, as known to those skilled in the art. The body region 356 of the active column is coupled to a substrate bias voltage V at terminal 331. bb The substrate bias voltage V bbcan be used, for example, during an erase operation. bb The supply voltage can be applied to the entire array of multi-gate vertical NOR strings, or can be decoded to selectively apply to one or more rows of vertical NOR strings. bb The lines connecting the power supply voltage to the body region 356 preferably run along the direction of the word lines.

[0033] FIG. 3b shows a basic circuit representation in the ZY plane of vertical NOR strings 305 formed in an active column, which represent a three-dimensional array of non-volatile storage TFTs that are coupled to a voltage ("V") on a shared local source line 355. ss "), and the shared local source line 355 has a parasitic capacitance (represented by capacitor 360) according to one embodiment of the present invention. Unlike the vertical NOR string 300 of FIG. 3A, the vertical NOR string 305 does not implement a GSL 313 and temporarily ss In this example, the GSL is replaced by a precharge transistor 370 that precharges a parasitic capacitor 360 that holds a voltage of 100 volts. Under this precharge scheme, the global source line (e.g., global source line 313 in FIG. 3A) and its decode circuitry are unnecessary, thereby simplifying both the manufacturing process and circuit layout and providing a very tight footprint for each vertical NOR string. FIG. 3C highlights the structure of a non-volatile storage TFT 317 that can be used to perform the precharge function of a dedicated precharge transistor 370 in addition to its normal storage function. A dynamic read operation for the TFT 317 will be described later in connection with sensing the correct one of several threshold voltages to be programmed into the storage element 334 of the TFT 317.

[0034] 4A is a cross-sectional view in the ZY plane showing parallel active columns 431 and 432, each of which can form a vertical NOR string having the basic circuit representation shown in either FIG. 3A or FIG. 3B, according to one embodiment of the present invention. As shown in FIG. 4A, active columns 431 and 432 each include a vertical N+ doped local source region 455 and a vertical N+ doped local drain or bit line region 454 separated by a lightly P doped or undoped channel region 456. The P doped channel region 456, the N+ doped local source region 455, and the N+ doped local drain or bit line region 454 are coupled to a body bias voltage V bb , source supply voltage V ss , and the bit line voltage V bl In some embodiments of the present invention, such as when the active strips are sufficiently thin (e.g., 10 nm or less), the body bias voltage V bb The use of is optional. For sufficiently thin active strips, the voltage V bb The active regions are easily fully depleted under an appropriate voltage on the control gates so that they do not provide a solid supply voltage to the channel regions of the TFTs along the vertical NOR strings. The isolation region 436, which electrically isolates the active regions 431 and 432, can be either a dielectric insulator or an air gap. WL0-WL31 (and optionally WL CHGA vertical stack of word lines 423p, each labeled Y, provides control gates to the TFTs in the vertical NOR strings formed in active columns 431 and 432. The word line stacks 423p are typically formed as elongated metal conductors (e.g., tungsten, silicide, or silicide) extending along the Y direction that are electrically insulated from one another by a dielectric layer 426 formed of silicon oxide (e.g., SiO2) or an air gap. By providing a charge trapping material (not shown) between the word lines 423p and the P-doped channel regions 456, a non-volatile storage element can be formed at the intersection of each word line 423p and each P-doped channel region 456. For example, FIG. 4A illustrates, by dashed box 416, non-volatile storage elements (or storage transistors) T0 through T1. 31 The dashed box 470 indicates where a dedicated precharge transistor can be formed, and all transistors T0 to T 31 is in the off state, allowing charge to be transferred from the common local bit line region 454 to the common local source line region 455.

[0035] 4B is a cross-sectional view in the ZX plane showing active columns 430R, 430L, 431R, and 431L, charge trapping layers 432 and 434, and word line stacks 423p-L and 423p-R, according to one embodiment of the present invention. Similar to FIG. 4A, each of the vertical word line stacks 423p-L and 423p-R in FIG. 4B represents a stack of thin conductors, where p represents the number of word lines (e.g., word lines WL0-WL1) in the stack. 31) are indices labeling the vertical NOR strings formed on adjacent active columns 430L and 431R (in region 490) on the opposite side of the word line, as shown in FIG. 4B. For example, in FIG. 4B, word line WL31 in word line stack 423p-R serves as the control gate for both transistor 416L on active column 430L and transistor 416R on active column 431R. Adjacent word line stacks (e.g., word line stacks 423p-L and 423p-R) are separated by a distance 495, which is the width of trenches formed by etching successive word line layers, as described below. Active columns 430R and 430L and their respective charge trapping layers 432 and 434 are subsequently formed inside the trenches etched through the word line layers. Charge trapping layer 434 is disposed between word line stack 423p-R and vertical active columns 431R and 430L. As will be described in more detail below, during programming of transistor 416R, charge injected into charge trapping layer 434 is trapped in the portion of charge trapping layer 434 within dashed box 480. The trapped charge can be detected by shifting the threshold voltage of TFT 416R and measuring a read current flowing between local source region 455 and local drain region 454 on active column 431R (these regions are shown, for example, in an orthogonal cross section of the active column in FIG. 4A). In some embodiments, precharge word line 478 (i.e., WL CHG ) is provided as the control gate of a precharge TFT 470 used to charge the parasitic capacitance C of the local source line 455 (see capacitor 360 in FIG. 3B and local source line 455 in FIG. 4A) connected to ground or the source supply voltage V ss For convenience, the charge trapping layer 434 also provides a storage element for the precharge transistor 470, but is not itself used as a memory transistor. 31Precharging may be accomplished using either one of the memory transistors. One or more of these memory transistors may perform the function of a precharge transistor in addition to their storage function. To accomplish precharging, the voltage on the word line or control gate is temporarily raised a few volts above the highest programmable threshold voltage, and a voltage V applied to the local bit line 454 is applied. ss can be transferred to the local source line 455 (FIG. 4A). 31 By performing the precharge function, the need for a separate dedicated precharge TFT 470 is eliminated, however, care must be taken not to unduly disturb the threshold voltage of such a memory TFT when performing the precharge function.

[0036] Although active columns 430R and 430L are shown in FIG. 4B as two separate active columns separated by an air gap or dielectric isolation 433, adjacent vertical N+ local source lines may be implemented by a single shared vertical local source line. Similarly, the vertical N+ local drain, or bit line, may be implemented by a single shared vertical local bit line. Such a configuration provides a "vertical NOR string pair." In this configuration, active columns 430L and 430R can be considered two branches (hence, a "pair") within a single active column. The vertical NOR string pair provides dual-density storage via charge trapping layers 432 and 434 interposed between active columns 430R and 430L and opposing word line stacks 423p-L and 423p-R. In practice, active columns 430R and 430L may be combined into one active string by removing the air gap or dielectric insulator 433, forming a pair of NOR TFT strings implemented on two opposing sides of a single active column. Such a configuration achieves similar double-density storage because the TFTs formed on opposite sides of the active column are controlled by separate word line stacks and formed from separate charge trapping layers 434 and 432. Maintaining the separate, thin active columns 430R and 430L (i.e., maintaining them separate instead of merging them into a single active column) is advantageous because the TFTs in each active column are thinner than the merged columns and therefore can be more easily fully depleted under appropriate control gate voltage conditions, substantially reducing source-drain subthreshold leakage current between the vertical source region 455 and vertical drain region 454 of the active column (FIG. 4A).Even very long vertical NOR strings (e.g., 128 TFTs or more) can have ultra-thin (and therefore highly resistive) active columns because the TFTs in a vertical NOR string are connected in parallel, and because the TFTs in a string are connected in series, only one of many TFTs is switched on at a time, as opposed to the high resistance of a NAND-type TFT string, which must all be switched on to sense any of the TFTs in the string. For example, in a 32-TFT vertical NOR string, transistors T 30 To be able to read (FIG. 4A), the channel region 456 needs to have a channel length of only 20 nm, which is short compared to the corresponding channel length of a NAND string (which has a length 32 times longer, or 640 nm).

[0037] FIG. 4C shows a basic circuit representation in the ZX plane of vertical NOR string pair 491 and 492 according to one embodiment of the present invention. As shown in FIG. 4C, vertical NOR strings 451b and 452a share a common word line stack 423p-R in the manner shown for the vertical NOR strings of active strips 430L and 431R in FIG. 4B. For their commonly connected local bit lines, vertical NOR string pair 491 and 492 use global bit line 414-1 (GBL1) via access select transistor 411 and global bit line 414-2 (GBL2) via access select transistor 414, respectively. For their commonly connected local source lines, vertical NOR string pair 491 and 492 use global source line 413-1 (GSL1) and global source line 413-2 (GSL2), respectively (access select transistors for source line selection are also provided but are not shown in FIG. 4C). As shown in FIG. 4C, vertical NOR string pair 491 includes vertical NOR strings 451a and 451b that share a local source line 455, a local bit line 454, and an optional body connection 456. Vertical NOR string pair 491 thus represents vertical NOR strings formed on active columns 430R and 430L of FIG. 4B. Word line stacks 423p-L and 423p-R (in this example, 31≧p≧0) provide the control gates for vertical NOR string 451a and vertical NOR string 451b, respectively. The word lines controlling the gates in the stacks are decoded by decoding circuitry formed in the substrate to ensure that the appropriate voltages are applied to the addressed TFTs (i.e., the activated word line) and unaddressed TFTs (i.e., all other inactive word lines in the string). FIG. 4C shows how the same word line stacks 423p-R are used for storage transistors 416L and 416R on active columns 430L and 431R of FIG. 4B.Thus, vertical NOR string 451b of vertical NOR string pair 491 and vertical NOR string 452a of vertical string pair 492 correspond to adjacent vertical NOR strings formed on active columns 430L and 431R in Figure 4B. Word line stacks 423p-L are used for storage transistors (e.g., storage transistor 415R) of vertical NOR string 451a.

[0038] 4C are eliminated and replaced by a parasitic capacitor C between a shared N+ local source line 455 (common to both vertical NOR strings 451a and 451b) and its multiple associated word lines 423p-L and 423p-R. In a vertical stack of 32 TFTs, each of the 32 word lines contributes a parasitic capacitor to provide a total parasitic capacitance C, which temporarily holds the voltage provided by the pre-charge TFT 470 to generate a virtual source voltage V ss This occurs during the relatively short duration of a read or programming operation. In this embodiment, the virtual source voltage temporarily held on capacitor C is supplied from global bit line GBL1 to local source line 455 via access transistor 411 and precharge transistor 470. Alternatively, the dedicated precharge transistor 470 can be omitted if, in addition to their storage function, one or more of the memory TFTs in the vertical NOR string are used to precharge the local source line 455 by momentarily raising the word line voltage above the highest programmed voltage. However, if a storage TFT is used for this purpose, care must be taken to avoid over-programming of the storage TFT. The virtual V ss The use of voltages provides the important advantage of eliminating hardwired global source lines (e.g., GLS1, GLS2) and their associated decoding circuitry and access transistors, thereby substantially simplifying the process flow and design challenges and enabling significantly more compact vertical NOR strings.

[0039] FIG. 5 illustrates a global NOR bit line 514-1 (GBL1), a global source line 507 (GSL1), and a common body bias source 506 (VBL1) of an active column 531, according to one embodiment of the present invention. bb 5, a bit line access select transistor 511 connects GBL1 to a local bit line 554, and a buried contact 556 connects the P body region on the active strip to a body bias source 506 (V bb) are optionally connected to the bit line access select transistors 511. The bit line access select transistors 511 are formed above the active columns 531 in FIG. 5. However, alternatively, the bit line access select transistors 511 may be formed at the bottom of the active columns 531 or in the substrate 505 (not shown in FIG. 5). In FIG. 5, the bit line access select transistors 511 may be formed, for example, in separate islands of N+ / P- / N+ doped polysilicon stacks along with the access select word line 585. When a sufficiently large voltage is applied to select the word line 585, the P channel is inverted, thereby connecting the local bit line 554 to GBL1. The word line 585 runs along the same direction (i.e., the Y direction) as the word line 523p, which serves as the control gate to the TFTs of the vertical NOR string. The word line 585 may be formed separately from the word line 523p. In one embodiment, GBL1 runs horizontally along the X-direction (i.e., perpendicular to the word line direction), and bit line access select transistor 511 provides access to local bit line 554, which is just one local bit line for many vertical NOR strings served by GBL1. To increase the efficiency of read and program operations, in a multi-gate NOR string array, thousands of global bit lines can be used to access in parallel the local bit lines of thousands of vertical NOR strings accessed by word line 585. In FIG. 5, local source line 555 is connected to global source line 513-1 (GSL1) via contact 557 and can be decoded, for example, by decoding circuitry in substrate 505. Alternatively, as previously described, the global source line can couple a virtual source voltage V ss and temporarily pre-charge the parasitic capacitor 560 (ie, the parasitic capacitor C) of the local source line 555 via the TFT 570.

[0040] The support circuits formed on the substrate 505 include address encoders, address decoders, sense amplifiers, input / output drivers, shift registers, latches, compare cells, power lines, bias and reference voltage generators, inverters, NAND, NOR, exclusive-OR and other logic gates, other memory elements, sequencers, state machines, etc. The multi-gate NOR string array can be organized as multiple blocks of circuits having multiple multi-gate NOR string arrays.

[0041] 6A illustrates the TFT 685 (TFT) of the vertical NOR string 451a of the vertical NOR string pair 491, as described above in connection with FIG. 4C. L ) and TFT684 (T R ) is a cross-sectional view in the XY plane. 6, TFTs 684 and 685 share an N+ local source region 655 and an N+ local drain or bit line region 654, both of which extend as elongated pillars along the Z direction. (The N+ local source region 655 corresponds to the local source line 455 in FIG. 4A, and the N+ local drain region 654 corresponds to the local bit line 454 in FIG. 4A.) In this embodiment, P-doped channel regions 656L and 656R form a pair of active strings between the local source pillar 655 and the local drain pillar 654, which are separated from each other by an isolation region 640 and extend along the Z direction. A charge trapping layer 634 is formed between the word lines 623p-L (WL31-0) and 623p-R (WL31-1) and the outside of the channel regions 656L and 656R. The charge trapping layer 634 can be, for example, a thin film of tunnel dielectric (e.g., silicon dioxide) followed by a thin layer of charge trapping material such as silicon nitride or conductive nanodots embedded in a non-conductive dielectric material, or the gate dielectric material of a transistor consisting of an isolated floating gate, capped with a layer of blocking dielectric such as ONO (Oxide-Nitride-Oxide) or a high-k film such as aluminum oxide or hafnium oxide, or a combination of such dielectrics. The source-drain conductors are controlled by word lines 623p-L and 623p-R, respectively, forming a control gate outside the charge trapping layer 634. The TFT 684 (T R ) by maintaining an appropriate inhibit voltage on word line 623p-L. L ) is turned off. Similarly, L ) by maintaining an appropriate inhibit voltage on word line 623p-R. R ) off.

[0042] In the embodiment shown in FIG. 6A , the word lines 623p-L and 623p-R are contoured to reduce reverse tunneling efficiency during erasure and increase tunneling efficiency into the TFTs 684 and 685 during programming. Specifically, as known to those skilled in the art, the curvature 675 of the channel region 656R amplifies the electric field at the interface between the polysilicon of the active channel and the tunnel dielectric during programming and reduces the electric field at the interface between the word line and the blocking dielectric during erasure. This feature is particularly useful for storing more than one bit per TFT transistor in a multilevel cell (MLC) configuration. Using this technique, two, three, four, or more bits can be stored in each TFT. In fact, the TFTs 684 and 685 can be used as analog storage TFTs with a continuum of memory states. After a programming sequence (described below), electrons are trapped in the charge trapping layer 634, as indicated schematically by the dashed line 680. In Figure 6A, global bit lines 614-1 and 614-2 extend perpendicular to word lines 623p-R and 623p-L and are located either above or below the vertical NOR strings corresponding to bit lines 414-1 and 414-4 in Figure 4C. As discussed above in connection with Figure 2, the word lines extend the entire length of memory block (memory structure) 100 along the X direction, and the global bit lines extend the width of memory block (memory structure) 100 along the Y direction. Importantly, in Figure 6A, word line 623p-R is shared by TFTs 684 and 683 of the two vertical NOR strings on opposite sides of word line 623p-R. Thus, global bit line 614-1 (GBL1) contacts local drain or bit line region 657-1 ("odd address"), and global bit line 614-2 (GBL2) contacts local drain or bit line region 657-2 ("even address") to allow TFTs 684 and 683 to be read or programmed independently.To achieve this effect, the contacts along global bit lines 614-1 and 614-2 are staggered so that each global bit line contacts every other pair of vertical NOR strings along an X-direction row.

[0043] Similarly, global source lines (not shown in FIG. 6A) located at the bottom or top of the multi-gate NOR string array may run parallel to the global bit lines and contact the local source lines of vertical NOR string pairs at even or odd addresses. Alternatively, the transient virtual supply voltage V of the parasitic capacitor C (i.e., capacitor 660) ss If precharging to is used, there is no need to provide a global source line, simplifying the decoding scheme and process complexity.

[0044] FIG. 6A shows only one of several possible embodiments in which vertical NOR string pairs are provided with stacked word lines. For example, the curvature 675 of channel region 656R can be made even more curvature. Conversely, such curvature can be completely eliminated (i.e., straightened) as shown in the embodiment of FIG. 6B. In the embodiment of FIG. 6B, the spacing of isolation region 640 of FIG. 6A is reduced or completely eliminated by merging channel regions 656L and 656R into a single region 656(L+R), allowing for a dual-channel configuration (e.g., TFT 685(T L ) and 684(T R) are on opposite sides of the same active strip. Greater area efficiency can be achieved without sacrificing the area efficiency. In the embodiment of FIGS. 6A and 6B, the vertical NOR strings that share a word line are staggered relative to each other (not shown), but they can be placed closer to each other to reduce the effective footprint of each vertical NOR string. While FIGS. 6A and 6B show a direct connection between the global bit line 614-1 and the N+ doped local drain bit line pillar 654 (LBL-1) via a contact, such a connection can also be achieved using a bit line access select transistor (e.g., bit line access select transistor 511 of FIG. 5, not shown in FIGS. 6A and 6B).

[0045] In the embodiment of Figures 6A and 6B, dielectric isolation between the N+ doped local drain region 654 and the adjacent local N+ doped source region 658 (corresponding to isolation region 436 in Figure 4A) can also be established, for example, by defining word lines 623p-R and 623p-L to be smaller than the thickness of two back-to-back charge trapping layers so that the charge trapping layers merge with them during the deposition process. The resulting merger of the deposited charge trapping layers forms the desired dielectric isolation. Alternatively, isolation between adjacent active strings can be achieved by using a high aspect ratio etch of N+ polysilicon to create a gap 676 (air gap or dielectric fill) that separates the N+ pillar 658 of one string from the N+ pillar 654 of the adjacent string (i.e., creating the gap (isolation region 436) shown in Figure 4A).

[0046] A contrast between prior art vertical NAND strings and the vertical NOR strings of the present invention is that both types of devices use thin film transistors with control gates and similar word line stacks, but the transistors are oriented differently. In prior art NAND strings, each vertical active strip may have 32, 48, or more TFTs connected in series. In contrast, each active column forming a vertical NOR string of the present invention may have one or two sets of multiple (32, 48, or more) TFTs connected in parallel. In prior art NAND strings, the word lines in some embodiments typically extend to encircle (or "wrap around") the active strips. In some embodiments of the vertical NOR strings of the present invention, individually designated left and right word lines are used for each active strip, thereby achieving doubled (i.e., paired) storage density for each global bit line, as shown in Figures 4C, 6A, and 6B. The vertical NOR strings of the present invention do not suffer from program disturb or read disturb problems or the slow latency of prior art NAND strings. Therefore, a vertical NOR string can have a larger number of TFTs than a vertical NAND string, but the vertical NOR string is more susceptible to low threshold voltage or other leakage between the long vertical source and drain diffusions (e.g., local source region 455 and local drain region 454 shown in FIG. 4A).

[0047] Two additional embodiments of the vertical NOR string of the present invention are shown in Figures 6C and 6D, in which all word lines in each word line stack wrap around the vertical active strip.

[0048] In FIG. 6C, a vertical NOR string is formed within a cavity formed by etching a stack of metal word lines and a dielectric isolation layer between the word lines. The fabrication process flow is similar to that of a prior art vertical NAND string, except that the transistors in the vertical NOR string are provided in parallel with each other rather than in series as in a vertical NAND string. The transistors in the vertical NOR string are formed by an N+ doped vertical pillar with an undoped or lightly doped channel region 656 that extends the entire depth of the cavity, providing a shared local source line 655 (LSL) and a shared local bit line 654 (drain) (LBL) for all TFTs along the vertical NOR string. Charge trapping regions 634, which provide charge storage elements, are located between the channel 656 and the word line stack 623p and are configured to trap charge along the vertical active strips of 2, 4, 8, 32, 64, or more TFTs (e.g., device 685 (T 10 6C , the word line stacks 623p extend in the Y direction, with individual horizontal strips (WL31-0), (WL31-1) separated from one another by dielectric isolation or air gaps 610. Global bit lines 614 (GBL) and global source lines 615 (GSL) extend horizontally in the row direction along the X direction perpendicular to the word lines. Each of the global bit lines 614 accesses a local bit line pillar 654 (LBL) along the row of vertical strips via an access select transistor (511 in FIG. 5, not shown here), which may be located either below or above the memory array. Similarly, each global source line 615 accesses a local source line pillar along that row. The structures shown in Figures 6A and 6B allow a pair of vertical NOR strings to fit into approximately the same area occupied by a single vertical NOR string in the embodiment of Figure 6C, and each TFT in each vertical NOR string shown in Figure 6C has two parallel conductive channels (i.e., channel regions 656a and 656b), and therefore can store more charge and increase or double the read current.

[0049] 6D illustrates a more compact vertical NOR string with wrap-around word lines according to one embodiment of the present invention. As shown in FIG. 6D, the vertical NOR strings are closely staggered, allowing word line stack 623p (WL31-0) to be shared by more vertical NOR strings. This staggering is made possible by the use of the parasitic capacitance C (i.e., capacitor 660) of local source line pillar 655 (LSL). As explained below, during read and program operations, a virtual voltage V ss By precharging capacitor 660 to temporarily hold the GND, a hardwired global source line (e.g., GSL 615 in FIG. 6c) is not required. While the vertical NOR strings of FIGS. 6C and 6D may not be significantly more area-efficient than prior art vertical NAND strings (e.g., the NAND strings of FIG. 1C), such vertical NOR strings are significantly longer than vertical NAND strings. For example, the vertical NOR strings of the present invention are fully capable of supporting strings of 128 to 512 or more TFTs in length within each stack. Such string lengths are not practical for vertical NAND strings given the significant limitations associated with series-connected TFT strings.

[0050] [Manufacturing process] 7A, 7B, 7C, and 7D are cross-sectional views of intermediate structures formed in the fabrication process of a multi-gate NOR string array, according to one embodiment of the present invention.

[0051] FIG. 7A illustrates a cross-sectional view in the ZY plane of semiconductor structure 700 after low-resistivity layers 723p have been formed on substrate 701, according to one embodiment of the present invention. In this example, p is an integer between 0 and 31, representing each of the 32 word lines. As shown in FIG. 7A, semiconductor structure 700 includes low-resistivity layers 723-0 through 723-31. Semiconductor substrate 701 may represent, for example, a P-doped bulk silicon wafer in which support circuitry for memory structure 700 is formed, prior to forming vertical NOR strings. Such support circuitry may include both analog and digital logic circuits. Some examples of such support circuitry may include shift registers, latches, sense amplifiers, comparison cells, power lines, bias and reference voltage generators, inverters, NAND, NOR, exclusive-OR, and other logic gates, input / output drivers, address decoders including bit line and word line decoders, other memory elements, sequencers, and state machines. To provide these support circuits, conventional N-well, P-well, triple-well (not shown), and N-well (not shown) structures may be used, as known to those skilled in the art. + Diffusion regions (e.g., region 707-0) and P + Diffusion regions (eg, region 706), low and high voltage transistors, capacitors, resistors, diodes, and interconnects are provided.

[0052] After the support circuitry is formed in and on the semiconductor substrate 701, an insulating layer 708 is provided, which may be, for example, a thick silicon dioxide layer deposited or grown. In some embodiments, one or more metal interconnect layers, including a global source line 713-0, may be formed, which may be provided as horizontal, narrow strips extending along a predetermined direction. The global source line 713-0 is connected to the circuitry 707 in the substrate 701 through an etched opening 714. For ease of explanation, the following description assumes that the global source line extends along the X direction. The metal interconnect lines may be formed by applying photolithographic patterning and etching to one or more deposited metal layers. (Alternatively, these metal interconnect lines may be formed using a conventional damascene wiring process, such as a conventional copper or tungsten damascene wiring process.) A thick dielectric layer 709 is then deposited, followed by planarization using conventional chemical-mechanical polishing (CMP).

[0053] Conductor layers 723-0 through 723-31 are formed in succession, with each conductor layer being isolated from the layers below and above it by intervening insulating layers 726. While 32 conductor layers are shown in FIG. 7A, any number of such layers may be provided. In practice, the number of conductor layers that can be provided depends on the process technology, such as the availability of a well-controlled anisotropic etching process that allows for cutting through multiple conductor layers and the dielectric isolation layers 726 between them. For example, conductor layer 723p may be formed by first depositing a 1-2 nm thick layer of titanium nitride (TiN), followed by a 10-50 nm thick layer of tungsten (W) or a similar refractory metal or silicide (such as nickel, cobalt, or tungsten silicide, or salicide, among others), followed by a thin layer of an etch-stop material such as aluminum oxide (Al2O3). Each conductor layer is either deposited and etched in block 700 or deposited as a block using a conventional damascene wiring process. In the embodiment shown in FIG. 7A, each successive conductor layer 723p extends (i.e., recessed) in the Y direction a distance (recessed by recess 727) that does not touch the edge of the previous metal layer, and all conductor layers are formed so that they are accessible from the top of structure 700 at later stages of the process. However, to reduce the number of masking and etching steps required to form the stepped conductor stack of FIG. 7A, it is possible to simultaneously form recessed surfaces 727 for multiple conductor layers using other process techniques known to those skilled in the art that do not require individually masking and etching each conductor surface to form exposed recessed surfaces 727. After a conductor layer is deposited and etched, a corresponding dielectric isolation layer 726 is deposited. The dielectric isolation layer 726 can be, for example, silicon dioxide having a thickness of 15 nm to 50 nm. Conventional CMP prepares the surface of each dielectric layer for deposition of the next conductor layer.The number of conductor layers in the stack of block 700 corresponds to at least the number of memory TFTs in the vertical NOR string, plus additional conductor layers that can be used as control gates for non-memory TFTs, such as precharge TFTs (e.g., precharge TFT 575 in FIG. 5 ), or for bit line access select TFTs (e.g., 585 bit line access select TFT 511 in FIG. 5 ).

[0054] A dielectric isolation layer 710 and a hard mask layer 715 are next deposited. The hard mask 715 is patterned to etch the conductor layer 723p to form long strips of as-yet-unformed word lines. An example of a masking pattern for the word lines 623p-R, 623p-L is shown in FIG. 6 , which includes features such as extensions in the word lines that converge toward each other at the separation (gap) 676 and recesses in each word line to create the desired curvature 675. Deep trenches are formed by anisotropically etching through successive conductor layers 723p and the intervening dielectric isolation layers 726 until the dielectric layer 709 at the bottom of the conductor layers 723p is reached. Because multiple conductor layers are etched, a photoresist mask by itself may not be robust enough to retain the desired word line pattern through multiple successive etches. To provide a robust mask, a hard mask layer 715 (e.g., carbon) is preferred, as known to those skilled in the art. The etch may terminate at the dielectric material 709, or at the landing pad 713 on the global source line, or at the substrate 701. It may be advantageous to provide an etch-stop barrier film (e.g., aluminum oxide) to protect the landing pad 713 from etching.

[0055] FIG. 7B is a cross-sectional view in the ZX plane of a semiconductor structure 700 according to an embodiment of the present invention, showing the etching of a continuous conductor layer 723p and a corresponding dielectric layer 726 to form a trench (e.g., a deep trench 795) that extends down to the dielectric layer 709. In FIG. 7B, the conductor layer 723p is anisotropically etched to form conductor stacks 723p-R and 723p-L separated from each other by the deep trench 795. This anisotropic etch is a high aspect ratio etch. To achieve best results, as known to those skilled in the art, it may be necessary to alternate the etch chemistry between conductor material etching and dielectric etching as different layers of material are etched. The anisotropy of the multi-step etch is important because undercutting of either layer should be avoided so that the conductor width and trench spacing of the resulting word lines at the bottom of the stack are approximately the same as the corresponding width and spacing of the word lines at the top or uppermost layer of the stack. Naturally, the greater the number of conductor layers in the stack, the more difficult it becomes to maintain tight pattern tolerances through multiple successive etches. To mitigate the difficulties associated with etching through, say, 64 or 128 or more conductor layers, etching can be performed in sections, for example, 32 layers each. The separately etched sections can be stitched together, for example, as taught in "Electronic Wiring Diagrams for Electrode Wiring," by John Wiley & Sons, Inc., 1999.

[0056] Etching through multiple conductor layers 723p of conductive material (e.g., tungsten or other intractable material) is much more difficult and time-consuming than etching through the intervening insulating layers 726. For this reason, an alternative process can be employed that eliminates the need for multiple etching of the conductor layers 723p. This process, well known to those skilled in the art, involves first replacing the conductor layers 723p of FIG. 7B with sacrificial layers of an easily etchable material. For example, the insulating layers 726 can be silicon dioxide, and the sacrificial layers (occupying the space shown as 723p in FIG. 7B) can be silicon nitride or another fast-etching dielectric material. Deep trenches are then anisotropically etched through alternating ONON (oxide-nitride-oxide-nitride) dielectric layers to form high stacks of dual dielectrics. At later stages in the fabrication process (described below), these stacks are supported by active vertical strips of polysilicon, allowing the sacrificial layers to be etched away, preferably by selective chemical or isotropic etching. The cavities thus formed are filled by conformal deposition of conductive material, resulting in conductive layers 723p separated by intervening insulating layers 726.

[0057] After the structure of Figure 7B is formed, a charge trapping layer 734 and a polysilicon layer 730 are conformally and successively deposited on the vertical sidewalls of the etched conductive word line stacks. A cross-section of the resulting structure in the ZX plane is shown in Figure 7C. As shown in Figure 7C, the charge trapping layer 734 is formed by first depositing a 5-15 nm thick blocking dielectric 732a, for example, a high-k dielectric film (e.g., aluminum oxide, hafnium oxide, or some combination of silicon dioxide and silicon nitride). Then, a charge trapping material 732b is deposited to a thickness of 4-10 nm. The charge trapping material 732b may be, for example, silicon nitride, silicon-rich oxynitride, conductive nanodots embedded in a dielectric film, or a thin conductive floating gate isolated from adjacent TFTs that share the same vertical active strip. The charge traps 732b may then be capped by a deposited conformal thin tunnel dielectric film (e.g., a silicon dioxide layer, or a silicon oxide-silicon nitride-silicon oxide ("ONO") triple layer) with a thickness in the range of 2-10 nm. The storage elements formed from the charge trapping layer 734 may be SONOS, TANOS, nanodot storage, isolated floating gate, or any suitable charge trapping sandwich structure known to those skilled in the art. The combined thickness of the charge trapping layer 734 is typically 15-25 nm.

[0058] After depositing the charge trapping layer 734, a masking step is used to form a contact opening at the bottom of the trench 795 by anisotropically etching through the charge trapping layer 734 and the dielectric layer 709 at the bottom of the trench 795, the contact opening comprising: Source power supply voltage V ss 7B) for the lower global source line landing pad 713 (see FIG. 7B) or for the global bit line voltage V bl (not shown) or the back bias supply voltage V bb5A. The trench 795 has a bottom P+ region 706 (see FIG. 7C) for contacting the charge trapping material 734. In some embodiments, this etching step is preceded by the deposition of an ultra-thin (e.g., 2-5 nm thick) layer of polysilicon to protect the vertical surfaces of the tunnel dielectric layer 732c during the contact opening etching of the charge trapping material 734 at the bottom of the trench 795. In one embodiment, each global source line is connected only to alternate locations in a row of vertical NOR string pairs. For example, in FIG. 5, for odd-numbered addressed word lines, an electrical contact (e.g., contact opening 557) is etched to connect the N+ doped local source line (e.g., local source line 555 in FIG. 5A) to global source line 513-1. Similarly, for even-numbered addressed word lines, an electrical contact is etched to connect the N+ doped local source line in a column of vertical NOR string pairs to global source line 513-2 (not shown in FIG. 5A). A parasitic capacitor C (i.e., capacitor 560 in FIG. 5A) provides a virtual V ss In embodiments using , the step of etching the charge trapping layer 734 at the bottom of the trench 795 can be skipped.

[0059] Polysilicon film 730 is then deposited to a thickness of 5-10 nm, shown as 730R and 730L in FIG. 7C on opposite sidewalls of trench 795. Polysilicon film 730 is either undoped or, preferably, doped with 1×10 boron. 16 / cm 3 ~1×10 17 / cm 3 , so that the TFTs formed therein may have a larger intrinsic threshold voltage. The trench 795 is wide enough to accommodate the charge trapping layer 734 and the polysilicon thin film 730 on its opposing sidewalls. Following the deposition of the polysilicon 730, the sacrificial layers in the stack described above are etched away, and the cavity thus formed is filled with a conformally deposited conductor layer 723p (FIG. 7C).

[0060] As shown in FIG. 7B , trench 795 extends along the Y direction. After the formation of the independent word line stacks 723p-L and 723p-R, in one embodiment, semiconductor structure 700 can have 16,000 or more parallel word line stacks, each serving as a control gate for 8,000 or more active columns, or 16,000 TFTs (8,000 TFTs on each side of the stack), formed along the length of each stack. With 64 word lines in each stack, each such multi-gate vertical NOR string array will ultimately have 16 billion TFTs. If each TFT stores two data bits, such a multi-gate vertical NOR string array can store 32 gigabits of data. Approximately 32 such multi-gate vertical NOR string arrays (plus a spare array) can be formed on a single semiconductor substrate, thereby providing a 1 terabit integrated circuit chip.

[0061] Figure 7D is a cross-sectional view in the XY plane of the upper surface of the structure of Figure 7C in one embodiment. Between word lines 723p-L and 723p-R are two sidewalls 730L and 730R of vertically deposited P-doped polysilicon structures (i.e., active columns). The deep gap 740 between sidewalls 730L and 730R can be filled with a fast-etching insulating dielectric material (e.g., silicon dioxide, liquid glass, or carbon-doped silicon oxide). The upper surface can then be planarized using conventional CMP. Next, a photolithography step exposes openings 776 and 777, followed by a high-aspect-ratio selective etch to recess the fast-etching dielectric material in the exposed regions 776 and 777 until it reaches the bottom of trench 795. A hard mask may be required during this etching step to avoid excessive pattern degradation during etching. The recessed voids are filled with in situ N+ doped polysilicon. The N+ dopant diffuses into very thin, lightly doped active polysilicon pillars 730L and 730R in the exposed voids to form N+ doped regions. Alternatively, the lightly doped polysilicon in the voids can be etched away by a short isotropic plasma etch or a selective wet etch before filling the voids with in situ N+ doped polysilicon. Next, CMP or a top surface etch removes the N+ polysilicon from the top surface, leaving heavily N+ polysilicon pylons in regions 754(N+) and 755(N+). These N+ pylons form the shared vertical local source line and shared vertical local bit line for the TFTs in the resulting vertical NOR strings.

[0062] Next, a dielectric isolation layer is deposited and patterned using photolithographic masking and etching steps. The etching step opens contacts connecting the vertical local bit lines to the horizontal global bit lines (e.g., from contact (connected to bit line 657-1) to the strings at odd addresses, and from contact 657-2 to the strings at even addresses, as shown in FIG. 6). A low-resistivity metal layer (e.g., tungsten) is deposited. The deposited metal is then patterned using photolithographic and etching steps to form global bit lines (e.g., global bit line 614-1 (GBL1) for the strings and global bit line 614-2 (GBL2) for the strings at odd addresses, as shown in FIG. 6). Alternatively, the global bit lines can be formed using a conventional copper damascene wiring process. All global bit lines, as well as all metal layers 723p (FIG. 7A) of the word line stack, are connected to the word line and bit line decode and sensing circuitry in the substrate by etched via holes, as known to those skilled in the art. The switches and sensing circuits, decoders and reference voltage sources may be provided for the global bit lines and global word lines individually or shared by some of the bit lines and word lines.

[0063] In some embodiments, the bit line access select transistors (511 in FIG. 5) and associated control gate word lines (e.g., word lines 585 in FIG. 5) are formed as independent vertical N+P-N+ transistors, as known to those skilled in the art, which selectively connect odd and even global bit lines (e.g., bit lines 614-1 and 614-2 in FIG. 6A) to vertical NOR strings at alternating odd and even addresses (e.g., local bit lines 657-1 and 657-2 in FIG. 6A).

[0064] [Read operation] Because the TFTs of a vertical NOR string are connected in parallel, in all embodiments of the present invention, all TFTs in an active column (including the active column in which a vertical NOR string pair is formed) should preferably be in enhancement mode, i.e., each TFT should have a positive gate-source threshold voltage, to suppress leakage current during read operations between the shared local source line and the shared local bit line (e.g., local bit line 454 and local source line 455 shown in FIG. 4C). Enhancement mode TFTs target a native TFT threshold voltage of about 1 V, typically 1×10. 16 ~1×10 17 / cm 3 This is achieved by doping the channel region (e.g., P-channel region 756 in FIG. 7C) with a concentration of boron. In such TFTs, all unselected word lines of the vertical NOR string pair in the active column are held at 0V. Alternatively, a read operation raises the voltage on the shared local N+ drain line (e.g., local source line 455 in FIG. 4C) to approximately 1.5V, holds the shared local N+ drain line (e.g., local bit line 454) at approximately 2V, and holds all unselected local word lines at 0V. This configuration is equivalent to setting the word lines to -1.5V relative to the source, thereby suppressing leakage current through TFTs with slightly depletion-mode threshold voltages, which can occur, for example, if the TFT is slightly over-erased.

[0065] After erasing the TFTs of the vertical NOR strings, a soft programming operation may be required to return the over-erased (i.e., depletion-mode threshold voltage) TFTs of the vertical NOR strings to their enhancement-mode threshold voltages. In FIG. 5, the P-channel TFTs are back-biased by the back bias voltage (V bb ) (also shown as body connection region 456 in FIG. 4C). V is used to modulate the threshold voltage of the TFTs in each active column to reduce subthreshold leakage current between the shared voltage supply and the shared N+ drain / local bit line. bbIn some embodiments, for a tunnel erase TFT whose control gate is held at 0V, a positive V bb Voltage can be used.

[0066] To read the data stored in the TFTs of a vertical NOR string pair, all TFTs on both vertical NOR strings of the vertical NOR string pair are first placed in the "off" state by holding all word lines in the multi-gate NOR string array at 0V. The addressed vertical NOR strings can share sensing circuits among several vertical NOR strings along a common word line using a decoding circuit. Alternatively, each vertical NOR string can be directly connected to a dedicated sensing circuit via a global bit line (e.g., GBL1 in Figure 4C). In the latter case, one or more vertical NOR strings sharing the same word line plane can be sensed in parallel. The local source lines of each addressed vertical NOR string are connected to V ss ∼0V, which can be done via a hardwired global source line (e.g., GSL1 in FIG. 4C) as shown schematically in FIG. 8A, or by setting V during precharge as shown schematically in FIG. 8B. bl A virtual V through a precharge transistor (e.g., precharge transistor 470 in FIG. 4C or transistor 317 in FIG. 3C) that momentarily drives ~0V into the parasitic capacitance C (e.g., capacitor 460 or capacitor 360) of the floating local source line 455 or 355. ss Either the voltage is set to ~0V or the voltage is set to ~0V.

[0067] Immediately after turning off precharge transistor 470, the local bit line (e.g., local bit line 454 in FIG. 4C) is pulled up to V through a bit line access select transistor (e.g., bit line access select transistor 411 in FIG. 4C or access select transistor 511 in FIG. 5). bl Set to ~2V. V bl~2V is also the voltage at the sense amplifier for the addressed vertical NOR string. At this time, the addressed word line rises in small incremental voltage steps from 0V to typically about 6V, while the unselected word lines of both the odd-addressed TFT and the even-addressed TFT of the vertical NOR string pair remain at 0V. The hardwired V in Figure 8A ss In this embodiment, the addressed TFT is programmed to a threshold voltage of 2.5V in one example, so that the voltage V on the local bit line LBL bl WL through the selected TFT S As soon as V exceeds 2.5V, the local source line (V ss ), resulting in a voltage drop (shown by the dashed arrow in FIG. 8A) that is detected by the sense amplifier corresponding to the selected global bit line. ss In this embodiment, the precharge transistor word line WL CHG is momentarily turned on to precharge the floating local source line LSL to 0V at the beginning of a read sequence. Next, the selected word line WL S As soon as the voltage increment step exceeds the programmed 2.5V, the selected TFT will increase the voltage on its local bit line to V bl The virtual voltage V is momentarily reduced from ~2V. This voltage dip (shown by the dashed arrow in Figure 8B) is detected by a sense amplifier on the global bit line connected to the selected local bit line. As known to those skilled in the art, there are other alternatives for accurately reading the programmed threshold voltage of the selected TFT. ss It should be noted that in embodiments that rely on parasitic capacitance C to temporarily hold , the taller the vertical stack, the larger the capacitance C and therefore the longer the hold time and the larger the read signal provided to the selected sense amplifier. To further increase C, in one embodiment, one or more dummy conductors can be added to the vertical string whose primary purpose is to increase capacitance.

[0068] In the case of an MLC implementation (i.e., a "multi-level cell" implementation in which each TFT stores more than one bit), the addressed TFT may be programmed to one of several voltages (e.g., 1 V (erased state), 2.5 V, 4 V, or 5.5 V). The addressed word line WL S The voltage is increased in voltage increment steps until the sense amplifier detects conduction of the TFT. Alternatively, a single word line voltage can be applied (e.g., up to about 6 volts) and the local bit line LBL (V bl The discharge rate of the vertical NOR strings can be compared to the discharge rate from several programmable reference voltages representing the stored multi-bit voltage states. This approach can be extended to continuum states, effectively providing analog storage. The programmable reference voltages are stored in dedicated reference vertical NOR strings located within the multi-gate vertical NOR string array, and their characteristics and background leakage are closely tracked during read and program. In vertical NOR string pairs, only the TFTs of one of the two vertical NOR strings can be read in each read cycle, while the TFTs on the other vertical NOR string are placed in the "off" state (i.e., all word lines are at 0V). Because the read voltage is applied to only one of the vertical NOR string's TFTs during a read cycle, read disturb conditions are essentially nonexistent.

[0069] In one embodiment of the present invention, 64 TFTs and one or more precharge TFTs may be provided for each vertical NOR string of a vertical NOR string pair. Each word line forms a capacitor at its intersection with its local vertical N+ source line pillar (see, e.g., capacitor 660 in FIG. 6A). A typical capacitance of such a capacitor is, for example, 1×10 18 F (Farad). Including all the capacitors in both vertical NOR strings, the total distributed capacitance C is approximately 1×10 16Farads, and this capacitance is the source voltage (V ss ) is sufficient to store the charge. The charging time through the bit line access select transistor 411 and precharge TFT 470 is on the order of a few nanoseconds, and this charging time does not add significantly to the read latency. Unlike a NAND string read operation, which requires many series-connected TFTs to conduct, reading from the TFTs in a vertical NOR string involves the conduction of only one of the TFTs in the vertical NOR string.

[0070] There are two main factors that contribute to the read latency of the vertical NOR string of the present invention: (a) the resistance R of the global bit line (e.g., GBL614-1 in FIG. 6A). bl and capacity C bl and (b) the voltage drop V on the local bit line (e.g., LBL-1) when the addressed TFT starts to conduct. bl The RC time delay associated with the global bit line is, for example, on the order of tens of nanoseconds for a 16,000 vertical NOR string. The read latency for reading the TFTs of a prior art vertical NAND string (e.g., the NAND string of FIG. 1B) is the sum of the capacitance C of the global bit line and the 32 or more series-connected TFTs. bl In contrast, in the vertical NOR string of the present invention, the read current discharges C bl is supplied through one addressed transistor (e.g., transistor 416L in FIG. 4A) in series with the bit line access select transistor 411, thereby providing the local bit line voltage (V bl ) discharges more quickly, resulting in much shorter latency.

[0071] 4C, one TFT at a time (e.g., TFT 416L in vertical NOR string 451b) is read out while all other TFTs in either vertical NOR string 451a or 451b of vertical NOR string pair 491 are held in the "off" state and their word lines are held at 0 V. TFT 416R in vertical NOR string 452a of vertical NOR string pair 492 shares word line W31 with TFT 416L, but vertical NOR string 452a uses global bit line 414-2, so TFT 416L is read out simultaneously with TFT 416L, while string 451b uses global bit line 414-1 (FIGS. 6A and 6B show how global bit lines 614-1 and 614-2 are provided for adjacent vertical NOR string pairs).

[0072] In one embodiment, the word line stack includes 32 or more word lines arranged in 32 planes. In a multi-gate vertical NOR string array, each plane contains 8000 word lines controlling 16000 TFTs, each connected to a dedicated sense amplifier, which can be read in parallel through 16000 global bit lines. Alternatively, if multiple global bit lines share a sense amplifier via decoding circuitry, the 16000 TFTs can be read over several consecutive read cycles. Reading a large number of discharge TFTs in parallel can increase the chip's ground power supply (V ss ) may cause voltage bounce, resulting in read errors. However, by using a precharged parasitic capacitor C on the local source line (i.e., the virtual source voltage (V ss ) is particularly advantageous in that such ground voltage bounce is eliminated. This is because the virtual supply voltage of the vertical NOR string is independent and not connected to the chip's ground supply.

[0073] [Program (write) and program disable operations] Programming of an addressed TFT can be achieved by tunneling (direct tunneling or Fowler-Nordheim tunneling) of electrons from the TFT's channel region (e.g., the channel region shown as 430L in Figure 4b) to its charge trapping layer (e.g., charge trapping layer 434) when a high programming voltage is applied between a selected word line (e.g., word line 423p-R) and the active channel region (e.g., the active channel region of body region 456 in Figure 4A). Because tunneling is highly efficient and requires very little current to program the TFT, parallel programming of tens of thousands of TFTs can be achieved with low power consumption. Programming by tunneling can require, for example, a 20V, 100-microsecond pulse. Preferably, programming is accomplished by a series of shorter-duration stepped voltage pulses starting at approximately 14V and building up to approximately 20V. Using stepped voltage pulses reduces electrical stress on the TFT and avoids overshooting the intended programmed threshold voltage.

[0074] After each programming high-voltage pulse, the addressed transistor is read to determine whether it has reached its target threshold voltage. If the target threshold voltage has not been reached, the next programming pulse applied to the selected word line is typically incremented by a few hundred millivolts. This program verify sequence is repeated by applying 0V to one addressed word line (i.e., control gate) with 0V applied to the local bit line (e.g., local bit line 454 in FIG. 4A) of the active column (e.g., column 430L in FIG. 4B). At these high word line programming voltages, the channel region of TFT 416L is inverted and held at 0V, allowing electrons to tunnel into the charge storage layer of TFT 416L. When read sensing indicates that the addressed TFT has reached its target threshold voltage, the addressed TFT must be inhibited from further programming, while other TFTs sharing the same word line can continue programming to their higher target threshold voltages. For example, when programming TFT 416L in vertical NOR string 451b, programming of all other TFTs in vertical NOR strings 451b and 451a must be inhibited by holding all their word lines at 0V.

[0075] After reaching the target threshold voltage, a half-select voltage (i.e., approximately 10 V) is applied to local bit line 454 to inhibit further programming of TFT416L. With 10 V applied to the channel region and 20 V applied to the control gate, only a net 10 V is applied to the charge trapping layer, so Fowler-Nordheim tunneling current is insignificant and no significant further programming of TFT416L occurs during the remaining sequence of stepped voltage pulses up to 20 V. By raising local bit line 454 to 10 V while continuing to ramp the programming voltage pulses on word line WL31, all TFTs in the vertical NOR string sharing the same selected word line are successfully programmed to their higher target threshold voltages. This program-read-program-inhibit sequence is essential to accurately program hundreds of thousands of TFTs in parallel to their various target threshold voltage states in a multilevel cell storage system. Such program inhibition of overprogramming of individual TFTs can potentially cause threshold voltage oversteer or merging with the next higher target threshold voltage state. Although TFT416R and TFT416L share the same word line, they belong to different vertical NOR string pairs 452 and 451. Because their respective bit line voltages are supplied via GBL1 and GBL2 and controlled independently, it is possible to program both TFT416L and TFT416R with the same programming pulse voltage sequence. For example, TFT416L can be programmed at any time, and TFT416R can be inhibited from programming at any time. Because vertical NOR strings 451a and 451b of vertical NOR string pair 491 are controlled by separate word lines 423p-L and 423p-R, respectively, these programming and programming inhibit voltage conditions can be met, and the voltage of each local bit line can be set independently of all other vertical NOR string pairs.During programming, unselected word lines in either the addressed or unaddressed word line stacks can be at 0V, a half-select voltage of 10V, or floated. In embodiments where the global source line (e.g., GSL1 in FIG. 4C) is accessed through a source access select transistor (not shown in FIG. 4C), the access select transistor is turned off during programming, and the voltage on the local source line 455 tracks the voltage on the local bit line 454 during programming and programming inhibit. The same is true for embodiments where the voltage on the local source line is provided by its parasitic capacitance C, represented by capacitor 460 in FIG. 4C. In the embodiment of FIG. 4C, where a global source line is present but a source access select transistor is not, the voltage applied to the addressed string's global source line 413-1 should preferably track the voltage on the addressed global bit line 414-1 during programming and programming inhibit.

[0076] Each incrementally increasing voltage programming pulse is followed by a read cycle to determine whether TFTs 416L and 416R have reached their respective target threshold voltages. If they have, the drain, source, and body voltages are raised to 10V (or these voltages are floated to approach 10V), inhibiting further programming, while word line WL31 continues to program other addressed TFTs on the same plane that have not yet reached their target threshold voltages. This sequence ends when all addressed TFTs are read-verified as being correctly programmed. In the case of MLC, programming of one of several threshold voltage states can be accelerated by setting each addressed global bit line to one of several predetermined voltages (e.g., 0V, 1.5V, 3.0V, or 4.5V, representing four different states of the two bits of data to be stored) and then applying a stepped programming pulse (up to approximately 20V) to word line WL31. In this way, the addressed TFT receives a predetermined one of the available tunneling voltages (i.e., 20V, 18.5V, 17V, and 15.5V, respectively), and a predetermined threshold voltage is programmed into the TFT in a single programming sequence. Fine, precise programming pulses can then be applied at the individual TFT level.

[0077] [High-speed fully parallel programming] Due to the parasitic capacitance C inherent in each local source line of a multi-gate vertical NOR string array, all local source lines of the multi-gate vertical NOR string array can have 0V (for programming) or 10V (for inhibit) momentarily applied (e.g., via global bit line GBL1 and bit line access select transistor 411 and precharge transistor 470) to all vertical NOR strings before applying the high-voltage pulse sequence. This procedure can be performed by addressing word line planes on a plane-by-plane basis. For each addressed word line plane, a programming pulse sequence can be applied to many or all word lines in the addressed word line plane while holding all word lines in other word line planes at 0V, programming many TFTs in the addressed plane in parallel, followed by individual read verify, and optionally resetting the local source lines of appropriately programmed TFTs to the program inhibit voltage. This approach has a significant advantage because, although programming times are relatively long (i.e., approximately 100 microseconds), precharging or read-verifying all local source line capacitors that share an addressed word line plane is over 1000 times faster. Therefore, it makes sense to program as many TFTs as possible in parallel on each word line plane. This accelerated programming capability has an even greater advantage in MLC programming, which is significantly slower than single-bit programming.

[0078] [Erase operation] In some charge-trapping materials, the erase operation is performed by reverse tunneling of trapped charges, which can be rather slow, sometimes requiring tens of milliseconds of 20V or more pulses. Therefore, the erase operation can be performed at the vertical NOR string array level ("block erase") and is often performed in the background. A typical vertical NOR string array has 64 word line planes, each controlling, for example, 16,384 × 16,384 TFTs, for a total of approximately 1.7 billion TFTs. Thus, a 1-terabit chip can contain approximately 30 such vertical NOR arrays, with each TFT storing two bits of data. In some embodiments, block erase can be performed by applying approximately 20V to the P-channel shared by all TFTs in the vertical NOR string (e.g., body connection 456 in FIG. 4C and contact 556 in FIG. 5) while holding all word lines in the block at 0V. The duration of the erase pulse must be such that most of the TFTs in the block are erased to a slight enhancement-mode threshold voltage, i.e., between 0V and 1V. Some TFTs will overshoot and be erased to depletion mode (i.e., a slightly negative threshold voltage). As part of the erase command, soft programming may be required to return over-erased TFTs to a slight enhancement-mode threshold voltage after the erase pulse ends. A vertical NOR string that may contain one of the depletion-mode TFTs that cannot be programmed to enhancement mode may need to be retired and replaced by a spare string.

[0079] Alternatively, rather than supplying the erase pulse to the body (i.e., P layer), the voltages of the local source lines and local bit lines (e.g., local source line 455 and local bit line 454 in FIG. 4C) on all vertical NOR string pairs in the vertical NOR string array are raised to approximately 20 V while all word lines in all word line planes are held at 0 V for the duration of the erase pulse. This scheme requires the global source line and global bit line selection decoders to use high-voltage transistors that can withstand 20 V at their junctions. Alternatively, all TFTs sharing an addressed word line plane can be erased together by applying a -20 V pulse to all word lines in the addressed plane while holding the word lines in all other planes at 0 V. All other voltages of the vertical NOR string pairs are held at 0 V. This erases only the XY slice of all TFTs touched by one addressed plane of word lines.

[0080] [Semi-volatile NOR TFT string] Some charge-trapping materials suitable for use in vertical NOR strings (e.g., oxide-nitride-oxide, or "ONO") typically have long data retention times on the order of years, but relatively low endurance (i.e., performance degradation after typically on the order of 10,000 or fewer write-erase cycles). However, in some embodiments, a charge-trapping material can be selected that stores charge with very short retention times but greatly improved endurance (e.g., retention times on the order of minutes or hours, endurance capable of tens of millions of write-erase cycles). For example, in the embodiment of FIG. 7C, the tunnel dielectric layer 732c, typically a 6-8 nm layer of SiO2, can be thinned to about 2 nm or replaced with another dielectric material (e.g., SiN). The much thinner dielectric layer allows the use of modest voltages (as opposed to Fowler-Nordheim tunneling, which requires higher voltages) to introduce electrons by direct tunneling into the charge-trapping layer, where electrons are trapped for minutes to hours or days. The charge trapping layer 732b can be silicon nitride, conductive nanodots dispersed in a thin dielectric film, or a combination of other charge trapping films including an isolated thin floating gate. The blocking layer 732a can be silicon dioxide, aluminum oxide, hafnium oxide, silicon nitride, a high-k dielectric, or any combination thereof. The blocking layer 732a prevents electrons in the charge trapping layer 732b from escaping to the control gate word line. The trapped electrons will eventually leak into the active region 730R as a result of breakdown of the ultrathin tunnel dielectric layer or by reverse direct tunneling. Other combinations of charge trapping materials can also be used, but the resulting combination results in a "semi-volatile" storage TFT with high durability but low retention, requiring periodic write or read refresh operations to replenish lost charge.The vertical NOR string of the present invention has a relatively fast read access (i.e., low latency), allowing it to be used in several applications currently requiring the use of dynamic random access memory (DRAM). The vertical NOR string of the present invention has the distinct advantage of consuming much less power than DRAM, which cannot be integrated into a three-dimensional stack, and having a much lower cost per bit than DRAM, since the refresh cycle only needs to be performed approximately once every few minutes or hours, whereas DRAM requires a refresh every few milliseconds. The three-dimensional semi-volatile storage TFT of the present invention can be achieved by selecting appropriate materials (e.g., those described above) for the charge trapping material, appropriately adapting the program / read / program inhibit / erase conditions, and incorporating periodic data refresh.

[0081] [NROM / Mirror Bit NOR TFT String] In another embodiment of the present invention, the vertical NOR string can be programmed using a channel hot electron injection method used in two-dimensional NROM / mirror bit transistors, as known to those skilled in the art. Using the embodiment of FIG. 4A as an example, the programming conditions for channel hot electron injection can be 8V on the control gate (i.e., word line 423p), 0V on the local source line 455, and 5V on the local drain line 454. A charge representing one bit is stored in a charge storage layer at one end of the channel region (in body region 456) adjacent to the junction with local bit line 454. By reversing the polarity of local source line 455 and local bit line 454, a charge representing a second bit is programmed and stored in the charge storage layer at the opposite end of channel region 456 next to the junction with local source line 455. Reading both bits requires a read in the reverse order of programming, as known to those skilled in the art. Channel hot electron programming is much less efficient than programming by direct tunneling or Fowler-Nordheim tunneling, and is therefore not suitable for the massively parallel programming possible with tunneling. However, each TFT has twice the bit density, making it attractive for applications such as archival memory. Erasing an NROM TFT can be accomplished using the conventional NROM erase mechanism, which utilizes band-to-band tunneling-induced hot hole injection to neutralize the charge of trapped electrons: by applying -5 V to the word line, 0 V to the local source line 455, and 5 V to the local bit line 454. Alternatively, the NROM TFT can be programmed with a high positive substrate voltage V across the body region 456 with the word line at 0 V. bb Due to the high programming currents associated with channel hot electron injection programming, all embodiments of vertical NROM TFT strings must use hardwired local source and bit lines, as in the embodiments of Figures 3A and 6C.

[0082] The above detailed description is provided to illustrate particular embodiments of the present invention and is not intended to be limiting. Many variations and modifications are possible within the scope of the invention, as defined by the following claims.

Claims

1. 1. A memory structure including a plurality of memory cells formed on a planar surface of a semiconductor substrate having one or more voltage sources formed therein or on the surface thereof and organized as a NOR string, comprising: each memory cell includes a storage transistor having a channel region, a data storage region, a gate terminal, a first drain or source terminal, and a second drain or source terminal, the storage transistor having a variable threshold voltage indicative of a physical state of the data storage region; The memory structure comprises: a word line connected to the gate terminal of one or more of the storage transistors and supplying a control voltage during a read operation; a bit line connecting the first drain or source terminal of each storage transistor to a data detection circuit; a source line connected to the second drain or source terminal of each storage transistor; an insulating layer; a conductor layer electrically connecting the channel region to one of the voltage sources in the semiconductor substrate to provide a bias voltage for the channel region; the bit lines and the source lines each include columns of semiconductor material of a first conductivity type extending along a first direction that is substantially perpendicular to the planar surface; the insulating layer forms an isolation column between the bit line and the source line to electrically isolate the bit line and the source line from each other; the conductor layer includes columns of semiconductor material of a second conductivity type opposite to the first conductivity type, the columns of semiconductor material extending along the first direction and surrounding the bit lines, the source lines, and the isolation columns; the source line provides sufficient capacitance to maintain at least a predetermined voltage difference between the second drain or source terminal and the gate terminal during the read operation; The memory structure further comprises a precharge transistor for charging the capacitor to a predetermined voltage before the read operation.

2. 2. The memory structure of claim 1, During the read operation, when the control voltage exceeds the variable threshold voltage, the control voltage causes the storage transistor to discharge the capacitance.

3. 2. The memory structure of claim 1, A memory structure wherein the capacitance is provided by a parasitic capacitance of the source line.

4. 1. A memory structure formed on a planar surface of a semiconductor substrate having one or more voltage sources formed therein or on the surface thereof, (a) a plurality of word lines; (b) a plurality of source lines; (c) a plurality of bit lines, each bit line and each source line being a column of semiconductor material of a first conductivity type extending along a first direction that is substantially perpendicular to the planar surface; (d) a plurality of insulating layers, each insulating layer being an isolated column adjacent one of the bit lines and one of the source lines, electrically isolating the adjacent bit lines and the adjacent source lines from each other; (e) a plurality of conductor layers, each conductor layer including a column of semiconductor material of a second conductivity type opposite the first conductivity type, the column of semiconductor material extending along the first direction and surrounding one of the isolation columns, an adjacent one of the bit lines, and an adjacent one of the source lines; (f) an array of NOR memory strings, each NOR memory string including a plurality of storage transistors; Including, (i) each storage transistor includes a channel region, a data storage region, a gate terminal, a first drain or source terminal, and a second drain or source terminal; (ii) each storage transistor has a variable threshold voltage that indicates a physical state of the data storage region; (iii) each storage transistor is (1) one of the word lines connecting to the gate terminal to provide a control voltage during a read operation; (2) one of the bit lines connecting the first drain or source terminal to a data detection circuit, and one of the source lines connected to the second drain or source terminal; and (3) one of the conductor layers electrically connecting the channel region to one of the voltage sources of the semiconductor substrate to provide a bias voltage for the channel region; associated with, the source line provides sufficient capacitance to maintain at least a predetermined voltage difference between the second drain or source terminal and the gate terminal during the read operation; The memory structure further comprises a precharge transistor for charging the capacitor to a predetermined voltage before the read operation.

5. 5. The memory structure of claim 4, 1. The memory structure further comprising, for each NOR memory string, (i) a common drain region providing the first drain or source terminal of the storage transistor of the NOR memory string, and (ii) a common source region providing the second drain or source terminal of the storage transistor of the NOR memory string.

6. 6. The memory structure of claim 5, a first set of conductors each extending along a second direction substantially parallel to the planar surface, (i) the first set of conductors providing the word lines of the array, and (ii) the gate terminals of the storage transistors of each NOR memory array connected to corresponding others of the word lines.

7. 7. The memory structure of claim 6, The memory structure, wherein the first set of conductors provides one or more dummy conductors for each of the source lines to increase parasitic capacitance of the source lines.

8. 7. The memory structure of claim 6, A memory structure wherein in each NOR memory string, the data storage regions of the storage transistors are each part of a layer of charge trapping material provided over the channel regions of the storage transistors.

9. 9. The memory structure of claim 8, The memory structure wherein the channel region of the storage transistor is of the second conductivity type.

10. 7. The memory structure of claim 6, the NOR memory strings are arranged along both the second direction and a third direction, the third direction being substantially parallel to the planar surface and substantially orthogonal to the second direction.

11. 7. The memory structure of claim 6, 1. A memory structure comprising: a common source region of each NOR memory string electrically floating with respect to circuitry formed in the semiconductor substrate except when the channel region of one or more of the storage transistors of the NOR memory string is rendered conductive.

12. 7. The memory structure of claim 6, A memory structure wherein each word line is shared among multiple of the NOR memory strings of the array.

13. 11. The memory structure of claim 10, a second set of conductors extending along the third direction, a first group of the second set of conductors functioning as the bit lines of the array, such that each bit line connects a portion of circuitry in the semiconductor substrate to the common drain region of the storage transistors of one of the NOR memory strings in the array.

14. 14. The memory structure of claim 13, The second set of conductors is formed between the array and the planar surface.

15. 14. The memory structure of claim 13, The second set of conductors is formed above the array.

16. 14. The memory structure of claim 13, The memory structure wherein the first group of the second set of conductors are connected to the common drain region through select transistors.

17. 17. The memory structure of claim 16, A memory structure wherein a second group of the second set of conductors are connected to the drain or source terminals of the select transistors through conductor-filled via holes.

18. 7. The memory structure of claim 6, A memory structure in which each storage transistor has a unique enhancement-mode threshold voltage.

19. 7. The memory structure of claim 6, The memory structure, wherein the circuitry of the semiconductor substrate includes a voltage source for providing a predetermined voltage for memory operation.

20. 20. The memory structure of claim 19, The memory structure, wherein the predetermined voltages include voltages for program, program inhibit, read and erase voltages.

21. 7. The memory structure of claim 6, A memory structure wherein the variable threshold voltage of each storage transistor is set using Fowler-Nordheim tunneling or direct tunneling.

22. 22. The memory structure of claim 21, A memory structure wherein the variable threshold voltage is set to a level corresponding to one of two or more states of charge.

23. 7. The memory structure of claim 6, The channel region of each storage transistor is electrically connected to the semiconductor substrate.

24. 24. The memory structure of claim 23, The semiconductor substrate provides a predetermined back bias voltage to the channel region of each storage transistor that suppresses sub-threshold leakage during the read operation.

25. 7. The memory structure of claim 6, A memory structure wherein the first set of conductors each comprise one of N+ doped polysilicon, P+ doped polysilicon, and a high work function refractory metal with respect to a silicide or a polycide.

26. 7. The memory structure of claim 6, A memory structure wherein the data storage region of each storage transistor includes one or more layers of silicon nitride or bandgap engineered oxide-nitride-oxide dielectric layers.

27. 7. The memory structure of claim 6, A memory structure in which each storage transistor of each NOR memory string can be individually addressed for programming, inhibiting programming, erasing, or said read operations.

28. 7. The memory structure of claim 6, A memory structure wherein the storage transistor is non-volatile or quasi-volatile.

29. 7. The memory structure of claim 6, During a read operation, the capacitance of the common source region of each NOR memory string is charged to a virtual ground voltage.

30. 30. The memory structure of claim 29, 1. A memory structure wherein a gate electrode of a selected storage transistor is raised to a predetermined voltage to enable sensing of a threshold voltage of the selected storage transistor, and the gate electrodes of all other storage transistors of the NOR memory string are held in a non-conductive state.

31. 30. The memory structure of claim 29, A memory structure wherein during a programming operation, the capacitance of the common source region is momentarily precharged to a virtual ground voltage.

32. 7. The memory structure of claim 6, 1. A memory structure comprising: in a selected one of the storage transistors of a selected NOR memory string, one or more programming voltage pulses are applied to selected one or more of the first set of conductors to initiate efficient Fowler-Nordheim tunneling or direct tunneling of charge from the channel region, the common source region, and the common drain region to the charge trapping material in the data storage region; and all others of the first set of conductors are held at a voltage that inhibits the initiation of efficient Fowler-Nordheim tunneling or direct tunneling of charge from the channel region, the common source region, and the common drain region to the charge trapping material in the unselected data storage region.

33. 7. The memory structure of claim 6, A memory structure in which the storage transistors of multiple NOR memory strings are erased in a single operation.

34. 7. The memory structure of claim 6, A memory structure wherein one or more of said one or more NOR memory strings serves as a reference memory string.

35. 35. The memory structure of claim 34, The memory structure, wherein the circuitry in the semiconductor substrate includes a differential sense amplifier that compares a signal received from a storage transistor in one of the NOR memory strings with a signal received from a corresponding storage transistor in the reference memory string.

36. 35. The memory structure of claim 34, A memory structure, wherein one or more storage transistors of the reference memory string are programmed to set a reference threshold voltage.

37. 7. The memory structure of claim 6, A memory structure, wherein one or more of the NOR memory strings function as spare strings, each spare string being configurable to replace a NOR memory string in the array.

38. 35. The memory structure of claim 34, A memory structure wherein the threshold voltages programmed into the storage transistors of the reference memory string correspond to programmed states under a multi-bit scheme.

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