Semiconductor wafer evaluation device, semiconductor wafer evaluation system, and semiconductor wafer evaluation method

Abstract

To efficiently determine whether defects of a semiconductor wafer with a plurality of chips formed thereon are a known phenomenon, and prevent deterioration in manufacturing efficiency due to the unnecessary line-out of the semiconductor wafer.SOLUTION: Provided is a semiconductor wafer determination method including: subjecting a plurality of chips formed on a semiconductor wafer to a functional test after wafer processing; generating an image 24f with a tendency of defects based on functional test data 24a; inputting the image 24f with a tendency of defects into a learned model M; determining whether the defects of the semiconductor wafer is a known phenomenon; and, based on the determination results, displaying whether the semiconductor wafer is to be lined out.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor wafer judgment device, a semiconductor wafer judgment system, and a semiconductor wafer judgment method for judging whether or not a defect in a semiconductor wafer on which a plurality of Large Scale Integrated (LSI) chips (hereinafter simply referred to as "chips") are formed is a known defect. [Background technology]

[0002] 2. Description of the Related Art Conventionally, a technique is known in which a plurality of chips are formed on a semiconductor wafer, and each chip is inspected for defects to determine whether each chip is a non-defective product that operates correctly or a defective product.

[0003] For example, Patent Document 1 discloses a technology in which an image of a semiconductor wafer is captured by a camera using scattered light, and the captured image is used to inspect the semiconductor wafer for the presence or absence of surface or internal defects. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 10-340935 Summary of the Invention [Problem to be solved by the invention]

[0005] However, since the technique disclosed in Patent Document 1 is an inspection method using an image of a semiconductor wafer, it is not possible to inspect defects in electrical characteristics that occur in the semiconductor wafer.

[0006] Furthermore, in an actual semiconductor wafer manufacturing process, if the proportion of non-defective chips among all chips contained in the semiconductor wafer is below a predetermined value (e.g., 80%) or if defective chips are present in a specific location, the semiconductor wafer is released from the manufacturing process. In this case, the device disclosed in Patent Document 1 simply inspects for the presence or absence of defects, and therefore cannot determine whether the semiconductor wafer should be released from the manufacturing process.

[0007] The present invention has been made to solve the problems (issues) of the above-mentioned conventional technology, and has an object to provide a semiconductor wafer judgment device, a semiconductor wafer judgment system, and a semiconductor wafer judgment method that can efficiently judge whether or not a defect in a semiconductor wafer on which multiple chips are formed is a known phenomenon, and prevent a decrease in manufacturing efficiency due to unnecessary line-out of semiconductor wafers. [Means for solving the problem]

[0008] In order to solve the above-mentioned problems and achieve the object, the present invention provides a semiconductor wafer judgment device for judging whether or not a semiconductor wafer on which a plurality of integrated circuits are formed is to be lined out, the device comprising: a function test means for performing a function test to judge whether or not the plurality of integrated circuits are non-defective; a judgment means for judging whether or not a defect in the semiconductor wafer is a known phenomenon when the plurality of integrated circuits do not satisfy a predetermined condition as a result of the function test; and a notification means for notifying that the semiconductor wafer is to be lined out when the judgment means judges that the defect in the semiconductor wafer is not a known phenomenon. The predetermined condition is when the ratio of the integrated circuits determined to be non-defective among the plurality of integrated circuits is less than a predetermined threshold, or when the integrated circuits determined to be defective among the plurality of integrated circuits are present in a predetermined local area. It is characterized by:

[0010] Furthermore, in the above invention, the present invention is characterized in that the determination means determines whether or not the defect in the semiconductor wafer is a known phenomenon using a trained model obtained by deep learning a multilayer neural network through supervised learning.

[0011] Furthermore, in the above invention, the present invention is characterized in that the trained model is generated by applying first training data consisting of an image of a semiconductor wafer having a defect of a known phenomenon and its correct answer data, and second training data consisting of an image of a semiconductor wafer having a defect of an unknown phenomenon and its correct answer data to the multilayer neural network to perform supervised learning.

[0012] The present invention also provides a semiconductor wafer assessment system having a semiconductor wafer assessment device that determines whether a semiconductor wafer formed with a plurality of integrated circuits should be lined out, and a server device that can communicate with the semiconductor wafer assessment device, wherein the server device comprises: a generation means that generates a trained model by applying first training data consisting of an image of a semiconductor wafer having a defect of a known phenomenon and its control data, and second training data consisting of an image of a semiconductor wafer having a defect of an unknown phenomenon and its control data, to a multilayer neural network to perform supervised learning; and a notification means that notifies the semiconductor wafer assessment device of the trained model generated by the generation means, and the semiconductor wafer assessment device comprises: a functional test means that performs a functional test to determine whether the plurality of integrated circuits are non-defective; a determination means that, when the plurality of integrated circuits do not satisfy predetermined conditions through the functional test, determines using the trained model whether the defect in the semiconductor wafer is a known phenomenon; and a notification means that notifies the semiconductor wafer to be lined out when the determination means determines that the defect in the semiconductor wafer is not a known phenomenon.

[0013] The present invention also provides a semiconductor wafer evaluation method in a semiconductor wafer evaluation system having a semiconductor wafer evaluation device that evaluates whether or not a semiconductor wafer on which a plurality of integrated circuits are formed should be lined out, and a server device that can communicate with the semiconductor wafer evaluation device, the method including: a generation step in which the server device applies first training data consisting of an image of a semiconductor wafer having a defect of a known phenomenon and its supervised data, and second training data consisting of an image of a semiconductor wafer having a defect of an unknown phenomenon and its supervised data, to a multilayer neural network to generate a trained model by performing supervised learning; and a notification step in which the server device notifies the semiconductor wafer evaluation device of the trained model generated in the generation step. 、 The semiconductor wafer evaluation device performs a function test to determine whether the plurality of integrated circuits are non-defective. process and a determination step in which the semiconductor wafer determination device determines whether or not a defect in the semiconductor wafer is a known phenomenon using the trained model when the plurality of integrated circuits do not satisfy predetermined conditions through the functional test, and a notification step in which the semiconductor wafer determination device notifies the user that the semiconductor wafer should be removed from the line when the determination step determines that the defect in the semiconductor wafer is not a known phenomenon. [Effects of the Invention]

[0014] According to the present invention, it is possible to efficiently determine whether a defect in a semiconductor wafer on which a plurality of chips are formed is a known phenomenon, and to prevent a decrease in manufacturing efficiency due to unnecessary line-out of semiconductor wafers. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 1 is a diagram showing an outline of a semiconductor wafer judgment system according to this embodiment. [Figure 2] FIG. 2 is a diagram showing the system configuration of the semiconductor wafer determination system shown in FIG. [Figure 3] FIG. 3 is a functional block diagram showing functions of the server device shown in FIG. [Figure 4] FIG. 4 is an explanatory diagram for explaining an overview of supervised learning in the server device shown in FIG. [Figure 5] FIG. 5 is a flowchart showing a procedure for generating a trained model in the server device shown in FIG. [Figure 6] FIG. 6 is a functional block diagram showing the functions of the determination device shown in FIG. [Figure 7] FIG. 7 is a diagram illustrating an example of the trained model illustrated in FIG. [Figure 8] FIG. 8 is an explanatory diagram for explaining the determination of whether or not a defect is a known phenomenon. [Figure 9] FIG. 9 is a diagram showing an example of the function test data shown in FIG. [Figure 10] FIG. 10 is a diagram showing an example of the map data shown in FIG. [Figure 11] FIG. 11 is a diagram showing an example of the variety parameters and sequence data shown in FIG. [Figure 12] FIG. 12 is a diagram showing an example of the weighting parameters and the defect tendency image shown in FIG. [Figure 13] FIG. 13 is a diagram showing an example of the determination result data shown in FIG. [Figure 14] FIG. 14 is a flowchart (part 1) showing the processing procedure of the determination device shown in FIG. [Figure 15] FIG. 15 is a flowchart (part 2) showing the processing procedure of the determination device shown in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0016] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a semiconductor wafer determination device, a semiconductor wafer determination system, and a semiconductor wafer determination method according to the present invention will be described in detail with reference to the accompanying drawings.

[0017] <Semiconductor wafer evaluation system overview> An overview of the semiconductor wafer judgment system according to this embodiment will be described. FIG. 1 is an explanatory diagram for explaining the overview of the semiconductor wafer judgment system according to this embodiment. In this embodiment, a case where defect judgment is performed in a functional test performed after wafer processing of a semiconductor wafer will be described. The following mainly describes a case where a trained model that has undergone deep learning using a CNN (Convolutional Neural Network) is used, but the present invention is not limited to this. It is also possible to apply machine learning using gradient boosting based on a decision tree algorithm, or to use an analysis tool such as Microsoft Excel (registered trademark).

[0018] Conventionally, in a functional test performed after wafer processing of a semiconductor wafer, each chip formed on the semiconductor wafer is inspected to determine whether it is a good product or a defective product. If the number of good chips is equal to or greater than a predetermined value, the semiconductor wafer is transferred to the next chip manufacturing process. If the number of good chips is less than the predetermined value or if defective chips exist in a local area, the semiconductor wafer is removed from the line and the cause of the defect is analyzed.

[0019] Here, when a semiconductor wafer is lined out of the manufacturing process, if the tendency for defects to occur within the surface of the semiconductor wafer (hereinafter referred to as a "semiconductor wafer defect") of the chip is a known phenomenon, it is sufficient to take measures against the known phenomenon without lined out the semiconductor wafer. However, in the past, even if the defect in the semiconductor wafer was a known phenomenon, the person in charge had to analyze the cause of the defect, which took time, and ultimately caused a decrease in manufacturing efficiency.

[0020] Therefore, in the semiconductor wafer judgment system according to this embodiment, a function test is performed on a plurality of chips on a semiconductor wafer, and the test result data is stored.Then, a defect tendency image 24f is generated based on the test result data.

[0021] This defect tendency image 24f is input to a trained model M that has been previously trained in a supervised manner using deep learning. As a result, the trained model M outputs the probability that the defect in the semiconductor wafer is a known phenomenon. Then, based on this probability, it is determined whether the defect in the semiconductor wafer is a known phenomenon. If it is determined that it is a known phenomenon, the semiconductor wafer is displayed as not being lined out, and if it is determined that it is not a known phenomenon, the semiconductor wafer is displayed as being lined out. Note that, for the sake of convenience of explanation, a case has been shown in which the trained model M outputs the probability that the defect in the semiconductor wafer is a known phenomenon, but the trained model M can also output a score that the defect in the semiconductor wafer is a known phenomenon.

[0022] To explain the above series of steps in detail, the semiconductor wafer judgment system performs a function test on multiple chips on a semiconductor wafer after wafer processing, and stores the test results in a memory unit as function test data 24a (S1).The function test data 24a stored in the memory unit is then converted into array data 24d.The converted array data 24d is then weighted and then converted into a monochrome grayscale defect tendency image 24f (S2).

[0023] This defect tendency image 24f is input to a trained model M that has been generated in advance by supervised deep learning (S3). This trained model M has been trained using training data consisting of images in which semiconductor wafer defects are known phenomena and their correct answer data R, and training data consisting of images in which semiconductor wafer defects are not known phenomena and their correct answer data R.

[0024] As a result, the trained model M outputs the probability that the defect in the semiconductor wafer is a known phenomenon and the probability that the defect in the semiconductor wafer is not a known phenomenon (S4). Then, based on this probability that the defect is a known phenomenon and the probability that the defect is not a known phenomenon, it is determined whether the defect in the semiconductor wafer is a known phenomenon (S5). Then, if it is determined that the defect in the semiconductor wafer is a known phenomenon, a message is displayed to not line out the semiconductor wafer. On the other hand, if it is determined that the defect in the semiconductor wafer is not a known phenomenon, a message is displayed to line out the semiconductor wafer and to have it analyzed by a human (S6).

[0025] Next, we will explain the system configuration of the semiconductor wafer determination system shown in Fig. 1. Fig. 2 is a diagram showing the system configuration of the semiconductor wafer determination system shown in Fig. 1. As shown in Fig. 2, the semiconductor wafer determination system includes a server device 10, a determination device 20, a measurement device 30, a stage controller 40, a prober 50, a semiconductor wafer 60, a chip 61, a movable stage 70, and probes 80a and 80b.

[0026] The server device 10 and the determination device 20 are connected to a network N. The determination device 20 and the measurement device 30 are connected by a control line. The determination device 20 and the stage controller 40 are connected by a control line. The measurement device 30 and the probes 80a and 80b are connected by signal lines for transmitting voltages, currents, and signals. The stage controller 40 and the operating stage 70 are connected by a control line.

[0027] The server device 10 performs supervised learning using training data on a multilayer neural network CNNB to generate a trained model M, and notifies the generated trained model M to the determination device 20. To perform supervised learning by deep learning using CNNB, a large amount of training data is required. For this reason, in this embodiment, a training image A is prepared in advance.

[0028] The training image A consists of an image and its correct answer data R of a semiconductor wafer in which a defect in the semiconductor wafer was determined to be a known phenomenon through functional testing of multiple chips on the semiconductor wafer in the past, and an image and its correct answer data R of a semiconductor wafer in which a defect in the semiconductor wafer was determined to be a known phenomenon through functional testing.

[0029] The judgment device 20 performs the following processes: receiving the functional test result data sent from the measuring device 30; converting the functional test result data into data to generate a defect tendency image 24f; inputting the defect tendency image 24f into the trained model M to judge whether or not the defect in the semiconductor wafer is a known phenomenon; and displaying whether or not the semiconductor wafer should be lined out of the manufacturing process based on the judgment result.

[0030] The measuring device 30 applies voltage and logic signals to the chip via the probes 80a and 80b, performs a function test on the chip, and transmits the result data of the function test to the determining device 20. The stage controller 40 controls the operating stage 70 and performs a process of bringing the chip 61 into contact with the probes 80a and 80b.

[0031] The prober 50 fixes the semiconductor wafer 60 to the upper surface of the prober 50. When fixing to the upper surface, for example, negative pressure is applied to the upper surface of the prober 50 to suction the semiconductor wafer 60. The semiconductor wafer 60 is a substrate made of silicon material, compound semiconductor material, or the like, on which chips are formed. The chip 61 is a large-scale integrated circuit manufactured on the semiconductor wafer 60. Note that a plurality of chips 61 (for example, 100 chips) are manufactured on the semiconductor wafer 60.

[0032] <Configuration of Server Device 10> Next, a description will be given of the configuration of the server device 10 shown in Fig. 2. Fig. 3 is a functional block diagram showing the configuration of the server device 10 shown in Fig. 2. Fig. 4 is a diagram showing an overview of generation of a trained model M by the server device 10 shown in Fig. 2.

[0033] 3, the server device 10 has a display unit 11, an operation unit 12, a communication I / F unit 13, a storage unit 14, and a control unit 15. The display unit 11 is a display device such as a liquid crystal panel or a display device, and the operation unit 12 is an input device such as a keyboard or a mouse. The communication I / F unit 13 is an interface unit for communicating with other devices such as a determination device 20.

[0034] The storage unit 14 is a storage device such as a hard disk drive or non-volatile memory, and stores the teacher image A, CNNB, and trained model M. The teacher image A is an image prepared in advance to allow CNNB to perform supervised learning. CNNB is a convolutional multilayer neural network for generating the trained model M. The trained model M is a model obtained as a result of performing supervised learning by deep learning using the teacher image A and ground truth data R (probability of a known phenomenon).

[0035] The control unit 15 is a control unit that performs overall control of the server device 10, and includes a learning processing unit 15a and a trained model transmission unit 15b. In practice, a trained model generation program including these is loaded into a CPU and executed, causing the learning processing unit 15a and the trained model transmission unit 15b to execute a trained model generation process including processes corresponding to each of them.

[0036] The learning processing unit 15a is a processing unit that performs supervised learning of deep learning using a teacher image A and correct answer data R as learning data. Specifically, as shown in Fig. 4, the teacher image A is input to CNNB, and backpropagation is performed based on the correct answer data R, for example, to repeat the supervised learning process of determining the weight of each path, thereby generating a learned model M. Note that the correct answer data R, i.e., the probability that it is a known phenomenon, can be assigned by the person performing the supervised learning.

[0037] The learned model transmission unit 15b is a processing unit that notifies the determination device 20 of the learned model M. The determination device 20 uses this learned model M to calculate the probability that the defect in the semiconductor wafer is a known phenomenon.

[0038] <Processing Procedure of Server Device 10> Next, a description will be given of the processing procedure of the server device 10. Fig. 5 is a flowchart showing the processing procedure of the server device 10 shown in Fig. 2. When a teacher image A is input (step S101), the server device 10 causes CNNB to perform supervised learning using the teacher image A and the correct answer data R (step S102).

[0039] If the predetermined termination condition is not met (step S103: No), the process returns to step S101, where a new training image A is input and the same process is repeated. If the predetermined termination condition is met (step S103: Yes), the trained model M is stored in the storage unit 14 (step S104), and the trained model M is transmitted to the determination device 20 (step S105), and the above series of processes is terminated.

[0040] <Configuration of Determination Device 20> Next, a description will be given of the configuration of the determination device 20 shown in Fig. 2. Fig. 6 is a functional block diagram showing the configuration of the determination device 20 shown in Fig. 2. As shown in Fig. 6, the determination device 20 has a display unit 21, an operation unit 22, a communication I / F unit 23, a storage unit 24, and a control unit 25.

[0041] The display unit 21 is a display device such as a liquid crystal panel or a display device, and the operation unit 22 is an input device such as a keyboard or a mouse. The communication I / F unit 23 is an interface unit for communicating with other devices such as the server device 10, the measurement device 30, and the stage controller 40.

[0042] The storage unit 24 is a storage device such as a hard disk drive or a nonvolatile memory, and stores functional test data 24a, map data 24b, product type parameters 24c, array data 24d, weighting parameters 24e, defect tendency image 24f, trained model M, and judgment result data 24g. The functional test data 24a is data of test results obtained by conducting a functional test on a chip.

[0043] The map data 24b is data that associates chip numbers with test numbers for which the chip functional test results fall outside a predetermined range, based on the functional test data 24a. The product type parameters 24c are parameters that associate the array column size, array row size, test numbers, and their weights when converting the map data 24b into array data 24d. The array data 24d is array data obtained by rearranging the map data 24b according to the product type parameters 24c.

[0044] The weighting parameter 24e is a parameter that associates a weight with the brightness of a monochrome grayscale image when generating a defect tendency image 24f from array data 24d weighted by the product type parameter 24c. The defect tendency image 24f is generated from array data 24d using the brightness of the monochrome grayscale image associated by the weighting parameter 24e. The trained model M is a trained model that has undergone supervised training in the server device 10. The determination result data 24g is data obtained by inputting the defect tendency image 24f into the trained model M, calculating the probability of whether or not it is a known phenomenon, and determining whether or not it is a known phenomenon.

[0045] Here, we will explain the layer structure of the trained model M. The trained model M shown in Figure 7 is a diagram showing an example of the layer structure of the trained model M, and here it has a convolution layer (Convolution) 91, a convolution layer (Convolution) 92, an average pooling layer (Average Pooling) 93, a convolution layer (Convolution) 94, an average pooling layer (Average Pooling) 95, a fully connected layer (Fully Connect) 96, a fully connected layer (Fully Connect) 97, and an output layer (Softmax) 98.

[0046] Convolutional layers 91, 92, and 94 generate feature maps by convolving filters with nearby nodes in the previous layer to extract local features. Average pooling layers 93 and 95 further reduce the feature maps output from the previous convolutional layer to create new feature maps in order to aggregate local features. In this way, the hidden layers of a CNN are formed by convolutional layers and average pooling layers.

[0047] The fully connected layers 96 and 97 connect the feature maps from which the feature portions have been extracted to one node and output values ​​converted by a predetermined activation function. This activation function can be a well-known technique such as ReLU (Rectified Linear Unit). The output layer 98 converts the output (feature variables) from the fully connected layer 97 into probabilities using a softmax function and outputs the probability of correct classification. A dropout layer can also be added to avoid overfitting. The basic structure of CNN is well-known technology, so a detailed explanation of it will be omitted here.

[0048] The control unit 25 is a control unit that performs overall control of the determination device 20, and includes a function test processing unit 25a, a test data conversion unit 25b, a determination unit 25c, and a determination result processing unit 25d. In practice, by loading these programs into a CPU and executing them, the function test processing unit 25a, the test data conversion unit 25b, the determination unit 25c, and the determination result processing unit 25d will execute the processes corresponding to them, respectively.

[0049] The function test processing unit 25a receives result data of the function test performed by the measuring device 30 and stores it in the storage unit as function test data 24a. The test data conversion unit 25b performs data conversion on the function test data 24a based on the map data 24b, the product type parameters 24c, the arrangement data 24d, and the weighting parameters 24e, and generates a defect tendency image 24f.

[0050] The determination unit 25c is a processing unit that determines whether a defect in a semiconductor wafer is a known phenomenon using the trained model M. Specifically, as shown in FIG. 8, the defect tendency image 24f is input to the trained model M, the probability of whether a defect in a semiconductor wafer that has undergone a functional test is a known phenomenon is calculated, and the calculated probability is used to determine whether the defect is a known phenomenon. For example, if the probability of the defect being a known phenomenon is 0.8 or more, the defect is determined to be a known phenomenon, and if the probability of the defect not being a known phenomenon is 0.8 or more, the defect is determined to be not a known phenomenon. Based on the determination result of whether the defect is a known phenomenon, the determination result processing unit 25d displays a message indicating that the semiconductor wafer should not be lined out if the defect is a known phenomenon, and a message indicating that the semiconductor wafer should be lined out and that a human analyzes the cause if the defect is not a known phenomenon.

[0051] Next, an example of the functional test data 24a will be described. Fig. 9 is a diagram showing an example of the functional test data 24a shown in Fig. 6. As shown in Fig. 9, wafer number, chip number, chip position X axis, chip position Y axis, test 1, test 2, test 3, test 4, and test 5 are associated with each other. The chip position represents the physical position of the chip on the semiconductor wafer when the horizontal direction of the semiconductor wafer is the X axis and the vertical direction is the Y axis.

[0052] Here, the wafer number "1" and chip number "1" are associated with chip position X-axis "1", chip position Y-axis "1", test 1 "-", test 2 "-", test 3 "-", test 4 "-", and test 5 "-". Note that the test number "-" indicates that a functional test has not been performed. Also, the wafer number "1" and chip number "2" are associated with chip position X-axis "11", chip position Y-axis "1", test 1 "-", test 2 "-", test 3 "-", test 4 "-", and test 5 "-".

[0053] The figure also shows a situation in which wafer number "1" and chip number "3" are associated with chip position X-axis "21", chip position Y-axis "1", test 1 "-", test 2 "-", test 3 "-", test 4 "-", and test 5 "-". The figure also shows a situation in which wafer number "1" and chip number "15" are associated with chip position X-axis "41", chip position Y-axis "11", test 1 "-", test 2 "-", test 3 "-", test 4 "-", and test 5 "-". The figure also shows a situation in which wafer number "1" and chip number "16" are associated with chip position X-axis "41", chip position Y-axis "11", test 1 "3.3", test 2 "1.52", test 3 "1.51", test 4 "0.1", and test 5 "1.51".

[0054] The diagram also shows a situation in which wafer number "1" and chip number "17" are associated with chip position X-axis "51," chip position Y-axis "11," test 1 "3.2," test 2 "1.51," test 3 "1.50," test 4 "0.2," and test 5 "1.52." The diagram also shows a situation in which wafer number "1" and chip number "18" are associated with chip position X-axis "61," chip position Y-axis "11," test 1 "3.3," test 2 "1.52," test 3 "1.52," test 4 "0.1," and test 5 "1.51." The diagram also shows a situation in which wafer number "2" and chip number "1" are associated with chip position X-axis "1," chip position Y-axis "1," test 1 "-," test 2 "-," test 3 "-," test 4 "-," and test 5 "-."

[0055] Also, it shows a situation where wafer number "2" and chip number "2" are associated with chip position X-axis "11", chip position Y-axis "1", test 1 "-", test 2 "-", test 3 "-", test 4 "-", and test 5 "-". Also, it shows a situation where wafer number "2" and chip number "3" are associated with chip position X-axis "21", chip position Y-axis "1", test 1 "-", test 2 "-", test 3 "-", test 4 "-", and test 5 "-".

[0056] Next, an example of the map data 24b will be described. Fig. 10 is a diagram showing an example of the map data 24b shown in Fig. 6. The map data 24b is data obtained by converting the test results of the function test data 24a shown in Fig. 9.

[0057] Specifically, when a measurement value in the functional test data 24a indicates a value outside the range of specified values, the test number is associated with the chip number. As shown in Figure 10, the test number "0" is associated with the chip number "1" of the wafer number "01." Also, the test number "0" is associated with the chip number "2" of the wafer number "01."

[0058] It also shows that test number "0" is associated with chip number "3" of wafer number "01." It also shows that test number "0" is associated with chip number "15" of wafer number "01." It also shows that test number "5" is associated with chip number "16" of wafer number "01."

[0059] It also shows that test number "5" is associated with chip number "17" of wafer number "01." It also shows that test number "5" is associated with chip number "18" of wafer number "01." It also shows that test number "0" is associated with chip number "1" of wafer number "02."

[0060] It also shows that the test number "0" is associated with the chip number "2" of the wafer number "02." It also shows that the test number "0" is associated with the chip number "3" of the wafer number "02." It also shows that the test number "0" is associated with the chip number "15" of the wafer number "02."

[0061] It also shows that test number "0" is associated with chip number "16" of wafer number "02". It also shows that test number "0" is associated with chip number "17" of wafer number "02". It also shows that test number "0" is associated with chip number "18" of wafer number "02". Test number "0" indicates a situation where no test has been performed, test number "1" indicates a situation where all test results are within the specified values ​​(good product), and test number "5" indicates a situation where test 4 is outside the specified values.

[0062] Next, an example of the product type parameters 24c and the array data 24d will be described. Fig. 11 is a diagram showing an example of the product type parameters 24c and the array data 24d shown in Fig. 6. As shown in Fig. 11(a), the product type parameters 24c indicate parameters used when converting the map data 24b into the array data 24d. Here, the array data size (number of columns), the array data size (number of rows), the test number, and the weight are associated with each other.

[0063] This example shows that the array data size is "11 columns" and "10 rows." It also shows that the weight "0" is associated with test number "0," the weight "0" is associated with test number "1," the weight "3" is associated with test number "2," the weight "1" is associated with test number "3," the weight "1" is associated with test number "4," and the weight "5" is associated with test number "5."

[0064] It also shows a situation in which a weight of "4" is assigned to test number "6", a weight of "2" to test number "7", a weight of "3" to test number "8", a weight of "2" to test number "9", and a weight of "1" to test number "10".

[0065] The array data 24d is generated for each semiconductor wafer and is generated by converting the map data 24b based on the product parameter 24c. Specifically, the data in the first row and first column of the array data 24d is "a 11 ", the data of chip number "1" in the map data 24b is "a 11 Then, the data of chip number "2" in the map data 24b is converted into "a 12 Thereafter, the data of the map data 24b is converted into the array data 24d in the same manner, and the data of the chip number "12" is converted into "a 21 11(b), the array data 24d is converted into "a" in which the data of chip number "1" of wafer number "01" in the map data 24b is 11 ” is converted into the test number “0”. In addition, the data of the chip number “2” of the wafer number “01” in the map data 24b is converted into the array data 24d “a 12 " is converted to test number "0".

[0066] Also, the data of chip number "3" of wafer number "01" in map data 24b is "a 13 The data of the wafer number "01" and the chip number "15" in the map data 24b are converted into the test number "0" in the array data 24d. 24 The data of the wafer number "01" and the chip number "16" in the map data 24b are converted into the test number "0" in the array data 24d. 25 The figure shows the data being converted as test number "5".

[0067] Also, the data of chip number "17" of wafer number "01" in the map data 24b is a 26The data of the wafer number "01" and the chip number "18" in the map data 24b are converted into the test number "5" in the array data 24d. 27 The figure shows a situation where data conversion is performed with test number "5" in the array data 24d. Similar conversion is performed for the rest of the data up to chip number "110" of wafer number "01", which is the last chip. Note that weights (not shown) are also stored in the array data 24d together with the test numbers.

[0068] Next, an example of the weighting parameter 24e and the defect tendency image 24f will be described. Fig. 12 is a diagram showing an example of the weighting parameter 24e and the defect tendency image 24f shown in Fig. 6. As shown in Fig. 12(a), the weighting parameter 24e associates the luminance of the monochrome grayscale image with the weight of the product type parameter 24c. Here, a situation is shown in which a luminance of "255" is associated with a weight of "0". Also, a situation is shown in which a luminance of "255" is associated with a weight of "1".

[0069] Also, a situation is shown in which a weight of "2" corresponds to a luminance of "204." Also, a situation is shown in which a weight of "3" corresponds to a luminance of "153." Also, a situation is shown in which a weight of "4" corresponds to a luminance of "102." Also, a situation is shown in which a weight of "5" corresponds to a luminance of "0."

[0070] The defect tendency image 24f is an image generated from the brightness of the monochrome grayscale image based on the weighting parameter 24e for the weight of the array data 24d. As shown in FIG. 12(b), the defect tendency image 24f is an image generated from the brightness of the monochrome grayscale image based on the weighting parameter 24e for the weight of the array data 24d. 11 The data of the array data 24d is converted to a brightness of "255" and converted to white data. 12 This shows the situation where the data is converted to a brightness of "255" and converted to white data.

[0071] Also, a in sequence data 24d 13The data of the array data 24d is converted to a brightness of "255" and converted to white data. 24 The data of the array data 24d is converted to a brightness of "255" and converted to white data. 25 This shows the situation where the data is converted to a brightness of "0" and converted to black data.

[0072] Also, a in sequence data 24d 26 The data of the array data 24d is converted to a brightness of "0" and converted to black data. 27 The data of the array data 24d is converted to a brightness of "0" and converted to black data. 1011 The same conversion is performed on the data.

[0073] Next, an example of the determination result data 24g will be described. Fig. 13 is a diagram showing an example of the determination result data 24g shown in Fig. 6. As shown in Fig. 13, a situation is shown in which "Image 1" of the defect tendency image 24f is associated with a probability of "0.82" that it is a known phenomenon, a probability of "0.18" that it is not a known phenomenon, and a determination result of "known phenomenon."

[0074] Also, a situation is shown in which "Image 2" of the defect trend image 24f is associated with a probability of "1.00" that it is a known phenomenon, a probability of "0.00" that it is not a known phenomenon, and a judgment result of "known phenomenon." Also, a situation is shown in which "Image 3" of the defect trend image 24f is associated with a probability of "1.00" that it is a known phenomenon, a probability of "0.00" that it is not a known phenomenon, and a judgment result of "known phenomenon." Also, a situation is shown in which "Image 4" of the defect trend image 24f is associated with a probability of "0.998" that it is a known phenomenon, a probability of "0.002" that it is not a known phenomenon, and a judgment result of "known phenomenon."

[0075] The figure also shows a situation in which "Image 5" of the defect trend image 24f is associated with a probability of "0.00" that it is a known phenomenon, a probability of "1.00" that it is not a known phenomenon, and a judgment result of "not a known phenomenon." The figure also shows a situation in which "Image 6" of the defect trend image 24f is associated with a probability of "0.002" that it is a known phenomenon, a probability of "0.998" that it is not a known phenomenon, and a judgment result of "not a known phenomenon." The figure also shows a situation in which "Image 7" of the defect trend image 24f is associated with a probability of "0.00" that it is a known phenomenon, a probability of "1.00" that it is not a known phenomenon, and a judgment result of "not a known phenomenon." The figure also shows a situation in which "Image 8" of the defect trend image 24f is associated with a probability of "0.00" that it is a known phenomenon, a probability of "1.00" that it is not a known phenomenon, and a judgment result of "not a known phenomenon."

[0076] Next, the processing procedure of the determination device 20 will be described. Figures 14 and 15 are flowcharts showing the processing procedure of the determination device 20 shown in Figure 6. The determination device 20 performs a function test on all chips on a semiconductor wafer and stores function test data 24a in a storage unit (step S201). Next, the determination device 20 calculates the yield rate and detects whether defective chips are locally concentrated in a part of the wafer surface based on the function test data 24a (step S202).

[0077] If the yield rate is not 80% or less or if there is no local concentration of defective chips (step S203: No), the determination device 20 displays a message not to line out the semiconductor wafer (step S209) and ends the series of processes. If the yield rate is 80% or less or if there is local concentration of defective chips (step S203: Yes), the determination device 20 converts the stored function test data 24a into map data 24b (step S204).

[0078] Next, the map data 24b is converted into array data 24d based on the product type parameters 24c (step S205). The array data 24d is then converted based on the weighting parameters 24e to generate a defect tendency image 24f (step S206). The defect tendency image 24f is then input to the trained model M, and it is determined whether or not the defect is a known phenomenon (step S207).

[0079] If the determination result is a known phenomenon (step S208: Yes), the determination device 20 displays a message to not line out the semiconductor wafer (step S209), and ends the series of processes. If the determination result is not a known phenomenon (step S208: No), the determination device 20 displays a message to line out the semiconductor wafer and perform cause analysis by a human, and ends the series of processes.

[0080] As described above, in this embodiment, a functional test is performed on multiple chips formed on a semiconductor wafer after wafer processing, a defect tendency image 24f is generated based on the functional test data 24a, the defect tendency image 24f is input to the trained model M, a determination is made as to whether or not the defect in the semiconductor wafer is a known phenomenon, and based on the determination result, a display is made as to whether or not the semiconductor wafer should be lined out. Therefore, if the defect in the semiconductor wafer is a known phenomenon, the semiconductor wafer does not need to be lined out unnecessarily, making it possible to prevent a decrease in manufacturing efficiency.

[0081] In the above embodiment, the determination device 20 performs determination using a trained model M that has undergone deep learning using CNN. However, the present invention is not limited to this, and a trained model generated by machine learning other than deep learning can also be used. For example, a trained model generated using gradient boosting machine learning based on a decision tree algorithm can be used. Furthermore, instead of using a trained model, the determination device 20 can also perform determination using commercially available software such as Microsoft Excel (registered trademark) with an analysis tool added in, or a newly programmed dedicated app. In these cases, the server device 10 provides the trained model, commercially available software, or dedicated app to the determination device 20.

[0082] The configurations illustrated in the above embodiments are merely functional schematics and are not necessarily physically configured as shown. In other words, the distribution and integration of each device is not limited to that illustrated, and all or part of the devices can be functionally or physically distributed and integrated in any unit depending on various loads, usage conditions, etc. [Industrial Applicability]

[0083] The semiconductor wafer judgment device, semiconductor wafer judgment system, and semiconductor wafer judgment method according to the present invention are suitable for efficiently judging whether or not a defect in a semiconductor wafer on which multiple chips are formed is a known phenomenon, and for preventing a decrease in manufacturing efficiency due to unnecessary line-out of semiconductor wafers. [Explanation of symbols]

[0084] A Teacher's Image BCNN M trained models N Network R correct answer data 10 Server device 11 Display section 12 Control section 13 Communication I / F section 14 Storage section 15 Control Unit 15a Learning processing unit 15b Trained model transmission unit 20 Judgment device 21 Display section 22 Control section 23 Communication I / F section 24 Memory section 24a Functional Test Data 24b map data 24c Variety Parameters 24d sequence data 24e Weighting parameters 24f Defect Trend Image 24g Judgment result data 25 Control Unit 25a Functional test processing section 25b Test data conversion section 25c Judgment section 25d Judgment result processing section 30 Measuring Equipment 40 Stage Controller 50 Prober 60 semiconductor wafers 61 chips 70 Operating Stages 80a, 80b probes 91, 92, 94 Convolutional Layers 93, 95 Average Pooling Layer 96, 97 All imaging layers 98 Output Layer

Claims

1. A semiconductor wafer determination device for determining whether or not a semiconductor wafer on which a plurality of integrated circuits are formed is to be lined out, a function test means for performing a function test to determine whether the plurality of integrated circuits are non-defective; a determining means for determining whether or not the defect in the semiconductor wafer is a known phenomenon when the plurality of integrated circuits do not satisfy a predetermined condition in the functional test; a notification means for notifying that the semiconductor wafer is to be removed from the line when the determination means determines that the defect in the semiconductor wafer is not a known phenomenon; Equipped with The predetermined condition is: A semiconductor wafer judgment device characterized in that the ratio of integrated circuits judged to be good among the plurality of integrated circuits is less than a predetermined threshold, or the integrated circuits judged to be defective among the plurality of integrated circuits are present in a predetermined local area.

2. The determination means 2. The semiconductor wafer judgment device according to claim 1, wherein the device judges whether or not a defect in the semiconductor wafer is a known phenomenon using a trained model obtained by deep learning a multilayer neural network through supervised learning.

3. The trained model is 3. The semiconductor wafer judgment device according to claim 2, wherein the first teacher data is composed of an image of a semiconductor wafer having a defect of a known phenomenon and its correct answer data, and the second teacher data is composed of an image of a semiconductor wafer having a defect of an unknown phenomenon and its correct answer data, and the first teacher data is generated by applying the first teacher data to the multilayer neural network to perform supervised learning.

4. A semiconductor wafer determination system including a semiconductor wafer determination device that determines whether or not a semiconductor wafer on which a plurality of integrated circuits are formed is to be lined out, and a server device that can communicate with the semiconductor wafer determination device, The server device a generation means for applying first training data consisting of an image of a semiconductor wafer having a defect of a known phenomenon and its supervised data, and second training data consisting of an image of a semiconductor wafer having a defect of an unknown phenomenon and its supervised data to a multilayer neural network to generate a trained model by performing supervised learning; a notification means for notifying the semiconductor wafer evaluation device of the trained model generated by the generation means; Equipped with The semiconductor wafer evaluation device includes: a function test means for performing a function test to determine whether the plurality of integrated circuits are non-defective; a determination means for determining whether a defect in the semiconductor wafer is a known phenomenon using the trained model when the plurality of integrated circuits do not satisfy a predetermined condition in the functional test; a notification means for notifying that the semiconductor wafer is to be removed from the line when the determination means determines that the defect in the semiconductor wafer is not a known phenomenon; A semiconductor wafer evaluation system comprising:

5. 1. A semiconductor wafer evaluation method in a semiconductor wafer evaluation system having a semiconductor wafer evaluation device that determines whether or not a semiconductor wafer on which a plurality of integrated circuits are formed is to be lined out, and a server device that can communicate with the semiconductor wafer evaluation device, comprising: a generation step in which the server device applies first training data consisting of an image of a semiconductor wafer having a defect of a known phenomenon and its supervised data and second training data consisting of an image of a semiconductor wafer having a defect of an unknown phenomenon and its supervised data to a multilayer neural network to generate a trained model; a notification step in which the server device notifies the semiconductor wafer evaluation device of the trained model generated by the generation step; a function test step in which the semiconductor wafer evaluation device performs a function test to determine whether the plurality of integrated circuits are non-defective; a determination step in which the semiconductor wafer determination device determines whether or not a defect in the semiconductor wafer is a known phenomenon using the trained model when the plurality of integrated circuits do not satisfy a predetermined condition through the functional test; a notification step in which the semiconductor wafer determination device notifies the user that the semiconductor wafer is to be lined out when the determination step determines that the defect in the semiconductor wafer is not a known phenomenon; A semiconductor wafer evaluation method comprising:

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