Selector-only memory write operation

Abstract

An apparatus, method and memory system are provided. A memory system eliminates threshold voltage (Vth) drift in threshold-switching memory elements prior to programming by applying first and second voltages of opposite polarities to all selector-only memory (SOM) cells to be programmed, and then applying two programming voltages of two polarities to program the cells into two states.

Description

[Technical Field]

[0001] Memories are widely used in various electronic devices, such as mobile phones, digital cameras, personal digital assistants, medical electronic devices, mobile computing devices, non-mobile computing devices, and data servers. Memory can include non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a power source (e.g., a battery).

[0002] The memory cells may reside in a cross-point memory array. In a memory array having a cross-point architecture, a first set of conductive lines extends across the surface of a substrate, and a second set of conductive lines is formed on top of the first set of conductive lines and extends across the substrate in a direction perpendicular to the initial layer. The memory cells are located at the cross-point junctions of the two sets of conductive lines. A cross-point memory array is sometimes referred to as a crossbar memory array.

[0003] One type of memory cell includes a programmable resistive memory element, such as a magnetoresistive memory element. Magnetoresistive random access memory (MRAM) cells use magnetization to represent stored data. Bits of data are written to an MRAM cell by changing the magnetization direction of the magnetic element ("free layer") in the MRAM cell, and the bits are read by measuring the resistance of the MRAM cell, which varies with the direction of magnetization. However, cross-point memory arrays can have other types of memory cells. For example, cross-point memory arrays can have memory cells of other technologies, such as ReRAM, PCM (Phase Change Memory), and FeRAM.

[0004] In some cross-point memory architectures, each memory cell includes a threshold selector in series with a programmable resistive memory element. In such architectures, the programmable resistive memory element is programmed to store data, while the threshold selector is used to select the memory cell. The threshold selector has a high resistance (off or non-conducting state) until it is biased to a voltage above its threshold voltage (Vt) or a current above its threshold current (It), and until its voltage bias drops below Vhold ("Voffset") or a current below a holding current Ihold. After Vt is exceeded, and while Vhold is exceeded across the threshold selector, the threshold selector has a relatively low resistance (on or conducting state). The threshold selector remains on until its current is reduced to Ihold, which is less than the holding current, or the voltage is reduced to Vhold, which is less than the holding voltage. When this occurs, the threshold selector returns to its off (high) resistance state. One example of a threshold selector is the Ovonic Threshold Switch (OTS). Other examples of threshold switching selectors include, but are not limited to, Volatile Conductive Bridge (VCB), Metal-Insulator-Metal (MIM), or other materials that provide a highly nonlinear dependence of current on select voltage.

[0005] In some cross-point architectures, memory cells include threshold-switching selectors that are used as both selectors and programmable memory elements. Such architectures may be referred to as either selector-only memory (SOM) cells or self-selecting memory cells. The threshold voltage (Vth) of an SOM cell when read with a voltage of a given polarity may depend on the polarity of the write voltage used to program the SOM cell. SOM cells that are written and read with voltages of the same polarity may exhibit a lower Vth than SOM cells that are written and read with voltages of the opposite polarity. The memory system may assign a default polarity to the read voltage, which allows SOM cells to be programmed to a first state using a write voltage of a first polarity and to a second state using a write voltage of a second polarity opposite the first polarity.

[0006] However, over time, the Vth of a threshold switching selector can drift, which presents a technical challenge. FIG. 1A shows a graph of the threshold voltage of a SOM cell over time. FIG. 1B is a table illustrating a conventional programming scheme used in conjunction with a SOM cell. In this programming scheme, state W0 is written with a voltage of the same polarity as the read voltage. However, state W1 is written with a voltage of the opposite polarity to the read voltage. Reads may be performed with a default polarity voltage. The read voltage polarity may be selected by the memory system but is the same for each read. Column 60 indicates the last voltage applied to the memory cell that resulted in firing the cell (e.g., switching on the selector). The up and down arrows in the table of FIG. 1B are used to indicate the relative polarities of the voltages. Column 62 indicates the new data being written to the cell.

[0007] Referring now to FIG. 1A, an SOM cell programmed to state W0 (with a "down polarity write voltage") and immediately read (with a "down polarity read voltage") has a Vth near star 20. An SOM cell programmed to state W1 (with an "up polarity write voltage") and immediately read (with a "down polarity read voltage") has a Vth near star 22. Plot 10 illustrates the upward drift in Vth of a W0 state cell. When read after a significant time delay (with a down polarity read voltage), the W0 cell may have a Vth near the B-level Vth, as indicated by arrow 30. When read after a significant time delay (with a down polarity read voltage), the W1 cell may have a Vth near the A-level Vth, as indicated by arrow 32. Vth column 64 of the table in FIG. 1B summarizes the Vth of a particular cell, which depends on the relative polarity of the last fire voltage (column 60) and the polarity of the write voltage (column 62). The cell with the last fire of W1 and the new data of W1 has voltages of the same polarity for these two voltages. Therefore, writing new data W1 sees a low Vth of B. However, the cell with the last fire of W1 and the new data of W0 has voltages of the opposite polarity for these two voltages. Therefore, writing new data W0 sees a low Vth of A. The cell with the last fire of W0 (or R0) and the new data of W1 has voltages of the opposite polarity for these two voltages. Therefore, writing new data W1 sees a high Vth of A. The cell with the last fire of W0 (or R0) and the new data of W0 has voltages of the same polarity for these two voltages. Therefore, writing new data W0 sees a low Vth of B.

[0008] Reading or programming memory cells in a crossbar architecture can encounter a "half-select" problem. When programming memory cells, a full program voltage is applied across selected memory cells. The memory system may apply 0V across some of the cells that are not to be programmed ("fully unselected cells"). However, in some techniques, the memory system applies half the program voltage across some of the cells that should not be programmed. Such cells are referred to as "half-selected cells." Depending on the Vth of the half-selected cells, the threshold switching selectors may undesirably switch on during a program operation. A similar half-select problem can occur during a read operation.

[0009] Referring again to FIG. 1A, the half-select (HS) margin is shown. The HS margin can be calculated as Vth_Max / 2-Vth_Min. In the example of FIG. 1A, Vth_Max is the maximum value of plot 12 ("A") and Vth_Min is the minimum value of plot 10. Therefore, the HS margin is the difference between dashed line 42 and dashed line 44. [Brief explanation of the drawings]

[0010] Similar numbered elements refer to common components in different figures.

[0011] [Figure 1A] 1 shows a graph of the threshold voltage of a SOM cell over time. [Figure 1B] 1 is a table illustrating a conventional programming scheme used in connection with a SOM cell. [Figure 2] FIG. 1 is a block diagram of one embodiment of a non-volatile memory system connected to a host. [Figure 3A] FIG. 2 is a block diagram of one embodiment of a memory die. [Figure 3B] FIG. 1 is a block diagram of one embodiment of an integrated memory assembly including a control die and a memory structure die. [Figure 4A]1 illustrates a perspective view of one embodiment of a portion of a memory array forming a cross-point architecture. [Figure 4B] 4B and 4C show side and top views, respectively, of the cross-point structure of FIG. 4A. [Figure 4C] 4B and 4C show side and top views, respectively, of the cross-point structure of FIG. 4A. [Figure 4D] 1 illustrates a perspective view of an embodiment of a portion of a two-level memory array forming a cross-point architecture. [Figure 5] 1 illustrates an embodiment of a structure of a SOM cell. [Figure 6A] 1 illustrates an embodiment for accessing a selected SOM cell in a cross-point memory structure. [Figure 6B] 1 illustrates an embodiment for accessing a selected SOM cell in a cross-point memory structure. [Figure 7] 10 is a flow chart of one embodiment of a process for programming a two-terminal threshold switching selector in a crosspoint array. [Figure 8] 1 shows two "Vth distributions" for an embodiment of programming a SOM cell. [Figure 9A] 10 is a table detailing one embodiment of programming SOM cells in a cross-point memory structure. [Figure 9B] 10 illustrates threshold voltage over time for an embodiment of operating a SOM cell in a cross-point memory architecture. [Figure 10] 1 is a flowchart of one embodiment of a process for programming a SOM cell in a cross-point memory structure. [Figure 11] 1 is a flowchart of one embodiment of a process for programming a SOM cell in a cross-point memory structure. [Figure 12] 1 is a flowchart of one embodiment of a process for programming a SOM cell in a cross-point memory structure. DETAILED DESCRIPTION OF THE INVENTION

[0012] Techniques for programming selector-only memory cells in a cross-point memory structure are disclosed. The threshold-switching memory elements may include, but are not limited to, Ovonic Threshold Switches (OTS). In one embodiment, a memory system eliminates Vth drift in the threshold-switching memory elements prior to programming. Eliminating Vth drift allows the memory system to use a lower magnitude for the program voltage. Reducing the magnitude of the program voltage reduces unintentional selection of half-selected memory cells. In one embodiment, Vth drift is eliminated by applying first and second voltages of opposite polarities to all of the SOM cells to be programmed. Two programming voltages of two polarities are then applied to program the cells into two states. Furthermore, the magnitude of the voltage used to eliminate Vth drift may be selected based on factors such as the expected Vth drift of the SOM cells.

[0013] Referring again to FIG. 1B , the High (or A) Vth in the Vth column 64 is a problem threshold voltage that could potentially result in erroneous selection of a half-selected memory cell. This is because the larger the “A level,” the smaller the HS margin. Embodiments of the programming process can reduce the Vth of the cell before programming so that such problem cases do not exist. Thus, the magnitude of the programming voltage can be reduced while still maintaining sufficient HS margin. Thus, erroneous selection of a half-selected memory cell is prevented or at least reduced.

[0014] In one embodiment, the memory system includes SOM cells residing in a cross-point memory array structure. In a memory array having a cross-point architecture, a first set of conductive lines extends across a surface of a substrate, and a second set of conductive lines is formed on top of the first set of conductive lines and extends across the substrate in a direction perpendicular to the first set of conductive lines. Memory cells are located at the cross-point junctions of the two sets of conductive lines. A cross-point memory array is sometimes referred to as a crossbar memory array.

[0015] As used herein, the terms "top" and "bottom," "upper" and "lower," and "vertical" and "horizontal," and their configurations, are by way of example and for illustration only, and are not intended to limit the description of the present technology, insofar as references may be interchanged in location and orientation. Also, as used herein, the terms "substantially," "approximately," and / or "about" mean that a specified dimension or parameter may vary within acceptable tolerances for a given application.

[0016] 2 is a block diagram of one embodiment of a non-volatile memory system (or more simply, "memory system") 100 connected to a host system 120. In one embodiment, the memory cells have threshold switching selectors, such as OTS. Many types of memory systems can be used with the techniques proposed herein. Exemplary memory systems include dual in-line memory modules (DIMMs), solid state drives ("SSDs"), memory cards, and embedded memory devices. However, other types of memory systems can also be used.

[0017] The memory system 100 of FIG. 2 includes a memory controller 102, a memory 104 for storing data, and a local memory (e.g., SOM, MRAM, ReRAM, DRAM) 140. The local memory 140 may be non-volatile and may retain data after power-off. The local memory 140 may be volatile and may not be expected to retain data after power-off. In one embodiment, the local memory 140 includes SOM cells. In one embodiment, the local memory does not need to retain data after power-off. However, the local memory may retain data after power-off. In one embodiment, the memory controller 102 and / or the local memory controller 164 provide access to the SOM cells in the local memory 140. For example, the memory controller 102 may provide access within a cross-point array of SOM cells in the local memory 140. In another embodiment, the memory controller 102 or the interface 126, or both, are eliminated, and the memory packages are directly connected to the host 120 through a bus such as a DDRn. Alternatively, they are connected to a host memory management unit (MMU). In another example, the memory controller 102 or portions thereof are moved onto the memory 104 for direct connection of the memory 104 to the host, such as by providing parity bits, ECC, and wear levels on the memory 104 along with a DDRn interface to / from the host or MMU. The term memory system as used throughout this specification is not limited to the memory system 100. For example, the local memory 140 or the combination of the local memory 140 and the local memory controller 164 can be considered a memory system. Similarly, the host memory 124 or the combination of the host processor 122 and the host memory 124 can be considered a memory system.

[0018] The components of the memory system 100 shown in FIG. 2 are electrical circuits. The memory controller 102 includes a host interface 152, a processor 156, an ECC engine 158, a memory interface 160, a local memory controller 164, refresh logic 172, and a wear level 174. The host interface 152 is connected to and communicates with the host 120. The host interface 152 is also connected to a network-on-chip (NOC) 154. The NOC is a communications subsystem on an integrated circuit. The NOC can span synchronous and asynchronous clock domains or use unlocked asynchronous logic. NOC technology applies networking theory and methods to on-chip communications, offering significant improvements over traditional bus and crossbar interconnects. Compared to other designs, NOCs improve the scalability of systems-on-chip (SoCs) and the power efficiency of complex SoCs. The wires and links of a NOC are shared by many signals. A high level of parallelism is achieved because all links within a NOC can operate on different data packets simultaneously. Thus, as the complexity of integrated subsystems continues to increase, the NOC provides improved performance (e.g., throughput) and scalability compared to previous communication architectures (e.g., dedicated point-to-point signal wires, shared buses, or segmented buses with bridges). In other embodiments, the NOC 154 can be replaced by a bus. The processor 156, ECC engine 158, memory interface 160, local memory controller 164, refresh logic 172, and wear level 174 are connected to and communicate with the NOC 154. The local memory controller 164 is used to operate and communicate with the local high-speed memory 140 (e.g., MRAM). In other embodiments, the local high-speed volatile memory 140 can be DRAM, SRAM, or another type of volatile memory.

[0019] ECC engine 158 performs error correction services. For example, ECC engine 158 performs data encoding and decoding of parity bits provided on or off memory as part of a codeword used for error correction of data fetched from memory 140 or 104. In one embodiment, ECC engine 158 is an electrical circuit programmed by software. For example, ECC engine 158 may be a processor that can be programmed. In other embodiments, ECC engine 158 is a custom, dedicated hardware circuit without any software. In one embodiment, the functionality of ECC engine 158 is implemented by processor 156. In one embodiment, local memory 140 includes an ECC engine, with or without a wear-level engine. In one embodiment, memory 104 includes an ECC engine, with or without a wear-level engine.

[0020] Processor 156 performs various controller memory operations, such as programming, erasing, reading, and memory management processes. Although a separate wear level 174 is shown, wear level 174 may be implemented by processor 156. Also, although refresh logic 172 is shown, refresh may be implemented by processor 156. In one embodiment, processor 156 is programmed by firmware. In another embodiment, processor 156 is a custom, dedicated hardware circuit without any software. Processor 156 also implements a translation module, either as a software / firmware process or as a dedicated hardware circuit. In many systems, non-volatile memory is addressed internally to the storage system using physical addresses associated with one or more memory dies. However, host systems use logical addresses to address various memory locations. This allows the host to assign data to consecutive logical addresses, while the storage system is free to store data between locations on one or more memory dies as desired. To implement this system, memory controller 102 (e.g., a translation module) performs address translation between the logical addresses used by the host and the physical addresses used by the memory dies. One exemplary implementation is to maintain a table (i.e., the L2P table described above) that identifies current translations between logical addresses and physical addresses. Entries in the L2P table may include identifiers for a logical address and a corresponding physical address. Although the logical address-to-physical address table (i.e., the L2P table) includes the word "table," it need not be a literal table. Rather, the physical address-to-logical address table (i.e., the L2P table) can be any type of data structure. In some examples, the memory space of the storage system is so large that local memory 140 cannot hold all of the L2P tables. In such cases, the entire set of L2P tables is stored in memory 104, and a subset of the L2P tables is cached in local high-speed memory 140 (the L2P cache).

[0021] Memory interface 160 communicates with memory device 104. In one embodiment, memory device 104 includes a cross-point array of SOM cells. In one embodiment, memory device 104 includes NAND memory cells. In one embodiment, the memory interface provides a toggle mode interface. Other interfaces may also be used. In some example implementations, memory interface 160 (or another portion of controller 102) implements a scheduler and buffers for sending and receiving data from one or more memory dies.

[0022] In one embodiment, local memory 140 includes an ECC engine. Local memory 140 can be used to perform other functions, such as wear leveling. Further details of on-chip memory maintenance are described in U.S. Patent No. 10,545,692, entitled "Memory Maintenance Operations During Refresh Window," and U.S. Patent No. 10,885,991, entitled "Data Rewrite During Refresh Window," both of which are incorporated herein by reference in their entireties. In one embodiment, local memory 140 is synchronous. In one embodiment, local memory 140 is asynchronous.

[0023] In one embodiment, the memory device 104 includes multiple memory packages. Each memory package includes one or more memory dies. Accordingly, the memory controller 102 is connected to one or more memory dies. In one embodiment, the memory packages may include types of memory such as storage class memory (SCM) based on programmable resistive random access memory (SOM, ReRAM, MRAM, FeRAM, or RRAM) or phase change memory (PCM). In one embodiment, the memory controller 102 provides access to memory cells in a cross-point array within the memory device 104.

[0024] The memory controller 102 communicates with the host system 120 via an interface 152 that implements a protocol such as Compute Express Link (CXL). Alternatively, such a controller can be eliminated and the memory package placed directly on a host bus, such as DDRn or CXL. To interact with the memory system 100, the host system 120 includes a host processor 122, a host memory 124, and an interface 126, connected along a bus 128. The host memory 124 is the host's physical memory and can be a SOM, DRAM, SRAM, ReRAM, MRAM, non-volatile memory, or another type of storage. In one embodiment, the host memory 124 includes a cross-point array of programmable resistive memory cells, each with a threshold-switching selector that functions as a SOM.

[0025] Host system 120 is external to and separate from memory system 100. In one embodiment, memory system 100 is embedded within host system 120. Host memory 124 may be referred to herein as a memory system. The combination of host processor 122 and host memory 124 may be referred to herein as a memory system. In one embodiment, such host memory may be a cross-point memory using SOM cells.

[0026] FIG. 3A is a block diagram illustrating an example of a memory die 292 capable of implementing the techniques described herein. In one embodiment, the memory die 292 is included in the local memory 140, and in one embodiment, the memory die 292 is included in the storage device 104. In one embodiment, the memory die 292 is included in the host memory 124. The memory die 292 includes a memory structure 202 that can include any of the memory cells described below. The memory structure 202 can include one or more memory arrays. The array demarcation lines of the memory structure 202 include various layers of word lines organized as rows and various layers of bit lines organized as columns. However, other orientations, including, for example, diagonal patterns, can also be implemented to conserve space. The memory die 292 includes a row control circuit 220, whose output 208 is connected to each word line of the memory structure 202. The row control circuitry 220 receives a group of M row address signals and one or more various control signals from the system control logic circuitry 260 and typically includes circuits such as a row decoder 222, a row driver 224, and a block select circuitry 226 for both read and write operations. The row control circuitry 220 may also include read / write circuitry. In one embodiment, the row decode and control circuitry 220 has sense amplifiers 228, each including circuitry for sensing the state (e.g., voltage) of a word line of the memory structure 202. In one embodiment, by sensing the word line voltage, the condition or bit state of a memory cell (e.g., a SOM cell) in the cross-point array is determined, either directly or by a sense amplifier comparing the accessed memory cell voltage to a reference voltage. The memory die 292 also includes a column decode and control circuitry 210, whose input / output 206 is connected to each bit line of the memory structure 202. Although only a single block is shown for the memory structure 202, a memory die may include multiple arrays, or "tiles," that can be individually accessed.The column control circuitry 210 receives a group of N column address signals and one or more various control signals from the system control logic 260 and may typically include circuits such as a column decoder 212, a column decoder or driver 214, a block select circuitry 216, and read / write circuits and I / O multiplexers.

[0027] System control logic 260 receives data and commands from the host system and provides output data and status to the host system. In other embodiments, system control logic 260 receives data and commands from a separate controller circuit and provides output data to that controller circuit, which communicates with the host system. Such a controller system may implement an interface such as DDR, DIMM, CXL, PCIe, etc. In another embodiment, these data and commands are sent and received directly from the memory package to the host without a separate controller, with any required controller being within each die or an additional die in a multi-chip memory package. In some embodiments, system control logic 260 includes a state machine 262 that provides die-level control of memory operations. In one embodiment, state machine 262 is programmable by software. In other embodiments, state machine 262 is implemented entirely in hardware (e.g., electrical circuitry) without the use of software. In another embodiment, state machine 262 is replaced by a microcontroller or microprocessor. The system control logic 260 may also include a power control module 264 that controls the power, current source currents, and voltages supplied to the rows and columns of the memory structure 202 during memory operations, and may include charge pump and regulator circuits for creating regulated voltages and respective on / off controls for wordline and bitline selection of the memory cells. In some embodiments, the power control 264 includes one or more current sources. The current sources may be used to provide read and / or write currents. The system control logic 260 includes a storage device 266 that may be used to store parameters for operating the memory structure 202. The system control logic 260 also includes refresh logic 272 and wear leveling logic 274. Such system control logic may be commanded by the host 120 or memory controller 102 to the refresh logic 272, which may load on-chip stored row and column addresses (pointers) that may be incremented after a refresh.Such address bits can simply be selected (to refresh the OTS), or such addresses can be read, corrected by steering through the ECC engine 269, and then stored in a "spare" location that is also effectively incremented to the wear level (so all codewords are periodically read, corrected, and relocated across the chip under control of the wear leveling logic 274), so that usage of each bit across the chip is more uniform. Such operations can be more directly controlled by an external controller, for example, a host of PCIe or CXL or DDRn controllers located separately from the memory chip or on the memory die.

[0028] Commands and data are transferred between the memory controller 102 and the memory die 292 via a memory controller interface 268 (also referred to as a "communications interface"). Such an interface may be, for example, PCIe, CXL, or DDRn. The memory controller interface 268 is an electrical interface for communicating with the memory controller 102. An example of the memory controller interface 268 includes a toggle mode interface. Other I / O interfaces may also be used. For example, the memory controller interface 268 may implement a toggle mode interface that connects to a toggle mode interface of the memory interface 228 / 258 for the memory controller 102. In one embodiment, the memory controller interface 268 includes a set of input and / or output (I / O) pins that connect to the controller 102. In another embodiment, the interface is a JEDEC standard DDRn or LPDDRn, such as DDR5 or LPDDR5, or a subset thereof with smaller pages and / or relaxed timing.

[0029] The system control logic 260, located in a controller on a memory die within a memory package, may include an error correction code (ECC) engine 269. The ECC engine 269 may be referred to as an on-die ECC engine because it is on the same semiconductor die as the memory cells. That is, the on-die ECC engine 269 may be used to encode data and parity bits to be stored in the memory structure 202, decode the decoded data, and correct errors. The encoded data may be referred to herein as a codeword or an ECC codeword. The ECC engine 269 may be used to execute a decoding algorithm and perform error correction. Thus, the ECC engine 269 may decode the ECC codeword. In one embodiment, the ECC engine 269 can decode data more quickly by decoding directly without iterations. Having the ECC engine 269 on the same die as the memory cells enables faster decoding. The ECC engine 269 can use a wide variety of decoding algorithms, including, but not limited to, Reed-Solomon, Bose-Chaudhuri-Hocquenghem (BCH), and Low-Density Parity Check (LDPC).

[0030] In some embodiments, all of the elements of memory die 292, including system control logic 260, may be formed as part of a single die. In other embodiments, some or all of system control logic 260 may be formed on a different die, such as an external controller chip.

[0031] In one embodiment, memory structure 202 comprises a three-dimensional memory array of non-volatile or volatile memory cells, with multiple memory levels formed on a single substrate, such as a wafer. The memory structure may comprise any type of non-volatile or volatile memory monolithically formed in one or more physical levels of memory cells having active areas disposed on a silicon or silicon-on-insulator (or other type) substrate. In another embodiment, memory structure 202 comprises a two-dimensional memory array of non-volatile memory cells.

[0032] The exact types of memory array architectures or memory cells included in memory structure 202 are not limited to the examples above. Many different types of memory array architectures or memory technologies can be used to form memory structure 202. No particular non-volatile memory technology is required for purposes of the newly claimed embodiments presented herein. Examples of technologies suitable for memory cell architectures in memory structure 202 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit line arrays, etc.

[0033] An example of a SOM cross-point memory is an OTS selector / memory element arranged in a cross-point array accessed by X- and Y-lines (e.g., word lines and bit lines). In another embodiment, the memory cell may include a conductive bridge memory element. A conductive bridge memory element may also be referred to as a programmable metallization cell. A conductive bridge memory element may be used as a state-change element based on the physical rearrangement of ions in a solid electrolyte. In some cases, a conductive bridge memory element may include two solid metal electrodes with a thin solid electrolyte film between the two electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper). As temperature increases, the mobility of ions also increases, lowering the programming threshold of the conductive bridge memory cell. Therefore, a conductive bridge memory element may have a wide range of programming thresholds over temperature.

[0034] In some embodiments, the memory structure includes phase change memory (PCM). Phase change memory (PCM) exploits the unique behavior of chalcogenide glasses. One embodiment uses a GeTe-Sb2Te3 superlattice to achieve a non-thermal phase change by simply changing the coordination state of germanium atoms with a laser pulse (or light pulse from another light source). Memory cells are programmed with current pulses that can change the coordination of the PCM material or switch it between amorphous and crystalline states. The use of "pulse" herein does not require a square pulse, but includes vibrations or bursts of sound (continuous or non-continuous), current, voltage, light, or other waves. Additionally, the current forced to write can be rapidly driven to a peak value and then linearly ramped down, for example, with an edge rate of 500 ns. Forcing such peak currents can be limited by zoned voltage standards that vary depending on the location of the memory cell along the word line or bit line. In one embodiment, a phase change memory cell includes a phase change memory element in series with a threshold switching selector, such as an OTS.

[0035] Those skilled in the art will appreciate that the technology described herein is not limited to a single particular memory structure, memory architecture, or material composition, but rather covers many related memory structures within the spirit and scope of the technology as described herein and as understood by those skilled in the art.

[0036] The elements in FIG. 3A can be grouped into two parts: the memory structure 202 and the peripheral circuitry, which includes all of the other elements. An important characteristic of a memory circuit is its capacity, which can be increased by increasing the area of ​​the memory die 292 devoted to the memory structure 202. However, this reduces the area of ​​the memory die available for peripheral circuitry or increases the cost associated with the chip area. This can impose very severe limitations on these peripheral elements. For example, the need to fit sense amplifier circuitry within the available area can place significant constraints on the sense amplifier design architecture. With respect to the system control logic 260, reduced area availability can limit the available functionality that can be implemented on-chip. As a result, the amount of area devoted to the memory structure 202 and the amount of area devoted to the peripheral circuitry are fundamental tradeoffs in the design of the memory die 292. Such tradeoffs can result in more IR drop by using a larger xy array of memory between the driver circuits on the word lines and bit lines, which can benefit more from the use of voltage limits and voltage-compliant zoning by memory cell location along the word lines and bit lines.

[0037] Another area where memory structures 202 and peripheral circuits often conflict is in the processes involved in forming these regions, as these regions often involve different process technologies and the trade-offs of having different technologies on a single die. For example, such sense amplifier circuits, charge pumps, logic elements in state machines, and other peripheral circuits in system control logic 260 often use PMOS devices. In some cases, memory structures will be based on CMOS devices. Process operations for fabricating CMOS dies differ in many aspects from process operations optimized for NMOS-only technologies.

[0038] To ameliorate these limitations, the embodiments described below can separate the elements of FIG. 3A onto separately formed dies, which are then bonded together. FIG. 3B shows an integrated memory assembly 270 having a memory structure die 280 and a control die 290. The memory structure 202 is formed on the memory structure die 280, and some or all of the peripheral circuit elements, including one or more control circuits, are formed on the control die 290. For example, the memory structure die 280 can be formed solely of memory elements, such as arrays of SOM cells or other memory types of memory cells. Some or all of the peripheral circuitry, even if it includes elements such as decoders and sense amplifiers, can then be moved to the control die. This allows each semiconductor die to be individually optimized according to its technology. This allows more space for peripheral elements, which can incorporate additional functionality that could not easily be incorporated if the die were limited by the margins of the same die holding the memory cell array. The two dies can then be bonded together in a bonded multi-die integrated memory assembly, with the array on one die connected to the peripheral elements on the other die. The following focuses on an integrated memory assembly of one memory die and one control die, although other embodiments may use additional dies, such as two memory dies and one control die.

[0039] 3A, memory structure die 280 of FIG. 3B includes memory structure 202, which may include multiple independently accessible arrays or "tiles." System control logic 260, row control circuitry 220, and column control circuitry 210 are located within control die 290. In some embodiments, all or a portion of column control circuitry 210 and all or a portion of row control circuitry 220 are located on memory structure die 280. In some embodiments, some of the circuitry in system control logic 260 is located on memory structure die 280.

[0040] 3B shows column control circuitry 210 on control die 290 coupled to memory structures 202 on memory structure die 280 through electrical pathways 293. For example, electrical pathways 293 may provide electrical connections between column decoder 212, driver circuitry 214, and block select 216 and the bit lines of memory structure 202. The electrical pathways may extend from column control circuitry 210 in control die 290 through pads on control die 290 that are bonded to corresponding pads on memory structure die 280 that are connected to the bit lines of memory structure 202. Each bit line of memory structure 202 may have a corresponding electrical pathway within electrical pathway 293 that includes a pair of bond pads that connect to column control circuitry 210. Similarly, row control circuitry 220, including row decoder 222, row driver 224, block select 226, and sense amplifier 228, is coupled to memory structure 202 through electrical pathways 294. Each of electrical pathways 294 may correspond to a word line, for example. Additionally, additional electrical paths may be provided between the control die 290 and the memory structure die 280 .

[0041] For purposes of this document, the phrase "control circuitry" may include one or more of the memory controller 102, local memory controller 164, processor 156, system control logic 260, column control circuitry 210, row control circuitry 220, host processor 122, a microcontroller, a state machine, and / or other control circuitry or similar circuitry used to control non-volatile memory. A control circuitry may include hardware alone or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of a control circuitry. A control circuitry may include a processor, FPGA, ASIC, integrated circuit, or other type of circuitry. Such control circuitry may include a driver, such as a direct drive by connecting a node through a transistor (gate to power supply) that drives to a certain voltage, such as a power supply. Such control circuitry may include a current source driver.

[0042] As used herein, the term "device" may include, but is not limited to, one or more of memory system 100, local memory 140, local memory controller 164 and / or a combination of memory controller 102 and local memory 140, storage device 104, memory die 292, integrated memory assembly 270, and / or control die 290.

[0043] In the following discussion, the memory structure 202 of FIGS. 3A and 3B will be considered in the context of a cross-point architecture. A cross-point architecture includes a first set of conductive lines or wires, such as word lines, that extend in a first direction relative to the underlying substrate, and a second set of conductive lines or wires, such as bit lines, that extend in a second direction relative to the underlying substrate. Memory cells are located at the intersections of the word lines and bit lines. The memory cells at these cross-points can be formed according to any of several techniques, including those described above. The following discussion will primarily focus on embodiments based on a cross-point architecture using SOM cells, each having a threshold-switching selector, such as an Ovonic Threshold Switch (OTS), to configure a selectable memory bit. However, embodiments are not limited to the selectors being OTS.

[0044] FIG. 4A shows a perspective view of one embodiment of a portion of a memory array 402 forming a cross-point architecture. The memory array 402 of FIG. 4A is an example of an implementation of the memory structure 202 of FIG. 3A or 3B, and the memory die 292 or memory structure die 280 can include multiple such memory arrays 402. The memory array 402 can be included in the local memory 140 or the host memory 124. The bit lines BL1-BL5 are arranged in a first direction (represented as extending into the page) relative to a substrate (not shown) underlying the die, and the word lines WL1-WL5 are arranged in a second direction (across the page) perpendicular to the first direction, or diagonally to provide crossovers where memory cells are interconnected between the WL and BL. FIG. 4A illustrates an embodiment in which the word lines WL1-WL5 and BL1-BL5 both extend horizontally relative to the substrate, while the memory cells, two of which are shown at 401, are arranged to provide a current (I cell 4D ) is oriented to flow vertically. In a memory array with additional layers of memory cells, such as those discussed below with respect to FIG. 4D , there are corresponding additional layers of bit lines and word lines. One pattern, for example, from the bottom layer: WL, memory cell, BL, memory cell, WL, WL, memory cell, BL, memory cell, WL.

[0045] As shown in FIG. 4A, memory array 402 includes a plurality of memory cells 401. Memory cells 401 may include rewritable memory elements, such as may be implemented using a switching threshold selector that can be operated to have a programmable resistance. Memory cells 401 may be referred to herein as programmable resistance memory cells. Memory cells 401 may also be referred to herein as self-selecting memory cells or selector-only memory cells. The switching threshold selector may be implemented using an ovonic threshold switch (OTS), a volatile conductive bridge (VCB), a metal-insulator-metal (MIM), or other materials that provide a highly nonlinear dependence of current or resistance on various select voltages. While the following discussion focuses on memory cells comprised of OTS memory elements, much of the discussion is more generally applicable. Current in memory cells of the first memory level is indicated by arrow I. cell Although shown as flowing upward as indicated by , current can flow in either direction to write or read the memory cell bit state, as discussed in more detail below.

[0046] 4B and 4C show side and top views, respectively, of the cross-point structure of FIG. 4A. The side view of FIG. 4B shows one bottom wire, i.e., word line WL1, and top wires, i.e., bit lines BL1-BL2. n At the cross-point between each top wire and bottom wire, there is a SOM memory cell 401. FIG. 4C shows the M bottom wires WL1-WL M and N upper wires BL1 to BL NFIG. 1 is a top view showing the cross-point structure of a SOM memory cell. In a binary embodiment, the SOM cell at each cross-point can be programmed to one of two resistance states: high and low. SOM memory cell design embodiments and techniques for programming them are described in more detail below. In some embodiments, these sets of wires are arranged consecutively as "tiles," and such tiles can be paired adjacently in the word line (WL) direction and orthogonally in the bit line direction to create modules. Such modules can be formed by combining 2x2 tiles to form four tiles, and the WL drivers between tiles can be "center-driven," with the WLs running continuously over the transistor drivers approximately in the middle of the lines. Similarly, the BL drivers can be located between pairs of center-driven tiles in the BL direction, so that the transistor drivers and their area are shared between the pair of tiles. Copper or other types of low-resistance vias can decode and connect the transistor drivers / selects to the WL or BL. In addition to the memory elements in the memory cells between the WL and BL, a series select element such as an OTS can also be included.

[0047] The cross-point array of Figure 4A shows an embodiment with one layer of word lines and bit lines, with SOM or other memory technology for memory cells located at the intersections of two sets of conductive lines. To increase the storage density of a memory die, multiple layers of such memory cells and conductive lines can be formed. A two-layer example is shown in Figure 4D.

[0048] 4D illustrates a perspective view of an embodiment of a portion of a two-level memory array forming a cross-point architecture. Similar to FIG. 4A, FIG. 4D illustrates the word lines WL 1、1 ~WL 1、4 3A shows a first layer 418 of memory cells 401 of a memory array 403 connected at the cross points of the first layer of bit lines BL1-BL5. The memory array 403 may be included in the memory structure 202 of FIG. 3A or 3B. A second layer 420 of memory cells is located above the bit lines BL1-BL5 and between these bit lines and word lines WL 2、1 ~WL2、4 WLs are formed between the first and second sets of WLs. In effect, the WLs are shared. In an alternative, the second layer may include another deck of WLs above the WLs shown and below the second deck of WLs. While FIG. 4D shows two layers of memory cells 418 and 420, this structure can be extended upward through additional alternating layers of similarly patterned word lines and bit lines. Depending on the embodiment, the word lines and bit lines of the array in FIG. 4D can be biased for read or program operations so that current in each layer flows from the word line layer to the bit line layer, or vice versa. The two layers can be configured with driver selection in either a positive or negative direction to have current flow in the same direction in each layer for a given operation, or to have current flow in opposite directions. Memory cells can be arranged in the same orientation within the first and second layers, allowing for the use of opposite current directions for each layer for read or write. Alternatively, the memory cells may be arranged in an inverted or flipped orientation when placed between the BL and WL in the second layer (allowing for the use of currents in the same direction as those used to read or write in the memory cells in the first layer.) As will be apparent to those skilled in the art, two layers can be extended to three or more layers.

[0049] The use of a cross-point architecture enables small-footprint arrays, and several such arrays can be formed on a single die. The memory cells formed at each cross-point can be resistive-type memory cells, with data values ​​encoded as different resistance levels. Depending on the embodiment, the memory cells can be binary-valued, having either a low-resistance state or a high-resistance state, or can be multi-level cells (MLC) that can have additional resistance intermediate the low-resistance state. The cross-point arrays described herein can be used in the memory die 292 of FIG. 3A , the local memory 140 of FIG. 2 , and / or the host memory 124 of FIG. 2 , or any other configuration in which additional memory is useful. Resistive-type memory cells can be formed according to many of the techniques herein, such as OTS. The following discussion is presented primarily in the context of memory arrays using a cross-point architecture with binary-valued OTS memory cells, but many of the discussions are more generally applicable to other memory elements within the memory cells in a cross-point array, or other configurations apparent to those skilled in the art.

[0050] 5 illustrates the structure of one embodiment of a SOM cell. SOM cell 401 can be used, for example, as programmable resistive memory cell 401 in FIGS. 4A-4D. The SOM cell includes a bottom electrode 501, a spacer 512, a threshold switching selector (TSS) memory element 502, a spacer 514, and a top electrode 511. In some embodiments, bottom electrode 501 is a word line and top electrode 511 is a bit line. In other embodiments, bottom electrode 501 is a bit line and top electrode 511 is a word line. The state of the memory cell is based on the state of TSS memory element 502.

[0051] Data is written to a SOM memory cell by programming the TSS memory element 502 with a program (or write) signal (e.g., program current, program voltage) having a desired polarity. In one embodiment, the SOM memory cell is programmed to a first state (W0) using a program signal of a first polarity and to a second state (W1) using a program signal of a second polarity. The SOM memory cell may be read using a read signal (e.g., read current, read voltage). The polarity of the read signal relative to the polarity of the program signal may affect the Vth of the SOM cell. In one embodiment, a read signal having the same polarity as the program signal results in a lower Vth than a read signal having the opposite polarity to the program signal. Typically, a memory system chooses the polarity of the read signal and then matches the polarity of the read signal when determining the state of the SOM cell. Thus, the polarity of the program signal effectively results in a higher / lower Vth when read with a read signal of the chosen polarity.

[0052] The threshold switching selector 502 can also function as a selector for selecting a memory cell for a memory operation. The threshold switching selector 502 has a high resistance (off or non-conducting state) until it is biased to a voltage (Vth) above its threshold voltage or a current above its threshold current, and until its voltage bias falls below Vhold (also known as “Voffset”) or the current falls below Ihold. After Vth is exceeded, and while Vhold is exceeded across the switching selector, the switching selector has a low resistance (on or conducting state). The threshold switching selector remains on until its current is reduced to Ihold, which is less than the holding current, or the voltage is reduced to Vhold, which is less than the holding voltage. When this occurs, the threshold switching selector returns to its off (high) resistance state. Thus, a voltage or current sufficient to turn on the associated threshold switching selector is applied to select the memory cell at the crossing point. One example of a threshold switching selector is the ovonic threshold switching material of an ovonic threshold switch (OTS). Exemplary threshold switching materials include Ge-Se, Ge-Se-N, Ge-Se-As, Ge-Se-Sb-N, Ge58Se42, GeTe6, Si-Te, Zn-Te, C-Te, B-Te, Ge-As-Te-Si-N, Ge-As-Se-Te-Si, and Ge-Se-As-Te, with atomic percentages ranging from a few percent to over 90 percent for each element. In one embodiment, the threshold switching selector 502 is a two-terminal device. The threshold switching selector 502 can also include an additional conductive layer. For example, a spacer 514 is shown between the switching selector 502 and the top electrode 511. The spacer layer 514 can be a single conductive layer or can be composed of multiple conductive layers. The threshold switching selector 502 can also include an additional conductive layer on the interface with the bottom electrode 501. For example, a spacer 512 is shown between the switching selector 502 and the bottom electrode 501. The spacer layer 512 on the interface with the bottom electrode 501 can be a single conductive layer or can be composed of multiple conductive layers.Examples of conductive layers adjacent to the OTS include carbon, carbon nitride, carbon silicide, tungsten carbon, titanium, titanium nitride, tungsten, tungsten nitride, tantalum, tantalum nitride, etc. A threshold voltage switch has a threshold voltage (Vt) above which the resistance of the device changes substantially from insulating or semi-insulating to conductive.

[0053] FIG. 6A illustrates an embodiment of a memory array 600 having a cross-point architecture. The memory array 600 may be included in the memory structure 202 of FIG. 3A or 3B. The array 600 includes a set of first conductive lines 606a-606h and a set of second conductive lines 608a-608d. In one embodiment, the set of first conductive lines 606a-606h are word lines and the set of second conductive lines 608a-608b are bit lines. For ease of discussion, the set of first conductive lines 606a-606h may be referred to as word lines and the set of second conductive lines 608a-608b may be referred to as bit lines. However, the set of first conductive lines 606a-606h may be bit lines and the set of second conductive lines 608a-608b may be word lines.

[0054] The memory array 600 includes several programmable resistive memory cells 401. The programmable resistive memory cells 401 may be referred to as self-selecting memory cells or selector-only memory cells. In one embodiment, each cell 401 has a structure similar to that of the cell of FIG. 5. Each memory cell 401 is connected between one of the first conductive lines 606 and one of the second conductive lines 608 (e.g., at the intersection of one of the first conductive lines 606 and one of the second conductive lines 608). Each SOM cell 401 includes a threshold switching selector (not shown in FIG. 6A). The threshold switching selector 502 becomes conductive in response to application of a voltage level above the threshold voltage of the threshold switching selector 502 and remains conductive at a lower resistance until the current through the switching selector 502 is reduced below the selector holding current Ihold. The threshold switching selector 502 may be a two-terminal device. In one embodiment, the threshold switching selector 502 comprises an OTS.

[0055] Techniques for programming SOM cells are disclosed. For purposes of discussion, memory cell 401a is selected for a memory operation, such as a read or write. Consider an example of programming threshold switch selector 502. Selected memory cell 401a is at the cross point of selected word line 606g and selected bit line 608b. A selected memory cell refers to a memory cell selected for a memory operation, such as a read or write. A selected memory cell is connected between a selected word line and a selected bit line. In one embodiment, to program a selected memory cell 401a, a select voltage, such as a voltage adjacent to a selected bit line (e.g., bit line 608b), is applied, and a program (or write) voltage (Vs) is applied to a selected word line (e.g., word line 606g). A "selected word line" means that the word line is connected to at least one selected memory cell. Alternatively, a memory cell can be selected by applying a program voltage (Vs) to a selected bit line while applying a select voltage to the selected word line.

[0056] In one approach, word lines not connected to a selected memory cell may be driven by a voltage that is approximately half the magnitude of the voltage across the selected cell. As shown in FIG. 6A, a voltage referred to as a half-select voltage (Vs / 2) is applied to word lines 606a, 606b, 606c, 606d, 606e, 606f, and 606h, respectively. The half-select voltage (Vs / 2) has approximately half the magnitude of the voltage across the selected cell (Vs). For programming, the voltage Vs may be referred to as a program voltage. For example, the voltage Vs may be referred to as a read voltage.

[0057] In one approach, bit lines not connected to a selected memory cell may be driven with a voltage that is approximately half the magnitude of the voltage across the selected cell. As shown in Figure 6A, bit lines 608a, 608c, and 608d each have a voltage applied to them referred to as a half-select voltage (Vs / 2). As mentioned above, the half-select voltage (Vs / 2) has approximately half the magnitude of the voltage across the selected cell (Vs).

[0058] Some of the memory cells connected to the selected word line are referred to herein as half-selected memory cells. The voltage across the half-selected memory cells is approximately half the voltage across the selected memory cells. Each half-selected memory cell 401b connected to the selected word line has Vs applied to the selected word line and Vs / 2 applied to the respective bit line. Thus, each half-selected memory cell 401b has Vs / 2 applied across it.

[0059] Some of the memory cells connected to the selected bit line are referred to herein as half-selected memory cells. The voltage across these half-selected memory cells is approximately half the voltage across the selected memory cell. Each half-selected memory cell 401c connected to the selected bit line has 0V applied to the selected bit line and Vs / 2 applied to the respective word line. Thus, each half-selected memory cell 401c has Vs / 2 applied across it.

[0060] The threshold switching selector 502 in such half-selected memory cells 401b, 401c should not be turned on during operations such as read or write. However, if the Vth of the threshold switching selector 502 is less than Vs / 2, the threshold switching selector 502 may be turned on during memory operations. Disclosed herein are techniques for preventing (or at least reducing the likelihood of) the threshold switching selector 502 in half-selected memory cells 401b, 401c from turning on during memory operations such as read or write. In one embodiment, Vth drift is removed from the memory cells before programming, which allows the program voltage to have a lower magnitude. Reducing the magnitude of the program voltage reduces the magnitude of Vs / 2, reducing the probability that a half-selected memory cell will be erroneously selected.

[0061] The other memory cells are completely unselected, meaning that they have approximately 0V across the memory cell. A completely unselected memory cell 401d is shown in Figure 6A. In this example, each completely unselected memory cell 401d has Vs / 2 applied to its word line and Vs / 2 applied to its bit line.

[0062] In the example of FIG. 6A, there are more word lines than bit lines in the cross-point array. In another embodiment, there are more bit lines than word lines in the cross-point array. In another embodiment, the number of bit lines equals the number of word lines in the cross-point array. In the example of FIG. 6A, there are twice as many word lines as bit lines in the cross-point array, but different ratios can be used. This allows for different tile sizes to be achieved. For example, a tile may have 1024 BLs by 2048 WLs, which can be configured into modules of 2048 by 4096 cells by centrally driving the WLs and BLs across four tiles. In one embodiment, a read or write is performed on a group of memory cells, for example, by selecting one memory cell in each of several tiles. In some embodiments, more than one memory cell from a tile may be selected for read.

[0063] FIG. 6A is shown and described as using a voltage-force approach, where a voltage is applied to a selected word line. In one embodiment, a forced current approach is used to access the SOM cells. The forced current approach can be used to read or write the SOM cells. FIG. 6B shows an example of a current-force approach. In the current-force approach, an access current (e.g., I access ) is driven onto the selected word line (or I access ) and sinks current from the selected word line depending on the direction of the voltage. The selected bit line may be held at ground. As a result, current charges the voltage on the selected word line. In one embodiment, the maximum magnitude of the selected word line voltage is limited to Vs. Alternatively, the selected bit line may be held at a higher voltage and current is sunk from the selected word line. A voltage is applied to the unselected word lines and unselected bit lines. The magnitude of the voltage to the unselected word lines and unselected bit lines may be similar to the example of FIG. 6A. The half-select problem discussed in connection with the voltage-force approach may also occur in the current-force approach. Here, terms such as program signal may include both program voltage and program current. Similarly, terms such as read signal may include both read voltage and read current.

[0064] 7 is a flowchart of one embodiment of a process 700 for programming SOM cells 401 in a cross-point array. Process 700 may be used to program SOM cells 401 such as those discussed in FIG. 5. In one embodiment, SOM cells 401 include OTSs that function as programmable resistive memory elements. Process 700 may be performed in parallel for many memory cells, such as performing the process in selected memory cells in different tiles 600. In one embodiment, process 700 is performed by one or more control circuits, such as, but not limited to, one or more of memory controller 102, system control logic 260, column control circuitry 210, row control circuitry 220, a microcontroller, a state machine, host processor 122, and / or other control circuitry or other similar circuitry used to control non-volatile memory.

[0065] Step 702 involves selecting a first polarity for subsequent read signals applied to SOM cell 401. Step 702 can be omitted if the first polarity selection has already been established and does not need to be changed. The first polarity can be positive or negative. Current polarity can be defined based on the voltage across the cell caused by the current. Here, positive or negative polarity can be defined, for example, for a selected word line and a selected bit line.

[0066] Step 704 includes determining whether to store a first bit value or a second bit value in SOM cell 401. As an example, the first bit value is "0" and the second bit value is "1." As another example, the first bit value is "1" and the second bit value is "0." However, the bit values ​​can be reversed from this example.

[0067] If a first bit value is to be stored, step 706 is performed. Step 706 involves applying a programming (or write) signal having a first polarity to SOM cell 401. Thus, the programming signal in step 706 has the same polarity as the read signal when the cell is subsequently read.

[0068] If a second bit value is to be stored, step 708 is performed. Step 708 involves applying a programming signal having a second polarity to SOM cell 401. The second polarity is opposite to the first polarity. Thus, the programming signal in step 708 has an opposite polarity to the subsequent read signal. Steps 702, 706, and 708 may apply the signals using either current-force or voltage-force techniques.

[0069] FIG. 8 shows example Vth distributions for a group of SOM cells 402 after programming using process 700. FIG. 8 shows two "Vth distributions" of SOM cells 401 measured when read with a read signal of a first polarity considered in process 700. Vth distribution 810 represents SOM cells 401 storing a first bit value. Vth distribution 820 represents SOM cells 401 storing a second bit value. The vertical axis represents memory cell number and is in log scale. The horizontal axis represents the Vth of the threshold switching selector, assuming the SOM cells 401 are read with a read voltage having a pre-assigned first polarity. A reference resistor R_ref is shown between the two Vth distributions 810, 820. In one embodiment, R_ref is used to distinguish between the two Vth distributions. Note that Vth distributions 810, 820 could be reversed if the SOM cells were instead read with a read signal having a second polarity.

[0070] FIG. 9A is a table 950 detailing one embodiment of programming a SOM cell in a cross-point memory architecture. Prior to programming, the memory cell can be in either the W0 state or the W1 state. The "Last Fire" column 952 refers to the last signal that fired (e.g., turned on) the cell being programmed. The last fire can be a write signal or a read signal. In this example, for a normal read operation, the read signal has the same polarity as the write signal used to program to the W0 state. The arrows in table 950 indicate the relative polarities of the read and write signals. The normal read signal is referred to as R0 because it has the same polarity as the signal used to program to the W0 state. The read and write signals can be voltages or currents. The "New Data" column 954 indicates how the memory cell is programmed. In this example, a cell currently in the W1 state can be programmed to either the W1 state or the W0 state. A cell currently in the W0 state can be programmed to either the W1 state or the W0 state.

[0071] Step 1 in this example is referred to as "read down," which refers to the downward arrow in step 1 of table 950. The "up arrow" and "down arrow" in table 950 refer to the relative polarity of the signals. Step 2 in this example is referred to as "read up," which refers to the upward arrow in step 2 of table 950. The term "read" is used for steps 1 and 2 because the signal magnitude is similar to a normal read signal (and less than a typical program voltage). However, the memory system does not need to determine the state of the memory cell in response to the application of the "read signal." In steps 1 and 2, the read signal can be applied to all memory cells in the group being programmed. Step 3 in this example covers both "write down" and "write up." Write down refers to the downward arrow in step 3 of table 950. Write up refers to the upward arrow in step 3 of table 950. The write signal is selectively applied to only those memory cells that are to be programmed to the state associated with the write signal. Steps 1 and 2 are referred to as reading and are performed before the programming of step 3. However, the readout order of step 1 and step 2 can be swapped. The light up and light down can be decomposed into separate light up and light down steps.

[0072] Table 950 is discussed in more detail with reference to FIG. 9B. FIG. 9B illustrates threshold voltages over time for an embodiment operating a SOM cell in a cross-point memory architecture. A memory cell programmed to the W0 state may have a Vth of approximately C_low immediately after programming (t0). A memory cell programmed to the W1 state may have a Vth of approximately C_high immediately after programming (t0). The above assumes that a read is performed with an R0 signal having the same polarity as the signal used to program W0. The terms "low Vth state" and "high Vth state" are used herein to refer to two such states having different threshold voltages (programmed with different polarity program voltages), assuming a default polarity read signal. Plot 906 illustrates the upward drift of the Vth of a threshold switching selector in a SOM cell programmed to the W0 state. By t1, the Vth of the W0 cell has drifted to "B." Plot 908 illustrates the upward drift of the Vth of a threshold switching selector in a SOM cell programmed to the W1 state. By t1, the Vth of the W1 cell has drifted to "A." While the amount of Vth drift shown in Figure 9B is quite large, even smaller Vth drifts can cause problems such as half-select issues.

[0073] The Vth column 956 of table 950 in FIG. 9A summarizes the Vth of a particular cell, which depends on the relative polarity of the last fire voltage (column 952) and the polarity of the write voltage (column 954). A cell with a last fire of W1 and new data of W1 has a voltage of the same polarity for these two voltages. Therefore, the cell has a low Vth of B while writing the new data. However, a cell with a last fire of W1 and new data of W0 has a voltage of the opposite polarity for these two voltages. Therefore, the cell has a high Vth of A while writing the new data. A cell with a last fire of W0 (or R0) and new data of W1 has a voltage of the opposite polarity for these two voltages. Therefore, the cell has a high Vth of A while writing the new data. A cell with a last fire of W0 (or R0) and new data of W0 has a voltage of the same polarity for these two voltages. Therefore, the cell has a low Vth of B while writing the new data.

[0074] Referring now to an embodiment of a programming procedure, step 1 may include applying a read signal to all cells in the group of cells to be programmed. For ease of discussion, the read signal is referred to as a read voltage. However, the read signal may be a read current that increases (or decreases) a selected word line voltage, resulting in a voltage across the selected memory cell (the voltage may be clamped or otherwise limited to a maximum read voltage). Step 1 fires (switches on) all memory cells that have a Vth less than or equal to the magnitude of the maximum read voltage. Referring to FIG. 9B, the maximum read voltage may be "MaxV for read." Such a read-down voltage switches on the selector in the last cell, the first of which was W0. Furthermore, firing the selector may refresh the Vth such that the Vth is lowered from B to C. Referring to plot 906 of FIG. 9B, the Vth is refreshed from the B level (at t1) to the C_low level (at t0). However, the W1 cell has a Vth greater than MaxV for read and therefore is not triggered (fired) by the read-down voltage. Therefore, the W1 cell is not refreshed.

[0075] Step 2 is read-up, which fires (turns on) the memory cell last programmed in W1. This read signal can be applied to all memory cells in the group being programmed. Note that read-up has the same polarity as the W1 signal. This has the effect of lowering the Vth for the W1 cell. Therefore, step 2 indicates that the W1 cell has a Vth of B. Referring to FIG. 9B, the maximum magnitude of the read voltage can be "MaxV for Read." However, the polarity of the read voltage is opposite to that of the read voltage in step 1. This read-up voltage turns on the selector in the last cell, which was originally W1. Therefore, plot 908 can be considered a plot of Vth assuming read-down. However, applying the read voltage can be considered to move the W1 cell from plot 906 to plot 908. As a result, the read-up voltage is large enough to turn on (fire) the selector in the W1 cell. Therefore, the selector in the W1 cell can be refreshed. The Vth can be lowered from B to C. 9B, assuming the cell is read again with the read-up voltage, the Vth can be refreshed from the B level (t1) to the C_low level (t0). However, reading the cell again with the read-down voltage can result in a Vth of C_high.

[0076] Step 3 in this example covers both "write down" and "write up." The write down signal is only applied to cells that are to be written to the W0 state. Assuming the default read is a read down signal, by definition all cells written with a write down signal will end up in the C_low state. The write up signal is only applied to cells that are to be written to the W1 state. Assuming the default read is a read down signal, by definition all cells written with a write up signal will end up in the C_high state.

[0077] The programming process allows the magnitude of the programming voltage to be reduced while still maintaining sufficient HS margin. Referring to FIG. 9B, the following are some example values ​​for illustration: The value of C_low may be approximately 2.5V. The value of C_high may be approximately 3.5V. The amount of Vth drift over an example period may be approximately 0.5V (for both states). Thus, the maximum drift value for the high Vth state may be approximately 4.0V, and the maximum drift value for the low Vth state may be approximately 3.0V. In this example, the magnitude of MaxV for read may be approximately 3.25V. Thus, MaxV for read may be midway between the maximum drift value for low Vth and the maximum drift value for high Vth. Applying +3.25V across the cell switches on the threshold switch selector for the low Vth state. Applying −3.25V across the cell switches on the threshold switch selector for the high Vth state. Assuming that the high-Vth state cells are refreshed to about 3.5V (for the default read polarity, which is positive in this example), a program voltage having a magnitude of about 3.7V can be used to allow for a safety margin. The program voltages for the two states can have the same magnitude but opposite polarities.

[0078] FIG. 10 is a flowchart of one embodiment of a process 1000 for programming SOM cells in a cross-point memory structure. The SOM cells each have a threshold switching selector, such as, but not limited to, an OTS. Process 1000 may use a voltage-forcing technique, such as that of FIG. 6A, or a current-forcing technique, such as that of FIG. 6B. Step 1002 includes applying a first signal having a first polarity to a group of memory cells selected for programming. In one embodiment, the group includes one memory cell in each of a plurality of tiles. The first signal switches on threshold switching selectors in a first set of memory cells. The first set of memory cells may be, for example, memory cells last programmed to W0. In one embodiment, memory cells last programmed to W1 do not fire (e.g., the threshold switching selectors are not switched on). Step 1002 may refresh the Vth of the threshold switching selectors in the first set of cells. Referring to plot 906 of FIG. 9B as an example, the Vth may be refreshed from a B level to a C_low level. Referring to FIG. 6A, voltage Vs may be replaced with Vread. Step 1002 may include applying Vread to the selected word line while applying 0V to the selected bit line. Referring to FIG. 6B, Iaccess may be replaced with Iread and Vs may be replaced with Vread. Step 1002 may include applying Iread to the selected word line while applying 0V to the selected bit line. In both voltage-force and current-force examples, a positive voltage exists across the selected cell from the selected word line to the selected bit line. Also, in step 1002, Vread / 2 may be applied to unselected word lines and unselected bit lines.

[0079] Step 1004 includes applying a second signal having a second polarity to the group of memory cells selected for programming. The second signal switches on threshold switching selectors in the second set of memory cells. The second set of memory cells may be, for example, the memory cells last programmed to W1. The second signal may have the same magnitude (but opposite polarity) as the first signal. Step 1004 may refresh the Vth of the threshold switching selectors in the second set of cells. Step 1004 may include applying Vread to the selected bit line while applying 0V to the selected word line. Step 1004 may include applying a negative read current to the selected word line while applying Vs to the selected bit line. Here, the negative read current means that the current driver may sink current from the selected word line. Step 1004 may also apply Vread / 2 to unselected word lines and unselected bit lines. In both the voltage-force and current-force examples, a negative voltage exists across the selected cell from the selected word line to the selected bit line.

[0080] Step 1006 includes applying a third signal having a first polarity to a third set of the group of memory cells after applying both the first signal and the second signal to the group of memory cells. The third signal programs the threshold switching selectors of the memory cells in the third set to the first state. The third set of cells may include, for example, cells to be programmed to W0. With reference to FIG. 9A, the third set may include some cells having a last fire 952 (before read) of W1 and some cells having a last fire 952 (before read) of W0. With reference to FIG. 6A, voltage Vs may be replaced with Vwrite. Step 1006 may include applying Vwrite to a selected word line while applying 0V to a selected bit line. With reference to FIG. 6B, Iaccess may be replaced with Iwrite and Vs may be replaced with Vwrite. Step 1006 may include applying Iwrite to a selected word line while applying 0V to a selected bit line. Also, Vwrite / 2 may be applied to unselected word lines and unselected bit lines in step 1006. In both the voltage-force and current-force examples, a positive voltage exists across the selected cell from the selected word line to the selected bit line.

[0081] Step 1008 includes applying a fourth signal having a second polarity to a fourth set of the group of memory cells after applying both the first signal and the second signal to the group of memory cells. The fourth signal programs the threshold switching selectors of the memory cells in the fourth set to a second state. The fourth set of cells may include, for example, cells to be programmed to W1. Referring to FIG. 9A, the fourth set may include some cells having a last fire 952 (before read) of W1 and some cells having a last fire 952 (before read) of W0. Referring to FIG. 6A, step 1008 may include applying Vwrite to the selected bit line while applying 0V to the selected word line. For unselected word lines and unselected bit lines, Vs may be replaced with Vwrite. Referring to FIG. 6B, Iaccess may be replaced with Iwrite having a negative value (e.g., the current driver sinks Iwrite from the selected word line 606g). Vs may be replaced with Vwrite. Also, Vwrite / 2 can be applied to unselected word lines and unselected bit lines in step 1008. In both the voltage-force and current-force examples, a negative voltage exists across the selected cell from the selected word line to the selected bit line.

[0082] In one embodiment, steps 1006-1008 are performed simultaneously. For example, selected SOM cells in each of a first set of tiles may be written in step 1006, and selected SOM cells in each of a second set of tiles may be written in step 1008. In one embodiment, step 1006 is performed before step 1008. In one embodiment, step 1008 is performed before step 1006.

[0083] FIG. 11 is a flowchart of one embodiment of a process 1100 for programming SOM cells in a cross-point memory structure. The SOM cells each have a threshold switching selector, such as, but not limited to, an OTS. Process 1100 provides further details about one embodiment of process 1000. In one embodiment, the group of cells to be programmed includes one memory cell in each of several tiles. Process 1100 may use a voltage-forcing technique, such as that of FIG. 6A, or a current-forcing technique, such as that of FIG. 6B. Step 1102 includes applying a first read signal to the group of memory cells to trigger cells programmed to a first state but not a second state. As an example, the first read signal may trigger cells programmed to W0 but not cells programmed to W1. Triggering the cells may turn on the threshold switching selector and refresh the Vth of the threshold switching selector. Step 1102 may include applying Vread to a selected word line while applying 0V to a selected bit line. Step 1102 may include applying Iread to the selected word line while applying 0 V to the selected bit line. The voltage across each memory cell may be limited or capped when applying Iread.

[0084] Step 1104 includes applying a second read signal to the group of memory cells. The second read signal has an opposite polarity to the first read signal. Applying the second read signal applies the same maximum voltage across the memory cells as applying the first read signal. The second signal switches on threshold switching selectors in at least a second set of memory cells. The second set of memory cells may be, for example, memory cells last programmed to W1. Step 1104 may refresh the Vth of the threshold switching selectors in the second set of cells. Step 1104 may include applying Vread to a selected bit line while applying 0V to a selected word line. Step 1104 may include sinking Iread from the selected word line while applying a select voltage to the selected bit line. The voltage across each memory cell may be limited or capped when applying Iread.

[0085] Step 1106 includes applying a first write signal to a first set of the group of cells to write the first set to a first state. The first write signal has the same polarity as the first read signal. The first set of cells may include, for example, cells to be programmed to W0. Step 1106 may include applying Vwrite to a selected word line while applying 0V to a selected bit line. Step 1106 may include applying Iwrite to a selected word line while applying 0V to a selected bit line.

[0086] Step 1108 includes applying a second write signal to a second set of the group of cells to write the second set to a second state. The second write signal has the same polarity as the first write signal. The second set of cells may include, for example, cells to be programmed to W1. Step 1108 may include applying Vwrite to selected bit lines while applying 0V to selected word lines. Step 1108 may include sinking Iwrite from the selected word lines while applying a select voltage to the selected bit lines.

[0087] In one embodiment, steps 1106-1108 are performed simultaneously. In one embodiment, step 1106 is performed before step 1108. In one embodiment, step 1108 is performed before step 1106.

[0088] FIG. 12 is a flowchart of one embodiment of a process 1200 for programming SOM cells in a cross-point memory structure. The SOM cells each have a threshold switching selector, such as, but not limited to, an OTS. Process 1200 provides further details about one embodiment of process 1000. In one embodiment, the group of SOM cells being programmed includes one memory cell in each of several tiles. Process 1200 may use a voltage-forcing technique, such as that of FIG. 6A, or a current-forcing technique, such as that of FIG. 6B. Step 1202 includes inducing a first voltage across each cell in the group of memory cells to reduce threshold voltage drift in the threshold switching selectors in the memory cells in the group most recently programmed to the first state. The first set of memory cells may be, for example, the memory cells last programmed to W0. Step 1202 may include applying a first voltage to a selected word line while applying 0V to a selected bit line. Step 1202 may include applying a current to a selected word line while applying 0V to a selected bit line to produce a first voltage across each cell. In one embodiment, the first voltage has a maximum magnitude. In a current-force approach, a fixed magnitude current may be used to charge the selected word line, but the word line voltage may be limited to a maximum voltage.

[0089] Step 1204 includes creating a second voltage across each cell in the group of memory cells following the first voltage. The second voltage may have the same magnitude but opposite polarity as the first voltage. The second voltage may reduce threshold voltage drift in the threshold switching selectors in the memory cells in the group most recently programmed to the second state (e.g., W1). Step 1204 may include applying the second voltage to the selected bit line while applying 0V to the selected word line. Step 1204 may include sinking current from the selected word line while applying a high voltage to the selected bit line to create the second voltage across each cell. In a current-forcing approach, the selected word line and the selected bit line may each be precharged to a voltage approximately half the final voltage of the selected bit line (e.g., 1.65V). The selected bit line may then be raised to a higher voltage (e.g., 3.3V) using the current used to lower the voltage on the selected word line. In this example, the lowest voltage that the selected word line can reach is 0 V. Therefore, the voltage across the selected cell is limited to a maximum voltage.

[0090] Step 1206 includes causing a third voltage having a first polarity voltage across each cell in the first set of groups of memory cells to write the threshold switching selectors in the first set of memory cells to a first state. The first set of cells may include, for example, cells to be programmed to W0. Step 1206 may include applying Vwrite to a selected word line while applying 0V to a selected bit line. Step 1206 may include applying a write current to the selected word line while applying 0V to the selected bit line to create the third voltage across each cell.

[0091] Step 1208 includes causing a fourth voltage having a second polarity voltage across each cell in the second set of group of memory cells to write the threshold switching selectors in the second set of memory cells to a second state. The second set of cells may include, for example, cells to be programmed to W1. Step 1208 may include applying Vwrite to the selected bit line while applying 0V to the selected word line. Step 1208 may include sinking a write current from the selected word line while applying a high voltage to the selected bit line to cause the fourth voltage across each cell.

[0092] In one embodiment, steps 1206 and 1208 are performed simultaneously. In one embodiment, step 1206 is performed before step 1208. In one embodiment, step 1208 is performed before step 1206.

[0093] In view of the above, it can be seen that, according to one embodiment, an apparatus includes one or more control circuits configured to couple to a cross-point structure having self-selected memory cells. Each self-selected memory cell has a threshold switching selector. The one or more control circuits are configured to apply a first signal having a first polarity to a group of memory cells selected for programming. The first signal switches on threshold switching selectors in the first set of memory cells. The one or more control circuits are configured to apply a second signal having a second polarity to the group of memory cells selected for programming. The second signal switches on threshold switching selectors in the second set of memory cells. The one or more control circuits are configured to apply a third signal having the first polarity to a third set of groups of memory cells after applying both the first and second signals to the group of memory cells. The third signal programs the threshold switching selectors in the third set of memory cells to a first state. The one or more control circuits are configured to apply a fourth signal having a second polarity to a fourth set of groups of memory cells after applying both the first and second signals to the group of memory cells. A fourth signal programs the threshold switching selectors in the fourth set of memory cells to a second state.

[0094] In a further embodiment, the one or more control circuits are configured to establish a magnitude of the first signal to produce a maximum voltage across the memory cells in the group between a first highest drift threshold voltage of the memory cells in the group most recently programmed to the first state and a second highest drift threshold voltage of the memory cells in the group most recently programmed to the second state.

[0095] In a further embodiment, one or more control circuits are configured to establish a magnitude of the first signal to produce a maximum voltage across the memory cells in the group at a midpoint between a first highest drift threshold voltage of the memory cells in the group programmed to a low threshold voltage state and a second highest drift threshold voltage of the memory cells in the group programmed to a high threshold voltage state.

[0096] In a further embodiment, the first set of memory cells are those most recently programmed to the first state, the first set of memory cells are those most recently programmed to the first state, and the first signal has a magnitude and polarity that switches on the threshold switching selectors of the memory cells most recently programmed to the first state but does not switch on the threshold switching selectors of the memory cells most recently programmed to the second state.

[0097] In a further embodiment, the first signal has a magnitude and polarity that eliminates drift in the threshold voltage of the threshold switching selector of the first set of memory cells but does not switch on the threshold switching selector of the second set of memory cells.

[0098] In a further embodiment, the second signal has a magnitude and polarity that eliminates drift in the threshold voltages of the threshold switching selectors of the second set of memory cells most recently programmed to the second state.

[0099] In a further embodiment, the first signal has a magnitude that distinguishes between the first state and the second state, and the second signal has a magnitude that distinguishes between the first state and the second state.

[0100] In a further embodiment, the one or more control circuits are configured to simultaneously apply a third signal to a third set of the group of memory cells and a fourth signal to a fourth set of the group of memory cells.

[0101] In a further embodiment, the one or more control circuits are configured to apply a third signal to the third set of memory cells and a fourth signal to the fourth set of memory cells without determining the memory cell state in response to either the first signal or the second signal.

[0102] In a further embodiment, the first signal and the second signal are voltages having substantially the same magnitude.

[0103] In a further embodiment, the first signal and the second signal are currents having substantially the same magnitude.

[0104] One embodiment includes a method for operating a cross-point memory structure having self-selecting memory cells. The method includes applying a first read signal to a group of memory cells, the first read signal triggering the most recently programmed memory cell to a first state but not the most recently programmed memory cell to a second state. The first read signal has a first polarity and creates a first maximum voltage across each particular cell in the group. The method includes applying a second read signal to the group of memory cells after applying the first read signal to the group. The second read signal has a second polarity opposite the first polarity and creates a first maximum voltage across each particular cell in the group. The method includes applying a first write signal to a first set of the group of memory cells to write the first set to a first state after applying both the first read signal and the second read signal to the group of memory cells. The first write signal has a first polarity. The method includes applying both the first read signal and the second read signal to the group of memory cells, and then applying a second write signal to a second set of the group of memory cells to write the second set to a second state, the second write signal having a second polarity.

[0105] One embodiment includes a memory system including a cross-point memory structure having first conductive lines, second conductive lines, and memory cells. Each memory cell is at a junction of one of the first conductive lines and one of the second conductive lines. Each memory cell has a threshold switching selector. The memory system includes one or more control circuits in communication with the cross-point memory structure. The one or more control circuits are configured to induce a first voltage across each memory cell in a group of memory cells selected for programming. The first voltage has a first maximum magnitude and a first polarity that reduces threshold voltage drift in the threshold switching selector in memory cells in the group most recently programmed to the first state. The one or more control circuits are configured to induce a second voltage across each memory cell in the group of memory cells after inducing the first voltage across the group of memory cells. The second voltage has substantially the first maximum magnitude and a second polarity opposite to the first polarity. The one or more control circuits are configured to induce a third voltage having a first polarity across each memory cell in a first set of memory cells in the group to write the threshold switch selector in the first set of memory cells to a first state, the third voltage occurring after inducing both the first voltage and the second voltage, and the one or more control circuits are configured to induce a fourth voltage having a second polarity across each memory cell in a second set of memory cells in the group to write the threshold switch selector in the second set of memory cells to a second state, the fourth voltage occurring after inducing both the first voltage and the second voltage.

[0106] For purposes of this specification, references in the specification to "an embodiment," "one embodiment," "some embodiments," or "another embodiment" may be used to describe different or the same embodiment.

[0107] For purposes of this specification, a connection may be a direct connection or an indirect connection (e.g., through one or more other parts). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element, or indirectly connected to the other element through intervening elements. When an element is referred to as being directly connected to another element, there are no intervening elements between the element and the other element. Two devices are in "communication" if they are directly or indirectly connected such that they can communicate electronic signals between each other.

[0108] For purposes of this specification, the term "based on" may be read as "based at least in part on."

[0109] For purposes of this specification, the use of numerical terms such as "first," "second," and "third" objects without additional context does not imply an ordering of the objects, but instead may be used for identification purposes to distinguish between different objects.

[0110] As used herein, the terms "top" and "bottom," "upper" and "lower," and "vertical" and "horizontal," and their configurations, are exemplary and illustrative only and are not intended to limit the description of the present technology, insofar as references may be interchanged in location and orientation. Also, as used herein, the terms "substantially" and / or "about" mean that a specified dimension or parameter may vary within acceptable tolerances for a given application.

[0111] The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to be limited to the precise form disclosed. Many modifications and variations are possible in light of the above teachings. The described embodiments were chosen to best explain the principles of the proposed technology and its practical application, thereby enabling those skilled in the art to best utilize this technology in various embodiments, with various modifications as appropriate for the particular uses contemplated. It is intended that the scope be defined by the claims appended hereto.

Claims

1. 1. An apparatus comprising: one or more control circuits configured to couple to a cross-point structure having self-selecting memory cells, each self-selecting memory cell having a threshold switching selector, the one or more control circuits comprising: applying a first signal having a first polarity to a group of memory cells selected for programming, the first signal switching on the threshold switching selectors in the first set of memory cells; applying a second signal having a second polarity to the group of memory cells selected for programming, the second signal switching on the threshold switching selectors in a second set of the memory cells; applying a third signal having the first polarity to a third set of the group of memory cells after applying both the first signal and the second signal to the group of memory cells, the third signal programming the threshold switching selectors in the third set of memory cells to a first state; and applying a fourth signal having the second polarity to a fourth set of the group of memory cells after applying both the first signal and the second signal to the group of memory cells, the fourth signal programming the threshold switching selectors in the fourth set of memory cells to a second state.

2. 2. The apparatus of claim 1, wherein the one or more control circuits are configured to establish a magnitude of the first signal to produce a maximum voltage across the memory cells in the group between a first highest drift threshold voltage of a memory cell in the group most recently programmed to the first state and a second highest drift threshold voltage of a memory cell in the group most recently programmed to the second state.

3. 2. The apparatus of claim 1, wherein the one or more control circuits are configured to establish a magnitude of the first signal to produce a maximum voltage across the memory cells in the group at a midpoint between a first highest drift threshold voltage of memory cells in the group that are programmed to a low threshold voltage state and a second highest drift threshold voltage of memory cells in the group that are programmed to a high threshold voltage state.

4. 2. The apparatus of claim 1, wherein the first set of memory cells are those most recently programmed to the first state, and the first signal has a magnitude and polarity that switches on the threshold switching selectors of the memory cells most recently programmed to the first state but does not switch on the threshold switching selectors of the memory cells most recently programmed to the second state.

5. 2. The apparatus of claim 1, wherein the first signal has a magnitude and polarity that eliminates drift in the threshold voltage of the threshold switching selector of the first set of memory cells but does not switch on the threshold switching selector of the second set of memory cells.

6. 6. The apparatus of claim 5, wherein the second signal has a magnitude and polarity that eliminates drift in the threshold voltage of the threshold switching selector of the second set of memory cells most recently programmed to the second state.

7. the first signal has a magnitude that distinguishes between the first state and the second state; 2. The apparatus of claim 1, wherein the second signal has the magnitude that distinguishes between the first state and the second state.

8. 2. The apparatus of claim 1, wherein the one or more control circuits are configured to simultaneously apply the third signal to the third set of the group of memory cells and the fourth signal to the fourth set of the group of memory cells.

9. the one or more control circuits:

2. The apparatus of claim 1, configured to apply the third signal to the third set of memory cells and the fourth signal to the fourth set of memory cells without determining a memory cell state in response to either the first signal or the second signal.

10. The apparatus of claim 1 , wherein the first signal and the second signal are voltages having substantially the same magnitude.

11. The apparatus of claim 1 , wherein the first signal and the second signal are currents having substantially the same magnitude.

12. 1. A method for operating a cross-point memory structure having self-selecting memory cells, the method comprising: applying a first read signal to the group of memory cells, the first read signal having a first polarity and producing a first maximum voltage across each particular cell in the group, the first read signal triggering the memory cell most recently programmed to a first state but not the memory cell most recently programmed to a second state; applying a second read signal to the group of memory cells after applying the first read signal to the group, the second read signal having a second polarity opposite to the first polarity and producing the first maximum voltage across each particular cell in the group; applying a first write signal to the first set of memory cells of the group to write the first set to the first state after applying both the first read signal and the second read signal to the group of memory cells, the first write signal having the first polarity; applying both the first read signal and the second read signal to the group of memory cells, and then applying a second write signal to the second set of the group of memory cells to write the second set to the second state, the second write signal having the second polarity.

13. 13. The method of claim 12, further comprising establishing a magnitude of the first read signal to produce a maximum voltage across the memory cells in the group between a first highest drift threshold voltage of a memory cell in the group most recently programmed to the first state and a second highest drift threshold voltage of a memory cell in the group most recently programmed to the second state.

14. 13. The method of claim 12, further comprising establishing a magnitude of the first read signal to produce a maximum voltage across the memory cells in the group at a midpoint between a first highest drift threshold voltage of memory cells programmed to a low threshold voltage state and a second highest drift threshold voltage of memory cells programmed to a high threshold voltage state.

15. 13. The method of claim 12, wherein applying the first write signal to the first set of groups and applying the second write signal to the second set of groups occurs without determining a memory cell state in response to either the first read signal or the second read signal.

16. 1. A memory system comprising: a cross-point memory structure having first conductive lines, second conductive lines, and memory cells, each memory cell being at a junction of one of the first conductive lines and one of the second conductive lines, each memory cell having a threshold switching selector; one or more control circuits in communication with the cross-point memory structure, the one or more control circuits comprising: establishing a first voltage across each memory cell in a group of memory cells selected for programming, the first voltage having a first maximum magnitude and a first polarity that reduces threshold voltage drift in the threshold switching selector in memory cells in the group most recently programmed to a first state; establishing a second voltage across each memory cell in the group of memory cells after establishing the first voltage on the group of memory cells, the second voltage having substantially the first maximum magnitude and a second polarity opposite to the first polarity; causing a third voltage having the first polarity across each memory cell in a first set of memory cells in the group to write the threshold switching selectors in the first set of memory cells to the first state, the third voltage occurring after causing both the first voltage and the second voltage; one or more control circuits configured to induce a fourth voltage having the second polarity across each memory cell in the group in a second set of memory cells in the group to write the threshold switching selector in the second set of memory cells to a second state, the fourth voltage occurring after inducing both the first voltage and the second voltage.

17. 17. The memory system of claim 16, wherein the one or more control circuits are configured to cause the first maximum magnitude for the first voltage to be between a first highest drift threshold voltage of the memory cell most recently programmed to the first state and a second highest drift threshold voltage of a memory cell most recently programmed to the second state.

18. 17. The memory system of claim 16, wherein the one or more control circuits are configured to effect the first maximum magnitude for the first voltage at a midpoint between a first highest drift threshold voltage of memory cells programmed to a low threshold voltage state and a second highest drift threshold voltage of memory cells programmed to a high threshold voltage state.

19. the one or more control circuits:

17. The memory system of claim 16, configured to cause the first maximum magnitude for the first voltage to refresh drift threshold voltages of the memory cells most recently programmed to the first state without triggering the threshold switching selector in the memory cells most recently programmed to the second state.

20. the one or more control circuits:

17. The memory system of claim 16, configured to simultaneously induce the third voltage across memory cells in the first set and induce the fourth voltage across memory cells in the second set.

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