Gate-all-around transistor architecture with filled dielectric material - Patents.com

Abstract

A semiconductor device and method for manufacturing the semiconductor device are described that includes front side processing to form source / drain cavities and filling the cavities with a sacrificial layer, which is then removed during back side processing to form metal filled back side power rail vias.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE

[0001] Embodiments of the present disclosure relate generally to semiconductor devices. In particular, embodiments of the present disclosure are directed to gate-all-around (GAA) devices that include a filled dielectric material and methods for fabricating the same. [Background technology]

[0002]

[0002] Transistors are a key component of most integrated circuits. A transistor's drive current, and therefore its speed, is proportional to its gate width, so faster transistors generally require larger gate widths. Therefore, there is a trade-off between transistor size and speed, and "fin" field-effect transistors (finFETs) have been developed to address the conflicting goals of transistors with maximum drive current and minimum size. FinFETs feature a fin-shaped channel region that significantly increases the size of a transistor without significantly increasing the transistor's footprint, and are currently utilized in many integrated circuits. However, finFETs have their own drawbacks.

[0003]

[0003] As the feature sizes of transistor devices continue to shrink to achieve greater circuit density and higher performance, improved transistor device structures are needed to improve electrostatic coupling and reduce adverse effects such as parasitic capacitance and off-state leakage. Examples of transistor device structures include planar structures, fin field effect transistor (FinFET) structures, and gate-all-around (GAA) structures. The GAA device structure includes several lattice-matched channels suspended within a stacked configuration and connected by source / drain regions. The GAA structure provides good electrostatic control and can find wide adoption in complementary metal-oxide-semiconductor (CMOS) wafer fabrication.

[0004]

[0004] Connecting the semiconductor to the power rail is typically done on the front side of the cell, which requires a large cell area. For backside power rail formation, the wafer thickness is thinned after frontside processing using a chemical mechanical planarization (CMP) process that does not have an etch stop layer. This results in overpolishing during CMP and problems with some wafer thickness characteristics. For backside power rail formation, via etching is performed through the silicon from the backside of the wafer to gain access to the source-epi. Because this process does not have an etch stop layer, it can be overetched, resulting in shorts, or underetched, resulting in opens. Therefore, improved semiconductor devices and methods for their manufacture are needed. Summary of the Invention

[0005]

[0005] One or more embodiments of the present disclosure are directed to a method of forming a semiconductor device. In one or more embodiments, the method of forming the semiconductor device includes forming a superlattice structure on a top surface of a shallow trench isolation structure on a substrate, the superlattice structure including a plurality of horizontal channel layers and a corresponding plurality of semiconductor material layers arranged alternately in a plurality of stacked pairs, forming a plurality of source trenches and a plurality of drain trenches adjacent to the superlattice structure on the substrate, extending at least one of the plurality of source trenches and at least one of the plurality of drain trenches to form a source cavity and a drain cavity, depositing a sacrificial layer in the source cavity and the drain cavity, forming a source region and a drain region on the sacrificial layer, forming a gate structure on the top surface of the superlattice structure, etching to form a plurality of aligned via openings in the sacrificial layer, removing the sacrificial layer to form at least one opening extending from the plurality of vias to the source region and the drain region, and depositing metal in the plurality of via openings and in the opening to form the plurality of vias.

[0006]

[0006] Further embodiments of the present disclosure are directed to a method of forming a semiconductor device. In one or more embodiments, the method of forming the semiconductor device includes forming a superlattice structure on top of a shallow trench isolation on a substrate, the superlattice structure including a plurality of horizontal channel layers and a corresponding plurality of semiconductor material layers arranged alternately in a plurality of stacked pairs; forming a gate structure on top of the superlattice structure; forming a plurality of source trenches and a plurality of drain trenches adjacent to the superlattice structure on the substrate; extending at least one of the plurality of source trenches and at least one of the plurality of drain trenches to form a source cavity and a drain cavity; depositing a sacrificial layer in the source cavity and the drain cavity; forming a replacement metal gate adjacent to the superlattice structure; forming CT and CG in electrical contact with the source and drain regions; forming a first metal line; rotating the semiconductor device 180 degrees; planarizing the substrate; depositing an interlayer dielectric material on the substrate; forming a backside power rail via in the substrate to the sacrificial layer; removing the sacrificial layer to form at least one opening extending from the backside power rail via to the source and drain regions; and depositing metal in the backside power rail via and in the opening.

[0007]

[0007] Further embodiments include a non-transitory computer readable medium containing instructions that, when executed by a controller of a processing chamber, cause the processing chamber to perform a plurality of steps, including forming a superlattice structure on top of a shallow trench isolation on a substrate, the superlattice structure including a plurality of horizontal channel layers and a corresponding plurality of semiconductor material layers arranged alternately in a plurality of stacked pairs; forming a plurality of source trenches and a plurality of drain trenches adjacent to the superlattice structure on the substrate; and forming a plurality of source trenches and a plurality of drain trenches to form source cavities and drain cavities. and depositing a gate structure on the top surface of the superlattice structure; etching to form a plurality of aligned via openings in the sacrificial layer; removing the sacrificial layer to form at least one opening extending from the plurality of vias to the source and drain regions; and depositing metal in the plurality of via openings and in the opening to form the plurality of vias.

[0008]

[0008] So that the features of the present disclosure described above may be understood in detail, a more particular description of the present disclosure briefly summarized above may be had by reference to several embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the attached drawings illustrate only typical embodiments of the present disclosure, and the present disclosure may admit of other equally effective embodiments, and therefore the attached drawings should not be considered as limiting the scope of the present disclosure. [Brief explanation of the drawings]

[0009] [Figure 1-1] 1-1 and 1-2 (collectively FIG. 1) are process flow diagrams of methods according to one or more embodiments. [Figure 1-2]1-1 and 1-2 (collectively FIG. 1) are process flow diagrams of methods according to one or more embodiments. [Figure 2A]

[0010] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2B]

[0011] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2C]

[0012] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2D]

[0013] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2E]

[0014] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2F]

[0015] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2G]

[0016] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2H]

[0017] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2I]

[0018] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2J]

[0019] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2K]

[0020] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2L]

[0021] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2M]

[0022] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2N]

[0023] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2O]

[0024] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2P]

[0025] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2Q]

[0026] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2R]

[0027] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2S]

[0028] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2T]

[0029] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2U]

[0030] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2V]

[0031] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2W]

[0032] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 3]

[0033] 1 illustrates a cluster tool in accordance with one or more embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0010]

[0034] To facilitate understanding, the same reference numerals have been used, where possible, to designate identical elements common to the figures. The figures are not to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated in other embodiments without further description.

[0011]

[0035] Before describing several example embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of structure or process steps set forth in the following description. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0012]

[0036] The term "substrate," as used herein and in the appended claims, refers to a surface or portion of a surface upon which a process acts. It will also be appreciated by those skilled in the art that when reference is made to a substrate, it may refer to only a portion of the substrate, unless the context clearly dictates otherwise. Furthermore, when reference is made to deposition on a substrate, it may refer to both a bare substrate and a substrate upon which one or more films or features have been deposited or formed.

[0013]

[0037] As used herein, "substrate" refers to any substrate or material surface formed on a substrate on which a film treatment is performed during a manufacturing process. For example, substrate surfaces on which treatments can be performed include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. Substrates can be exposed to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate (or otherwise create or graft target chemical moieties to impart chemical functionality), anneal, and / or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, the present disclosure also provides that any of the disclosed film processing steps may also be performed on underlying layers formed on the substrate, as disclosed in more detail below. The term "substrate surface" is intended to include such underlying layers, as the context indicates. Thus, for example, if a film / layer or partial film / layer is being deposited on a substrate surface, the exposed surface of the newly deposited film / layer would be the substrate surface. What a given substrate surface comprises will depend on what film is being deposited and the particular chemistry used.

[0014]

[0038] As used herein and in the appended claims, the terms "precursor," "reactant," "reactive gas," and the like are used interchangeably to refer to any gas species capable of reacting with the substrate surface.

[0015]

[0039] A transistor is a circuit component or element that is often formed on a semiconductor device. Depending on the circuit design, transistors may be formed on the semiconductor device in addition to capacitors, inductors, resistors, diodes, conductive lines, etc. Generally, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source and drain regions include doped substrate regions and exhibit a doping profile suitable for a particular application. The gate is disposed above a channel region and includes a gate dielectric interposed between the gate electrode in the substrate and the channel region.

[0016]

[0040] As used herein, the term "field effect transistor" or "FET" refers to a transistor that uses an electric field to control the electrical behavior of the device. Enhancement-mode field effect transistors generally exhibit very high input impedance at low temperatures. The conductivity between the drain and source terminals is controlled by the electric field within the device. The electric field is generated by a voltage difference between the body and gate of the device. The three terminals of a FET are the source (S), through which carriers enter the channel, the drain (D), through which carriers leave the channel, and the gate (G), which is the terminal that controls the conductivity of the channel. Conventionally, the current entering the channel at the source (S) is expressed as I S and the current entering the channel at the drain (D) is I D The voltage between the drain and source is V DS By applying a voltage to the gate (G), a current (i.e., I D ) can be controlled.

[0017]

[0041] A metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of field-effect transistor (FET). It has an insulated gate, and the voltage across the gate determines the device's conductivity. This ability to change conductivity in response to an applied voltage is used to amplify or switch electronic signals. MOSFETs rely on modulation of charge concentration through a metal-oxide-semiconductor (MOS) capacitor between a body electrode and a gate electrode located above the body and insulated from all other device regions by a gate dielectric layer. Compared to a MOS capacitor, a MOSFET contains two additional terminals (source and drain), each connected to a separate, highly doped region separated by a body region. These regions can be p-type or n-type, but must both be the same type, opposite the type of the body region. The source and drain (unlike the body) are highly doped, as indicated by a "+" symbol after the doping type.

[0018]

[0042] If the MOSFET is an n-channel or nMOSFET, the source and drain are n+ regions and the body is a p region. If the MOSFET is a p-channel or pMOSFET, the source and drain are p+ regions and the body is an n region. The source is so named because it is the source of charge carriers (electrons for an n-channel, holes for a p-channel) that flow through the channel; similarly, the drain is so named because it is where charge carriers leave the channel.

[0019]

[0043] As used herein, "fin field effect transistor (FinFET)" refers to a MOSFET transistor constructed on a substrate with gates located on two or three sides of the channel, forming a double or triple gate structure. FinFET devices are given the generic name FinFET because the channel region forms a "fin" on the substrate. FinFET devices have fast switching times and high current densities.

[0020]

[0044] As used herein, the term "gate-all-around (GAA)" is used to refer to an electronic device, e.g., a transistor, in which a gate material surrounds a channel region on all sides. The channel region of a GAA transistor may comprise a nanowire, nanoslab, or nanosheet, a bar-shaped channel, or other suitable channel configuration known to those skilled in the art. In one or more embodiments, the channel region of a GAA device comprises multiple vertically spaced horizontal nanowires or horizontal bars, making the GAA transistor a stacked horizontal gate-all-around (hGAA) transistor.

[0021]

[0045] As used herein, the term "nanowire" refers to a wire measuring 10 nanometers (10 -9 Nanowires refer to nanostructures having diameters on the order of tens of nanometers. Nanowires may also be defined as having a length-to-width ratio of greater than 1000. Alternatively, nanowires may be defined as structures whose thickness and diameter are constrained to tens of nanometers or less, but whose length is not. Nanowires are used in transistors and some laser applications and, in one or more embodiments, are made of semiconducting, metallic, insulating, superconducting, or molecular materials. In one or more embodiments, nanowires are used in transistors for logic CPUs, GPUs, MPUs, and volatile (e.g., DRAM) and nonvolatile (e.g., NAND) devices. As used herein, the term "nanosheet" refers to two-dimensional nanostructures having thicknesses on the scale ranging from about 0.1 nm to about 1000 nm.

[0022]

[0046] Embodiments of the present disclosure are illustrated by drawings, which illustrate devices (e.g., transistors) and processes for forming transistors according to one or more embodiments of the present disclosure. Those skilled in the art will recognize that the illustrated processes are merely exemplary possible uses for the disclosed processes, and that the disclosed processes are not limited to the applications illustrated.

[0023]

[0047] One or more embodiments of the present disclosure are described with reference to several drawings. In one or more embodiment methods, transistors, such as gate-all-around transistors, are fabricated using standard process flows. In some embodiments, an advanced chemical mechanical planarization (CMP) process is used to achieve the backside power rail, using shallow trench isolation (STI) as an etch stop for backside wafer polishing. Fill dielectric material and backside power rail are integrated for GAA transistor applications. In one or more embodiments, the fill dielectric material serves as an effective etch stop for the backside power rail via etch process, connecting the bottom of the NMOS and PMOS source epi.

[0024]

[0048] In one or more embodiment methods, transistors, e.g., gate-all-around transistors, are fabricated using a standard process flow. After the source / drain cavities are recessed, the dimensions of the source / drain cavities are expanded and a sacrificial fill material is deposited. Fabrication proceeds with inner spacer formation, source / drain epitaxy, interlayer dielectric formation, replacement gate formation, CT and CG formation, and front metal line formation. The substrate is then inverted and planarized. An interlayer dielectric is deposited on the backside, backside power rail vias are patterned, and the interlayer dielectric is etched. A damascene trench is formed and the sacrificial layer fill is removed to form an opening. Metal is deposited in the opening, and then a backside metal line is formed. In one or more embodiments, the sacrificial layer fill material is advantageously selective. When etched, it forms self-aligned trenches and / or vias, thus avoiding misalignment.

[0025]

[0049] FIG. 1 illustrates a process flow diagram of method 6 for forming a semiconductor device according to some embodiments of the present disclosure. FIGS. 2A-2W illustrate stages in the fabrication of a semiconductor structure according to some embodiments of the present disclosure. Below, method 6 is described with reference to FIGS. 2A-2W. FIGS. 2A-2W illustrate cross-sectional views of an electronic device (e.g., a GAA) according to one or more embodiments. Method 6 may be part of a multi-step fabrication process for a semiconductor device. Thus, method 6 may be performed in any suitable process chamber coupled to a cluster tool. The cluster tool may include process chambers for fabricating semiconductor devices, such as chambers configured for etching, deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), oxidation, or any other suitable chamber used in the fabrication of semiconductor devices.

[0026]

[0050] 2A-2W illustrate several manufacturing steps 8 through 44 of FIG. 1. Referring to FIG. 1, a method 6 of forming a device 100 begins in step 8 by providing a substrate 102. In some embodiments, the substrate 102 may be a bulk semiconductor substrate. As used herein, the term "bulk semiconductor substrate" refers to a substrate composed entirely of semiconductor material. A bulk semiconductor substrate may be composed of any suitable semiconductor material and / or combination of semiconductor materials for forming a semiconductor structure. For example, the semiconductor layer may be crystalline silicon (e.g., Si <100> or Si <111> The semiconductor substrate 102 may comprise one or more materials such as silicon dioxide, strained silicon (developed by IBM), silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, gallium arsenide, or other suitable semiconductor materials. In some embodiments, the semiconductor material is silicon (Si). In one or more embodiments, the semiconductor substrate 102 comprises a semiconductor material, such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), other semiconductor materials, or any combination thereof. In one or more embodiments, the substrate 102 comprises one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), or phosphorus (P). Although some examples of materials from which the substrate may be formed are described herein, any material that may serve as a foundation upon which passive and active electronic devices (e.g., transistors, memory, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic device) may be built is within the spirit and scope of the present disclosure.

[0027]

[0051] In some embodiments, the semiconductor material may be a doped material, such as n-type doped silicon (n-Si) or p-type doped silicon (p-Si). In some embodiments, the substrate may be doped using any suitable process, such as an ion implantation process. As used herein, the term "n-type" refers to a semiconductor made by doping an intrinsic semiconductor with an electron-donating element during fabrication. The term n-type comes from the negative charge carried by electrons. In n-type semiconductors, electrons are the majority carriers and holes are the minority carriers. As used herein, the term "p-type" refers to a well of positive charge (or holes). Relative to n-type semiconductors, p-type semiconductors have a higher hole concentration than electron concentration. In p-type semiconductors, holes are the majority carriers and electrons are the minority carriers. In one or more embodiments, the dopant is selected from one or more of boron (B), gallium (Ga), phosphorus (P), arsenic (As), other semiconductor dopants, or combinations thereof.

[0028]

[0052] 1 and 2A, in some embodiments, an etch stop layer 103 may be formed on the top surface of the substrate in step 10. The etch stop layer 103 may comprise any suitable material known to those skilled in the art. In one or more embodiments, the etch stop layer 103 comprises silicon germanium (SiGe). In one or more embodiments, the etch stop layer 103 has a high germanium (Ge) content. In one or more embodiments, the amount of germanium ranges from 30% to 50%, including 35% to 45%. Without being bound by theory, a germanium content of 30% to 50% is believed to increase the selectivity of the etch stop layer and minimize stress defects. In one or more embodiments, the etch stop layer has a thickness in the range of 5 nm to 30 nm. The etch stop layer 103 may function as an etch stop for planarization (e.g., CMP), dry etching, or wet etching during backside processing.

[0029]

[0053] In one or more non-illustrated embodiments, in step 12, an epitaxial layer, for example epitaxial silicon, may be deposited on the etch stop layer 103. The epitaxial layer has a thickness in the range of 20 nm to 100 nm.

[0030]

[0054] 1 and 2A, in one or more embodiments, at least one superlattice structure 101 is formed on the top surface of the substrate 102 or on the top surface of the etch stop layer 103 and the epitaxial layer in step 14. The superlattice structure 101 includes a plurality of semiconductor material layers 104 and a corresponding plurality of horizontal channel layers 106 arranged alternately in a plurality of stacked pairs. In some embodiments, the plurality of stacked layers includes silicon (Si) and silicon germanium (SiGe). In some embodiments, the plurality of semiconductor material layers 104 includes silicon germanium (SiGe) and the plurality of horizontal channel layers 106 includes silicon (Si). In other embodiments, the plurality of horizontal channel layers 106 includes silicon germanium (SiGe) and the plurality of semiconductor material layers 104 includes silicon (Si).

[0031]

[0055] In some embodiments, the plurality of semiconductor material layers 104 and the corresponding plurality of horizontal channel layers 106 may include any number of lattice-matched material pairs suitable for forming the superlattice structure 204. In some embodiments, the plurality of semiconductor material layers 104 and the corresponding plurality of horizontal channel layers 106 include from about 2 to about 50 pairs of lattice-matched materials.

[0032]

[0056] In one or more embodiments, the thickness of the semiconductor material layers 104 and the horizontal channel layers 106 ranges from about 2 nm to about 50 nm, from about 3 nm to about 20 nm, or from about 2 nm to about 15 nm.

[0033] 1 and 2B, in one or more embodiments, in step 16, the superlattice structure 101 is patterned to form openings 108 between adjacent stacks 105. Patterning may be performed by any suitable technique known to those skilled in the art. As used in this context, the term "opening" refers to any intentional surface irregularity. Suitable examples of openings include, but are not limited to, trenches having a top, two sides, and a bottom. The openings may have any suitable aspect ratio (ratio of feature depth to feature width). In some embodiments, the aspect ratio is about 5:1, about 10:1, about 15:1, about 20:1, about 25:1, about 30:1, about 35:1, or about 40:1 or greater.

[0034]

[0057] 1 and 2C, in step 18, shallow trench isolation (STI) 110 is formed. As used herein, "shallow trench isolation (STI)" refers to an integrated circuit feature that prevents current leakage. In one or more embodiments, the STI is created by depositing one or more dielectric materials (such as silicon dioxide) to fill the trench or opening 108 and removing excess dielectric using techniques such as chemical mechanical planarization.

[0035]

[0058] 1 and 2D, in some embodiments, a replacement gate structure 113 (e.g., a dummy gate structure) is formed over and adjacent to the superlattice structure 101. The dummy gate structure 113 defines a channel region of the transistor device. The dummy gate structure 113 may be formed using any suitable conventional deposition and patterning process known in the art.

[0036]

[0059] In one or more embodiments, the dummy gate structure 113 includes one or more of a gate 114 and a polysilicon layer 112. In one or more embodiments, the dummy gate structure 113 includes one or more of tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum (TiAl), and N-doped polysilicon.

[0037]

[0060] 1 and 2E, in some embodiments, in step 22, sidewall spacers 116 are formed along outer sidewalls of dummy gate structures 113 on superlattice structure 101. Sidewall spacers 116 comprise any suitable insulating material known in the art, such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, etc. In some embodiments, the sidewall spacers are formed using any suitable conventional deposition and patterning process known in the art, such as atomic layer deposition, plasma-enhanced atomic layer deposition, plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, or isotropic deposition.

[0038]

[0061] 1 and 2F, in step 24, in one or more embodiments, source / drain trenches 118 are formed adjacent to (ie, on either side of) the superlattice structure 101.

[0039]

[0062] 1 and 2G, in step 26, in one or more embodiments, the source / drain trenches 118 are deepened and widened by lateral etching to form cavities 119 below the superlattice structure 101. The cavities 119 may have any suitable depth and width. In one or more embodiments, the cavities 119 extend through the shallow trench isolation 110 and into the substrate 102. In one or more embodiments, the etch stop layer 103 is removed during etching of the cavities 119, thereby extending the cavities 119 down to the substrate 102.

[0040]

[0063] The cavity 119 may be formed by any suitable means known to those skilled in the art. The etching process of step 26 may include any suitable etching process that is selective to the source-drain trenches 118. In some embodiments, the etching process of step 26 includes one or more of a wet etch or a dry etch. The etching process may be a directional etch.

[0041]

[0064] In some embodiments, the dry etching process may include conventional plasma etching or a remote plasma-assisted dry etching process, such as the SiCoNi™ etch process available from Applied Materials, Inc., Santa Clara, California. In the SiCoNi™ etch process, the device is exposed to H, NF, and / or NH plasma species, such as plasma-excited hydrogen and fluorine species. For example, in some embodiments, the device may be subjected to simultaneous exposure to H, NF, and NH plasma. The SiCoNi™ etch process may be performed in a SiCoNi™ etch preclean chamber. The SiCoNi™ etch preclean chamber may be integrated into one of a variety of multi-processing platforms, including the Centura®, Dual ACP, Producer® GT, and Endura® platforms, all of which are commercially available from Applied Materials, Inc. The wet etching process may include a hydrofluoric (HF) acid final process (i.e., a so-called "HF last" process), in which a HF etch of the surface is performed, leaving the surface hydrogen-terminated. Alternatively, any other liquid-based pre-epitaxial pre-cleaning process may be employed. In some embodiments, the process includes a sublimation etch for native oxide removal. The etching process may be plasma-based or thermal-based. The plasma process may be any suitable plasma (e.g., conductively coupled plasma, inductively coupled plasma, microwave plasma).

[0042]

[0065] 1 and 2H, in step 28, a sacrificial layer 120 is deposited in cavity 119. Sacrificial layer 120 may comprise any suitable material known to those skilled in the art. In one or more embodiments, sacrificial layer 120 may comprise any suitable material having an etch rate different from that of shallow trench isolation 110, as well as crystalline silicon and crystalline silicon germanium (SiGe). In one or more embodiments, sacrificial layer 120 comprises a dielectric material. As used herein, the term "dielectric material" refers to an electrical insulator that can be polarized in an electric field. In some embodiments, the dielectric material comprises one or more of an oxide, a carbon-doped oxide, silicon dioxide (SiO), porous silicon dioxide (SiO), silicon nitride (SiN), silicon dioxide / silicon nitride, a carbide, an oxycarbide, a nitride, an oxynitride, an oxycarbonitride, a polymer, a phosphosilicate glass, a fluorosilicate (SiOF) glass, or an organosilicate glass (SiOCH). In one or more embodiments, the sacrificial layer 120 comprises a silicon oxide (SiO x ), silicon nitride (SiN), silicon carbide (SiC), boron-doped silicon, silicon-doped boron, metal, metal oxide, metal silicide, metal carbide, and high-k dielectric materials. In some embodiments, the high-k dielectric material is selected from one or more of aluminum oxide (Al2O3), hafnium oxide (HfO2), and the like. In one or more particular embodiments, the sacrificial layer 120 is silicon oxide (SiO x ) is included. In one or more specific embodiments, the sacrificial layer 120 has a thickness in the range of 2 nm to 50 nm.

[0043]

[0066] In some embodiments, the dielectric material 120 is deposited on the substrate 102 using conventional chemical vapor deposition techniques. In some embodiments, the sacrificial layer 120 is recessed below the top surface of the substrate 102, thereby forming a lower portion of the superlattice structure 101 from the substrate 102.

[0044]

[0067] 1 and 2I, in step 30, an inner spacer layer 121 is formed on each of the horizontal channel layers 106. The inner spacer layer 121 may comprise any suitable material known to those skilled in the art. In one or more embodiments, the inner spacer layer 121 comprises a nitride material. In certain embodiments, the inner spacer layer 121 comprises silicon nitride.

[0045]

[0068] 2J and 1, in step 32, in some embodiments, buried PMOS source 122 and NMOS source 123 regions are formed in source / drain trenches 118. In some embodiments, buried PMOS source 122 is formed adjacent a first end of superlattice structure 101, and NMOS source 123 is formed adjacent a second, opposite end of superlattice structure 101. In some embodiments, buried PMOS source 122 and NMOS source 123 regions are formed from any suitable semiconductor material, such as, but not limited to, silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon phosphide (SiP), or silicon arsenide (SiAs). In some embodiments, buried PMOS source 122 and NMOS source 123 regions may be formed using any suitable deposition process, such as an epitaxial deposition process. In some embodiments, the buried PMOS source 122 and NMOS source 123 regions are independently doped with one or more of phosphorus (P), arsenic (As), boron (B), and gallium (Ga).

[0046]

[0069] 1 and 2K, in step 34, an interlayer dielectric (ILD) layer 124 is blanket deposited over the substrate 102, including the PMOS source 122 and NMOS source 123 regions, the dummy gate structure 113, and the sidewall spacers 116. The ILD layer 124 may be deposited using conventional chemical vapor deposition (e.g., plasma-enhanced chemical vapor deposition or low-pressure chemical vapor deposition). In one or more embodiments, the ILD layer 124 is formed from any suitable dielectric material, such as, but not limited to, undoped silicon oxide, doped silicon oxide (e.g., BPSG or PSG), silicon nitride, and silicon oxynitride. In one or more embodiments, the ILD layer 124 is then polished back using conventional chemical mechanical planarization to expose the top of the dummy gate structure 113. In some embodiments, the ILD layer 124 is polished back to expose the top of the dummy gate structure 113 and the top of the sidewall spacers 116.

[0047]

[0070] The dummy gate structure 113 may be removed to expose the channel region 108 of the superlattice structure 101. The ILD layer 124 protects the PMOS source 122 and NMOS source 123 regions during removal of the dummy gate structure 113. The dummy gate structure 113 may be removed using any conventional etching method, such as plasma dry etching or wet etching. In some embodiments, the dummy gate structure 113 comprises polysilicon, and the dummy gate structure 113 is removed by a selective etching process. In some embodiments, the dummy gate structure 113 comprises polysilicon, and the superlattice structure 101 comprises alternating layers of silicon (Si) and silicon germanium (SiGe).

[0048]

[0071] 1 and 2L, in step 36, formation of a semiconductor device, e.g., a GAA, continues according to conventional procedures involving the release of nanosheets and the formation of a replacement metal gate 126. In particular, in one or more non-illustrated embodiments, the semiconductor material layers 104 are selectively etched between the horizontal channel layers 106 in the superlattice structure 101. For example, if the superlattice structure 101 is composed of silicon (Si) and silicon germanium (SiGe) layers, the silicon germanium (SiGe) is selectively etched to form channel nanowires. The semiconductor material layers 104, e.g., silicon germanium (SiGe), can be removed using any known etchant selective to the horizontal channel layers 106, where the etchant etches the semiconductor material layers 104 at a significantly higher rate than the horizontal channel layers 106. In some embodiments, a selective dry etching or wet etching process may be used. In some embodiments where the nanosheet channel layers 106 are silicon (Si) and the semiconductor material layers 104 are silicon germanium (SiGe), the silicon germanium layer can be selectively removed using a wet etchant, such as, but not limited to, a carboxylic acid / nitric acid / HF solution and a citric acid / nitric acid / HF solution. Removal of the semiconductor material layers 104 leaves voids between the horizontal channel layers 106. The voids between the horizontal channel layers 106 have a thickness of about 3 nm to about 20 nm. The remaining horizontal channel layers 106 form a vertical array of channel nanowires coupled to the PMOS source 122 and NMOS source 123 regions. The channel nanowires extend parallel to the top surface of the substrate 102 and are aligned with each other to form a single row of channel wires.

[0049]

[0072] In one or more embodiments, a high-k dielectric is formed. The high-k dielectric may be any suitable high-k dielectric material deposited by any suitable deposition technique known to those skilled in the art. In some embodiments, the high-k dielectric comprises hafnium oxide. In some embodiments, a conductive material, such as titanium nitride (TiN), tungsten (W), cobalt (Co), or aluminum (Al), is deposited on the high-k dielectric to form a replacement metal gate 126. The conductive material may be formed using any suitable deposition process, such as, but not limited to, atomic layer deposition (ALD), to ensure that a layer having a uniform thickness is formed around each of the multiple channel layers.

[0050]

[0073] Referring to FIGS. 1 and 2M and 2N, in step 38: PMOS source 122 and NMOS source 123 regions Drain contact (CT) 132 for Replacement Metal Gate 126 A contact point (CG) 134 to the

[0051]

[0074] 1 and 2O-2P, in step 40, a metal (M0) line 142 and a metal (M1) line 146 are formed and electrically connected to a via (V1) 144.

[0052]

[0075] Referring to FIG. 2Q, in step 42, the device 100 is rotated or flipped 180 degrees, so that the substrate 102 is now at the top of the figure. Referring to FIG. 2R, in one or more embodiments, the substrate 102 is planarized, stopping on the STI oxide 110. Planarization can be any suitable planarization process known to those skilled in the art, including, but not limited to, chemical mechanical polishing (CMP). In some embodiments, an advanced chemical mechanical planarization (CMP) process is used, using shallow trench isolation (STI) 110 as an etch stop layer for backside wafer polishing to achieve the backside power rail. Advanced CMP uses endpoint detection (EDP). Precise process control and EDP are required to minimize dishing and erosion within the structure. Conventional CMP does not use endpoint detection (EDP). In one or more embodiments, prior to rotation, the front side is bonded to copper (Cu) metallization in the final layer using hybrid bonding (oxide-to-oxide and Cu-to-Cu) or electrostatic dummy wafer bonding.

[0053]

[0076] 1 and 2S, in step 44, an interlayer dielectric material 148 is deposited on the backside. The interlayer dielectric material 148 may be deposited by any suitable means known to those skilled in the art. The interlayer dielectric material 148 may include any suitable material known to those skilled in the art. In one or more embodiments, the interlayer dielectric material 148 includes one or more of silicon nitride (SiN), carbide, or boron carbide to enable high aspect ratio etching and metallization.

[0054]

[0077] 2S, in step 46, in one or more embodiments, backside vias 152 are patterned. The vias 152 may be formed by any suitable means known to those skilled in the art. In one or more embodiments, the vias 152 may be formed by patterning and etching the interlayer dielectric material 148 and removing the substrate 102 to form the vias 152. When the vias 152 are patterned, they extend from the top surface of the interlayer dielectric material 148 to the sacrificial layer 120. Thus, in one or more embodiments, the sacrificial layer 120 functions as an etch stop. In some embodiments, the aspect ratio of the vias 152 is about 5:1, about 10:1, about 15:1, about 20:1, about 25:1, about 30:1, about 35:1, or about 40:1 or greater.

[0055]

[0078] In step 48, the sacrificial layer 120 is selectively removed to form openings 156 over the source / drains (PMOS source 122 and NMOS source 123 regions), as shown in FIG. 2T.

[0056]

[0079] In step 50, device 100 is silicided and a barrier layer 158 is deposited in via 152, as shown in FIG. 2U. Barrier layer 158 may comprise any suitable material known to those skilled in the art. In some embodiments, barrier layer 158 comprises titanium nitride (TiN) or tantalum nitride (TaN).

[0057]

[0080] 2V, in step 52, metal 160 is deposited on barrier layer 158 in via 152. Metal 160 may include any suitable metal known to those skilled in the art. In one or more embodiments, metal 160 is selected from one or more of tungsten (W), molybdenum (Mo), cobalt (Co), copper (Cu), ruthenium (Ru), and the like.

[0058]

[0081] 1 and 2W, in step 54, backside metal lines (MO) 162 are formed. Without being bound by theory, it is believed that placing the power rail on the backside can increase the cell area by between 20% and 30%.

[0059]

[0082] Further embodiments of the present disclosure are directed to a processing tool 300 for forming the described GAA devices and methods, as shown in FIG. 3. Various multi-processing platforms may be utilized, including the Reflexion® CMP, Selectra® Etch, Centura®, Dual ACP, Producer® GT, and Endura® platforms available from Applied Materials®. The cluster tool 300 includes at least one central transfer station 314 having multiple sides. A robot 316 is disposed within the central transfer station 314 and configured to move a robot blade and wafer to each of the multiple sides.

[0060]

[0083] The cluster tool 300 includes multiple processing chambers 308, 310, and 312 (also referred to as process stations) connected to a central transfer station. The various processing chambers provide separate processing regions isolated from adjacent process stations. The processing chambers may be any suitable chambers, including, but not limited to, pre-clean, pre-clean, deposition, annealing, etch, etc. The specific arrangement of process chambers and components may vary depending on the cluster tool and should not be construed as limiting the scope of the present disclosure.

[0061]

[0084] 3, a factory interface 318 is connected to the front of the cluster tool 300. The factory interface 318 includes a loading and unloading chamber 302 on the front 319 of the factory interface 318.

[0062]

[0085] The size and shape of the loading and unloading chambers 302 can vary depending on, for example, the substrates to be processed in the cluster tool 300. In the illustrated embodiment, the loading and unloading chambers 302 are sized to hold a wafer cassette having multiple wafers disposed within the cassette.

[0063]

[0086] A robot 304 resides within a factory interface 318 and is capable of moving between the loading chamber and the unloading chamber 302. The robot 304 is capable of transferring wafers from a cassette in the loading chamber 302 through the factory interface 318 to a load lock chamber 320. The robot 304 is also capable of transferring wafers from the load lock chamber 320 through the factory interface 318 to a cassette in the unloading chamber 302.

[0064]

[0087] In some embodiments, the robot 316 is a multi-arm robot capable of independently moving multiple wafers at a time. The robot 316 is configured to move wafers between chambers around the transfer chamber 314. Individual wafers are carried on a wafer transfer blade positioned at the distal end of the first robotic mechanism.

[0065]

[0088] A system controller 357 communicates with the robot 316 and the multiple processing chambers 308, 310, and 312. The system controller 357 can be any suitable component capable of controlling the processing chambers and the robot. For example, the system controller 357 can be a computer including a central processing unit (CPU) 392, memory 394, input / output (I / O) 396, and support circuits 398.

[0066]

[0089] The processes may generally be stored in the memory of the system controller 357 as software routines that, when executed by a processor, cause the process chamber to perform the processes of the present disclosure. The software routines may also be stored and / or executed by a second processor (not shown) located remotely from the hardware controlled by the processor. Some or all of the methods of the present disclosure may also be performed in hardware. Thus, the processes may be implemented in software and implemented in hardware using a computer system, for example, as an application-specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. The software routines, when executed by a processor, transform a general-purpose computer into a special-purpose computer (controller) that controls chamber operation to perform the processes.

[0067]

[0090] In some embodiments, the system controller 357 is configured to control a rapid thermal processing chamber to crystallize the template material.

[0068]

[0091] In one or more embodiments, the processing tool includes a central transfer station with a robot configured to move wafers; a plurality of process stations, each process station connected to the central transfer station and providing a processing area separated from the processing areas of adjacent process stations, the plurality of process stations including a template deposition chamber and a template crystallization chamber; and a controller connected to the central transfer station and the plurality of process stations, the controller configured to activate the robot to move wafers between the process stations and to control the process performed at each of the process stations.

[0069]

[0092] In the context of describing the materials and methods described herein (particularly in the context of the claims below), use of the terms “a,” “an,” and “the” and similar referents is to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. The recitation of ranges of values ​​herein is merely intended to serve as a shorthand method of individually referencing each individual value falling within the range, unless otherwise stated herein, and each individual value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., “such as”) provided herein, is intended merely to better describe the materials and methods and does not limit the scope unless specifically claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

[0070]

[0093] Throughout this specification, references to "one embodiment," "certain embodiment," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of phrases such as "in one or more embodiments," "in a particular embodiment," "in one embodiment," or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment of the present disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0071]

[0094] Although the disclosure herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed method and apparatus without departing from the spirit and scope of the disclosure. Therefore, it is intended that the present invention cover such modifications and variations as come within the scope of the appended claims and their equivalents.

Claims

1. 1. A method of forming a semiconductor device, comprising: forming a superlattice structure on top of a shallow trench isolation on a substrate, the superlattice structure including a plurality of horizontal channel layers and a corresponding plurality of semiconductor material layers arranged alternately in a plurality of stacked pairs; forming a plurality of source trenches and a plurality of drain trenches adjacent to the superlattice structure on the substrate; extending at least one of the plurality of source trenches and at least one of the plurality of drain trenches to form a source cavity and a drain cavity; depositing a sacrificial layer within the source cavity and within the drain cavity; forming source and drain regions on the sacrificial layer; forming a gate structure on top of the superlattice structure; etching to form a plurality of aligned via openings in the sacrificial layer; removing the sacrificial layer to form at least one opening extending from the plurality of vias to the source region and the drain region; and depositing metal into the plurality of via openings and into the openings to form a plurality of vias; extending at least one of the plurality of source trenches and at least one of the plurality of drain trenches includes laterally etching to form a source cavity and a drain cavity. method.

2. 10. The method of claim 1, wherein the sacrificial layer has a different etch selectivity than the shallow trench isolation and the substrate.

3. The sacrificial layer is made of silicon oxide (SiO x ), silicon nitride (SiN), silicon carbide (SiC), boron doped silicon, silicon doped boron, metals, metal oxides, metal silicides, metal carbides, and high dielectric constant materials.

4. The method of claim 1 , wherein the sacrificial layer has a thickness in the range of 2 nm to 50 nm.

5. 10. The method of claim 1, wherein the plurality of semiconductor material layers comprises silicon germanium (SiGe) and the plurality of horizontal channel layers comprises silicon (Si).

6. 2. The method of claim 1, wherein the plurality of semiconductor material layers comprises silicon (Si) and the plurality of horizontal channel layers comprises silicon germanium (SiGe).

7. The method of claim 1 , wherein forming the source and drain regions comprises growing an epitaxial layer in those regions.

8. 10. The method of claim 1, wherein the source and drain regions are independently doped with one or more of phosphorus (P), arsenic (As), boron (B), and gallium (Ga).

9. 10. The method of claim 1, wherein the gate structure comprises one or more of tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum (TiAl), and N-doped polysilicon.

10. The method of claim 1 , wherein the method is performed in a processing chamber without breaking vacuum.

11. 1. A method of forming a semiconductor device, comprising: forming a superlattice structure on top of a shallow trench isolation on a substrate, the superlattice structure including a plurality of horizontal channel layers and a corresponding plurality of semiconductor material layers arranged alternately in a plurality of stacked pairs; forming a gate structure on top of the superlattice structure; forming a plurality of source trenches and a plurality of drain trenches adjacent to the superlattice structure on the substrate; extending at least one of the plurality of source trenches and at least one of the plurality of drain trenches to form a source cavity and a drain cavity; depositing a sacrificial layer within the source cavity and within the drain cavity; forming an inner spacer layer over each of the plurality of horizontal channel layers; forming source and drain regions on the sacrificial layer; forming a replacement metal gate adjacent to the superlattice structure; forming a contact in electrical contact with the source region and a contact in electrical contact with the replacement metal gate; forming a first metal line; rotating the semiconductor device by 180 degrees; planarizing the substrate; depositing an interlayer dielectric material on the substrate; forming a backside power rail via in the substrate to the sacrificial layer; removing the sacrificial layer to form at least one opening extending from the backside power rail via to the source region and the drain region; and depositing metal in the backside power rail via and in the opening; extending at least one of the plurality of source trenches and at least one of the plurality of drain trenches includes laterally etching to form a source cavity and a drain cavity. method.

12. 12. The method of claim 11, wherein the sacrificial layer has a different etch selectivity than the shallow trench isolation and the substrate.

13. The sacrificial layer is made of silicon oxide (SiO x 12. The method of claim 11 , wherein the dielectric layer comprises one or more of silicon nitride (SiN), silicon carbide (SiC), boron doped silicon, silicon doped boron, a metal, a metal oxide, a metal silicide, a metal carbide, and a high dielectric constant material.

14. The method of claim 11 , wherein the sacrificial layer has a thickness in the range of 2 nm to 50 nm.

15. 1. A non-transitory computer-readable medium containing instructions that, when executed by a controller of a processing chamber, cause the processing chamber to perform a plurality of steps, the plurality of steps comprising: forming a superlattice structure on top of a shallow trench isolation on a substrate, the superlattice structure including a plurality of horizontal channel layers and a corresponding plurality of semiconductor material layers arranged alternately in a plurality of stacked pairs; forming a plurality of source trenches and a plurality of drain trenches adjacent to the superlattice structure on the substrate; extending at least one of the plurality of source trenches and at least one of the plurality of drain trenches to form a source cavity and a drain cavity; depositing a sacrificial layer within the source cavity and within the drain cavity; forming source and drain regions on the sacrificial layer; forming a gate structure on top of the superlattice structure; etching to form a plurality of aligned via openings in the sacrificial layer; removing the sacrificial layer to form at least one opening extending from the plurality of vias to the source region and the drain region; and depositing metal into the plurality of via openings and into the openings to form a plurality of vias; extending at least one of the plurality of source trenches and at least one of the plurality of drain trenches includes laterally etching to form a source cavity and a drain cavity. Non-transitory computer-readable medium.

16. 16. The non-transitory computer-readable medium of claim 15, wherein the sacrificial layer has a different etch selectivity than the superlattice structure and the substrate.

17. The sacrificial layer is made of silicon oxide (SiO x 20. The non-transitory computer-readable medium of claim 15, comprising one or more of silicon nitride (SiN), silicon carbide (SiC), boron doped silicon, silicon doped boron, a metal, a metal oxide, a metal silicide, a metal carbide, and a high dielectric constant material.

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