semiconductor memory device

Abstract

To provide a semiconductor storage device which operates suitably.SOLUTION: A semiconductor storage device includes a plurality of first memory layers and a plurality of second memory layers which are alternately arranged along a first direction. The plurality of first memory layers and the plurality of second memory layers include a plurality of memory strings and first wiring commonly connected to them. The plurality of first memory layers and the plurality of second memory layers include a signal amplification circuit electrically connected to the first wiring, second wiring electrically connected to the signal amplification circuit, a first switch transistor connected to the second wiring, third wiring electrically connected to the second wiring through the first switch transistor, and fourth wiring electrically connected to the second wiring without through the first switch transistor. The semiconductor storage device includes a plurality of first via-contact electrodes extending along the first direction and connected to the third wiring on the first memory layer and a plurality of second via-contact electrodes extending along the first direction and connected to the fourth wiring on the second memory layer.SELECTED DRAWING: Figure 11

Description

[Technical Field]

[0001] The present embodiment relates to a semiconductor memory device. [Background technology]

[0002] 2. Description of the Related Art A semiconductor memory device is known in which a plurality of memory cells are stacked in a direction intersecting the surface of a substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 10,607,995 [Patent Document 2] Japanese Patent Application Publication No. 2017-056452 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor memory device that operates favorably is provided. [Means for solving the problem]

[0005] A semiconductor memory device according to one embodiment includes a substrate and a plurality of first memory layers and a plurality of second memory layers arranged alternately in a first direction intersecting a surface of the substrate. The substrate includes a plurality of local block regions arranged in a second direction intersecting the first direction, and hook-up regions arranged in the second direction relative to the plurality of local block regions. In the plurality of local block regions, the plurality of first memory layers and the plurality of second memory layers each include a plurality of memory strings extending in the second direction and arranged in a third direction intersecting the first and second directions, and a first wiring extending in the third direction and commonly connected to the plurality of memory strings. In the hook-up region, the plurality of first memory layers and the plurality of second memory layers each include a signal amplifier circuit electrically connected to the first wiring, a second wiring connected to the signal amplifier circuit, a first switch transistor connected to the second wiring, a third wiring electrically connected to the second wiring via the first switch transistor, and a fourth wiring electrically connected to the second wiring without passing through the first switch transistor. The hook-up region includes a plurality of first via contact electrodes extending in a first direction and connected to third wirings in a plurality of first memory layers, and a plurality of second via contact electrodes extending in the first direction and connected to fourth wirings in a plurality of second memory layers. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a schematic perspective view showing a configuration of a portion of a semiconductor memory device according to a first embodiment. [Figure 2] FIG. 2 is a schematic plan view showing a configuration of a part of the semiconductor memory device. [Figure 3] FIG. 2 is a schematic perspective view showing a configuration of a part of the semiconductor memory device. [Figure 4] FIG. 2 is a schematic circuit diagram showing a configuration of a part of the semiconductor memory device. [Figure 5] FIG. 3 is a schematic plan view showing an enlarged view of a portion indicated by A in FIG. 2. [Figure 6] FIG. 6 is a schematic plan view showing an enlarged view of a portion indicated by B in FIG. 5. [Figure 7]FIG. 3 is a schematic plan view showing an enlarged view of a portion indicated by C1 in FIG. 2. [Figure 8] 8 is a schematic cross-sectional view of the structure shown in FIG. 7 taken along line DD' and viewed in the direction of the arrow. [Figure 9] 8 is a schematic cross-sectional view of the structure shown in FIG. 7 taken along line EE' and viewed in the direction of the arrow. [Figure 10] FIG. 3 is a schematic plan view showing an enlarged view of a portion indicated by C2 in FIG. 2. [Figure 11] 1 is a schematic circuit diagram for explaining a configuration of a portion of a semiconductor memory device according to an embodiment of the present invention. [Figure 12] FIG. 2 is a schematic circuit diagram for explaining a configuration of a part of the semiconductor memory device. [Figure 13] FIG. 2 is a schematic plan view for explaining a configuration of a part of the semiconductor memory device. [Figure 14] FIG. 2 is a schematic plan view for explaining a configuration of a part of the semiconductor memory device. [Figure 15] FIG. 2 is a schematic circuit diagram showing a configuration of a part of the semiconductor memory device. [Figure 16] FIG. 2 is a schematic circuit diagram showing a configuration of a part of the semiconductor memory device. [Figure 17] 10 is a schematic timing chart for explaining a read operation of the semiconductor memory device. [Figure 18] FIG. 10 is a schematic circuit diagram for explaining the read operation. [Figure 19] FIG. 10 is a schematic circuit diagram for explaining the read operation. [Figure 20] FIG. 10 is a schematic circuit diagram for explaining the read operation. [Figure 21] FIG. 10 is a schematic circuit diagram for explaining the read operation. [Figure 22] FIG. 10 is a schematic circuit diagram for explaining the read operation. [Figure 23] FIG. 10 is a schematic circuit diagram for explaining the read operation. [Figure 24]FIG. 10 is a schematic circuit diagram for explaining the read operation. [Figure 25] FIG. 10 is a schematic circuit diagram for explaining the read operation. [Figure 26] FIG. 10 is a schematic circuit diagram for explaining the read operation. [Figure 27] FIG. 10 is a schematic circuit diagram for explaining the read operation. [Figure 28] FIG. 10 is a schematic circuit diagram for explaining the read operation. [Figure 29] FIG. 10 is a schematic circuit diagram for explaining the read operation. [Figure 30] FIG. 10 is a schematic circuit diagram for explaining the read operation. [Figure 31] FIG. 10 is a schematic circuit diagram for explaining the read operation. [Figure 32] FIG. 10 is a schematic circuit diagram for explaining the read operation. [Figure 33] FIG. 10 is a schematic circuit diagram for explaining the read operation. [Figure 34] FIG. 10 is a schematic circuit diagram for explaining the configuration of a portion of a semiconductor memory device according to a second embodiment. [Figure 35] FIG. 10 is a schematic circuit diagram for explaining the configuration of a portion of a semiconductor memory device according to a second embodiment. [Figure 36] FIG. 10 is a schematic plan view illustrating a configuration of a portion of a semiconductor memory device according to a second embodiment. [Figure 37] FIG. 10 is a schematic plan view for explaining a configuration of a portion of a semiconductor memory device according to another embodiment. [Figure 38] FIG. 10 is a schematic plan view for explaining a configuration of a portion of a semiconductor memory device according to another embodiment. [Figure 39] FIG. 10 is a schematic circuit diagram for explaining a configuration of a portion of a semiconductor memory device according to another embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Next, semiconductor memory devices according to embodiments will be described in detail with reference to the drawings. Note that the following embodiments are merely examples and are not intended to limit the present invention. The following drawings are schematic, and for the sake of explanation, some configurations may be omitted. Furthermore, parts common to multiple embodiments are given the same reference numerals, and explanations thereof may be omitted.

[0008] Furthermore, in this specification, the term "semiconductor memory device" may refer to a memory die, or may refer to a memory system including a controller die, such as a memory chip, a memory card, or an SSD (Solid State Drive). Furthermore, it may refer to a configuration including a host computer, such as a smartphone, a tablet terminal, or a personal computer.

[0009] Furthermore, in this specification, when a first component is said to be "electrically connected" to a second component, the first component may be directly connected to the second component, or the first component may be connected to the second component via wiring, a semiconductor member, a transistor, etc. For example, when three transistors are connected in series, the first transistor is "electrically connected" to the third transistor even if the second transistor is in the OFF state.

[0010] Furthermore, in this specification, when it is said that a first configuration is "connected between" a second configuration and a third configuration, it may mean that the first configuration, the second configuration, and the third configuration are connected in series, and that the second configuration is connected to the third configuration via the first configuration.

[0011] Furthermore, in this specification, when it is said that a circuit or the like "conducts" two wirings or the like, it may mean, for example, that the circuit or the like includes a transistor or the like, that the transistor or the like is provided in the current path between the two wirings, and that the transistor or the like is in the ON state.

[0012] In this specification, a predetermined direction parallel to the upper surface of the substrate is called the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is called the Y direction, and a direction perpendicular to the upper surface of the substrate is called the Z direction.

[0013] In addition, in this specification, a direction along a predetermined plane may be referred to as the first direction, a direction along this predetermined plane that intersects with the first direction may be referred to as the second direction, and a direction that intersects with this predetermined plane may be referred to as the third direction. These first, second, and third directions may or may not correspond to any of the X, Y, and Z directions.

[0014] Furthermore, in this specification, expressions such as "upper" and "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is referred to as "up," and the direction approaching the substrate along the Z direction is referred to as "lower." Furthermore, when referring to a certain configuration, the lower surface or lower end refers to the surface or end of the configuration facing the substrate, and when referring to the upper surface or upper end, refers to the surface or end of the configuration facing away from the substrate. Furthermore, surfaces that intersect with the X or Y direction are referred to as side surfaces, etc.

[0015] [First embodiment] [composition] 1 is a schematic perspective view showing a partial configuration of a semiconductor memory device according to the first embodiment. The semiconductor memory device according to this embodiment includes a semiconductor substrate Sub and a memory cell array layer L provided above the semiconductor substrate Sub. MCA and the memory cell array layer L MCA The transistor layer L T And, it is equipped with.

[0016] The semiconductor substrate Sub is a semiconductor substrate such as silicon (Si) containing P-type impurities such as boron (B). MCA A part of the peripheral circuitry that controls the internal configuration may also be provided.

[0017] Memory cell array layer L MCA The transistor layer L is provided with memory cells MC, which will be described later. TThe memory cell array layer L MCA A control circuit is provided for controlling the configuration therein.

[0018] [Memory cell array layer L MCA [Medium configuration] 2 is a schematic plan view showing a configuration of a part of the semiconductor memory device according to this embodiment. The semiconductor memory device according to this embodiment has a plurality of local block regions R LBLK and multiple hookup areas R HU and a plurality of local block connection line regions R LBIG and a local block area R LBLK are arranged in a matrix in the X and Y directions. HU are the local block regions R arranged in the Y direction. LBLK The hook-up area R HU are aligned in the X direction and are local block regions R LBLK The local block connection line area R LBIG are the local block regions R arranged in the Y direction. LBLK and the corresponding hookup area R HU The local block connection line area R LBIG is a set of these local block regions R in the X direction. LBLK and hookup area R HU Along with.

[0019] In the example in Figure 2, two local block regions R are arranged in the Y direction. LBLK A local block connection line LBI_a extending in the X direction is provided between these two local block regions R LBLK The components in the area are connected to the local block connection line LBI_a. LBIG A local block connection line LBI_b extending in the Y direction is provided in the hook-up region R. A plurality of local block connection lines LBI_a arranged in the Y direction are commonly connected to this local block connection line LBI_b.HU The local block connection lines LBI_b are connected to the transistor layer L through the configuration of the local block connection lines LBI_c and the like. T The device is electrically connected to the structure therein.

[0020] [Local Block Region R LBLK [Medium configuration] Fig. 3 is a schematic perspective view showing a configuration of a portion of the semiconductor memory device according to this embodiment, and Fig. 4 is a schematic circuit diagram showing a configuration of a portion of the semiconductor memory device according to this embodiment.

[0021] As shown in FIG. 3, the memory cell array layer L MCA has a plurality of memory layers ML arranged in the Z direction. In Fig. 3, the odd-numbered memory layers ML counting from the bottom are shown as memory layers ML_O. The even-numbered memory layers ML counting from the bottom are shown as memory layers ML_E. An insulating layer 101 such as silicon oxide (SiO2) is provided between two memory layers ML adjacent to each other in the Z direction.

[0022] As shown in Figure 4, the local block area R LBLK Each of the memory layers ML includes a plurality of string units SU. Each of the string units SU includes a plurality of memory units MU provided corresponding to a plurality of memory layers ML. Each of the memory units MU includes two memory strings MS. One end of each of the two memory strings MS is connected to a local block connection line LBI_a. The other ends of each of the two memory strings MS are connected to a common source line SL.

[0023] The memory string MS includes a drain-side select transistor STD, a plurality of memory cells MC (memory transistors), and a source-side select transistor STS. The drain-side select transistor STD, the plurality of memory cells MC, and the source-side select transistor STS are connected in series between a local block connection line LBI_a and a source line SL. Hereinafter, the drain-side select transistor STD and the source-side select transistor STS may be simply referred to as select transistors (STD, STS).

[0024] The memory cell MC is a field-effect transistor. The memory cell MC includes a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film includes a charge storage layer. The threshold voltage of the memory cell MC changes depending on the amount of charge in the charge storage layer. The memory cell MC stores one bit or multiple bits of data. A word line WL is connected to each of the gate electrodes of the memory cells MC included in one memory unit MU. These word lines WL are connected to each of the gate electrodes of one local block region R. LBLK It is commonly connected to all memory units MU in the memory block.

[0025] The select transistors (STD, STS) are field-effect transistors. The select transistors (STD, STS) include a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate electrodes of the select transistors (STD, STS) are connected to select gate lines (SGD, SGS), respectively. The two drain-side select gate lines corresponding to the two memory strings MS are each connected in common to all memory units MU in one string unit SU. The two source-side select gate lines SGS corresponding to the two memory strings MS are each connected in common to all memory units MU in one string unit SU.

[0026] Fig. 5 is a schematic plan view showing an enlarged view of a portion indicated by A in Fig. 2. Fig. 6 is a schematic plan view showing an enlarged view of a portion indicated by B in Fig. 5.

[0027] As shown in Figure 5, the local block area R LBLK In the memory cell region R, a plurality of memory cell regions R are arranged in the Y direction. MC and two memory cell regions R adjacent in the Y direction. MC The ladder area R is set between LD Also, the local block area R LBLK At the Y-direction end of the SGD In addition, two local block regions R aligned in the Y direction are provided. LBLK Between them, there is a local block connection line region R LBIL is provided.

[0028] 6, the memory layer ML includes a plurality of semiconductor layers 110 arranged in the X direction. These semiconductor layers 110 respectively correspond to the plurality of memory cell regions R described with reference to FIG. MC , multiple ladder regions R LD , and the select transistor region R SGD The semiconductor layer 110 extends in the Y direction over a range of 100 sq. m. The semiconductor layer 110 functions as, for example, a channel region of a plurality of memory cells MC (FIG. 4) connected in series and a channel region of select transistors (STD, STS) connected thereto. The semiconductor layer 110 may include, for example, undoped polycrystalline silicon (Si).

[0029] Memory cell area R MC 6, a plurality of via electrodes 120 are provided in the memory cell region R, which are located between two semiconductor layers 110 adjacent to each other in the X direction and aligned in the Y direction. MC , the memory layer ML includes a plurality of gate insulating layers 130 provided between the semiconductor layer 110 and the side surfaces of the plurality of via electrodes 120 in the X direction.

[0030] The via electrodes 120 function as, for example, gate electrodes of multiple memory cells MC and word lines WL connected thereto. As shown in FIG. 6, the via electrodes 120 may include a barrier conductive layer 121 made of titanium nitride (TiN) or the like and a conductive layer 122 made of tungsten (W) or the like. As shown in FIG. 3, the via electrodes 120 extend in the Z direction, penetrating multiple memory layers ML. An insulating layer 123 (FIG. 6) made of silicon oxide (SiO2) or the like is provided between two via electrodes 120 adjacent to each other in the Y direction.

[0031] The gate insulating layer 130 includes, for example, a tunnel insulating layer 131 provided on the side surface of the semiconductor layer 110 in the X direction, a charge storage layer 132 provided on the side surface of the tunnel insulating layer 131 in the X direction, and a block insulating layer 133 provided on the side surface of the charge storage layer 132 in the X direction.

[0032] The tunnel insulating layer 131 may include, for example, silicon oxide (SiO2).

[0033] The charge storage layer 132 may contain, for example, polycrystalline silicon (Si), etc. Furthermore, this polycrystalline silicon (Si) may contain N-type impurities such as phosphorus (P) or P-type impurities such as boron (B), or may not contain these impurities.

[0034] The block insulating layer 133 may include, for example, silicon oxide (SiO2), etc. Alternatively, the block insulating layer 133 may include aluminum oxide (AlO), hafnium oxide (HfO), or other insulating metal oxide films.

[0035] Select transistor region R SGD In FIG. 6, a conductive layer 140 and a via electrode 150 are provided between two semiconductor layers 110 adjacent to each other in the X direction and aligned in the Y direction. SGD , the memory layer ML includes a plurality of semiconductor layers 160 connected to one end of a plurality of semiconductor layers 110 in the Y direction.

[0036] The conductive layer 140 functions as, for example, a contact electrode for forming a hole channel in the semiconductor layer 110 or for supplying a voltage to the hole channel formed in the semiconductor layer 110. For example, as shown in FIG. 6 , the conductive layer 140 may include a semiconductor layer 141 made of polycrystalline silicon (Si) or the like containing a P-type impurity such as boron (B), and a conductive layer 142 made of titanium nitride (TiN) or the like. The conductive layer 140 extends in the Z direction, penetrating the multiple memory layers ML. A semiconductor layer 143 made of undoped polycrystalline silicon (Si) or the like may be provided on the outer peripheral surface of the conductive layer 140. The semiconductor layer 143 may be omitted.

[0037] The via electrode 150 functions as, for example, gate electrodes of multiple drain-side select transistors STD and drain-side select gate lines SGD connected thereto. For example, as shown in FIG. 6, the via electrode 150 may include a semiconductor layer 151 made of polycrystalline silicon (Si) or the like containing N-type impurities such as phosphorus (P), and a conductive layer 152 made of titanium nitride (TiN) or the like. The via electrode 150 extends in the Z direction, penetrating the multiple memory layers ML. An insulating layer 153 made of silicon oxide (SiO2) or the like is provided on the outer periphery of the via electrode 150. An insulating layer 154 made of silicon oxide (SiO2) or the like may be provided in the center of the via electrode 150. The width of the via electrode 150 in the Y direction may be larger than the width of the conductive layer 140 in the Y direction.

[0038] The semiconductor layer 160 may include, for example, a semiconductor layer such as polycrystalline silicon (Si) containing N-type impurities such as phosphorus (P). Furthermore, an insulating layer 161 is provided between two semiconductor layers 160 adjacent to each other in the X direction. The insulating layer 161 may include, for example, silicon oxide (SiO2). The insulating layer 161 extends in the Z direction, penetrating the multiple memory layers ML.

[0039] Ladder Area R LDIn FIG. 5, a conductive layer 140 or a via electrode 150 is provided between two semiconductor layers 110 adjacent to each other in the X direction. Although not shown, a semiconductor layer 143 (FIG. 6) and an insulating layer 153 (FIG. 6) are provided on the outer peripheral surfaces of the conductive layer 140 and the via electrode 150, respectively.

[0040] Local block connection line region R LBIL In FIG. 6, the memory layer ML includes a conductive layer 170. Also, the local block connection line region R LBIL 1, a plurality of insulating layers 171 (FIG. 6) are provided along the conductive layer 170 and arranged in the X direction.

[0041] The conductive layer 170 functions as, for example, a local block connection line LBI_a (FIG. 2). The conductive layer 170 may contain, for example, titanium nitride (TiN). The conductive layer 170 extends in the X direction and is connected to a plurality of semiconductor layers 110 via a plurality of semiconductor layers 160. The conductive layer 170 is connected to two local block regions R aligned in the Y direction. LBLK The semiconductor layer 110 is electrically connected to the semiconductor layer 110 therein.

[0042] The insulating layer 171 may include, for example, silicon oxide (SiO 2 ), etc. The insulating layer 171 extends in the Z direction, penetrating the multiple memory layers ML, as shown in FIG.

[0043] [Local block connection line area R LBIG [Medium configuration] Local block connection line region R LBIG , the memory layer ML includes a pair of conductive layers 180 extending in the Y direction. LBIG , a plurality of insulating layers 181 are provided, which are positioned between two conductive layers 180 adjacent to each other in the X direction and are aligned in the Y direction.

[0044] The conductive layer 180 functions as, for example, a local block connection line LBI_b (FIG. 2). The conductive layer 180 may contain, for example, titanium nitride (TiN). The conductive layer 180 extends in the Y direction and is connected to one end of each of the plurality of conductive layers 170 in the X direction.

[0045] The insulating layer 181 may include, for example, silicon oxide (SiO2) or the like. The insulating layer 181 extends in the Z direction, penetrating through the multiple memory layers ML. Note that an insulating layer 182 made of silicon oxide (SiO2) or the like is provided between two insulating layers 181 adjacent to each other in the Y direction. The width of the insulating layer 181 in the X direction may be larger than the width of the insulating layer 182 in the X direction.

[0046] [Hookup Area R HU [Medium configuration] [Hookup Configuration] Fig. 7 is a schematic plan view showing an enlarged view of a portion indicated by C1 in Fig. 2. Fig. 8 is a schematic cross-sectional view of the structure shown in Fig. 7 taken along line DD' and viewed in the direction of the arrows. Fig. 9 is a schematic cross-sectional view of the structure shown in Fig. 7 taken along line EE' and viewed in the direction of the arrows.

[0047] As shown in Figure 7, the hook-up area R HU In the X direction, multiple leader line regions R LLE ,R LLO and two adjacent leader line regions R in the X direction. LLE ,R LLO The via contact electrode region R CC And, it is provided.

[0048] Leader area R LLE ,R LLO In the memory layer ML, the memory layer ML includes a conductive layer 190 extending in the X direction. LLE ,R LLO 1, a plurality of insulating layers 191 are provided along the conductive layer 190 in the X direction.

[0049] The conductive layer 190 functions as a local block connection line LBI_c (FIG. 2). LLE The local block connection line LBI_c corresponding to the conductive layer 190 in the lead-out line region R LLO The local block connection line LBI_c corresponding to the conductive layer 190 in the middle may be referred to as a local block connection line LBI_co. The conductive layer 190 may contain, for example, titanium nitride (TiN). The conductive layer 190 is electrically connected to the conductive layer 180 described with reference to FIGS. 2 to 6. In the example of FIG. 7, a plurality of convex curved surfaces corresponding to a plurality of insulating layers 191 are provided on the side surface of the conductive layer 190 in the Y direction.

[0050] The insulating layer 191 may include, for example, an insulating layer of silicon oxide (SiO 2 ), etc. The insulating layer 191 extends in the Z direction, penetrating the multiple memory layers ML, as shown in FIG.

[0051] Via contact electrode area R CC 7, a plurality of via contact electrodes CC are provided in the via contact electrode region R CC , the memory layer ML includes an insulating layer 102 such as silicon nitride (Si 3 N 4 ).

[0052] The via contact electrode CC includes, for example, a substantially cylindrical portion 192 and a substantially disk-shaped portion 193 provided at the lower end of the portion 192, as shown in FIG.

[0053] The portion 192 may include, for example, a barrier conductive layer 194 made of titanium nitride (TiN) or the like, and a conductive layer 195 made of tungsten (W) or the like. The portion 192 extends in the Z direction, penetrating the multiple memory layers ML. An insulating layer 196 made of silicon oxide (SiO2) or the like may be provided on the outer circumferential surface of the portion 192. A portion of the outer circumferential surface of the insulating layer 196 contacts the insulating layer 101. A portion of the outer circumferential surface of the insulating layer 196 contacts the insulating layer 102. The radial thickness of the portion of the insulating layer 196 that contacts the insulating layer 102 may be greater than the radial thickness of the portion that contacts the insulating layer 101.

[0054] The portion 193 may include a barrier conductive layer 194 made of, for example, titanium nitride (TiN). The portion 193 is included in one of the memory layers ML and is connected to the side surface in the X direction of the conductive layer 190 included in one of the memory layers ML. HU via contact electrodes CC corresponding to all the memory layers ML may be provided in the memory layer ML. In this case, the number of via contact electrodes CC may be the same as the number of memory layers ML or may be greater than the number of memory layers ML.

[0055] As shown in FIG. 7, the contour of portion 192 may be formed along the circumference of a circle having a predetermined radius. A portion of portion 193 may be formed along the circumference of a circle having a larger radius. The remaining portion of portion 193 may be formed inside the circle. For example, in the example shown in FIG. 7, the connection portion of portion 193 with conductive layer 190 includes multiple concave curved surfaces. This portion is formed inside the circle. In the example shown in FIG. 7, the connection portion of portion 193 with insulating layer 196 includes concave curved surfaces formed along the outer periphery of a circle whose center is the center of the via contact electrode CC corresponding to insulating layer 196. This portion is formed inside the circle. The area of ​​portion 193 in the XY cross section may be larger than the area of ​​portion 192 in the XY cross section.

[0056] As illustrated in FIG. 8, in the memory layer ML_O, the lead-out line region R LLO In the memory layer ML_O, the conductive layer 190 provided in the lead-out region R LLE The conductive layer 190 provided on the via contact electrode CC is not connected to the via contact electrode CC.

[0057] In addition, in the memory layer ML_E, the lead line region R LLO The conductive layer 190 provided in the lead-out region R is not connected to the via-contact electrode CC. LLE A conductive layer 190 provided on the via contact electrode CC is connected to the via contact electrode CC.

[0058] [Configuration of preamplifier circuit PA and switch circuit ES_SW] Fig. 10 is a schematic plan view showing an enlarged view of a portion indicated by C2 in Fig. 2. Figs. 11 and 12 are schematic circuit diagrams for explaining a partial configuration of the semiconductor memory device according to this embodiment. Figs. 13 and 14 are schematic plan views for explaining a partial configuration of the semiconductor memory device according to this embodiment.

[0059] 13 and 14, the via contact electrode CC connected to the conductive layer 190 in the memory layer ML_E is referred to as the via contact electrode CC E Also, the via contact electrode CC connected to the conductive layer 190 in the memory layer ML_O is shown as the via contact electrode CC O is shown as

[0060] As shown in FIGS. 11 and 12, each of the memory layers ML_O and ML_E includes a preamplifier circuit PA and a switch circuit ES_SW.

[0061] 11 and 12, the preamplifier circuit PA includes nodes N1 to N3. The node N1 is electrically connected to the conductive layer 180 (local block connection line LBI_b) described with reference to FIGS. 5, 6, etc. The node N2 is electrically connected to the local block connection line LBI_co. The node N2 is also electrically connected to the local block connection line LBI_ce via a switch circuit ES_SW. The node N3 is electrically connected to a voltage supply line to which a ground voltage is supplied.

[0062] The preamplifier circuit PA also includes a transistor Tr1 connected between nodes N1 and N2, transistors Tr2 and Tr3 connected in series between nodes N2 and N3, and a transistor Tr4 connected between nodes N1 and N3. The transistors Tr1 to Tr4 are, for example, N-channel field effect transistors.

[0063] The source electrode of the transistor Tr1 is connected to the node N2, the drain electrode of the transistor Tr1 is connected to the node N1, and the gate electrode of the transistor Tr1 is connected to the signal line Pre_WE.

[0064] The source electrode of the transistor Tr2 is connected to the drain electrode of the transistor Tr3, the drain electrode of the transistor Tr2 is connected to the node N2, and the gate electrode of the transistor Tr2 is connected to the signal line Pre_RE.

[0065] The source electrode of the transistor Tr3 is connected to the node N3, the drain electrode of the transistor Tr3 is connected to the source electrode of the transistor Tr2, and the gate electrode of the transistor Tr3 is connected to the node N1.

[0066] The source electrode of the transistor Tr4 is connected to the node N3, the drain electrode of the transistor Tr4 is connected to the node N1, and the gate electrode of the transistor Tr4 is connected to the signal line Pre_reset.

[0067] The switch circuit ES_SW includes a transistor Tr5. The source electrode of the transistor Tr5 is connected to the local block connection line LBI_ce. The drain electrode of the transistor Tr5 is connected to the node N2. The gate electrode of the transistor Tr5 is connected to the signal line EO_selector.

[0068] 11 illustrates the via contact electrodes CC. As described above, the local block connection lines LBI_ce in the memory layer ML_E are connected to the via contact electrodes CC, and are connected to the transistor layer L T On the other hand, the local block connection line LBI_co in the memory layer ML_E is not connected to the via contact electrode CC. T Not connected to the internal configuration.

[0069] Similarly, the via contact electrodes CC are also shown in Fig. 12. As described above, the local block connection lines LBI_ce in the memory layer ML_O are not connected to the via contact electrodes CC. T On the other hand, the local block connection line LBI_co in the memory layer ML_O is connected to the via contact electrode CC, and is connected to the transistor layer L T connected to the internal configuration.

[0070] 13 and 14, the memory layer ML includes a conductive layer 210. In addition, a plurality of insulating layers 211 are provided in the hook-up region, aligned along the conductive layer 210.

[0071] The conductive layer 210 functions as the node N1 described with reference to Figures 11 and 12. The conductive layer 210 may include, for example, a barrier conductive layer such as titanium nitride (TiN) and a conductive layer such as tungsten (W).

[0072] The insulating layer 211 may include, for example, silicon oxide (SiO 2 ), etc. The insulating layer 211 extends in the Z direction, penetrating through a plurality of memory layers ML, as shown in FIG.

[0073] 13 and 14, the memory layer ML includes a conductive layer 220. In addition, a plurality of insulating layers 221 arranged along the conductive layer 220 are provided in the hook-up region.

[0074] The conductive layer 220 functions as the node N2 described with reference to Figures 11 and 12. The conductive layer 220 may include, for example, a barrier conductive layer such as titanium nitride (TiN) and a conductive layer such as tungsten (W).

[0075] The insulating layer 221 may include, for example, silicon oxide (SiO 2 ), etc. The insulating layer 221 extends in the Z direction, penetrating through the multiple memory layers ML.

[0076] 13 and 14, the memory layer ML includes a plurality of semiconductor layers 230. In addition, a plurality of via electrodes 231 connected to the plurality of semiconductor layers 230 are provided in the hook-up region.

[0077] The semiconductor layer 230 functions as the source regions of the transistors Tr3 and Tr4 described with reference to Figures 11 and 12. The semiconductor layer 230 may include, for example, polycrystalline silicon (Si) containing N-type impurities such as phosphorus (P).

[0078] 11 and 12. The via electrode 231 may include, for example, a barrier conductive layer such as titanium nitride (TiN) and a conductive layer such as tungsten (W). The via electrode 231 extends in the Z direction, penetrating through multiple memory layers ML, as shown in FIG. 10, for example.

[0079] 13 and 14, the memory layer ML includes a plurality of semiconductor layers 240. In addition, in the hook-up region, a plurality of via electrodes 241 provided corresponding to the plurality of semiconductor layers 240, and an insulating layer 242 covering the outer peripheral surfaces of the plurality of via electrodes 241 are provided.

[0080] The semiconductor layer 240 functions as the channel regions of the transistors Tr1, Tr2, Tr4, and Tr5 described with reference to Figures 11 and 12. The semiconductor layer 240 may include, for example, polycrystalline silicon (Si) containing P-type impurities such as boron (B).

[0081] The via electrode 241 functions as the gate electrodes of Tr1, Tr2, Tr4, and Tr5 described with reference to Figures 11 and 12. The via electrode 241 also functions as the signal lines Pre_WE, Pre_RE, Pre_reset, and EO_selector described with reference to Figures 11 and 12. The via electrode 241 may include, for example, a barrier conductive layer such as titanium nitride (TiN) and a conductive layer such as tungsten (W).

[0082] 11 and 12, the insulating layer 242 functions as a gate insulating film for the transistors Tr1, Tr2, Tr4, and Tr5. The insulating layer 242 may contain, for example, silicon oxide (SiO2). The via electrodes 241 and the insulating layer 242 extend in the Z direction, penetrating multiple memory layers ML, as shown in FIG.

[0083] 13 and 14, the memory layer ML includes a semiconductor layer 250 connected to a portion of the outer circumferential surface of the semiconductor layer 230, and an insulating layer 251 connected to a portion of the outer circumferential surface of the semiconductor layer 250. In addition, an insulating layer 252 connected to the semiconductor layer 250, and a semiconductor layer 253 connected to a portion of the outer circumferential surface of the semiconductor layer 250 are provided in the hook-up region.

[0084] The semiconductor layer 250 functions as a channel region of the transistor Tr3 described with reference to Figures 11 and 12. The semiconductor layer 250 may include, for example, polycrystalline silicon (Si) containing P-type impurities such as boron (B).

[0085] The insulating layer 251 functions as a gate insulating film of the transistor Tr3 described with reference to Figures 11 and 12. The insulating layer 251 may include, for example, silicon oxide (SiO2) or the like.

[0086] The insulating layer 252 may include, for example, silicon oxide (SiO 2 ), etc. The insulating layer 252 extends in the Z direction, penetrating the multiple memory layers ML.

[0087] The semiconductor layer 253 suppresses leakage current in the transistor Tr3 configured with the semiconductor layer 250 and the like. The semiconductor layer 253 may include, for example, polycrystalline silicon (Si) containing a P-type impurity such as boron (B). The concentration of the impurity contained in the semiconductor layer 253 is higher than the concentration of the impurity contained in the semiconductor layer 250. The semiconductor layer 253 extends in the Z direction, penetrating the multiple memory layers ML.

[0088] 13 and 14, the memory layer ML includes a plurality of semiconductor layers 260. In addition, a plurality of insulating layers 261 connected to the plurality of semiconductor layers 260 are provided in the hook-up region.

[0089] Some of the semiconductor layers 260 are connected to the conductive layer 210 and the semiconductor layer 240. Such semiconductor layers 260 function as drain regions of the transistors Tr1 and Tr4 described with reference to FIGS.

[0090] In addition, some of the multiple semiconductor layers 260 are connected to the two semiconductor layers 240 and the conductive layer 220. Such semiconductor layers 260 function as the source region of the transistor Tr1 and the drain region of the transistor Tr2 described with reference to FIGS.

[0091] In addition, some of the multiple semiconductor layers 260 are connected to the semiconductor layer 240 and the semiconductor layer 250. Such semiconductor layers 260 function as the source region of the transistor Tr2 and the drain region of the transistor Tr3 described with reference to FIGS.

[0092] In addition, some of the semiconductor layers 260 are connected to the conductive layer 220 and the semiconductor layer 240. Such a semiconductor layer 260 functions as the drain region of the transistor Tr5 described with reference to FIGS.

[0093] In addition, some of the semiconductor layers 260 are connected to the conductive layer 190 and the semiconductor layer 240. Such a semiconductor layer 260 functions as the source region of the transistor Tr5 described with reference to FIGS.

[0094] The semiconductor layer 260 may include, for example, polycrystalline silicon (Si) containing N-type impurities such as phosphorus (P).

[0095] The insulating layer 261 may include, for example, silicon oxide (SiO 2 ), etc. The insulating layer 261 extends in the Z direction, penetrating through a plurality of memory layers ML, as shown in FIG.

[0096] 13 and 14, the memory layer ML includes a semiconductor layer 270. The semiconductor layer 270 faces the semiconductor layer 250 via an insulating layer 251, and is connected to the conductive layer 210. In addition, an insulating layer 271 connected to the semiconductor layer 270 is provided in the hook-up region.

[0097] The semiconductor layer 270 functions as the gate electrode of the transistor Tr3 described with reference to Figures 11 and 12. The semiconductor layer 270 may include, for example, polycrystalline silicon (Si) containing N-type impurities such as phosphorus (P).

[0098] The insulating layer 271 may include, for example, silicon oxide (SiO 2 ), etc. The insulating layer 271 extends in the Z direction, penetrating through the multiple memory layers ML.

[0099] [Transistor Layer L T [Medium configuration] 15 and 16 are schematic circuit diagrams showing the configuration of a portion of the semiconductor memory device according to this embodiment.

[0100] Transistor layer L T The memory cell array ML_A includes a plurality of sense amplifier circuits SA_O provided corresponding to a plurality of memory layers ML_O, and a plurality of sense amplifier circuits SA_E provided corresponding to a plurality of memory layers ML_E.

[0101] As shown in FIG. 15, the sense amplifier circuit SA_O is connected to the bit line BL and the local block connection line LBI_co in the memory layer ML_O.

[0102] The sense amplifier circuit SA_O includes transistors Tr11 and Tr12 connected in series between the bit line BL and a voltage node Vss, transistors Tr13 and Tr14 connected in series between the bit line BL and a voltage node Vdd, transistor Tr15 connected between the voltage node Vpre and a via contact electrode CC, and transistor Tr16 connected between the bit line BL and a via contact electrode CC. The transistors Tr11, Tr12, Tr15, and Tr16 are, for example, N-channel field-effect transistors. The transistors Tr13 and Tr14 are, for example, P-channel field-effect transistors.

[0103] The source electrode of the transistor Tr11 is connected to the drain electrode of the transistor Tr12. The drain electrode of the transistor Tr11 is connected to the bit line BL. The gate electrode of the transistor Tr11 is connected to the signal line amp_RE. The source electrode of the transistor Tr12 is connected to the voltage node Vss. The gate electrode of the transistor Tr12 is connected to the via contact electrode CC.

[0104] The source electrode of transistor Tr13 is connected to the drain electrode of transistor Tr14. The drain electrode of transistor Tr13 is connected to bit line BL. The gate electrode of transistor Tr13 is connected to signal line / amp_RE. The source electrode of transistor Tr14 is connected to voltage node Vdd. The gate electrode of transistor Tr14 is connected to via contact electrode CC.

[0105] The transistor Tr15 has a source electrode connected to the via contact electrode CC, a drain electrode connected to the voltage node Vpre, and a gate electrode connected to the signal line amp_pre.

[0106] The source electrode of the transistor Tr16 is connected to the via contact electrode CC, the drain electrode of the transistor Tr16 is connected to the bit line BL, and the gate electrode of the transistor Tr16 is connected to the signal line amp_WE.

[0107] 16, the sense amplifier circuit SA_E is connected to the bit line BL and the local block connection line LBI_ce in the memory layer ML_E. The sense amplifier circuit SA_E has the same configuration as the sense amplifier circuit SA_O.

[0108] The sense amplifier circuits SA_O and SA_E can be controlled independently of each other, i.e., the signal lines amp_RE, / amp_RE, amp_pre, and amp_WE corresponding to the sense amplifier circuit SA_E are electrically independent of the signal lines amp_RE, / amp_RE, amp_pre, and amp_WE corresponding to the sense amplifier circuit SA_O, respectively, and different signals can be input thereto.

[0109] [Read operation] Fig. 17 is a schematic timing chart for explaining the read operation of the semiconductor memory device according to this embodiment. Figs. 18 to 33 are schematic circuit diagrams for explaining the read operation of the semiconductor memory device according to this embodiment.

[0110] 18 to 33 show the configurations of the memory layers ML_E and ML_O and the corresponding bit lines BL collectively. E / V O ) indicates the voltage state. The first voltage V E indicates the voltage state of the wiring included in the memory layer ML_E or the bit line BL corresponding to the memory layer ML_E. O indicates the voltage state of the wiring included in the memory layer ML_O or the bit line BL corresponding to the memory layer ML_O.

[0111] 18 to 33, the sense amplifier circuit SA_E is connected to the bit lines BL and the local block connection lines LBI_ce. However, as described with reference to FIGS. 15 and 16, the sense amplifier circuit SA_E is connected only to the bit lines BL and local block connection lines LBI_ce corresponding to the memory layer ML_E, and is not connected to the bit lines BL and local block connection lines LBI_ce corresponding to the memory layer ML_O.

[0112] 18 to 33, the sense amplifier circuit SA_O is connected to the bit lines BL and the local block connection lines LBI_co. However, as described with reference to FIGS. 15 and 16, the sense amplifier circuit SA_O is connected only to the bit lines BL and local block connection lines LBI_co corresponding to the memory layer ML_O, and is not connected to the bit lines BL and local block connection lines LBI_co corresponding to the memory layer ML_E.

[0113] At the timing when the read operation starts, as shown in FIG. 18, the voltages of the drain side select gate line SGD, source side select gate line SGS, and word line WL corresponding to the memory string MS that is the target of the read operation are set to “L”.

[0114] Furthermore, the voltages of the signal lines Pre_WE, Pre_RE, and Pre_reset corresponding to the preamplifier circuit PA are set to "L, L, L."

[0115] Moreover, the voltage of the signal line EO_selector corresponding to the switch circuit ES_SW is set to "L."

[0116] Furthermore, the voltages of the signal lines amp_RE, / amp_RE, amp_pre, and amp_WE corresponding to the sense amplifier circuits SA_E and SA_O are set to "L, H, L, L."

[0117] At timing t101 of the read operation, the local block connection line LBI_a in the memory layers ML_E and ML_O is discharged. For example, as shown in FIG. 19, the voltage of the signal line Pre_reset is set to "H." This turns on the transistor Tr4, and the voltage of the local block connection line LBI_a in the memory layers ML_E and ML_O becomes "L."

[0118] At timing t102 of the read operation, the voltage of the word line WL is adjusted. For example, the voltage of the selected word line WL is set to a predetermined read voltage. The read voltage is a voltage of a magnitude that turns the memory cell MC to an ON state or an OFF state depending on the data recorded in the memory cell MC. In addition, the voltage of the unselected word lines WL is set to a read pass voltage. The read pass voltage is a voltage of a magnitude that turns the memory cell MC to an ON state regardless of the data recorded in the memory cell MC.

[0119] At timing t103 of the read operation, the voltage of the drain-side select gate line SGD is set to "H", for example, as shown in Figure 19. This turns the drain-side select gate line SGD into the ON state, and the voltage in the memory string MS in the memory layers ML_E and ML_O becomes "L".

[0120] At timing t104 of the read operation, the voltage of the signal line EO_selector is set to "H" as shown in Fig. 19. This turns on the transistor Tr5.

[0121] At timing t105 of the read operation, the discharge of the local block connection line LBI_a in the memory layers ML_E and ML_O is completed. For example, as shown in FIG. 20, the voltage of the signal line Pre_reset is set to "L." This turns the transistor Tr4 into an OFF state.

[0122] At timing t106 of the read operation, a precharge operation is performed. For example, as shown in FIG. 21, the signal line Pre_WE and the signal line amp_pre corresponding to the sense amplifier circuit SA_E are set to "H." This causes the transistor Tr1 and the transistor Tr15 corresponding to the sense amplifier circuit SA_E to turn on. As a result, the voltages of the local block connection lines LBI_ce, LBI_co, and LBI_a in the memory layer ML_E and the memory string MS become "H." Furthermore, the voltages of the local block connection lines LBI_ce, LBI_co, and LBI_a in the memory layer ML_O and the memory string MS become "L."

[0123] At timing t107 of the read operation, the precharge operation is completed. For example, as shown in FIG. 22, the signal line Pre_WE and the signal line amp_pre corresponding to the sense amplifier circuit SA_E are set to "L." This causes the transistor Tr1 and the transistor Tr15 corresponding to the sense amplifier circuit SA_E to be turned off.

[0124] At timing t107 of the read operation, a discharge operation is performed. For example, as shown in Fig. 22, the voltage of the source-side select gate line SGS is set to "H." This turns the source-side select transistor STS into the ON state.

[0125] Here, read data R is read from the memory layer ML_E. That is, in the memory layer ML_E, the voltages in the local block connection line LBI_a and the memory string MS are "H". Therefore, if the threshold voltage of the selected memory cell MC is lower than the read voltage, the charges in the local block connection line LBI_a and the memory string MS are discharged, and these voltages become "L". In this case, the transistor Tr3 is in the OFF state. On the other hand, if the threshold voltage of the selected memory cell MC is higher than the read voltage, the charges in the local block connection line LBI_a and the memory string MS are not discharged, and these voltages are maintained at "H". In this case, the transistor Tr3 is in the ON state.

[0126] On the other hand, in the memory layer ML_O, the voltages of the local block connection line LBI_a and the memory string MS are "L." Therefore, regardless of the threshold voltage of the selected memory cell MC, the voltages of the local block connection line LBI_a and the memory string MS are maintained at "L." Therefore, the transistor Tr3 is turned off.

[0127] At timing t108 of the read operation, the discharge operation is completed. For example, as shown in FIG. 23, the voltages of the word line WL, the drain side select gate line SGD, and the source side select gate line SGS are set to "L." This causes the memory cell MC, the drain side select gate line SGD, and the source side select transistor STS to be turned off.

[0128] At timing t108 of the read operation, the preamplifier operates. For example, as shown in Fig. 23, the voltage of the signal line Pre_RE is set to "H." This turns on the transistor Tr2.

[0129] Here, the read data R corresponding to the memory layer ML_E is transferred to the sense amplifier circuit SA_E as inverted data / R. That is, in the memory layer ML_E, when transistor Tr3 is in the ON state, the ground voltage is supplied to node N2. Therefore, the voltage of node N2 becomes "L". In this case, transistor Tr12 in the sense amplifier circuit SA_E becomes OFF. Also, transistor Tr14 in the sense amplifier circuit SA_E becomes ON. On the other hand, when transistor Tr3 is in the OFF state, the ground voltage is not supplied to node N2. Therefore, the voltage of node N2 is maintained at "H". In this case, transistor Tr12 in the sense amplifier circuit SA_E becomes ON. Also, transistor Tr14 in the sense amplifier circuit SA_E becomes OFF.

[0130] In the memory layer ML_O, the transistor Tr3 is in the OFF state, and the voltage of the node N2 is maintained at “H”.

[0131] At timing t109 of the read operation, the voltage of the signal line EO_selector is set to "L" as shown in Fig. 24. This turns the transistor Tr5 into an OFF state.

[0132] At timing t110 of the read operation, the local block connection line LBI_a in the memory layers ML_E and ML_O is discharged. For example, as shown in FIG. 25, the voltage of the signal line Pre_reset is set to "H." This turns on the transistor Tr4, and the voltage of the local block connection line LBI_a in the memory layers ML_E and ML_O becomes "L."

[0133] At timing t111 of the read operation, an amplifier operation is performed. For example, as shown in FIG. 26, the signal lines amp_RE and / amp_RE corresponding to the sense amplifier circuit SA_E are set to "H, L." This turns on the transistors Tr11 and Tr13 in the sense amplifier circuit SA_E.

[0134] Here, the inverted data / R corresponding to the memory layer ML_E is transferred to the bit line BL as read data R. That is, in the sense amplifier circuit SA_E, when the transistor Tr12 is in the OFF state and the transistor Tr14 is in the ON state, the voltage of the bit line BL becomes "H". On the other hand, in the sense amplifier circuit SA_E, when the transistor Tr12 is in the ON state and the transistor Tr14 is in the OFF state, the voltage of the bit line BL becomes "L". The read data R transferred to the bit line BL is further transferred to a circuit not shown.

[0135] Also, at timing t111 of the read operation, the voltage of the drain-side select gate line SGD is set to "H", for example, as shown in Fig. 26. This turns the drain-side select gate line SGD into the ON state, and the voltage in the memory string MS in the memory layers ML_E and ML_O becomes "L".

[0136] At timing t112 of the read operation, the amplifier operation is terminated. For example, as shown in FIG. 27, the signal lines amp_RE and / amp_RE corresponding to the sense amplifier circuit SA_E are set to "L, H." This turns off the transistors Tr11 and Tr13 in the sense amplifier circuit SA_E.

[0137] At timing t112 of the read operation, the discharge of the local block connection line LBI_a in the memory layers ML_E and ML_O is completed. For example, as shown in FIG. 27, the voltage of the signal line Pre_reset is set to "L." This turns the transistor Tr4 into an OFF state.

[0138] At timing t113 of the read operation, a precharge operation is performed. For example, as shown in FIG. 28, the signal line Pre_WE and the signal line amp_pre corresponding to the sense amplifier circuit SA_O are set to "H." This causes the transistor Tr1 and the transistor Tr15 corresponding to the sense amplifier circuit SA_O to be turned on. Accordingly, the voltages of the local block connection lines LBI_co, LBI_a in the memory layer ML_O and the memory string MS become "H."

[0139] At timing t114 of the read operation, the precharge operation is completed. For example, as shown in FIG. 29, the signal line Pre_WE and the signal line amp_pre corresponding to the sense amplifier circuit SA_O are set to "L." This causes the transistor Tr1 and the transistor Tr15 corresponding to the sense amplifier circuit SA_O to be turned off.

[0140] Also, at timing t114 of the read operation, for example, as shown in FIG. 29, the bit line BL corresponding to the memory layer ML_E is set to "H".

[0141] At timing t115 of the read operation, a discharge operation is performed. For example, as shown in Fig. 30, the voltage of the source-side select gate line SGS is set to "H." This turns the source-side select transistor STS into the ON state.

[0142] Here, in the memory layer ML_O, the read data R is read out.

[0143] On the other hand, in the memory layer ML_E, the voltages of the local block connection line LBI_a and the memory string MS are maintained at "L".

[0144] At timing t116 of the read operation, the discharge operation is completed. For example, as shown in FIG. 31, the voltages of the word line WL, the drain side select gate line SGD, and the source side select gate line SGS are set to "L." This causes the memory cell MC, the drain side select gate line SGD, and the source side select transistor STS to be turned off.

[0145] At timing t116 of the read operation, the preamplifier operates. For example, as shown in Fig. 31, the voltage of the signal line Pre_RE is set to "H." This turns on the transistor Tr2.

[0146] Here, the read data corresponding to the memory layer ML_O is transferred to the sense amplifier circuit SA_O as inverted data / R.

[0147] In the memory layer ML_E, the transistor Tr3 is in the OFF state, and the voltage of the node N2 is maintained at "L".

[0148] At timing t117 of the read operation, an amplifier operation is performed. For example, as shown in FIG. 32, the signal lines amp_RE and / amp_RE corresponding to the sense amplifier circuit SA_O are set to "H" and "L," respectively. This turns on the transistors Tr11 and Tr13 in the sense amplifier circuit SA_O.

[0149] Here, the inverted data / R corresponding to the memory layer ML_O is transferred to the bit line BL as read data R. The read data R transferred to the bit line BL is further transferred to a circuit not shown.

[0150] At timing t118 of the read operation, the amplifier operation is terminated. For example, as shown in FIG. 33, the signal lines amp_RE and / amp_RE corresponding to the sense amplifier circuit SA_O are set to "L" and "H." This turns off the transistors Tr11 and Tr13 in the sense amplifier circuit SA_E.

[0151] Also, at timing t118 of the read operation, for example, as shown in FIG. 33, the bit line BL corresponding to the memory layer ML_O is set to "H".

[0152] [effect] As described with reference to FIG. 2, in the semiconductor memory device according to this embodiment, a plurality of local block areas R LBLK are arranged in the Y direction. In addition, these multiple local block regions R LBLK Instead of providing hookup regions for each of these local block regions R LBLK Corresponding common hookup area R HU According to this configuration, the hook-up region R HU It is possible to significantly reduce the area of ​​the

[0153] In the semiconductor memory device according to this embodiment, a plurality of local block areas R LBLK and hookup area R HU The local block connection line area R LBIG As shown in FIG. 3, the local block connection line area R LBIG In the example, each memory layer ML is provided with a conductive layer 180. In such a configuration, the electrostatic capacitance may become large between the multiple conductive layers 180 arranged in the Z direction.

[0154] Here, as described with reference to, for example, FIGS. 22 and 30, a discharge operation is performed in the read operation. In the discharge operation, the charges in the local block connection lines LBI_a and LBI_b are discharged via the memory string MS. Here, if such an operation is performed simultaneously in all memory layers ML, the time required for the discharge operation may vary greatly. In such a case, the data recorded in the selected memory cell MC may not be read out properly.

[0155] For example, when the selected memory cells MC are in the ON state in two memory layers ML aligned in the Z direction, the time required for the discharge operation in these two memory layers ML is relatively short. On the other hand, when the selected memory cells MC are in the ON state in only one of the two memory layers ML aligned in the Z direction, the time required for the discharge operation in these two memory layers ML is relatively long.

[0156] Therefore, in this embodiment, the sense amplifier circuit SA_O and the sense amplifier circuit SA_E are configured to be controllable independently of each other.

[0157] 22, in this embodiment, when a discharge operation corresponding to the memory layer ML_E is performed, the voltages of the local block connection lines LBI_a and LBI_b in the memory layer ML_O are set to the ground voltage. When a discharge operation corresponding to the memory layer ML_O is performed, the voltages of the local block connection lines LBI_a and LBI_b in the memory layer ML_E are set to the ground voltage.

[0158] According to this method, it is possible to significantly reduce the variation in the time required for the discharge operation in all memory layers ML, thereby making it possible to preferably read out the data stored in the selected memory cell MC.

[0159] Furthermore, when performing such an operation, it is also possible to transfer the read data R corresponding to the memory layer ML_E to the bit line BL, and then, after the charging of the bit line BL is completed, set the voltage of the drain-side select gate line SGD to “H” to acquire the read data R corresponding to the memory layer ML_O. However, in such a case, the time required for the read operation may increase by about twice.

[0160] 11 and 12, a transistor Tr5 is provided between the node N2 and the local block connection line LBI_ce. Also, a transistor Tr4 is provided between the node N3 and the local block connection line LBI_b.

[0161] According to this configuration, as explained with reference to FIG. 24, while read data R (inverted data / R) is held in the local block connection line LBI_ce in the memory layer ML_E, it is possible to electrically disconnect the local block connection line LBI_ce from the node N2 in all memory layers ML.

[0162] Also, as explained with reference to, for example, Figure 25, while read data R (inverted data / R) is held in the local block connection line LBI_ce in the memory layer ML_E, it is possible to supply ground voltage to the local block connection line LBI_ce and node N2 in all memory layers ML.

[0163] 26, the transfer of the read data R corresponding to the memory layer ML_E to the bit line BL and the discharge operation corresponding to the memory layer ML_O can be performed in parallel, thereby reducing the time required for the read operation.

[0164] In this embodiment, the transistors Tr4 and Tr5 are connected to the transistor layer L T (Fig. 1), but is provided in each memory layer ML. With this configuration, it may be possible to significantly reduce the circuit area.

[0165] [Second embodiment] Next, a description will be given of a semiconductor memory device according to a second embodiment. In the following description, the same parts as those in the semiconductor memory device according to the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted.

[0166] 34 and 35 are schematic circuit diagrams for explaining a partial configuration of the semiconductor memory device according to this embodiment, and Fig. 36 is a schematic plan view for explaining a partial configuration of the semiconductor memory device according to this embodiment.

[0167] The semiconductor memory device according to the second embodiment is basically configured in the same manner as the semiconductor memory device according to the first embodiment.

[0168] 11 and 12, in the first embodiment, in each memory layer ML, the node N2 and the local block connection line LBI_co are directly connected without passing through a transistor, etc. On the other hand, in the second embodiment, as shown in Figures 34 and 35, in each memory layer ML, a switch circuit OS_SW is provided in the current path between the node N2 and the local block connection line LBI_co.

[0169] The switch circuit OS_SW includes a transistor Tr6. The source electrode of the transistor Tr6 is connected to the local block interconnect line LBI_co. The drain electrode of the transistor Tr6 is connected to the node N2. The gate electrode of the transistor Tr6 is connected to the signal line EO_selector1.

[0170] In addition, in FIGS. 34 and 35, the signal line EO_selector corresponding to the switch circuit ES_SW is shown as a signal line EO_selector0.

[0171] 36, the switch circuit OS_SW may be configured similarly to the switch circuit ES_SW. That is, each memory layer ML may include a semiconductor layer 240 that functions as the channel region of the transistor Tr6 and a semiconductor layer 260 that functions as the source region and drain region of the transistor Tr6. Furthermore, the hook-up region may include a via electrode 241 that functions as the gate electrode of the transistor Tr6 and an insulating layer 242 that functions as the gate insulating film of the transistor Tr6.

[0172] According to this configuration, it is possible to make the capacitance of each wiring in the memory layer ML_E equal to the capacitance of each wiring in the memory layer ML_O, which may make it possible to more suitably execute a read operation.

[0173] [Other embodiments] The semiconductor memory devices according to the first and second embodiments have been described above. However, the configurations, operations, etc. described above are merely examples, and the specific configurations, operations, etc. can be adjusted as appropriate.

[0174] For example, in the semiconductor memory device according to the second embodiment, the switch circuit ES_SW may be omitted.

[0175] Furthermore, the read operation illustrated in FIG. 17 is merely an example, and the specific method can be adjusted as appropriate.

[0176] For example, in the semiconductor memory device according to the first embodiment, as described with reference to FIG. 17 and other figures, the amplifier operation corresponding to the memory layer ML_E and the control of the drain-side select gate line SGD for acquiring read data R corresponding to the memory layer ML_O are performed at the same time, t111. However, it is also possible that the operation from t111 to t118 corresponding to the memory layer ML_O starts at any time after the voltage of the signal line EO_selector is set to "L" and before the bit line BL corresponding to the memory layer ML_E is charged. This can shorten the time required for the read operation.

[0177] Furthermore, for example, the configuration of the preamplifier circuit PA as exemplified above is merely an example, and the specific configuration can be adjusted as appropriate.

[0178] 13 and 14, the transistor Tr3 includes a semiconductor layer 250 and a semiconductor layer 253 that contacts a portion of the outer peripheral surface of the semiconductor layer 250. On the other hand, in the example of Fig. 37, the transistor Tr3 includes a semiconductor layer 350 instead of the semiconductor layer 250. This configuration does not include the semiconductor layer 253.

[0179] The semiconductor layer 350 is basically configured in the same manner as the semiconductor layer 250. However, one insulating layer 251 is provided on the outer peripheral surface of the semiconductor layer 250, and the semiconductor layer 250 faces one semiconductor layer 270 via this insulating layer 251. On the other hand, two insulating layers 251 are provided on the outer peripheral surface of the semiconductor layer 350, and the semiconductor layer 350 faces two semiconductor layers 270 via these insulating layers 251. With this configuration, it is possible to increase the channel width of the transistor Tr3 formed by the semiconductor layer 350 and increase the ON current.

[0180] 13 and 14, the transistor Tr3 includes a semiconductor layer 250 and one insulating layer 252 in contact with the semiconductor layer 250. On the other hand, in the example of FIG. 38, the transistor Tr3 includes a semiconductor layer 450 in place of the semiconductor layer 250 and two insulating layers 252 in contact with the semiconductor layer 450.

[0181] The semiconductor layer 450 is basically configured in the same manner as the semiconductor layer 250. However, a portion of the outer peripheral surface of the semiconductor layer 250 is provided along the circumference of one circle whose center is the central position of one of the insulating layers 252. The remaining portion of the outer peripheral surface of the semiconductor layer 250 is provided within the range of this circle. On the other hand, a portion of the outer peripheral surface of the semiconductor layer 450 is provided along the circumference of two circles whose centers are the central positions of the two insulating layers 252, respectively. The remaining portion of the outer peripheral surface of the semiconductor layer 450 is provided within the range of at least one of the two circles. The opposing area between the semiconductor layer 450 and the semiconductor layer 270 is larger than the opposing area between the semiconductor layer 250 and the semiconductor layer 270. With this configuration, the channel length of the transistor Tr3 formed by the semiconductor layer 450 can be increased to suppress OFF leakage current.

[0182] Furthermore, the preamplifier circuit PA may include two or more circuit elements pa connected in parallel between nodes N1 and N2, as shown in Fig. 39. The circuit elements pa may include transistors Tr1, Tr2, Tr3, and Tr4, respectively, as described with reference to Figs.

[0183] Furthermore, the semiconductor memory devices according to the first and second embodiments include a so-called NAND flash memory. However, the configurations exemplified in the first and second embodiments can also be applied to semiconductor memory devices other than a NAND flash memory. For example, the configurations exemplified in the first and second embodiments can be applied to a configuration in which a semiconductor layer extending in the Y direction is provided in each of multiple memory layers ML and one or more memory transistors use this semiconductor layer as a channel region. The configurations exemplified in the first and second embodiments can also be applied to a configuration in which other memory transistors are provided. The configurations exemplified in the first and second embodiments can also be applied to other memories.

[0184] 7 to 9, the via contact electrode CC according to the first and second embodiments includes a portion 192 extending in the Z direction and a substantially disk-shaped portion 193 connected to the lower end of the portion 192. However, the configuration of the via contact electrode CC can be adjusted as appropriate. For example, in the first and second embodiments, the substantially disk-shaped portion 193 may be omitted from the via contact electrode CC. In such a case, for example, the lower ends of the multiple via contact electrodes CC may be connected to the upper surfaces of the multiple conductive layers 190 stacked in the Z direction, respectively.

[0185] [others] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0186] 110...semiconductor layer, 120...via electrode, 130...gate insulating layer, 140...conductive layer, 150...via electrode, 160...semiconductor layer, 170...conductive layer, 180...conductive layer, R LBLK …local block region, R HU …Hookup area, R LBIG ,R LBIL ...Local block connection line area.

Claims

1. A substrate; a plurality of first memory layers and a plurality of second memory layers alternately arranged in a first direction intersecting a surface of the substrate; a plurality of first sense amplifier circuits provided corresponding to the plurality of first memory layers; a plurality of second sense amplifier circuits provided corresponding to the plurality of second memory layers; Equipped with The substrate is a plurality of local block areas arranged in a second direction intersecting the first direction; hook-up regions aligned in the second direction with respect to the plurality of local block regions; Equipped with In the plurality of local block areas, the plurality of first memory layers and the plurality of second memory layers each include: a plurality of memory strings extending in the second direction and aligned in a third direction intersecting the first direction and the second direction; a first wiring extending in the third direction and connected in common to the plurality of memory strings; Equipped with In the hookup region, the plurality of first memory layers and the plurality of second memory layers each include: a signal amplifier circuit electrically connected to the first wiring; a second wiring connected to the signal amplifier circuit; a first switch transistor connected to the second wiring; a third wiring electrically connected to the second wiring via the first switch transistor; a fourth wiring electrically connected to the second wiring without passing through the first switch transistor; Equipped with The hook-up region is a plurality of first via contact electrodes extending in the first direction and connected to the third wirings in the plurality of first memory layers; a plurality of second via contact electrodes extending in the first direction and connected to the fourth wirings in the plurality of second memory layers; Equipped with each of the plurality of first sense amplifier circuits is electrically connected to a signal amplifier circuit included in one of the plurality of first memory layers via one of the plurality of first via contact electrodes and the third wiring included in one of the plurality of first memory layers; Each of the second sense amplifier circuits is electrically connected to a signal amplifier circuit included in one of the second memory layers via one of the second via contact electrodes and the fourth wiring included in one of the second memory layers. Semiconductor memory device.

2. the first switch transistors corresponding to the plurality of first memory layers and the first switch transistors corresponding to the plurality of second memory layers each include a first semiconductor layer; the hook-up region includes a first via electrode extending in the first direction; the first via electrode faces a plurality of first semiconductor layers included in the plurality of first memory layers and a plurality of first semiconductor layers included in the plurality of second memory layers; The first via electrodes function as gate electrodes of first switch transistors corresponding to the plurality of first memory layers and first switch transistors corresponding to the plurality of second memory layers.

2. The semiconductor memory device according to claim 1.

3. In the hook-up region, the plurality of first memory layers and the plurality of second memory layers each include a second switch transistor connected to the second wiring; the third wirings are electrically connected to the second wirings without passing through the second switch transistors; The plurality of fourth wirings are electrically connected to the second wirings via the second switch transistors.

3. The semiconductor memory device according to claim 1.

4. a plurality of second switch transistors corresponding to the plurality of first memory layers and a plurality of second switch transistors corresponding to the plurality of second memory layers each include a second semiconductor layer; the hook-up region includes a second via electrode extending in the first direction; the second via electrodes face a plurality of second semiconductor layers included in the plurality of first memory layers and a plurality of second semiconductor layers included in the plurality of second memory layers; The second via electrodes function as gate electrodes of second switch transistors corresponding to the plurality of first memory layers and second switch transistors corresponding to the plurality of second memory layers.

4. The semiconductor memory device according to claim 3.

5. a first voltage supply line that supplies a first voltage; The plurality of signal amplifier circuits corresponding to the plurality of first memory layers and the plurality of signal amplifier circuits corresponding to the plurality of second memory layers each include: a fifth wiring electrically connected to the first wiring; a first transistor electrically connected between the fifth wiring and the second wiring; a second transistor electrically connected between the second wiring and the first voltage supply line; a third transistor electrically connected between the second transistor and the first voltage supply line; a fourth transistor electrically connected between the fifth wiring and the first voltage supply line; Equipped with The fifth wiring is connected to the gate electrode of the third transistor.

5. The semiconductor memory device according to claim 1.

6. each of the local block regions includes a sixth wiring; Each of the plurality of memory strings includes: a plurality of memory cells connected in series; a first selection transistor electrically connected between the plurality of memory cells and the first wiring; a second selection transistor electrically connected between the plurality of memory cells and the sixth wiring; Equipped with The semiconductor memory device comprises: a second voltage supply line that supplies a second voltage higher than the first voltage; a fifth transistor electrically connected between the second voltage supply line and one of the plurality of first via contact electrodes; a sixth transistor electrically connected between the second voltage supply line and one of the plurality of second via contact electrodes; Equipped with For read operations, a voltage for turning on the fourth transistor is supplied to a gate electrode of the fourth transistor at a first timing; a voltage that turns on the fifth transistor is supplied to a gate electrode of the fifth transistor at a second timing that is later than the first timing; At a third timing that is later than the second timing, a voltage that turns the second selection transistor into an ON state is supplied to a gate electrode of the second selection transistor; a voltage that turns the fourth transistor into an ON state is supplied to a gate electrode of the fourth transistor at a fourth timing that is later than the third timing; a voltage that turns on the sixth transistor is supplied to a gate electrode of the sixth transistor at a fifth timing that is later than the fourth timing, At a sixth timing that is later than the fifth timing, a voltage that turns the second selection transistor into an ON state is supplied to the gate electrode of the second selection transistor.

6. The semiconductor memory device according to claim 5.

7. a voltage that turns the first switch transistor into an ON state is supplied to a gate electrode of the first switch transistor from the first timing to the third timing; At the fourth timing, the first switch transistor is in a state in which a voltage that turns the first switch transistor into an OFF state is supplied to a gate electrode thereof.

7. The semiconductor memory device according to claim 6.

8. At a seventh timing that is later than the third timing, data corresponding to the first memory layer is transferred to a first bit line; At an eighth timing after the seventh timing, a third voltage is supplied to the first bit line; a voltage that turns the first switch transistor into an OFF state is supplied to a gate electrode of the first switch transistor at a ninth timing that is after the third timing and before the fourth timing; At a tenth timing that is after the ninth timing and before the eighth timing, a voltage that turns the first selection transistor into an ON state is supplied to the gate electrode of the first selection transistor.

8. The semiconductor memory device according to claim 6.

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