Display device

Abstract

To simplify a photolithography process by reducing the number of light-exposure masks and manufacture a semiconductor device including an oxide semiconductor with high productivity at low cost.SOLUTION: In a manufacturing method for a semiconductor device including an inverted-staggered thin film transistor with a channel-etched structure, an etching step for an oxide semiconductor film and a conductive film is performed using a mask layer formed by a multi-level gradation mask 59a that is a light-exposure mask that makes light having transmitted through a light-blocking part 64 have a plurality of intensities. The etching step employs dry etching by etching gas.SELECTED DRAWING: Figure 30

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device including an oxide semiconductor and a manufacturing method thereof. [Background technology]

[0002] As typified by liquid crystal display devices, thin film transistors formed on flat plates such as glass substrates are , amorphous silicon, and polycrystalline silicon. Thin film transistors using silicon have low field effect mobility, but are suitable for enlarging the area of ​​glass substrates. On the other hand, thin film transistors using crystalline silicon have high field effect mobility. However, a crystallization process such as laser annealing is required, and enlarging the glass substrate is essential. However, it has the characteristic of not being adaptable.

[0003] In response to this, thin film transistors are being fabricated using oxide semiconductors, and they are being used in electronic devices and optical devices. For example, zinc oxide and In-G Thin film transistors were fabricated using a-Zn-O oxide semiconductors and used as switches for image display devices. Patent Documents 1 and 2 disclose techniques used in chip elements and the like. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 Summary of the Invention [Problem to be solved by the invention]

[0005] Thin film transistors with a channel formation region in an oxide semiconductor are made of amorphous silicon. The oxide semiconductor film has a higher field effect mobility than the thin film transistors used in the previous study. Film formation is possible at temperatures below 300°C using methods such as sputtering, and polycrystalline silicon The manufacturing process is simpler than that of thin film transistors using SiO2.

[0006] Using such oxide semiconductors, thin film transistors can be formed on glass substrates, plastic substrates, etc. and used in liquid crystal displays, electroluminescent displays, electronic paper, etc. Applications of this technology are expected.

[0007] In addition, a large number of exposure masks (also called photomasks) are used to manufacture thin film transistors. In this case, a method of forming a laminated structure by a photolithography process is used. The lithography process involves many steps, and it is important to consider factors such as manufacturing cost, yield, and productivity. Among these, the number of exposure masks, which are expensive to design and manufacture, is one of the factors that have a major impact on the Reducing this is a major challenge.

[0008] In view of the above-mentioned problems, the photolithography process is simplified by reducing the number of exposure masks. Another object is to manufacture a semiconductor device at low cost with high productivity. [Means for solving the problem]

[0009] In a method for manufacturing a semiconductor device having an inverted staggered thin film transistor, The mask layer formed by the multi-tone mask is an exposure mask with an intensity of The coating process is carried out.

[0010] The mask layer formed using the multi-tone mask has a shape with multiple film thicknesses, and etching By doing this, the shape can be further deformed, so multiple elements can be processed into different patterns. Therefore, one multi-tone mask can be used for the etching process. It is possible to form a mask layer corresponding to two or more different patterns. This reduces the number of steps and the corresponding photolithography steps, This makes it possible to simplify the above.

[0011] In the manufacturing process of an inverted staggered thin film transistor, the semiconductor film and the conductive film are processed into an island shape. and an etching process (first etching process) for etching the conductive film and the semiconductor layer into a source electrode layer and a drain electrode layer. An etching process (second etching) for etching the semiconductor layer having a recessed portion. The first etching step and the second etching step are called etching. This is done by dry etching using etching gas.

[0012] The etching gas may be a gas containing chlorine (chlorine-based gas, for example, Cl2, BCl3, Si Furthermore, oxygen or a rare gas (e.g., Ar) may be added to the above gas. An etching gas may also be used.

[0013] The oxide semiconductor used in this specification is InMO3(ZnO) m Thin (m>0) A thin film is formed, and a thin film transistor is fabricated using the thin film as the semiconductor layer. , gallium (Ga), iron (Fe), nickel (Ni), manganese (Mn) and cobalt ( Co) represents one or more metal elements selected from the group consisting of Ga and Co. In addition, there are cases where the above metal elements other than Ga are included, such as Ga and Ni or Ga and Fe. In addition, in the oxide semiconductor, there may be impurities other than the metal element contained as M. Contains Fe, Ni or other transition metal elements, or oxides of said transition metals as the solid element. In this specification, this thin film is also called an In-Ga-Zn-O based non-single crystal film. .

[0014] The crystalline structure of the In-Ga-Zn-O non-single crystal film is formed by sputtering and then heated at 200°C This is done at 500°C, typically 300-400°C for 10-100 minutes, so amorphous The structure of the thin film transistor is observed by XRD (X-ray diffraction). At a gate voltage of ±20V, the on / off ratio was 10 9 Above, create a mobility of 10 or more. It can be manufactured.

[0015] Another embodiment of the invention disclosed in this specification is a gate electrode layer on a substrate having an insulating surface. a gate insulating layer, an oxide semiconductor film, and a conductive film are stacked over the gate electrode layer; a first mask layer is formed over the oxide insulating layer, the oxide semiconductor film, and the conductive film; The oxide semiconductor film and the conductive film are etched in a first etching step using the oxide semiconductor film. A compound semiconductor layer and a conductive layer are formed, and the first mask layer is etched (ashed) to form a second A mask layer is formed, and the oxide semiconductor layer and the conductive layer are subjected to a second etching using the second mask layer. The oxide semiconductor layer, the source electrode layer, and the drain electrode layer are etched by a etching process. The first mask layer is formed by using an exposure mask that transmits light with multiple intensities. The first and second etching steps are performed by dry etching using an etching gas. The source electrode layer and the drain electrode layer are formed by etching in the oxide semiconductor layer having the recessed portion. It has a region with a thickness thinner than the region overlapping with the pole layer.

[0016] Another embodiment of the invention disclosed in this specification is a gate electrode layer on a substrate having an insulating surface. a gate insulating layer, a first oxide semiconductor film, a second oxide semiconductor film, and a gate insulating layer are formed on the gate electrode layer; a gate insulating layer, a first oxide semiconductor film, a conductive film, and a gate insulating layer; and forming a first mask layer on the conductive film, and forming a first oxide semiconductor layer using the first mask layer. the oxide semiconductor film, the second oxide semiconductor film, and the conductive film are etched in a first etching step, A first oxide semiconductor layer, a second oxide semiconductor layer, and a conductive layer are formed, and a first mask layer is formed. A second mask layer is formed by etching (ashing), and the first mask layer is formed by using the second mask layer. The oxide semiconductor layer, the second oxide semiconductor layer, and the conductive layer are etched by a second etching step. By this, an oxide semiconductor layer having a recess, a source region, a drain region, a source electrode layer and The first mask layer is an exposure mask that transmits light with a plurality of intensities. The first etching step and the second etching step are performed using an etching gas. The source region and the drain region are formed in the oxide semiconductor layer having the recess by dry etching using a method such as the following. The film has a region whose thickness is thinner than the film thickness of the region overlapping the in-region.

[0017] The method for manufacturing a semiconductor device disclosed in this specification solves at least one of the above problems.

[0018] Also, a second oxide semiconductor used as a source region and a drain region of a thin film transistor The film is thinner than the first oxide semiconductor film used as a channel formation region and has a larger thickness. It is preferable that the conductive material has a higher electrical conductivity (electrical conductivity).

[0019] The second oxide semiconductor film has n-type conductivity and functions as a source region and a drain region. do.

[0020] The first oxide semiconductor film has an amorphous structure, and the second oxide semiconductor film has an amorphous structure. The crystal grains (nanocrystals) in the second oxide semiconductor film may be included. Nanocrystals have a diameter of 1 nm to 10 nm, typically about 2 nm to 4 nm.

[0021] The second oxide semiconductor film used as the source and drain regions (n+ layer) is an In- A Ga-Zn-O based non-single crystal film can be used.

[0022] An insulating film covering the thin film transistor and in contact with the oxide semiconductor layer including the channel formation region is formed. It may be formed.

[0023] In addition, thin film transistors are easily damaged by static electricity, so the gate line or source It is preferable to provide a protection circuit for protecting the driver circuit on the same substrate as the line. is preferably configured using a nonlinear element using an oxide semiconductor.

[0024] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of processes or stacking. Furthermore, the specific names used in this specification are not intended to identify the invention. This does not indicate

[0025] In addition to liquid crystal display devices, display devices having a driving circuit include light-emitting devices using light-emitting elements. display devices, and display devices that use electrophoretic display elements and are also called electronic paper. .

[0026] In a light-emitting display device using a light-emitting element, a plurality of thin film transistors are provided in a pixel portion, and a pixel In the element part, the gate electrode of a thin film transistor and the source wiring of another transistor, The light-emitting device has a portion to which a drain wiring is connected. In the driving circuit of the thin film transistor, the gate electrode of the thin film transistor and the source The gate electrode has a portion for connecting a wiring or a drain wiring.

[0027] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Generally, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. [Effects of the Invention]

[0028] By reducing the number of exposure masks, the photolithography process is simplified, resulting in reliable semiconductors. The device can be manufactured at low cost and with good productivity. [Brief explanation of the drawings]

[0029] [Figure 1] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 2] 1A to 1C illustrate a semiconductor device. [Figure 3] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 4] 1A to 1C illustrate a semiconductor device. [Figure 5] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 6] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 7] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 8] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 9] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 10] 1A to 1C illustrate a semiconductor device. [Figure 11] 1A to 1C illustrate a semiconductor device. [Figure 12] 1A to 1C illustrate a semiconductor device. [Figure 13] 1A to 1C illustrate a semiconductor device. [Figure 14] FIG. 1 is a block diagram illustrating a semiconductor device. [Figure 15] FIG. 2 illustrates a configuration of a signal line driver circuit. [Figure 16] 4 is a timing chart illustrating the operation of the signal line driver circuit. [Figure 17] 4 is a timing chart illustrating the operation of the signal line driver circuit. [Figure 18] FIG. 2 is a diagram illustrating the configuration of a shift register. [Figure 19] FIG. 19 is a diagram for explaining the connection configuration of the flip-flop shown in FIG. 18. [Figure 20] 1A and 1B are diagrams illustrating pixel equivalent circuits of a semiconductor device. [Figure 21] 1A to 1C illustrate a semiconductor device. [Figure 22] 1A to 1C illustrate a semiconductor device. [Figure 23] 1A to 1C illustrate a semiconductor device. [Figure 24] 1A to 1C illustrate a semiconductor device. [Figure 25] 1A and 1B are diagrams illustrating examples of usage of electronic paper. [Figure 26] FIG. 1 is an external view showing an example of an electronic book. [Figure 27] FIG. 1 is an external view showing an example of a television device and a digital photo frame. [Figure 28] FIG. 1 is an external view showing an example of a gaming machine. [Figure 29] FIG. 1 is an external view showing an example of a mobile phone. [Figure 30] FIG. 10 is a diagram illustrating a multi-tone mask. DETAILED DESCRIPTION OF THE INVENTION

[0030] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. Those skilled in the art will recognize that various changes in form and details may be made without departing from the spirit and scope of the present invention. Therefore, the present invention should be interpreted as being limited to the following description of the embodiments. In the configuration described below, parts that have the same parts or similar functions are not included. The same reference numerals are used in common between different drawings for corresponding parts, and repeated explanations thereof will be omitted.

[0031] (Embodiment 1) A method for manufacturing a semiconductor device of this embodiment mode will be described with reference to FIGS.

[0032] FIG. 2A1 is a plan view of a thin film transistor 420 included in the semiconductor device of this embodiment mode. 2(A2) is a cross-sectional view taken along the line C1-C2 in FIG. 2(A1). The transistor 420 is an inverted staggered thin film transistor, and includes a gate electrode layer 401, a gate insulating layer 4 02, a semiconductor layer 403, which functions as a source region or a drain region, + Layer 404a, 4 04b, and source and drain electrode layers 405a and 405b.

[0033] 1A to 1E correspond to cross-sectional views illustrating a manufacturing process of a thin film transistor 420. FIG.

[0034] In FIG. 1A, a gate electrode is formed on a substrate 400 on which an insulating film 407 serving as a base film is provided. The insulating film 407 has a function of preventing diffusion of impurity elements from the substrate 400. The film is selected from a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, and a silicon oxynitride film. Alternatively, it can be formed by a stacked structure of a plurality of films. The gate electrode layer 401 is made of a material selected from molybdenum, titanium, and quartz. Metallic materials such as chromium, tantalum, tungsten, aluminum, copper, neodymium, and scandium It can be formed in a single layer or a laminated layer using a material or an alloy material containing these as the main component. do.

[0035] For example, the gate electrode layer 401 may have a two-layer laminate structure, such as a molybdenum layer on an aluminum layer. Two-layer structure with a layer stacked on top of a copper layer, or a two-layer structure with a molybdenum layer stacked on top of a copper layer, The titanium nitride layer and the tantalum nitride layer are laminated on the copper layer. It is preferable to use a two-layer structure in which a layer of tungsten is laminated with a layer of ribide. a tungsten layer or tungsten nitride layer and an aluminum-silicon alloy layer or an aluminum The layer may be a laminate of an alloy layer of titanium and titanium and a titanium nitride layer or a titanium layer. preferable.

[0036] A gate insulating layer 402, a first oxide semiconductor film 431, a second oxide semiconductor film 432, a gate insulating film 402, a gate electrode layer 401, a gate insulating film 402 ... A compound semiconductor film 432 and a conductive film 433 are stacked in this order.

[0037] The gate insulating layer 402 is formed by depositing silicon oxide using a plasma CVD method, a sputtering method, or the like. a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer, which may be formed as a single layer or a stacked layer; The gate insulating layer 402 can be formed by using C It is also possible to form a silicon oxide layer by the VD method. ethyl acetate (TEOS: chemical formula Si(OC2H5)4), tetramethylsilane (TMS: chemical formula Chemical formula: Si(CH3)4), tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane Methylcyclotetrasiloxane (OMCTS), hexamethyldisilazane (HMDS), Triethoxysilane (SiH(OC2H5)3), trisdimethylaminosilane (SiH Silicon-containing compounds such as (N(CH3)2)3) can be used.

[0038] Note that before the first oxide semiconductor film 431 was formed by a sputtering method, argon gas was introduced. The reverse sputtering is performed by introducing the silicon dioxide into the gate insulating layer 402 to generate plasma. It is preferable to remove the dust particles that are sputtered. In an argon atmosphere, a voltage is applied to the substrate side using an RF power supply to form plasma on the substrate. This is a method for modifying the surface. Note that nitrogen, helium, etc. can be used instead of argon atmosphere. Alternatively, the treatment may be carried out in an argon atmosphere to which oxygen, hydrogen, N2O, etc. have been added. Alternatively, the treatment may be carried out in an argon atmosphere to which Cl2, CF4, etc. have been added.

[0039] In addition, a contact region between the second oxide semiconductor film 432 and the conductive film 433 is formed by plasma treatment. In this embodiment, before the conductive film 433 is formed, the second The oxide semiconductor film 432 (in this embodiment, an In—Ga—Zn—O-based non-single-crystal film) is Plasma treatment is carried out in a nitrogen atmosphere.

[0040] The plasma treatment may be performed using nitrogen, helium, or the like instead of an argon atmosphere. It may be performed in an argon atmosphere to which oxygen, hydrogen, N2O, etc. have been added. The treatment may be carried out in an atmosphere containing Cl2, CF4, etc.

[0041] In this embodiment, the first oxide semiconductor film 431 and the second oxide semiconductor film 432 are An In-Ga-Zn-O based non-single crystal film is used. The second oxide semiconductor film 432 is formed under different deposition conditions from the second oxide semiconductor film 432. The second oxide semiconductor film 432 has high conductivity and low resistance. The oxide semiconductor obtained by sputtering under the condition of argon gas flow rate of 40 sccm was The second oxide semiconductor film 432 has n-type conductivity and an activation energy In this embodiment, the second acid (ΔE) is 0.01 eV or more and 0.1 eV or less. The compound semiconductor film 432 is an In-Ga-Zn-O based non-single crystal film, and is at least amorphous. The second oxide semiconductor film 432 has an amorphous structure and contains a crystalline component. The second oxide semiconductor film 432 may contain crystal grains (nanocrystals). Nanocrystals have a diameter of 1 nm to 10 nm, typically about 2 nm to 4 nm.

[0042] n + By providing the second oxide semiconductor film 432 as a metal layer, the conductive film 43 The first oxide semiconductor film 431 serving as a channel formation region is bonded to the first oxide semiconductor film 432. It has thermally stable operation compared to Schottky junctions. (source side) or stably absorbs the carriers in the channel (drain side), or In order to avoid creating a resistance component at the interface with the wiring, + It is effective to provide layers Furthermore, the low resistance allows good mobility to be maintained even at high drain voltages.

[0043] The gate insulating layer 402, the first oxide semiconductor film 431, the second oxide semiconductor film 432, and the conductive The film 433 can be continuously formed without being exposed to the atmosphere. By continuously forming films without any contamination from atmospheric components or contaminating impurity elements floating in the air, Since each lamination interface can be formed without any trouble, the variation in thin film transistor characteristics can be reduced. can be reduced.

[0044] The gate insulating layer 402, the first oxide semiconductor film 431, the second oxide semiconductor film 432, and the conductive A mask 434 is formed on the film 433 .

[0045] In this embodiment, an example is given in which exposure is performed using a high-contrast mask to form the mask 434. A resist is formed to form a mask 434. The resist may be a positive resist or A positive resist is used here.

[0046] Next, a multi-tone mask 59 is used as an exposure mask to irradiate the resist with light. Expose to light.

[0047] Here, exposure using the multi-tone mask 59 will be described with reference to FIG.

[0048] A multi-tone mask has three exposure levels: exposed, intermediately exposed, and unexposed. This is an exposure mask that allows light to be transmitted through multiple intensities. A resist mask with multiple (typically two) thickness regions created by the light and development process Therefore, by using a multi-tone mask, the number of exposure masks can be reduced. It is possible to reduce the number.

[0049] Typical examples of multi-tone masks include a gray-tone mask 59a as shown in FIG. 30(A), There is a half-tone mask 59b as shown in FIG. 30(C).

[0050] As shown in FIG. 30(A), the gray-tone mask 59a is made of a transparent substrate 63 and a The light-shielding portion 64 is formed by a light-shielding element 65 and a diffraction grating 65. On the other hand, the diffraction grating 65 has slits, dots, meshes, and other light transmitting portions. The light transmittance is controlled by setting the interval to be equal to or less than the resolution limit of the light used for exposure. The diffraction grating 65 may be a periodic slit, dot, mesh, or non-periodic grating. Periodic slits, dots, or meshes can all be used.

[0051] The light-transmitting substrate 63 may be a light-transmitting substrate such as quartz. The grating 65 can be formed using a light-shielding material that absorbs light, such as chromium or chromium oxide. Cut.

[0052] When the gray-tone mask 59a is irradiated with exposure light, as shown in FIG. 30(B), the light-shielding portion In 64, the light transmittance 66 is 0%, and the light blocking portion 64 and the diffraction grating 65 are provided. In the area where no light is emitted, the light transmittance 66 is 100%. The light transmittance of the diffraction grating 65 can be adjusted within a range of 70%. This is possible by adjusting the spacing and pitch of the slits, dots, or mesh.

[0053] As shown in FIG. 30(C), the halftone mask 59b is formed on a light-transmitting substrate 63 and The semi-transmitting portion 68 is made of MoSiN, and the light-shielding portion 67 is made of MoSiN. MoSi, MoSiO, MoSiON, CrSi, etc. can be used. The light-shielding layer 12 can be formed using a light-absorbing, light-shielding material such as chromium or chromium oxide.

[0054] When the halftone mask 59b is irradiated with exposure light, as shown in FIG. 30(D), the light-shielding portion In the case of 67, the light transmittance 69 is 0%, and the light-shielding portion 67 and the semi-transmitting portion 68 are provided. In the non-transparent region, the light transmittance 69 is 100%. The light transmittance of the semi-transmitting portion 68 can be adjusted within a range of 70%. This can be adjusted using 8 materials.

[0055] After exposure using a multi-tone mask, development produces a film with different film thicknesses as shown in Figure 1(B). A mask 434 can be formed having regions corresponding to the etched portions.

[0056] Next, a first etching step is performed using the mask 434, and the first oxide semiconductor film 431 The second oxide semiconductor film 432 and the conductive film 433 are etched to form an island shape. , a first oxide semiconductor layer 435, a second oxide semiconductor layer 436, and a conductive layer 437 are formed. This is possible (see Figure 1(B)).

[0057] Next, the mask 434 is ashed. As a result, the area of ​​the mask is reduced and the thickness is thinned. At this time, the resist of the mask in the thin film region (which overlaps with a part of the gate electrode layer 401) is The regions (which are to be removed) can be removed to form the isolated mask 438 (see FIG. 1(C)). .).

[0058] The first oxide semiconductor layer 435, the second oxide semiconductor layer 436, and the conductive oxide semiconductor layer 437 are formed using a mask 438. The layer 437 is etched by a second etching step to remove the semiconductor layer 403 and the n+ layer 404a. , 404b, and source and drain electrode layers 405a and 405b are formed (FIG. 1( See D). The semiconductor layer 403 is only partially etched to have a groove (recess). The semiconductor layer is then partially etched and exposed at the edge.

[0059] In this embodiment, the first etching step and the second etching step are performed using an etching gas. This is done using dry etching with a gas.

[0060] The etching gas may be a gas containing chlorine (chlorine-based gas, for example, chlorine (Cl2), boron chloride, etc.). Preferred are silicon chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride (CCl4), etc. By using a gas containing chlorine to etch, it is possible to reduce the amount of etching that would occur if a gas not containing chlorine were used. This is because, compared to the case where the etching is performed in a non-uniform manner, the etching variation within the surface can be reduced.

[0061] In addition, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (CF4) and sulfur fluoride (SF 6), nitrogen fluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (HBr ), oxygen (O2), and rare gases such as helium (He) and argon (Ar) Additive gases, etc. can be used.

[0062] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing) method and ICP (Inductively Coupled Plasma) A combined plasma etching method can be used. It is possible to etch into the desired processed shape. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) were determined as follows: The amount of power used, the temperature of the electrode on the substrate, etc. are adjusted appropriately.

[0063] In this embodiment, the etching is performed by ICP etching using Cl2 and O2 under the following conditions: The amount of power applied to the coil-type electrode was 1500 W, and the amount of power applied to the substrate-side electrode was 20 The heating was performed at 0 W, a pressure of 1.5 Pa, and a substrate temperature of -10°C.

[0064] In addition, the ICP etching method uses Cl2 (flow rate 100 sccm) as the etching gas. The etching conditions were: power applied to the coil electrode: 2000 W; The treatment may be performed under the conditions of a power amount applied to the electrode of 600 W, a pressure of 1.5 Pa, and a substrate temperature of -10°C.

[0065] The first oxide semiconductor film 431 is an In-Ga-Zn-O based non-single-crystal film, and the second oxide When the semiconductor film 432 is etched under the etching conditions, the edge of the semiconductor layer 403 is etched by 5 degrees. This allows the film to have a low taper angle of 0.1 mm or less, improving the coverage of the film to be laminated. During the etching process, the plasma emission intensity is measured, and the wavelength corresponding to each atom in the oxide semiconductor film is calculated. It is advisable to monitor the etching to determine the end point (also called the endpoint). This method prevents the thinning of the gate insulating layer under the semiconductor layer and the etching residue of the oxide semiconductor film. The etching can be controlled to reduce the damage.

[0066] Chlorine gas (Cl2) and oxygen gas (O2) (preferably the oxygen gas content in the etching gas) When etching is performed after adding silicon dioxide (content of 15% by volume or more), the gate insulating layer 402 is oxidized and nitrided. In the case where a silicon film is used for the first oxide semiconductor layer 435 and the second oxide semiconductor layer 436, This increases the selectivity with respect to the In-Ga-Zn-O based non-single crystal film that is used. Only the first oxide semiconductor film 431 and the second oxide semiconductor film 432 are selectively etched. This is because damage to the gate insulating layer 402 can be sufficiently reduced.

[0067] The first oxide semiconductor film 431, the second oxide semiconductor film 432, and the conductive film 433 are formed by a first etching. By dry etching in the etching step, the first oxide semiconductor film 431 and the second oxide semiconductor film 432 are Since the conductive film 432 and the conductive film 433 are anisotropically etched, the edge of the mask 434 and the The first oxide semiconductor layer 435, the second oxide semiconductor layer 436, and the conductive layer 437 have edges that are aligned with each other. , resulting in a continuous shape.

[0068] Similarly, the first oxide semiconductor layer 435, the second oxide semiconductor layer 436, and the conductive layer 437 are By dry etching in the etching step, the first oxide semiconductor layer 435 and the second oxide semiconductor layer 436 are Since the compound semiconductor layer 436 and the conductive layer 437 are anisotropically etched, the edge of the mask 438 The recess and edge of the semiconductor layer 403, the n+ layers 404a and 404b, the source electrode layer or the drain electrode layer The ends of the inner electrode layers 405a and 405b coincide with each other, forming a continuous shape.

[0069] In this embodiment, the semiconductor layer 403, the n+ layers 404a and 404b, the source electrode layer The drain electrode layers 405a and 405b have ends that are continuously laminated with the same taper angle. The shape of the oxide semiconductor and conductive material may change depending on the etching conditions. Because the grooves are different, they may have different taper angles and discontinuous edge shapes.

[0070] After this, the mask 438 is removed.

[0071] The source and drain electrode layers 405a and 405b may be formed of the semiconductor layer 40 It is preferable to use a material with a higher etching rate than 3. This is because dry etching As a result, the source electrode layer or the drain electrode layer 405a, 405b and the semiconductor layer 403 can be formed at once. In the case of etching, the etching rate of the semiconductor layer 403 is set to the value of the source electrode layer or the drain electrode layer. By making the etching rate of the electrode layers 405a and 405b smaller than that of the semiconductor layer 403, As a result, the semiconductor layer can be prevented from being excessively etched. It is possible to suppress the disappearance of 403.

[0072] After that, it is advisable to carry out a heat treatment at 200 to 600°C, typically 300 to 500°C. Here, the heat treatment is performed in a nitrogen atmosphere at 350° C. for 1 hour. 03, atoms of In-Ga-Zn-O-based oxide semiconductors constituting the n+ layers 404a and 404b This heat treatment (including photo-annealing) is performed on the semiconductor layer 403, n It is important in that it can release the strain that inhibits the movement of carriers in the + layers 404a and 404b. Note that the above heat treatment is performed at the timing when the first oxide semiconductor film 431 and the second oxide semiconductor film 432 are There is no particular limitation as long as it is after the oxide semiconductor film 432 is formed.

[0073] Further, oxygen radical treatment may be performed on the exposed recesses of the semiconductor layer 403. By performing the atomic radical treatment, a thin film transistor having the semiconductor layer 403 as a channel forming region is formed. Furthermore, by performing radical treatment, the semiconductor The radical treatment can recover the damage caused by etching of the silicon dioxide layer 403. It is preferable to carry out the reaction under an atmosphere of N2O, N2 containing oxygen, He, Ar, or the like. The radical treatment may be carried out in an atmosphere containing Cl2 and CF4. It is preferable to perform this without applying a bias voltage to the plate side.

[0074] Through the above steps, an inverted staggered thin film transistor 420 shown in FIG. 1(E) can be manufactured. can.

[0075] As in this embodiment, a plurality of (typically two types of) thicknesses are formed using a multi-tone mask. By using a resist mask with regions, the number of resist masks can be reduced. This simplifies the process and reduces costs, allowing reliable semiconductor devices to be produced at low cost. It can be manufactured with good efficiency.

[0076] (Embodiment 2) Here, in Embodiment 1, the source electrode layer and the drain electrode layer are in contact with the semiconductor layer. An example of a semiconductor device having a thin film transistor having such a configuration is shown in FIGS.

[0077] FIG. 4A1 is a plan view of a thin film transistor 460 included in the semiconductor device of this embodiment mode. 4(A2) is a cross-sectional view taken along the line D1-D2 in FIG. 4(A1). The transistor 460 is an inverted staggered thin film transistor, and includes a gate electrode layer 451, a gate insulating layer 4 52, a semiconductor layer 453, and source and drain electrode layers 455a and 455b.

[0078] 3A to 3E correspond to cross-sectional views illustrating a manufacturing process of the thin film transistor 460. FIG.

[0079] In FIG. 3A, a gate electrode layer 451 is provided over a substrate 450 on which an insulating film 457 is provided. In this embodiment, a silicon oxide film (thickness: 100 nm) is used as the insulating film 457. The gate insulating layer 452, the oxide semiconductor film 481, and the conductive film 483 are formed over the gate electrode layer 451. Layer them in order.

[0080] A contact region between the oxide semiconductor film 481 and the conductive film 483 is modified by plasma treatment. In this embodiment, the oxide semiconductor film 4 is preferably formed before the conductive film 483 is formed. 81 (in this embodiment, an In-Ga-Zn-O based non-single crystal film) in an argon atmosphere. Perform Zuma processing.

[0081] The plasma treatment may be performed using nitrogen, helium, or the like instead of an argon atmosphere. It may be performed in an argon atmosphere to which oxygen, hydrogen, N2O, etc. have been added. The treatment may be carried out in an atmosphere containing Cl2, CF4, etc.

[0082] The gate insulating layer 452, the oxide semiconductor film 481, and the conductive film 483 are formed without being exposed to air. By continuously forming films without exposing them to the atmosphere, atmospheric deposition is possible. The interfaces of the layers can be formed without being contaminated by impurity elements floating in the atmosphere or by chemicals. Therefore, variations in the characteristics of the thin film transistors can be reduced.

[0083] A mask 484 is formed over the gate insulating layer 452, the oxide semiconductor film 481, and the conductive film 483. .

[0084] In this embodiment, exposure using a multi-tone (high-tone) mask is used to form the mask 484. The mask 484 can be formed in the same manner as the mask 434 in the first embodiment. Cut.

[0085] After exposure using a multi-tone mask that transmits light with multiple intensities, the pattern is developed, resulting in the pattern shown in Figure 3. As shown in (B), a mask 484 having regions with different film thicknesses can be formed. By using a gradation mask, it is possible to reduce the number of exposure masks.

[0086] Next, a first etching step is performed using the mask 484, and the oxide semiconductor film 4481 and the conductive film 4482 are removed. The conductive film 483 is etched to form an island shape. 87 can be formed (see FIG. 3(B)).

[0087] Next, the mask 484 is ashed. As a result, the area of ​​the mask is reduced and the thickness is reduced. At this time, the resist of the mask in the thin film region (which overlaps with a part of the gate electrode layer 451) is The regions (which are to be removed) can be removed to form an isolated mask 488 (see FIG. 3(C)). .).

[0088] The oxide semiconductor layer 485 and the conductive layer 487 are etched using the mask 488 by a second etching step. The semiconductor layer 453, the source electrode layer 455a, and the drain electrode layer 455b are then etched away. (See FIG. 3D.) Note that the semiconductor layer 453 is only partially etched. The semiconductor layer has a groove (recess), and the edge is also partially etched and exposed. The shape is as follows.

[0089] In this embodiment, the first etching step and the second etching step are performed using an etching gas. This is done using dry etching with a gas.

[0090] The etching gas may be a gas containing chlorine (chlorine-based gas, for example, chlorine (Cl2), boron chloride, etc.). Preferred are silicon chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride (CCl4), etc. By using a gas containing chlorine to etch, it is possible to reduce the amount of etching that would occur if a gas not containing chlorine were used. This is because, compared to the case where the etching is performed in a non-uniform manner, the etching variation within the surface can be reduced.

[0091] In addition, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (CF4) and sulfur fluoride (SF 6), nitrogen fluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (HBr ), oxygen (O2), and rare gases such as helium (He) and argon (Ar) Additive gases, etc. can be used.

[0092] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing) method and ICP (Inductively Coupled Plasma) A combined plasma etching method can be used. It is possible to etch into the desired processed shape. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) were determined as follows: The amount of power used, the temperature of the electrode on the substrate, etc. are adjusted appropriately.

[0093] In this embodiment, the etching conditions are: The amount of power applied to the coil-type electrode is 1500 W, and the amount of power applied to the substrate-side electrode is 2 The heating was performed at 00 W, pressure of 1.5 Pa, and substrate temperature of -10°C.

[0094] Chlorine gas (Cl2) is mixed with oxygen gas (O2) (preferably 15% by volume or more) to perform etching. When a silicon oxynitride film is used for the gate insulating layer 452, the oxide semiconductor layer 4 The selectivity with the In-Ga-Zn-O based non-single crystal film used in 85 can be increased. Therefore, only the oxide semiconductor film 481 can be selectively etched.

[0095] When the oxide semiconductor film 481 and the conductive film 483 are dry-etched in the first etching step, Since the oxide semiconductor film 481 and the conductive film 483 are anisotropically etched, the mask 484 The edge portions of the oxide semiconductor layer 485 and the conductive layer 487 are aligned with each other, forming a continuous shape.

[0096] Similarly, the oxide semiconductor layer 485 and the conductive layer 487 are dry-etched in a second etching step. Then, the oxide semiconductor layer 485 and the conductive layer 487 are anisotropically etched. The end of the semiconductor layer 453, the recess and the end of the semiconductor layer 453, the source electrode layer or the drain electrode layer 45 The ends of 5a and 45b coincide with each other to form a continuous shape.

[0097] In this embodiment, the semiconductor layer 453, the source or drain electrode layer 455a, The end of 455b has a shape that is continuously laminated with the same taper angle, but the etching process The etching rate varies depending on the conditions and the materials of the oxide semiconductor layer and the conductive layer. They may have different taper angles and discontinuous edge shapes.

[0098] After this, the mask 488 is removed.

[0099] Through the above steps, an inverted staggered thin film transistor 460 shown in FIG. 3(E) can be manufactured. can.

[0100] As in this embodiment, a plurality of (typically two types of) thicknesses are formed using a multi-tone mask. By using a resist mask with regions, the number of resist masks can be reduced. This simplifies the process and reduces costs, allowing reliable semiconductor devices to be produced at low cost. It can be manufactured with good efficiency.

[0101] (Embodiment 3) In this embodiment mode, a manufacturing process of a display device including a thin film transistor will be described with reference to FIGS. 2 will be used to explain.

[0102] In FIG. 5(A), a light-transmitting substrate 100 is made of barium borosilicate glass or aluminum. A glass substrate such as borosilicate glass can be used.

[0103] Next, a conductive layer is formed on the entire surface of the substrate 100, and then a first photolithography process is performed. A resist mask is formed, and unnecessary parts are removed by etching to form wiring and electrodes (gate A gate wiring including an electrode layer 101, a capacitance wiring 108, and a first terminal 121 are formed. At this time, etching is performed so that at least the end of the gate electrode layer 101 is tapered. The cross section at this stage is shown in Figure 5(A). The top view at this stage is shown in Figure 7. is equivalent to

[0104] The gate wiring including the gate electrode layer 101, the capacitance wiring 108, and the first terminal 121 of the terminal portion are Heat-resistant conductive materials include titanium (Ti), tantalum (Ta), tungsten (W), Select from molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc) The elements mentioned above, or alloys containing the elements mentioned above, or alloys combining the elements mentioned above It is preferable to form the film from a nitride containing the above-mentioned elements. When forming the capacitor using low-resistance conductive materials such as aluminum (Al) or copper (Cu), aluminum alone is not heat-resistant. However, since it has problems such as poor durability and susceptibility to corrosion, it is recommended to use it in combination with the above heat-resistant conductive materials. Form.

[0105] Next, a gate insulating layer 102 is formed on the entire surface of the gate electrode layer 101. The film thickness of 02 is set to 50 to 250 nm using a sputtering method or the like.

[0106] For example, a silicon oxide film is used as the gate insulating layer 102 by sputtering, and the thickness is 100 nm. Of course, the gate insulating layer 102 is not limited to such a silicon oxide film. Silicon oxide nitride film, silicon nitride film, aluminum oxide film, tantalum oxide film, It may be formed as a single layer or a laminated structure made of these materials using other insulating films such as a film. good.

[0107] Before the oxide semiconductor film is formed, a reverse process in which argon gas is introduced to generate plasma is performed. It is preferable to perform sputtering to remove dust adhering to the surface of the gate insulating layer. Instead of the argon atmosphere, nitrogen, helium, etc. may be used. It may be carried out in an atmosphere containing oxygen, hydrogen, NO, etc. 2. It may be carried out in an atmosphere containing CF4 or the like.

[0108] Next, a first oxide semiconductor film 109 (in this embodiment, the first oxide semiconductor film 109) is formed over the gate insulating layer 102. After plasma treatment, the substrate is left unexposed to the atmosphere. The formation of the first In-Ga-Zn-O based non-single crystal film is a step of forming a gate insulating layer and a semiconductor film. This is useful in that it prevents dust and moisture from adhering to the interface. and a Zn-containing oxide semiconductor target (In2O3:Ga2O3:ZnO=1:1: 1), the distance between the substrate and the target was set to 170 mm, the pressure was 0.4 Pa, and the direct current (D C) Film formation is performed under an argon or oxygen atmosphere with a power of 0.5 kW. Note that pulsed direct current (DC) The use of a power source is preferable because it reduces dust and makes the film thickness distribution uniform. The thickness of the Ga—Zn—O based non-single crystal film is set to 5 nm to 200 nm. The thickness of the In-Ga-Zn-O based non-single crystal film 1 is set to 100 nm.

[0109] Next, the second oxide semiconductor film 111 (the second oxide semiconductor film 112 in this embodiment) was formed without being exposed to the air. In this example, In2O3:G A target of a2O3:ZnO = 1:1:1 was used, and the film formation conditions were a pressure of 0.4 Pa. The power was set to 500 W, the film formation temperature was set to room temperature, and an argon gas flow rate of 40 sccm was introduced. The target is In2O3:Ga2O3:ZnO=1:1:1. Although the film was intentionally made of SiO2, it contained crystal grains of 1 nm to 10 nm in size immediately after deposition. In some cases, a non-single crystal film containing In-Ga-Zn-O may be formed. Ratio, deposition pressure (0.1 Pa to 2.0 Pa), power (250 W to 3000 W: 8 inch diameter) By appropriately adjusting the temperature (room temperature to 100°C) and reactive sputtering film formation conditions, the crystal grains The presence or absence of crystal grains, the density of crystal grains, and the diameter size can be adjusted in the range of 1 nm to 10 nm. The thickness of the second In-Ga-Zn-O based non-single crystal film is set to 5 nm to 20 nm. In theory, if crystal grains are contained in the film, the size of the contained crystal grains must exceed the film thickness. In this embodiment, the thickness of the second In-Ga-Zn-O based non-single crystal film is set to 5 nm. do.

[0110] The first In-Ga-Zn-O based non-single-crystal film is For example, the film formation conditions for the second In-Ga-Zn-O based non-single crystal film are different from those for the first In-Ga-Zn-O based non-single crystal film. The ratio of the oxygen gas flow rate to the argon gas flow rate in the first In-Ga-Zn-O system non-single The conditions for forming the crystal film are such that the oxygen gas flow rate accounts for a large proportion. The deposition conditions for the In-Ga-Zn-O non-single crystal film in 2 are: rare gas (argon or helium) etc.) atmosphere (or oxygen gas 10% or less, argon gas 90% or more), and The conditions for forming the n-Ga-Zn-O non-single crystal film are an oxygen atmosphere (or an oxygen gas flow rate of 1000 MPa). (The flow rate of the gas is equal to or greater than that of the gas.)

[0111] The second In-Ga-Zn-O non-single crystal film was deposited in the chamber where the reverse sputtering was performed previously. The same chamber as the previous reverse sputtering may be used, or a different chamber may be used. The film may be formed using a bar.

[0112] There are two types of sputtering methods: RF sputtering, which uses a high frequency power supply for the sputtering power source, and DC sputtering. There is also the pulsed DC sputtering method, which applies a pulsed bias. The DC sputtering method is mainly used to deposit insulating films, while the DC sputtering method is mainly used to deposit metal films. It is used for.

[0113] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of materials in the same chamber. It is also possible to simultaneously discharge and deposit the same materials.

[0114] Also, a sputtering apparatus using a magnetron sputtering method equipped with a magnet mechanism inside the chamber and ECR sputtering using plasma generated by microwaves without glow discharge. There are sputtering devices that use this method.

[0115] In addition, in the film formation method using the sputtering method, the target material and the sputtering gas component are mixed during film formation. Reactive sputtering is used to form thin films of these compounds by chemically reacting them with each other. There is also a bias sputtering method in which a voltage is also applied to the substrate.

[0116] Next, a metal film was formed on the first oxide semiconductor film 109 and the second oxide semiconductor film 111. A conductive film 132 is formed by sputtering or vacuum deposition. A cross section at this stage is shown in FIG. shown in.

[0117] The material of the conductive film 132 is an element selected from Al, Cr, Ta, Ti, Mo, and W, or or an alloy containing the above elements as a component, or an alloy film of a combination of the above elements. In addition, when heat treatment is performed at 200 to 600°C, the heat resistance that can withstand this heat treatment is introduced. It is preferable to have a conductive film with Al as the only material. It is formed by combining it with a heat-resistant conductive material. The conductive materials include titanium (Ti), tantalum (Ta), tungsten (W), and molybdenum. Elements selected from (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc) or an alloy containing the above elements as components, or an alloy film containing a combination of the above elements, or It is formed from a nitride containing the above-mentioned elements as components.

[0118] Here, the conductive film 132 has a single-layer structure of a titanium film. Alternatively, a titanium film may be stacked on an aluminum film. A Ti film is layered on top of the Ti film, and an aluminum film containing Nd (Al-Nd) is layered on top of the Ti film. The conductive film 132 may be a silicon film, and a Ti film may be formed on top of the silicon film. Alternatively, the aluminum film may have a single layer structure containing the above.

[0119] Next, a second photolithography process is performed to form a resist mask 133. In this embodiment, a multi-tone (high-tone) mask is used to form the mask 133. The mask 133 is formed in the same manner as the mask 434 in the first embodiment. This can be done.

[0120] After exposure using a multi-tone mask that transmits light with multiple intensities, the pattern is developed, resulting in the pattern shown in Figure 5. As shown in (C), a mask 133 having regions with different film thicknesses can be formed. By using a gradation mask, it is possible to reduce the number of exposure masks.

[0121] Next, a first etching step is performed using a mask 133 to remove the first In—Ga—Zn—O The first oxide semiconductor film 109 is an In—Ga—Zn—O-based non-single-crystal film, and the second oxide semiconductor film 109 is an In—Ga—Zn—O-based non-single-crystal film. The second oxide semiconductor film 111, which is a crystalline film, and the conductive film 132 are etched to be processed into island shapes. As a result, the first oxide semiconductor layer 134, the second oxide semiconductor layer 135, and the conductive layer 136 (See FIG. 5(C)). The top view at this stage corresponds to FIG. 8. do.

[0122] Next, the mask 133 is ashed. As a result, the area of ​​the mask is reduced and the thickness is thinned. At this time, the resist of the mask in the thin film region (which overlaps with a part of the gate electrode layer 101) is The regions (which are to be removed) can be removed to form the isolated mask 131 (see FIG. 6(A)). .).

[0123] The first oxide semiconductor layer 134, the second oxide semiconductor layer 135, and the conductive oxide semiconductor layer 136 are formed using the mask 131. The layer 136 is etched in a second etching step to remove the semiconductor layer 103, the source region and The n+ layers 104a and 104b, which are drain regions, and the source or drain electrode layer 105 The semiconductor layer 103 is only partially etched to form grooves (recesses). The semiconductor layer has a portion where the edge is partially etched and exposed. become.

[0124] In this embodiment, the first etching step and the second etching step are performed using an etching gas. This is done using dry etching with a gas.

[0125] The etching gas may be a gas containing chlorine (chlorine-based gas, for example, chlorine (Cl2), boron chloride, etc.). Preferred are silicon chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride (CCl4), etc. By using a gas containing chlorine to etch, it is possible to reduce the amount of etching that would occur if a gas not containing chlorine were used. This is because, compared to the case where the etching is performed in a non-uniform manner, the etching variation within the surface can be reduced.

[0126] In addition, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (CF4) and sulfur fluoride (SF 6), nitrogen fluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (HBr ), oxygen (O2), and rare gases such as helium (He) and argon (Ar) Additive gases, etc. can be used.

[0127] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing) method and ICP (Inductively Coupled Plasma) A combined plasma etching method can be used. It is possible to etch into the desired processed shape. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) were determined as follows: The amount of power used, the temperature of the electrode on the substrate, etc. are adjusted appropriately.

[0128] In this embodiment, the etching conditions are: The amount of power applied to the coil-type electrode is 1500 W, and the amount of power applied to the substrate-side electrode is 2 The heating was performed at 00 W, pressure of 1.5 Pa, and substrate temperature of -10°C.

[0129] Etching is performed by adding oxygen gas (O2) (preferably 15% by volume or more) to chlorine gas (Cl2). When a silicon oxynitride film is used for the gate insulating layer 102, the first oxide semiconductor In—Ga—Zn—O-based non-single-crystal films used for the layer 134 and the second oxide semiconductor layer 135 Since the etching selectivity of the oxide semiconductor film can be increased, only the oxide semiconductor film can be selectively etched. It becomes possible to do this.

[0130] The first oxide semiconductor film 109, the second oxide semiconductor film 111, and the conductive film 132 are formed by a first etching. When dry etching is performed in the etching step, the first oxide semiconductor film 109 and the second oxide semiconductor film 108 are removed. Since the conductive film 111 and the conductive film 132 are anisotropically etched, the edge of the mask 133 and the The edges of the first oxide semiconductor layer 134, the second oxide semiconductor layer 135, and the conductive layer 136 are aligned. , resulting in a continuous shape.

[0131] Similarly, the first oxide semiconductor layer 134, the second oxide semiconductor layer 135, and the conductive layer 136 are When dry etching is performed in the etching step, the first oxide semiconductor layer 134 and the second oxide semiconductor layer 135 are removed. Since the compound semiconductor layer 135 and the conductive layer 136 are anisotropically etched, the edge of the mask 131 The recessed portion of the semiconductor layer 103, the n+ layers 104a and 104b, the source electrode layer or the drain electrode The edges of the layers 105a and 105b meet, forming a continuous shape.

[0132] Next, it is preferable to carry out a heat treatment at 200°C to 600°C, typically 300°C to 500°C. Here, the material is placed in a furnace and heat treated at 350°C for 1 hour in a nitrogen atmosphere. This heat treatment causes rearrangement at the atomic level in the In-Ga-Zn-O non-single crystal film. This releases the strain that inhibits carrier movement, so the heat treatment (including optical annealing) The timing of the heat treatment is important. There are no particular limitations as long as it is after the formation of the single crystal film, and it may be performed, for example, after the formation of the pixel electrode.

[0133] Furthermore, the exposed channel formation region of the semiconductor layer 103 is subjected to oxygen radical treatment. By performing oxygen radical treatment, the thin film transistor can be made normally off. In addition, by performing radical treatment, the semiconductor layer 103 can be etched. The damage can be repaired. Radical treatment involves O2, N2O, preferably oxygen. It is preferable to carry out the process in an atmosphere of N2, He, or Ar. The radical treatment may be carried out in an atmosphere containing a fluorine atom. stomach.

[0134] Through the above steps, a thin film transistor 170 having the semiconductor layer 103 as a channel forming region can be fabricated. The cross-sectional view at this stage is shown in Figure 6(A). The top view at this stage corresponds to Figure 9. Correct.

[0135] In the second etching step, the terminal layer 124, which is made of the same material as the semiconductor layer 103, The terminal 123, the source electrode layer or the drain electrode layer, which is made of the same material as the n+ layers 104a and 104b, The second terminal 122 made of the same material as the layers 105a and 105b is left in the terminal portion. The terminal 122 is a source wiring (a solution including the source electrode layer or the drain electrode layer 105a, 105b). The power supply is electrically connected to the power supply wiring.

[0136] A resist mask having regions of multiple (typically two types) thicknesses formed by a multi-tone mask. By using a mask, the number of resist masks can be reduced, which simplifies the process and reduces costs. This can be achieved.

[0137] Next, the mask 131 is removed, and a protective insulating layer 107 is formed to cover the thin film transistor 170. The protective insulating layer 107 is a silicon nitride film or a silicon oxide film obtained by sputtering or the like. A silicon oxide film, a silicon oxynitride film, an aluminum oxide film, a tantalum oxide film, or the like can be used. Cut.

[0138] Next, a third photolithography step is performed to form a resist mask, and a gate insulating layer 1 02, and the protective insulating layer 107 is etched to form a contact that reaches the drain electrode layer 105b. The etching here forms a hole 125 that reaches the second terminal 122. A contact hole 127 that leads to the first terminal 121 and a contact hole 126 that leads to the first terminal 121 are also formed. The cross section at this stage is shown in Figure 6(B).

[0139] Next, the resist mask is removed, and then a transparent conductive film is formed. are indium oxide (In2O3) and indium oxide tin oxide alloy (In2O3-SnO 2, abbreviated as ITO) is formed using a sputtering method or a vacuum deposition method. Etching of such materials is done with a hydrochloric acid solution. However, etching of ITO in particular Residues tend to be generated, so indium oxide zinc oxide alloy is used to improve etching processability. Gold (In2O3-ZnO) may also be used.

[0140] Next, a fourth photolithography step is performed to form a resist mask, and then etching is performed. The pixel electrode layer 110 is formed by removing unnecessary portions.

[0141] In addition, in this fourth photolithography step, the gate insulating layer 102 in the capacitance section The protective insulating layer 107 serves as a dielectric, and the capacitor wiring 108 and the pixel electrode layer 110 form a storage capacitor. is formed.

[0142] In the fourth photolithography step, the first terminal and the second terminal are resist-etched. The transparent conductive film 128 is covered with a mask to leave the transparent conductive film 128 and 129 formed on the terminal portion. 129 is an electrode or wiring used for connection with the FPC. The formed transparent conductive film 128 serves as a connection terminal electrode that functions as an input terminal of the gate wiring. The transparent conductive film 129 formed on the second terminal 122 serves as an input terminal of the source line. It is a terminal electrode for connection that functions as a

[0143] Next, the resist mask is removed, and the cross-sectional view at this stage is shown in FIG. The top view at this stage corresponds to Figure 10.

[0144] 11(A1) and 11(A2) are top views of the gate wiring terminal portion at this stage. The cross-sectional views are shown in Fig. 11(A1) and Fig. 11(A2) along the line E1-E2. In FIG. 11(A1), a transparent insulating film formed on the protective insulating film 154 The conductive film 155 is a terminal electrode for connection that functions as an input terminal. ), the terminal portion includes a first terminal 151 made of the same material as the gate wiring, and a source The connection electrode layer 153 is made of the same material as the gate wiring, and the gate insulating layer 152 and the semiconductor layer 15 7 and the n+ layer 158 are overlapped with each other, and are electrically connected by the transparent conductive film 155. The portion where the transparent conductive film 128 and the first terminal 121 are in contact with each other shown in FIG. 11( A1) corresponds to the portion where the transparent conductive film 155 and the first terminal 151 are in contact.

[0145] 11(B1) and 11(B2) are different from the source wiring terminal portion shown in FIG. 6(C). The top view and cross-sectional view of different source wiring terminal portions are shown in FIG. 11(B). 1) corresponds to a cross-sectional view taken along the line F1-F2 in FIG. 11(B2). The transparent conductive film 155 formed on the protective insulating film 154 is a contact that functions as an input terminal. In addition, in FIG. 11(B1), the terminal portion is the same as the gate wiring. The electrode layer 156 made of the material is formed on the second terminal 150 electrically connected to the source line. The electrode layer 1 overlaps the gate insulating layer 152, the semiconductor layer 157, and the n+ layer 158. 56 is not electrically connected to the second terminal 150, and the electrode layer 156 is connected to the second terminal 150. For example, by setting the potential to floating, GND, 0V, etc., noise can be reduced. A capacitance for preventing static electricity or a capacitance for preventing static electricity can be formed. 0 is electrically connected to the transparent conductive film 155 via the protective insulating film 154.

[0146] A plurality of gate wirings, source wirings, and capacitance wirings are provided depending on the pixel density. In addition, in the terminal section, a first terminal has the same potential as the gate wiring, a second terminal has the same potential as the source wiring, and The second terminal, the third terminal with the same potential as the capacitance wiring, and so on are arranged in a row. The number of terminals may be any number and may be determined appropriately by the implementer.

[0147] In this way, four photolithography processes were carried out using four photomasks. A pixel having a thin film transistor 170 which is a gate-type n-channel thin film transistor. The thin film transistor and storage capacitor can be completed. By arranging the pixels in a matrix corresponding to the active matrix type, For the sake of convenience, the present specification will discuss such a substrate. Such a substrate is called an active matrix substrate.

[0148] When manufacturing an active matrix liquid crystal display device, an active matrix substrate a liquid crystal layer is provided between the active matrix substrate and an opposing substrate on which an opposing electrode is provided; The common electrode is electrically connected to the counter electrode provided on the counter substrate. A fourth terminal electrically connected to the common electrode is provided on the active matrix substrate. This fourth terminal is used to set the common electrode to a fixed potential, such as GND or 0V. This is a terminal for connecting the

[0149] The pixel configuration is not limited to that shown in FIG. 10, and an example of a top view different from that shown in FIG. 10 is shown in FIG. In the case of 12, no capacitance wiring is provided, and the pixel electrode is connected to the gate wiring of the adjacent pixel, the protective insulating film, and the gate In this example, a storage capacitor is formed by stacking the capacitor wiring and the capacitor wiring The third terminal connected to the terminal 3 can be omitted. The same reference numerals will be used for the explanation.

[0150] In an active matrix liquid crystal display device, pixel electrodes arranged in a matrix form By driving the selected pixels, a display pattern is formed on the screen. A voltage is applied between the electrode and the counter electrode corresponding to the pixel electrode. The liquid crystal layer disposed between the electrode and the counter electrode is optically modulated, and this optical modulation produces a display pattern. is perceived by the observer as

[0151] When displaying moving images on a liquid crystal display device, the response of the liquid crystal molecules themselves is slow, which can cause afterimages. In order to improve the moving image characteristics of the LCD device, There is a driving technique called black insertion, which displays black every other frame.

[0152] In addition, the vertical cycle can be increased to 1.5 or 2 times the normal vertical cycle to improve the video characteristics. There is also a driving technology called double speed driving, which improves the image quality.

[0153] In addition, in order to improve the video characteristics of the LCD display, multiple LEDs (light emitting diodes) are used as backlights. A surface light source is formed by using a diode) light source or multiple EL light sources, etc., and a surface light source is formed. There is also a driving technology that drives each light source to light intermittently within one frame period. Therefore, three or more types of LEDs may be used, or white-emitting LEDs may be used. Since multiple LEDs can be controlled, the LE can be switched in accordance with the timing of the optical modulation of the liquid crystal layer. This driving technology can also synchronize the timing of the LEDs to be turned off. This is especially useful when displaying images with a large proportion of black areas occupying the entire screen. This can reduce power consumption.

[0154] By combining these driving technologies, the display characteristics such as the video characteristics of the LCD device can be improved. can be improved compared to the past.

[0155] The n-channel transistor obtained in this embodiment is an In-Ga-Zn-O based non-single crystal The crystal film is used in the channel formation region and has good dynamic characteristics, so these driving technologies They can be combined.

[0156] In addition, when a light-emitting display device is manufactured, one electrode (also called a cathode) of the organic light-emitting element is In order to set the low power supply potential, for example, GND or 0V, the cathode is connected to the terminal. A fourth terminal is provided for setting the voltage level, for example, GND, 0V, etc. When manufacturing a device, a power supply line is provided in addition to a source line and a gate line. Therefore, the terminal section is provided with a fifth terminal that is electrically connected to the power supply line.

[0157] As in this embodiment, by forming a thin film transistor using an oxide semiconductor, The manufacturing cost can be reduced.

[0158] As in this embodiment, a plurality of (typically two types of) thicknesses are formed using a multi-tone mask. By using a resist mask with regions, the number of resist masks can be reduced. This simplifies the process and reduces costs, allowing reliable semiconductor devices to be produced at low cost. It can be manufactured with good efficiency.

[0159] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0160] (Fourth embodiment) In this embodiment, in a display device which is an example of a semiconductor device, at least An example of manufacturing a part of a driver circuit and a thin film transistor disposed in a pixel portion will be described below. do.

[0161] The thin film transistors disposed in the pixel portion are formed according to any one of Embodiments 1 to 3. The thin film transistors shown in the first to third embodiments are n-channel TFTs, so that the Among them, part of the driver circuit can be configured with n-channel TFTs. It is formed on the same substrate as the resistor.

[0162] FIG. 1 shows an example of a block diagram of an active matrix liquid crystal display device, which is an example of a semiconductor device. The display device shown in FIG. 14(A) is a display device having a display element on a substrate 5300. A pixel portion 5301 having a plurality of pixels, a scanning line driver circuit 5302 for selecting each pixel, and a scanning line driver circuit 5303 for selecting each pixel. and a signal line driver circuit 5303 for controlling input of a video signal to the pixel.

[0163] The pixel portion 5301 is a signal line driver circuit 5303. The signal line driver circuit 5303 is arranged to extend in the column direction. The signal line driver circuit 5303 is connected to the signal line driver circuit 5303 by lines S1 to Sm (not shown). A plurality of scanning lines G1 to Gn (not shown) are arranged extending from 5302 in the row direction. The scanning line driver circuit 5302 is connected to the signal lines S1 to Sm and the scanning lines G1 to Gn. The image sensor has a plurality of pixels (not shown) arranged in a matrix. signal line Sj (one of the signal lines S1 to Sm), scanning line Gi (one of the scanning lines G1 to Gn), (either one) is connected.

[0164] The thin film transistors described in Embodiments 1 to 3 are n-channel TFTs. A signal line driver circuit configured with channel type TFTs will be described with reference to FIG.

[0165] The signal line driver circuit shown in FIG. 15 includes a driver IC 5601 and a group of switches 5602_1 to 5602_56. 02_M, a first wiring 5611, a second wiring 5612, a third wiring 5613 and a wiring 56 Each of the switch groups 5602_1 to 5602_M includes: A first thin film transistor 5603a, a second thin film transistor 5603b, and a third thin film transistor It has a transistor 5603c.

[0166] The driver IC 5601 is connected to a first wiring 5611, a second wiring 5612, and a third wiring 5613. and are connected to the wirings 5621_1 to 5621_M. 5602_M are connected to the first wiring 5611, the second wiring 5612, and the third wiring 561 3 and wiring 5621_1 to 5621_5 corresponding to the switch groups 5602_1 to 5602_M, respectively. Each of the wirings 5621_1 to 5621_M is connected to the first A thin film transistor 5603a, a second thin film transistor 5603b, and a third thin film transistor For example, the wiring 5621 in the Jth column is connected to three signal lines via a resistor 5603c. _J (one of the wirings 5621_1 to 5621_M) is connected to the switch group 5602 The first thin film transistor 5603a, the second thin film transistor 5603b, and and the third thin film transistor 5603c, the signal line Sj-1, the signal line Sj, the signal line S j+1 is connected to the

[0167] The first wiring 5611, the second wiring 5612, and the third wiring 5613 are each connected to a signal line. The number is entered.

[0168] It is desirable that the driver IC 5601 be formed on a single crystal substrate. The switch groups 5602_1 to 5602_M are formed on the same substrate as the pixel section. Therefore, the driver IC 5601 and the switch group 5602_1 to 5602_ It is recommended to connect to M via an FPC or similar.

[0169] Next, the operation of the signal line driver circuit shown in FIG. 15 will be described with reference to the timing chart of FIG. The timing chart in FIG. 16 is explained with reference to the timing chart when the i-th scanning line Gi is selected. Furthermore, the timing chart shows the selection period of the i-th scanning line Gi. is divided into a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Furthermore, when a scanning line of another row is selected, the signal line driving circuit of FIG. In this case, the same operation as in FIG. 16 is performed.

[0170] In the timing chart of FIG. 16, the wiring 5621_J in the Jth column is connected to the first thin-film transistor. a second thin film transistor 5603a, a second thin film transistor 5603b, and a third thin film transistor 560 When connected to signal line Sj-1, signal line Sj, and signal line Sj+1 via 3c It shows.

[0171] In the timing chart of FIG. 16, the timing at which the i-th scanning line Gi is selected, The on / off timing 5703a of the first thin film transistor 5603a, The on / off timing 5703b of the third thin film transistor 56 The on / off timing of 03c is input to 5703c and the J-th row wiring 5621_J. Signal 5721_J is shown.

[0172] The wirings 5621_1 to 5621_M are connected to the first sub-selection period T1 and the second sub-selection period T2. In the first sub-selection period T2 and the third sub-selection period T3, different video signals are input. For example, the video signal input to the wiring 5621_J in the first sub-selection period T1 is The signal is input to the signal line Sj-1 and input to the wiring 5621_J in the second sub-selection period T2. The video signal to be output is input to the signal line Sj, and the signal is output to the wiring 5621 during the third sub-selection period T3. The video signal input to the first sub-selection period is input to the signal line Sj+1. During the period T1, the second sub-selection period T2, and the third sub-selection period T3, the wiring 5621_ The video signals input to J are Data_j-1, Data_j, and Data_j+ Let's say it's 1.

[0173] As shown in FIG. 16, in the first sub-selection period T1, the first thin film transistor 5603 a is turned on, and the second thin film transistor 5603b and the third thin film transistor 5603c At this time, Data_j-1 input to the wiring 5621_J is turned off. The signal is input to the signal line Sj-1 via the transistor 5603a. Second sub-selection period T2 In this case, the second thin film transistor 5603b is turned on, and the first thin film transistor 5603a The third thin film transistor 5603c is turned off. The output Data_j is input to the signal line Sj via the second thin film transistor 5603b. In the third sub-selection period T3, the third thin film transistor 5603c is turned on, and the first The first thin film transistor 5603a and the second thin film transistor 5603b are turned off. At this time, Data_j+1 input to the wiring 5621_J is input to the third thin film transistor 56 It is input to the signal line Sj+1 via 03c.

[0174] From the above, the signal line driver circuit in FIG. 15 can achieve the following by dividing one gate selection period into three. During one gate selection period, a video signal is input from one wiring 5621 to three signal lines. Therefore, the signal line driver circuit of FIG. The number of connections between the substrate on which the display is mounted and the substrate on which the pixel section is formed is reduced to about one-third of the number of signal lines. By reducing the number of connections to about one-third, the signal line driver circuit of FIG. This can improve productivity and yield.

[0175] As shown in Figure 15, one gate selection period is divided into multiple sub-selection periods, and multiple sub-selection periods are During each selection period, a video signal is input from one line to each of multiple signal lines. As long as this can be achieved, there are no limitations on the arrangement, number, driving method, etc. of the thin film transistors.

[0176] For example, three or more signal lines are connected to one wiring in each of three or more sub-selection periods. When a video signal is input to each, a thin film transistor and a thin film transistor are controlled. However, it is necessary to divide one gate selection period into four or more sub-selection periods. Therefore, one gate selection period is divided into two or Preferably, it is divided into three sub-selection periods.

[0177] As another example, as shown in the timing chart of FIG. 17, one selection period is precharged. The first sub-selection period Tp, the first sub-selection period T1, the second sub-selection period T2, and the third selection period T3 are Furthermore, in the timing chart of FIG. 17, the scanning line Gi of the i-th row is selected. the timing at which the first thin film transistor 5603a is turned on and off; a, the on / off timing 5803b of the second thin film transistor 5603b, The on / off timing 5803c of the membrane transistor 5603c and the J-th column wiring 562 17 shows the signal 5821_J input to the precharge During the period Tp, the first thin film transistor 5603a and the second thin film transistor 5603 At this time, the input to the wiring 5621_J is turned on. The input precharge voltage Vp is applied to the first thin film transistor 5603a, the second thin film transistor 5603b, and the and the signal line Sj- 1, signal line Sj, and signal line Sj+1. The thin film transistor 5603a is turned on, and the second thin film transistor 5603b and the third thin film transistor At this time, the membrane transistor 5603c is turned off. a_j-1 is input to the signal line Sj-1 via the first thin film transistor 5603a. In the second sub-selection period T2, the second thin film transistor 5603b is turned on, and the first thin film transistor The third thin film transistor 5603a and the third thin film transistor 5603c are turned off. Data_j input to the wiring 5621_J is input to the second thin film transistor 5603b. During the third sub-selection period T3, the third thin film transistor 5603c is turned on, and the first thin film transistor 5603a and the second thin film transistor 5 At this time, Data_j+1 input to the wiring 5621_J is The signal is input to the signal line Sj+1 via the third thin film transistor 5603c.

[0178] From the above, the signal line driver circuit of FIG. 15 to which the timing chart of FIG. 17 is applied By providing a precharge selection period before the block selection period, the signal lines can be precharged. This allows for high-speed writing of video signals to the pixels. 16 are denoted by the same reference numerals, and the same parts or similar functions are shown. A detailed description of the portion having the symbol will be omitted.

[0179] The configuration of the scanning line driving circuit will be described. The scanning line driving circuit includes a shift register, a buffer, and a In some cases, a level shifter may be included. In the circuit, a clock signal (CLK) and a start pulse signal (SP) are input to the shift register. ) is input, the selection signal is generated. The generated selection signal is The signal is buffered and amplified in the scanning line and then supplied to the corresponding scanning line. The gate electrodes of the transistors are connected. Since they must all be turned on at the same time, the buffer must be able to pass a large current. It is used.

[0180] One form of a shift register used as part of a scanning line driving circuit will be explained with reference to FIGS. 18 and 19. I will explain.

[0181] The circuit configuration of the shift register is shown in Figure 18. The shift register shown in Figure 18 is a flip-flop. It consists of multiple flip-flops 5701_1 to 5701_n. A first clock signal, a second clock signal, a start pulse signal, and a reset signal are input. It works as it is.

[0182] The connection relationship of the shift register in Fig. 18 will be explained. The shift register in Fig. 18 has i-stage Flip-flop 5701_i (flip-flop 5701_1~5701_n) In either case, the first wiring 5501 shown in FIG. 19 is connected to the seventh wiring 5717_i-1. 19 is connected to the seventh wiring 5717_i+1. 19 is connected to the seventh wiring 5717_i, and The sixth wiring 5506 is connected to the fifth wiring 5715 .

[0183] In addition, the fourth wiring 5504 shown in FIG. 19 is the second wiring in the odd-numbered flip-flops. 5712, and in the even-numbered flip-flops, it is connected to the third wiring 5713. The fifth wiring 5505 shown in FIG.

[0184] However, the first wiring 5501 shown in FIG. 19 of the first-stage flip-flop 5701_1 is 19 of the n-th stage flip-flop 5701_n. The second wiring 5502 is connected to the sixth wiring 5716 .

[0185] The first wiring 5711, the second wiring 5712, the third wiring 5713, and the sixth wiring 57 16 can be called the first signal line, the second signal line, the third signal line, and the fourth signal line, respectively. Furthermore, the fourth wiring 5714 and the fifth wiring 5715 are respectively connected to the first power supply line and the This may also be called the power line 2.

[0186] Next, the details of the flip-flop shown in FIG. 18 are shown in FIG. 19. The flip-flop includes a first thin film transistor 5571, a second thin film transistor 5572, A third thin film transistor 5573, a fourth thin film transistor 5574, a fifth thin film transistor a sixth thin film transistor 5575, a sixth thin film transistor 5576, a seventh thin film transistor 5577, and and an eighth thin film transistor 5578. A second thin film transistor 5572, a third thin film transistor 5573, a fourth thin film transistor a fifth thin film transistor 5574, a fifth thin film transistor 5575, a sixth thin film transistor 5576, The seventh thin film transistor 5577 and the eighth thin film transistor 5578 are n-channel A transistor in which the gate-source voltage (Vgs) exceeds the threshold voltage (Vth) When this occurs, the device is in a conductive state.

[0187] Next, the connection configuration of the flip-flop shown in FIG. 19 will be described below.

[0188] A first electrode (either a source electrode or a drain electrode) of the first thin film transistor 5571 is connected to a fourth wiring 5504, and a second electrode (source) of the first thin film transistor 5571 is connected to a The other of the source electrode and the drain electrode is connected to a third wiring 5503 .

[0189] A first electrode of the second thin film transistor 5572 is connected to the sixth wiring 5506, and A second electrode of the thin film transistor 5572 is connected to a third wiring 5503 .

[0190] A first electrode of the third thin film transistor 5573 is connected to a fifth wiring 5505. The second electrode of the thin film transistor 5573 is the gate electrode of the second thin film transistor 5572. , and the gate electrode of the third thin film transistor 5573 is connected to the fifth wiring 5505. will be done.

[0191] A first electrode of the fourth thin film transistor 5574 is connected to a sixth wiring 5506, and The second electrode of the thin film transistor 5574 is the gate electrode of the second thin film transistor 5572. , and the gate electrode of the fourth thin film transistor 5574 is connected to the first thin film transistor 5 It is connected to the gate electrode of 571.

[0192] A first electrode of the fifth thin film transistor 5575 is connected to a fifth wiring 5505. The second electrode of the thin film transistor 5575 is the gate electrode of the first thin film transistor 5571. , and the gate electrode of the fifth thin film transistor 5575 is connected to the first wiring 5501. will be done.

[0193] A first electrode of the sixth thin film transistor 5576 is connected to the sixth wiring 5506. The second electrode of the thin film transistor 5576 is the gate electrode of the first thin film transistor 5571. , and the gate electrode of the sixth thin film transistor 5576 is connected to the second thin film transistor 5 It is connected to the gate electrode of 572.

[0194] A first electrode of the seventh thin film transistor 5577 is connected to the sixth wiring 5506. The second electrode of the thin film transistor 5577 is the gate electrode of the first thin film transistor 5571. , and the gate electrode of the seventh thin film transistor 5577 is connected to the second wiring 5502. A first electrode of the eighth thin film transistor 5578 is connected to the sixth wiring 5506. The second electrode of the eighth thin film transistor 5578 is connected to the gate of the second thin film transistor 5572. The gate electrode of the eighth thin film transistor 5578 is connected to the first wiring 550. Connected to 1.

[0195] The gate electrode of the first thin film transistor 5571 and the gate electrode of the fourth thin film transistor 5574 the gate electrode of the fifth thin film transistor 5575, the second electrode of the sixth thin film transistor The connection point of the second electrode of the seventh thin film transistor 5576 and the second electrode of the seventh thin film transistor 5577 is Further, the gate electrode of the second thin film transistor 5572, the gate electrode of the third thin film transistor 5573, and the gate electrode of the third thin film transistor 5574 are connected to the gate electrode of the second thin film transistor 5575. a second electrode of the fourth thin film transistor 5573; a second electrode of the fourth thin film transistor 5574; The gate electrode of the sixth thin film transistor 5576 and the gate electrode of the eighth thin film transistor 5578 The connection point of the two electrodes is designated as node 5544.

[0196] The first wiring 5501, the second wiring 5502, the third wiring 5503 and the fourth wiring 5504 are 504 are referred to as the first signal line, the second signal line, the third signal line, and the fourth signal line, respectively. Furthermore, the fifth wiring 5505 may be connected to a first power supply line, and the sixth wiring 5506 may be connected to a second power supply line. It can also be called a line.

[0197] In addition, the signal line driver circuit and the scanning line driver circuit are not limited to the n-channel TFTs shown in Embodiment 1. The n-channel TFT shown in Embodiment 1 can also be manufactured by Because of the high mobility, it is possible to increase the driving frequency of the driving circuit. The n-channel TFT shown in form 1 has a source region made of an In-Ga-Zn-O non-single crystal film. Or, the drain region reduces the parasitic capacitance, so the frequency characteristics (called f characteristics) For example, the scanning line driver circuit using the n-channel TFT shown in Embodiment 1 has high speed. This allows for faster frame rates and the insertion of black screens. It is also possible to realize things that can be realized.

[0198] Furthermore, the channel width of the transistor of the scanning line driving circuit can be increased, and multiple scanning lines can be formed. By arranging the drive circuit, it is possible to achieve an even higher frame frequency. When multiple scanning line driving circuits are arranged, the scanning line driving circuits for driving the even-numbered scanning lines are The circuit for driving the odd-numbered scanning lines is placed on one side, and the scanning line driving circuit for driving the odd-numbered scanning lines is placed on the other side. By placing multiple If signals are output to the same scanning line by the scanning line driving circuit, it is advantageous for increasing the size of the display device. do.

[0199] In addition, when an active matrix light-emitting display device, which is an example of a semiconductor device, is manufactured, At least one pixel is provided with a plurality of thin film transistors, so that multiple scanning line driving circuits are required. An example of a block diagram of an active matrix light emitting display device is shown in FIG. 4(B).

[0200] The light-emitting display device shown in FIG. 14B has a plurality of pixels each having a display element over a substrate 5400. A pixel portion 5401 for selecting each pixel, a first scanning line driver circuit 5402 for selecting each pixel, and a second scanning line driver circuit 5403 for selecting each pixel. A driver circuit 5404 and a signal line driver circuit 5405 for controlling the input of a video signal to a selected pixel 403 and

[0201] In the case where a video signal input to a pixel of the light-emitting display device shown in FIG. 14(B) is in a digital format, When a pixel is turned on, it emits light or does not emit light by switching the transistor on or off. Therefore, gray scale display can be performed using area gray scale or time gray scale. The stacked gray scale method divides one pixel into multiple sub-pixels, and each sub-pixel is independently driven based on a video signal. The time gray scale method is a driving method that displays gray scales by moving the pixel. This is a driving method that displays gradation by controlling the period during which the light is turned on.

[0202] Light-emitting elements have a higher response speed than liquid crystal elements, making them more suitable for time gray scale modulation than liquid crystal elements. Specifically, when displaying using the time gray scale method, one frame period is divided into multiple subframes. Then, in accordance with the video signal, the light emitting element of the pixel is By dividing the period into multiple subframes, The total length of the period during which pixels actually emit light during one frame is controlled by the video signal. It is possible to control the brightness and display gradation.

[0203] In the light-emitting display device shown in FIG. 14B, two switching TFTs are provided for one pixel. When the first scanning line is connected to the gate of one of the switching TFTs, The signal to be output is generated by the first scanning line driver circuit 5402, and the gate of the other switching TFT is A signal to be input to the second scanning line, which is a light source wiring, is generated by a second scanning line driver circuit 5404. The example shows a signal input to the first scanning line and a signal input to the second scanning line. The signal and the signal may be generated by one scanning line driving circuit. The operation of the switching element is controlled by the number of switching TFTs that the pixel has. In this case, a plurality of scanning lines may be provided for each pixel. The signals input to the lines may all be generated by one scanning line driver circuit, or may be generated by a plurality of scanning lines. It may be generated by the drive circuit.

[0204] In addition, in the light-emitting display device, the driver circuit may be configured with an n-channel TFT. A part of the driver circuit can be formed on the same substrate as the thin film transistor of the pixel portion. In addition, the signal line driver circuit and the scanning line driver circuit may be formed by using the n-channel TFTs shown in Embodiments 1 to 3. It is also possible to produce it using only FT.

[0205] The above-mentioned driving circuit is not limited to liquid crystal display devices and light-emitting display devices, but may also be used in It may also be used in electronic paper, which uses electrically connected elements to drive electronic ink. Electronic paper is also called an electrophoretic display (electrophoretic display), and has the same properties as paper. The advantages are readability, low power consumption compared to other display devices, and the possibility of making them thin and light. It has points.

[0206] Electrophoretic displays can be of various forms, but the first particle has a positive charge. A microcapsule containing a negatively charged particle and a second particle is immersed in a solvent or solute. By applying an electric field to the microcapsules, The particles in the capsule are moved in opposite directions to each other, and only the color of the particles that have gathered on one side is displayed. The first particles or the second particles contain a dye, and in the absence of an electric field, The first particle and the second particle have different colors (colorless). (including

[0207] Thus, electrophoretic displays allow materials with high dielectric constants to migrate to areas of high electric field. This is a display that utilizes the so-called dielectrophoretic effect. Electrophoretic displays do not require polarizing plates or opposing substrates, which are necessary for display devices, and are half the thickness and weight. Decrease.

[0208] The microcapsules dispersed in a solvent are called electronic ink. The electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. Color display is also possible by using color filters or particles containing pigments.

[0209] Furthermore, the microphone is appropriately placed on the active matrix substrate so as to be sandwiched between two electrodes. By arranging multiple microcapsules, an active matrix display device is completed. By applying an electric field to the cell, display can be performed. An active matrix substrate obtained by using transistors can be used.

[0210] The first particles and the second particles in the microcapsules may be made of a conductive material, an insulating material, Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A material selected from magnetochromic materials, magnetophoretic materials, or a composite material thereof Just use it.

[0211] Through the above steps, a highly reliable display device can be manufactured as a semiconductor device.

[0212] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0213] (Embodiment 5) A thin film transistor is manufactured, and the thin film transistor is used in a pixel portion and further in a driver circuit. A semiconductor device (also called a display device) having a display function can be manufactured. The transistor and part or the whole of the driver circuit are formed on the same substrate as the pixel section, On-panel formation is possible.

[0214] The display device includes a display element. The display element includes a liquid crystal element (also called a liquid crystal display element), a light-emitting element, A light-emitting element (also called a light-emitting display element) can be used. This category includes elements whose brightness is controlled by the light emitted from the light source, specifically inorganic EL (Electroluminescent) Also, electronic inks and other electronic devices are also included. A display medium whose contrast changes due to mechanical action can also be applied.

[0215] The display device also includes a panel in which a display element is sealed, and a controller for the panel. Furthermore, the display device is manufactured by a method for manufacturing the display device. In the process, the element substrate corresponds to one form before the display element is completed, and the element substrate is Each of the plurality of pixels includes a means for supplying a current to the display element. The pixel electrode of the display element may be formed only, or the conductive film that becomes the pixel electrode may be formed. may be in a state after the film is formed and before the pixel electrode is formed by etching, All forms apply.

[0216] In this specification, the term "display device" refers to an image display device, a display device, or an optical device. It also refers to connectors, such as FPC (Flexible Printed Circuit) integrated circuit) or TAB (Tape Automated Bon ding) tape or TCP (Tape Carrier Package) Modules with printed wiring boards attached to the end of TAB tape or TCP or the display element is mounted on an IC (integrated circuit) by the COG (Chip On Glass) method. The display device also includes all modules in which the display device (circuit) is directly mounted.

[0217] In this embodiment mode, the appearance and cross section of a liquid crystal display panel, which is one mode of a semiconductor device, will be described. 22 shows an embodiment formed on a first substrate 4001. Highly reliable thin film transistors containing the In-Ga-Zn-O non-single crystal film shown in 1 as a semiconductor layer The transistors 4010 and 4011 and the liquid crystal element 4013 are sandwiched between the second substrate 4006. 22(A) is a top view of the panel sealed with sealing material 4005, and FIG. 22(B) is a top view of the panel sealed with sealing material 4005. 1) This corresponds to the cross-sectional view at MN in (A2).

[0218] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this way, a sealing material 4005 is provided. A second substrate 4006 is provided on the path 4004. The line driver circuit 4004 is made up of a first substrate 4001, a sealing material 4005, and a second substrate 4006. The first substrate 4001 is sealed together with the liquid crystal layer 4008. In a region different from the region surrounded by the material 4005, a single crystal is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor film or a polycrystalline semiconductor film is mounted.

[0219] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, Wire bonding or TAB method can be used. is an example of mounting a signal line driver circuit 4003 by the COG method, and FIG. 22(A2) is This is an example in which a signal line driver circuit 4003 is mounted by the TAB method.

[0220] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. 22B, the thin film transistor included in the pixel portion 4002 is A transistor 4010 and a thin film transistor 4011 included in the scanning line driver circuit 4004 Insulating layers 4020 and 4022 are formed on the thin film transistors 4010 and 4011. 1 is provided.

[0221] The thin film transistors 4010 and 4011 are made of an In-Ga-Zn-O based non-single crystal film as a semiconductor layer. The highly reliable thin film transistor described in Embodiment 3 can be applied. In addition, the thin film transistor described in Embodiment 1 or 2 may be applied. In this embodiment, the thin film transistors 4010 and 4011 are n-channel thin film transistors. be.

[0222] The pixel electrode layer 4030 of the liquid crystal element 4013 is connected to the thin film transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is electrically connected to the second substrate 40. 06. The pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 are The overlapping portion corresponds to the liquid crystal element 4013. The electrode layer 4031 is provided with insulating layers 4032 and 4033 which function as alignment films. A liquid crystal layer 4008 is sandwiched between insulating layers 4032 and 4033 .

[0223] The first substrate 4001 and the second substrate 4006 may be made of glass or metal (typically, stainless steel). Stainless steel, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film, polyester film Alternatively, acrylic resin film can be used. Aluminum foil can also be used as a PVF film. A sheet sandwiched between films or polyester films can also be used.

[0224] 4035 is a columnar spacer obtained by selectively etching the insulating film. To control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 A spherical spacer may be used. is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. The common connection portion is used to connect the opposing electrode layer 40 via conductive particles disposed between the pair of substrates. The conductive particles can electrically connect the sealing material 40 to the common potential line. Included in 05.

[0225] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so the temperature range needs to be improved. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent has a response speed of 10 μs to It is optically isotropic, requiring no alignment treatment, and has little viewing angle dependency. stomach.

[0226] Although this embodiment is an example of a transmissive liquid crystal display device, a transflective liquid crystal display device may also be used. It can also be applied to a liquid crystal display device.

[0227] In the liquid crystal display device of this embodiment, a polarizing plate is provided on the outer side (viewing side) of the substrate, and a polarizing plate is provided on the inner side. An example is shown in which a colored layer and an electrode layer used for a display element are provided in this order, but the polarizing plate is provided on the inner side of the substrate. The laminated structure of the polarizing plate and the colored layer is not limited to that of the present embodiment. The coloring layer may be appropriately selected depending on the material and manufacturing process conditions of the coloring layer. A light-shielding film that functions as a light-shielding film may be provided.

[0228] In this embodiment, in order to reduce the surface unevenness of the thin film transistor, In order to improve the reliability of the thin film transistor obtained in the third embodiment, a protective film and The insulating layer 4020 and the insulating layer 4021 are covered with insulating layers that function as planarizing insulating films. The protective film also prevents contamination by organic matter, metals, water vapor, and other polluting impurities floating in the air. The protective film is formed by sputtering. Silicon oxide film, silicon nitride film, silicon oxynitride film, silicon nitride oxide film, aluminum oxide film, nitride A single layer or multilayer of an aluminum film, an aluminum oxynitride film, or an aluminum nitride oxide film In this embodiment, an example in which the protective film is formed by sputtering is shown. There is no limitation and various methods may be used for forming the layer.

[0229] Here, an insulating layer 4020 having a stacked structure is formed as a protective film. As the first layer of the silicon dioxide film, a silicon dioxide film is formed by sputtering. By using the above, it is possible to prevent hillocks in the aluminum film used as the source electrode layer and the drain electrode layer. It is effective in stopping.

[0230] An insulating layer is formed as the second layer of the protective film. The second layer is a silicon nitride film formed by sputtering. When the semiconductor is in a low temperature, mobile ions such as sodium penetrate into the semiconductor region and change the electrical characteristics of the TFT. This can prevent the problem from occurring.

[0231] After forming the protective film, the semiconductor layer may be annealed (at 300°C to 400°C). stomach.

[0232] An insulating layer 4021 is formed as a planarization insulating film. Heat-resistant organic compounds such as amide, acrylic, benzocyclobutene, polyamide, and epoxy. In addition to the above organic materials, low-k materials can also be used. , siloxane resin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. In addition, by stacking multiple insulating films made of these materials, it is possible to obtain an insulating layer. 4021 may be formed.

[0233] Siloxane-based resin is a Si-OS compound formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, an organic group having a fluoro group may be used. That's fine.

[0234] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, an SOG method, or the like, depending on the material. , spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife When the insulating layer 4021 is formed using a material liquid, The semiconductor layer may be annealed (at 300°C to 400°C) at the same time as the step of annealing. By combining the firing process of the edge layer 4021 with the annealing of the semiconductor layer, semiconductor devices can be efficiently manufactured. It becomes possible to do this.

[0235] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), Translucent materials such as indium zinc oxide and indium tin oxide doped with silicon oxide A conductive material can be used.

[0236] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of a conductive polymer (conductive polymer The conductive composition can be used to form the conductive film. The pixel electrode has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 550 nm. It is preferable that the resistance of the conductive polymer contained in the conductive composition is 70% or more. It is preferable that the electrical conductivity is 0.1 Ω·cm or less.

[0237] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0238] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 4 Various signals and potentials applied to 002 are supplied from FPC4018.

[0239] In this embodiment, the connection terminal electrode 4015 is connected to the pixel electrode layer 40 of the liquid crystal element 4013. The terminal electrode 4016 is formed from the same conductive film as the thin film transistors 4010 and 40 The connection terminal 11 is formed of the same conductive film as the source electrode layer and the drain electrode layer. The electrode 4015 and the terminal electrode 4016 are formed on the n+ layer 4025 and the semiconductor layer 4026. It is being done.

[0240] The connection terminal electrode 4015 is connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019. are electrically connected.

[0241] In FIG. 22, a signal line driver circuit 4003 is separately formed and mounted on a first substrate 4001. However, this embodiment is not limited to this configuration. Alternatively, a part of the signal line driver circuit or a part of the scanning line driver circuit may be formed separately and mounted. Alternatively, the circuit board may be formed separately and mounted.

[0242] FIG. 23 shows a TFT substrate 26 fabricated by the method for fabricating a semiconductor device disclosed in this specification. 1 shows an example of a liquid crystal display module constructed as a semiconductor device using the semiconductor device.

[0243] FIG. 23 shows an example of a liquid crystal display module, in which a TFT substrate 2600 and an opposing substrate 2601 are connected. The substrate is fixed by a bonding material 2602, and a pixel portion 2603 including a TFT and the like and a liquid crystal layer are disposed between the substrate and the bonding material 2602. A display element 2604 and a colored layer 2605 are provided to form a display area. is required for color display, and in the case of the RGB method, it corresponds to each color of red, green, and blue. A colored layer is provided corresponding to each pixel. On the outside, a polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are arranged. It is composed of a cathode ray tube 2610 and a reflector 2611, and a circuit board 2612 is a flexible wiring board. The wiring board 2609 is connected to the wiring circuit section 2608 of the TFT substrate 2600, and the controller It also incorporates external circuits such as a polarizing plate and a power supply circuit. The layers may be laminated with a retardation film interposed therebetween.

[0244] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-Plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) Switching mode, MVA (Multi-domain Vertical A alignment) mode, PVA(Patterned Vertical Alignment) mode nment), ASM(Axially Symmetric aligned Mic) ro-cell) mode, OCB(Optical Compensated Bire) fringence mode, FLC (Ferroelectric Liquid Crystal Crystal mode, AFLC (AntiFerroelectric Liquid Crystal) can be used.

[0245] By the above steps, a highly reliable liquid crystal display panel can be manufactured as a semiconductor device. do.

[0246] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0247] (Embodiment 6) In this embodiment, an example of electronic paper will be shown as a semiconductor device.

[0248] Figure 13 shows an active matrix electronic paper as an example of a semiconductor device. The thin film transistor 581 used in the device is the thin film transistor shown in Embodiment 3. It can be fabricated in the same way as a photodiode, and is a reliable device that contains an In-Ga-Zn-O based non-single crystal film as a semiconductor layer. In addition, the thin film transistor shown in Embodiment 1 or 2 The thin film transistor 581 of this embodiment can also be applied.

[0249] The electronic paper in Figure 13 is an example of a display device that uses the twisting ball display method. The spherical display method is an electrode layer that uses spherical particles painted in black and white as display elements. A potential difference is applied between the first electrode layer and the second electrode layer. This is a method of displaying by controlling the orientation of spherical particles by generating a magnetic field.

[0250] The thin film transistor 581 provided on the substrate 580 is a thin film transistor of a bottom gate structure. The first electrode layer 587 and the insulating layer 58 are connected by a source electrode layer or a drain electrode layer. 3. The insulating layer 584 and the insulating layer 585 are in contact with each other through openings formed therein and are electrically connected. Between the first electrode layer 587 and the second electrode layer 588, there are a black region 590a and a white region 590b. 0b and a spherical particle 589 having a cavity 594 filled with liquid therearound. The spherical particles 589 are filled with a filler 595 such as resin (see FIG. 13). In this embodiment, the first electrode layer 587 corresponds to a pixel electrode, and the second electrode The layer 588 corresponds to a common electrode. The second electrode layer 588 provided on the substrate 596 is a thin film transistor. It is electrically connected to a common potential line provided on the same substrate as the transistor 581. The second electrode layer 588 is connected to the second electrode layer 588 via conductive particles disposed between the pair of substrates 580. It can be electrically connected to a common potential line.

[0251] Also, instead of the twist ball, an electrophoretic element can be used. and a diameter of 10 μm to 20 μm that contains positively charged white particles and negatively charged black particles. Microcapsules of about 0 μm in size are used. When an electric field is applied by the first and second electrode layers, the microcapsules turn white. White particles and black particles move in opposite directions, allowing the display to be white or black. The display element that applies this principle is an electrophoretic display element, which is generally called electronic paper. Electrophoretic display elements have a higher reflectivity than liquid crystal display elements, so auxiliary lights are not required. It also consumes little power and the display can be seen even in dimly lit places. Even if power is not supplied to the display unit, the image that has been displayed can be retained. Therefore, the semiconductor device with a display function (simply a display device, or a device equipped with a display device) is The ability to preserve the displayed image even when the device (also known as a semiconductor device) is moved away This becomes possible.

[0252] Through the above steps, electronic paper with high reliability as a semiconductor device can be manufactured. .

[0253] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0254] (Embodiment 7) In this embodiment mode, a light-emitting display device is shown as an example of a semiconductor device. Here, a light-emitting element that uses electroluminescence is used as the element. Light-emitting devices that utilize electroluminescence are either organic or inorganic compounds that emit light. Generally, the former is called an organic EL element and the latter is called an inorganic EL element. It's been discovered.

[0255] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into the layers containing the light-emitting organic compounds, causing a current to flow. The recombination of the electrons and holes creates an excited state in the light-emitting organic compound. The excited state is then converted to the ground state, at which point light is emitted. Such a light-emitting element is called a current-excited light-emitting element.

[0256] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor interaction that utilizes the donor and acceptor levels. Thin-film inorganic EL devices sandwich the light-emitting layer between dielectric layers. Furthermore, this structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0257] FIG. 20 shows an example of a pixel configuration to which digital time gray scale driving can be applied as an example of a semiconductor device. This is a diagram.

[0258] The configuration and operation of a pixel to which digital time gray scale driving can be applied will be described. The n-type semiconductor uses an oxide semiconductor layer (In-Ga-Zn-O based non-single crystal film) in the channel formation region. 1 shows an example in which two channel-type transistors are used in one pixel.

[0259] The pixel 6400 includes a switching transistor 6401, a driving transistor 6402, It has a light emitting element 6404 and a capacitor element 6403. 01 has a gate connected to a scanning line 6406 and a first electrode (one of the source and drain electrodes) The first electrode (the other of the source electrode and the drain electrode) is connected to a signal line 6405, and the second electrode (the other of the source electrode and the drain electrode) is connected to a drive The driving transistor 6402 is connected to the gate of the driving transistor 6402. The gate is connected to a power supply line 6407 via a capacitor element 6403, and the first electrode is connected to a power supply line 640 7, and the second electrode is connected to the first electrode (pixel electrode) of the light emitting element 6404. The second electrode of the light emitting element 6404 corresponds to a common electrode 6408. It is electrically connected to a common potential line formed on the substrate.

[0260] A low power supply potential is set to the second electrode (common electrode 6408) of the light emitting element 6404. The low power supply potential is a low power supply potential with respect to the high power supply potential set to the power supply line 6407. Potential < High power supply potential. For example, GND, 0V, etc. are set as low power supply potential. The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404. Then, in order to make the light emitting element 6404 emit light by passing a current through the light emitting element 6404, a high power supply potential and the low power supply potential is set to be equal to or greater than the forward threshold voltage of the light emitting element 6404. Each potential is set.

[0261] The capacitor element 6403 is omitted by substituting the gate capacitance of the driving transistor 6402. The gate capacitance of the driving transistor 6402 is determined by the channel region A capacitance may be formed between the gate electrode and the transistor.

[0262] In the case of a voltage input voltage driving method, the gate of the driving transistor 6402 is connected to The driving transistor 6402 is either fully on or off. A video signal is input, that is, the driving transistor 6402 is operated in a linear region. The driving transistor 6402 is operated in a linear region, so that the voltage of the driving transistor 6402 is higher than the voltage of the power supply line 6407. A high voltage is applied to the gate of the driving transistor 6402. The signal line 6405 is connected to A voltage equal to or greater than (power supply line voltage+Vth of the driving transistor 6402) is applied.

[0263] Furthermore, when analog grayscale driving is performed instead of digital time grayscale driving, the input of the signal is different. By doing so, the same pixel configuration as in FIG. 20 can be used.

[0264] When analog gradation driving is performed, a light emitting element 6404 is connected to the gate of a driving transistor 6402. A voltage equal to or greater than the forward voltage of the light emitting element 64 and the Vth of the driving transistor 6402 is applied. The forward voltage in 04 refers to the voltage required to achieve the desired brightness, and It should be noted that the driving transistor 6402 is designed to operate in the saturation region. By inputting an optical signal, a current can be passed through the light emitting element 6404. In order to operate the transistor 6402 in the saturation region, the potential of the power supply line 6407 is The potential of the light emitting element is made higher than the gate potential of the capacitor 6402. A current corresponding to a video signal is passed through 6404, enabling analog gradation driving.

[0265] Note that the pixel configuration shown in Fig. 20 is not limited to this. For example, A switch, a resistor, a capacitor, a transistor, a logic circuit, or the like may be added.

[0266] Next, the configuration of the light emitting element will be described with reference to FIG. 21. Here, the driving TFT is The cross-sectional structure of a pixel will be explained using the example of the type shown in Figures 21(A), (B), and (C). The TFTs 7001, 7011, and 7021, which are driving TFTs used in semiconductor devices, are actually It can be fabricated in the same manner as the thin film transistor shown in the third embodiment, and is an In-Ga-Zn-O based non-single crystal The thin film transistor according to the first embodiment or the second embodiment includes a semiconductor layer. The thin film transistors shown in Embodiment 2 are applied as TFTs 7001, 7011, and 7021. You can also do this.

[0267] The light emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, a thin film transistor and a light emitting element are formed on the substrate, and light is taken from the surface opposite to the substrate. Top emission, bottom emission, and top emission. There are light-emitting elements with a double-sided emission structure that emits light from the side, and the pixel configuration is It can also be applied to optical elements.

[0268] A light emitting element with a top emission structure will be described with reference to FIG.

[0269] In FIG. 21(A), a TFT 7001 which is a driving TFT is an n-type, and a light emitting element 7002 emits light. FIG. 21(A) shows a cross-sectional view of a pixel when incident light exits the anode 7005 side. A cathode 7003 of the light emitting element 7002 and a TFT 7001 which is a driving TFT are electrically connected. A light-emitting layer 7004 and an anode 7005 are stacked in this order on a cathode 7003. 7003 uses various materials as long as they have a small work function and are conductive films that reflect light. For example, Ca, Al, CaF, MgAg, AlLi, etc. are preferable. The light-emitting layer 7004 may be composed of a single layer or a plurality of layers stacked together. When it is composed of multiple layers, the electron injection layer is formed on the cathode 7003. The electron transport layer, the light emitting layer, the hole transport layer, and the hole injection layer are laminated in this order. It is not necessary to provide all of the anodes. The anode 7005 is made of a conductive material that transmits light. For example, indium oxide containing tungsten oxide, indium oxide containing tungsten oxide Indium zinc oxide, indium oxide with titanium oxide, indium tin oxide with titanium oxide oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, oxidized silicon dioxide, A light-transmitting conductive film such as indium tin oxide to which indium is added may also be used.

[0270] The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 is the light-emitting element 7002. In the case of the pixel shown in FIG. 21(A), the light emitted from the light emitting element 7002 is The light is emitted toward the anode 7005 as shown by the mark.

[0271] Next, a light emitting element with a bottom emission structure will be described with reference to FIG. When 011 is n-type and light emitted from the light emitting element 7012 is emitted to the cathode 7013 side, 21(B) shows a cross-sectional view of the pixel. A cathode 7013 of a light-emitting element 7012 is formed on a light-transmitting conductive film 7017. On the cathode 7013, a light-emitting layer 7014 and an anode 7015 are laminated in this order. When the 015 has a light-transmitting property, a shielding layer for reflecting or blocking light is applied to cover the anode. The cathode 7013 may have a film 7016 formed thereon, as in the case of FIG. Various conductive materials with small electrical conductivity can be used. The thickness is set to a level that allows light to pass through (preferably, about 5 nm to 30 nm). For example, a 20 nm film An aluminum film having a thickness of 700 nm can be used as the cathode 7013. 014 is composed of a single layer, as in FIG. 21(A), but multiple layers are laminated. The anode 7015 does not need to transmit light, but as shown in FIG. As with 21(A), it can be formed using a light-transmitting conductive material. The shielding film 7016 may be made of, for example, a metal that reflects light, but is not limited to a metal film. For example, a resin containing a black pigment may be used.

[0272] The region where the light-emitting layer 7014 is sandwiched between the cathode 7013 and the anode 7015 is the light-emitting element 7012. In the case of the pixel shown in FIG. 21B, light emitted from the light-emitting element 7012 corresponds to The light is emitted toward the cathode 7013 as shown by the arrow.

[0273] Next, a light emitting element with a dual emission structure will be described with reference to FIG. Then, on the conductive film 7027 having light-transmitting properties and electrically connected to the driving TFT 7021, A cathode 7023 of the light-emitting element 7022 is formed as a film. A light-emitting layer 7024 is formed on the cathode 7023. The cathode 7023 is laminated in the same manner as in FIG. Various conductive materials with small electrical conductivity can be used. For example, Al having a thickness of 20 nm is used as the cathode 7023. The light-emitting layer 7024 can be formed of a single layer, as in FIG. The anode 70 may be formed by laminating a plurality of layers. 25 is formed using a light-transmitting conductive material, similar to that shown in FIG. It is possible.

[0274] The overlapping portion of the cathode 7023, the light-emitting layer 7024, and the anode 7025 is the light-emitting element 70. In the case of the pixel shown in FIG. 21C, the light emitted from the light emitting element 7022 is emitted to both the anode 7025 side and the cathode 7023 side as shown by the arrows.

[0275] Although organic EL elements have been described as light-emitting elements here, inorganic EL elements can also be used as light-emitting elements. It is also possible to provide an L element.

[0276] In this embodiment, a thin film transistor (driving TFT) that controls driving of a light emitting element is Although an example in which the light emitting element is electrically connected has been shown, it is possible to prevent a current from flowing between the driving TFT and the light emitting element. A control TFT may be connected.

[0277] Note that the semiconductor device described in this embodiment mode is not limited to the configuration shown in FIG. Various modifications are possible based on the technical ideas disclosed in this specification.

[0278] Next, the appearance and structure of a light-emitting display panel (also referred to as a light-emitting panel), which is one mode of a semiconductor device, will be described. The cross section will be explained with reference to FIG. 24. FIG. 24 shows a thin film transistor formed on a first substrate. The upper surface of the panel is formed by sealing the transistor and the light-emitting element with a sealing material between the second substrate and the panel. 24(B) corresponds to a cross-sectional view taken along line HI in FIG. 24(A).

[0279] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. 3b and the scanning line driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealing material 4505, and a second substrate 4506. The seal is sealed together with the filler 4507 by the sealant. Highly airtight protective film with little outgassing (lamination film, UV curable resin film) It is preferable to package (enclose) the product in a protective film (such as a film) or a cover material.

[0280] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b have a plurality of thin film transistors. In FIG. 24B, a thin film transistor 4510 included in a pixel portion 4502 and a signal 45 shows an example of a thin film transistor 4509 included in a line driver circuit 4503a.

[0281] The thin film transistors 4509 and 4510 are made of In-Ga-Zn-O based non-single crystal films as semiconductor layers. The highly reliable thin film transistor described in Embodiment 3 can be applied. In addition, the thin film transistor described in Embodiment 1 or 2 may be applied. In this configuration, the thin film transistors 4509 and 4510 are n-channel thin film transistors. be.

[0282] Further, 4511 corresponds to a light-emitting element, and a first electrode which is a pixel electrode of the light-emitting element 4511 The layer 4517 is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. The light-emitting element 4511 is configured by a first electrode layer 4517, an electroluminescent layer The second electrode layer 4512 and the second electrode layer 4513 are stacked in a stacked structure. The direction of the light emitting element 4511 is adjusted according to the direction of the light extracted from the light emitting element 4511. The configuration can be changed as appropriate.

[0283] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or organic polysiloxane. In particular, a photosensitive material is used to form an opening on the first electrode layer 4517, and the sidewall of the opening It is preferable to form the inclined surface so that the inclined surface has a continuous curvature.

[0284] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers stacked. It doesn't matter whether it's done or not.

[0285] The second electrode layer is formed to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4511. A protective film may be formed on the partition wall 4513 and the partition wall 4520. The protective film may be a silicon nitride film, A silicon nitride oxide film, a DLC film, or the like can be formed.

[0286] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are transmitted through the FPC 4518a, 4518b, and It is supplied by b.

[0287] In this embodiment, the connection terminal electrode 4515 is connected to the first electrode layer 4 The terminal electrode 4516 is formed from the same conductive film as the thin film transistors 4509 and 517. The source electrode layer and the drain electrode layer 510 are formed from the same conductive film. The connection terminal electrode 4515 and the terminal electrode 4516 are connected to the n+ layer 4525 and the semiconductor layer 4526 is formed on top.

[0288] The connection terminal electrode 4515 is connected to the terminal of the FPC 4518a via the anisotropic conductive film 4519. are electrically connected to each other.

[0289] The second substrate is not transparent to light, and is positioned in the direction of light extraction from the light emitting element 4511. In this case, glass plates, plastic plates, polyester films or A light-transmitting material such as an acrylic film is used.

[0290] In addition to inert gases such as nitrogen and argon, filler 4507 can also be used as UV-curable resin. It can be made of oil or thermosetting resin, and PVC (polyvinyl chloride), acrylic, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV In this embodiment, nitrogen is used as the filler. The material used was

[0291] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0292] The signal line driver circuits 4503a and 4503b and the scanning line driver circuits 4504a and 4504b are A driving circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate is Alternatively, only the signal line driver circuit, or a part of the signal line driver circuit, or the scanning line driver circuit may be mounted. Only the path or only a part of the path may be separately formed and mounted. In this embodiment, the structure shown in FIG. Not limited.

[0293] Through the above steps, a highly reliable light-emitting display device (display panel) can be manufactured as a semiconductor device. It is possible.

[0294] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0295] (Embodiment 8) The semiconductor device can be used as electronic paper. It can be used in any electronic device in any field. Using the par, electronic books (e-books), posters, in-car advertisements on trains and other vehicles, The present invention can be applied to the display of various cards such as credit cards. As shown in Figures 25 and 26.

[0296] FIG. 25(A) shows a poster 2631 made of electronic paper. In the case of printed matter, the exchange of advertisements is done manually, but in the case of electronically By using sub-paper, the display of advertisements can be changed in a short time. The poster is designed to be able to send and receive information wirelessly. Good too.

[0297] FIG. 25(B) shows an advertisement 2632 inside a vehicle such as a train. In the case of paper-based printed matter, the advertisements are exchanged manually. By using electronic paper, it is possible to change the display of advertisements in a short time without requiring a lot of manpower. In addition, stable images can be obtained without display distortion. In-car advertising is transmitted wirelessly. The configuration may be such that the above can be transmitted and received.

[0298] 26 shows an example of an electronic book 2700. For example, the electronic book 2700 includes: It consists of two housings, housing 2701 and housing 2703. The body 2703 is integrated with a shaft 2711, and the opening and closing movement is performed around the shaft 2711. This configuration allows the device to operate like a paper book. This becomes:

[0299] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a sentence is displayed on the right display unit (display unit 2705 in FIG. 26) and An image can be displayed on the display unit 2707 in FIG.

[0300] 26 shows an example in which the housing 2701 is provided with an operation unit. 701 includes a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. It may also be configured to include a touch panel, a pointing device, etc. On the side, there are external connection terminals (earphone terminal, USB terminal, or AC adapter and USB A configuration including a terminal that can be connected to various cables, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to have the function of an electronic dictionary. That's fine.

[0301] The electronic book 2700 may also be configured to be able to send and receive information wirelessly. The desired book data can be purchased and downloaded from the e-book server. is also possible.

[0302] (Embodiment 9) The semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). As the electronic device, for example, a television device (television or television receivers), computer monitors, digital cameras, digital video cameras digital photo frames, mobile phones (also called mobile phones or mobile phone devices), portable Examples include game machines, mobile information terminals, sound reproduction devices, and large game machines such as pachinko machines. do.

[0303] FIG. 27(A) shows an example of a television device 9600. The display unit 9603 is incorporated in the housing 9601. In this case, the housing 9601 is supported by a stand 9605. This shows a configuration in which the above is supported.

[0304] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by the remote control operation device 9610. The channel and volume can be controlled by the 9609, and the information displayed on the display 9603 is In addition, the remote control operation device 9610 can operate the video. A display portion 9607 for displaying information output from 9610 may be provided.

[0305] The television device 9600 is configured to include a receiver, a modem, and the like. It can receive more general TV broadcasts and can also receive them via wired or wireless modems. By connecting to a communication network, it can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0306] FIG. 27B shows an example of a digital photo frame 9700. The photo frame 9700 has a display unit 9703 built into a housing 9701. The unit 9703 is capable of displaying various images, for example, images taken with a digital camera. By displaying the image data, it can function like a normal photo frame.

[0307] The Digital Photo Frame 9700 has an operation panel, external connection terminals (USB terminal, US A terminal that can be connected to various cables such as B cable, etc., and a recording medium insertion section. These components may be incorporated on the same surface as the display unit, but they may be incorporated on the side or back. It is preferable to have a recording medium for a digital photo frame as it improves the design. A memory that stores image data taken with a digital camera is inserted into the body insertion section. The image data can be captured and the captured image data can be displayed on the display portion 9703 .

[0308] The digital photo frame 9700 may also be configured to be capable of transmitting and receiving information wirelessly. It is also possible to configure the device so that desired image data can be wirelessly acquired and displayed.

[0309] FIG. 28(A) shows a portable gaming machine, which is composed of two cabinets, a cabinet 9881 and a cabinet 9891. The housing 9881 is connected to a connector 9893 so as to be openable and closable. A display unit 9883 is incorporated in the housing 9891. The portable gaming machine shown in 28(A) also includes a speaker unit 9884, a recording medium insertion unit 988 6, LED lamp 9890, input means (operation key 9885, connection terminal 9887, sensor 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, Chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration (including functions for measuring movement, smell, or infrared rays), microphone 9889) Of course, the configuration of the portable gaming machine is not limited to the above, and It is sufficient if the semiconductor device disclosed in the above is included, and other auxiliary equipment is appropriately provided. The portable gaming machine shown in FIG. 28(A) can be used to play the game data recorded on a recording medium. The function of reading out programs or data and displaying them on the display, and wireless communication with other portable gaming machines The portable gaming machine shown in FIG. 28(A) has the function of sharing information by performing the above. The functions are not limited to these, and various functions can be provided.

[0310] FIG. 28(B) shows an example of a slot machine 9900, which is a large gaming machine. The machine 9900 has a display unit 9903 built into a housing 9901. Machine 9900 also has other operating means such as a start lever and stop switch, coin It is equipped with an insertion slot, a speaker, etc. Of course, the configuration of the slot machine 9900 is The present invention is not limited to the above, and may be configured to include at least the semiconductor device disclosed in this specification. , and other auxiliary equipment may be provided as appropriate.

[0311] FIG. 29(A) shows an example of a mobile phone 1000. The mobile phone 1000 has a housing In addition to the display unit 1002 incorporated in the 1001, the operation buttons 1003 and the external connection port 10 04, speaker 1005, microphone 1006, etc.

[0312] The mobile phone 1000 shown in FIG. 29(A) displays information by touching the display unit 1002 with a finger or the like. In addition, operations such as making a phone call or sending an email can be performed using the display. This can be done by touching 1002 with a finger or the like.

[0313] The screen of the display unit 1002 has three main modes. The first is a display mode that mainly displays images. The first mode is a display mode, and the second mode is an input mode that mainly inputs information such as characters. This is a display + input mode that combines two modes: display mode and input mode.

[0314] For example, when making a call or creating an email, the display unit 1002 is used to input characters. This is the main character input mode, and you can input characters displayed on the screen. It is preferable to display a keyboard or number buttons on most of the screen of the display unit 1002. I wish.

[0315] In addition, the mobile phone 1000 may include a sensor for detecting tilt, such as a gyro or an acceleration sensor. By providing a detection device having the above configuration, the orientation of the mobile phone 1000 (portrait or landscape) can be determined and the display The screen display of the display unit 1002 can be automatically switched.

[0316] The screen mode can be switched by touching the display unit 1002 or by operating the housing 1001. This is done by operating the button 1003. Also, depending on the type of image displayed on the display unit 1002, For example, if the image signal to be displayed on the display unit is a video signal, If it is data, the display mode is switched to, and if it is text data, the input mode is switched to.

[0317] In the input mode, the optical sensor of the display unit 1002 detects a signal and displays it. If there is no input by touch operation of the part 1002 for a certain period of time, the screen mode is changed to the input mode. Alternatively, the display mode may be switched from the normal mode to the display mode.

[0318] The display unit 1002 can also function as an image sensor. By touching the palm or fingers to the sensor 02, the palm print, fingerprint, etc. can be captured and identity authentication can be performed. In addition, the display unit may be equipped with a backlight that emits near-infrared light or a sensor that emits near-infrared light. By using a scanning light source, it is also possible to capture images of finger veins, palm veins, etc.

[0319] FIG. 29B is also an example of a mobile phone. The mobile phone in FIG. 29B has a housing 9411. A display device 9410 including a display portion 9412 and an operation button 9413 is mounted on a housing 9401. An operation button 9402, an external input terminal 9403, a microphone 9404, a speaker 9405, and The communication device 9400 includes a light emitting unit 9406 that emits light when an incoming call is received, and has a display function. The display device 9410 can be attached to and detached from the communication device 9400 having a telephone function in two directions as shown by the arrows. Therefore, the display device 9410 and the communication device 9400 can be attached to each other with their short axes facing each other. The display device 9410 and the communication device 9400 can be attached to each other with their long axes facing each other. When only the function is required, the display device 9410 is removed from the communication device 9400. The communication device 9400 and the display device 9410 can be used independently. Images or input information can be sent and received via wired or wireless communication, and each can be recharged with a battery. Having Terry.

Claims

1. a pixel portion including a plurality of pixels arranged in a matrix; Each of the plurality of pixels is A light-emitting element; a first transistor electrically connected to the light-emitting element and functioning as a driving transistor; a second transistor electrically connected to a gate of the first transistor and having a function as a switching transistor; a channel formation region of the first transistor and a channel formation region of the second transistor each include an oxide semiconductor containing In, Ga, and Zn; The first transistor is a first oxide semiconductor layer including a channel formation region of the first transistor; a first conductive layer having a region provided below the first oxide semiconductor layer and a region overlapping with the first oxide semiconductor layer; a second conductive layer having a region provided above the first oxide semiconductor layer and electrically connected to the first oxide semiconductor layer; a second oxide semiconductor layer, a third conductive layer having the same material as the first conductive layer, and a fourth conductive layer having the same material as the second conductive layer, located outside the pixel portion; the second oxide semiconductor layer contains In, Ga, and Zn; the third conductive layer has a region provided below the second oxide semiconductor layer and a region overlapping with the second oxide semiconductor layer; the fourth conductive layer has a region provided above the second oxide semiconductor layer and is electrically connected to the second oxide semiconductor layer and the third conductive layer; an insulating layer having a region provided between the second oxide semiconductor layer and the third conductive layer; the insulating layer has a plurality of openings for electrically connecting the third conductive layer and the fourth conductive layer; The display device, wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer is a non-single-crystal oxide semiconductor layer.

2. a pixel portion including a plurality of pixels arranged in a matrix; Each of the plurality of pixels is A light-emitting element; a first transistor electrically connected to the light-emitting element and functioning as a driving transistor; a second transistor electrically connected to a gate of the first transistor and having a function as a switching transistor; a channel formation region of the first transistor and a channel formation region of the second transistor each include an oxide semiconductor containing In, Ga, and Zn; The first transistor is a first oxide semiconductor layer including a channel formation region of the first transistor; a first conductive layer having a region provided below the first oxide semiconductor layer and a region overlapping with the first oxide semiconductor layer; a second conductive layer having a region provided above the first oxide semiconductor layer and electrically connected to the first oxide semiconductor layer; a first insulating layer having a region provided between the pixel electrode of the light-emitting element and the second conductive layer; the first insulating layer has a region in contact with an upper surface of the first oxide semiconductor layer, a second oxide semiconductor layer, a third conductive layer having the same material as the first conductive layer, and a fourth conductive layer having the same material as the second conductive layer, located outside the pixel portion; the second oxide semiconductor layer contains In, Ga, and Zn; the third conductive layer has a region provided below the second oxide semiconductor layer and a region overlapping with the second oxide semiconductor layer; the fourth conductive layer has a region provided above the second oxide semiconductor layer and is electrically connected to the second oxide semiconductor layer and the third conductive layer; a second insulating layer having a region provided between the second oxide semiconductor layer and the third conductive layer; the second insulating layer has a plurality of openings for electrically connecting the third conductive layer and the fourth conductive layer; the first insulating layer has a region in contact with an upper surface of the first conductive layer and a region in contact with an upper surface of the third conductive layer; the second insulating layer has a region in contact with an upper surface of the second conductive layer and a region in contact with an upper surface of the fourth conductive layer; The display device, wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer is a non-single-crystal oxide semiconductor layer.

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