Method for forming conductive pipes between adjacent features and integrated assembly having conductive pipes between adjacent features

Abstract

To provide integrated circuits having conductive pipes between neighboring features.SOLUTION: An integrated assembly 10 comprises: first to fourth tracks 77 which extend along an x-axis direction and which are spaced by intervening spaces 79; a first semiconductor-containing feature 80 along the first track, a second semiconductor-containing feature 82 along the fourth track, a first gating structure 60a extending along a y-axis direction and across the first to fourth tracks; a second gating structure 60b extending along the second direction and across the first to fourth tracks; first to third source / drain regions S / D-1 to 3 within the first semiconductor-containing feature; fourth to sixth source / drain regions S / D-4 to 6 within the second semiconductor-containing feature; a first conductive pipe 20a adjacent to the first semiconductor-containing feature and on an opposite side thereof from the second track; and a second conductive pipe 20b adjacent to the second semiconductor-containing feature and on an opposite side thereof from the third track.SELECTED DRAWING: Figure 23A

Description

[Technical Field]

[0001] Integrated assembly and method for forming the integrated assembly.Method for forming a conductive pipe between adjacent features.Integrated assembly having a conductive pipe between adjacent features. [Background technology]

[0002] Patterned features are commonly used in integrated assemblies. In some exemplary applications, the patterned features may be conductive features utilized as interconnects and / or utilized to provide appropriate voltages (e.g., VDD, VSS, etc.) to integrated circuits. Due to the tight spacing available for patterned features, fabricating patterned features becomes increasingly difficult as integration levels increase. It is desirable to develop new methods for forming patterned features and to develop new architectures that utilize patterned features. Summary of the Invention

[0003] An integrated circuit according to one aspect of the present invention includes first, second, third, and fourth tracks extending along a first direction and separated from one another by intervening spaces, the tracks and the intervening spaces alternating with one another along a second direction substantially perpendicular to the first direction, the tracks and the intervening spaces being on pitch; first semiconductor-containing features along the first tracks; and second semiconductor-containing features along the fourth track. a first gating structure spanning second, third, and fourth tracks; a second gating structure extending along the second direction and spanning the first, second, third, and fourth tracks; first, second, and third source / drain regions within the first semiconductor-containing feature, the first and second source / drain regions being on opposite sides of the second gating structure and the second and third source / drain regions being on opposite sides of the first gating structure; fourth, fifth, and sixth source / drain regions in a second semiconductor-containing feature, the fourth and fifth source / drain regions being on opposite sides of the second gating structure and the fifth and sixth source / drain regions being on opposite sides of the first gating structure; and a first conductive pipe adjacent to the first semiconductor-containing feature and on an opposite side of the first semiconductor-containing feature from the second track, the first conductive pipe being substantially parallel to the first semiconductor-containing feature; the first conductive pipe being separated from the first semiconductor-containing feature by a first distance that is less than about half the pitch; a second conductive pipe adjacent to the second semiconductor-containing feature and on an opposite side of the second semiconductor-containing feature from the third track, the second conductive pipe being substantially parallel to the second semiconductor-containing feature and separated from the second semiconductor-containing feature by a second distance that is less than about half the pitch; and a first electrical connection extending from the first source / drain region to the first conductive pipe.a second electrical connection extending from the third source / drain region to the first conductive pipe, and a third electrical connection extending from the sixth source / drain region to the second conductive pipe. [Brief explanation of the drawings]

[0004] [Figure 1] 1A and 1B are diagrams of areas of an exemplary integrated assembly.

[0022] Figure 1 is a schematic top view along section 1-1 of Figures 1A and 1B. [Figure 1A] 1A is a schematic cross-sectional side view taken along line AA of FIG. 1; [Figure 1B] 1A and 1B are diagrams of regions of an exemplary integrated assembly, respectively, and are schematic cross-sectional side views taken along line BB in FIG. [Figure 2] 1 is a schematic top view of an area of ​​an exemplary integrated assembly at successive process stages of an exemplary method; [Figure 2A] 2A-2C are diagrams of regions of an exemplary integrated assembly at successive process stages of an exemplary method; [Figure 3] 3 is a schematic top view of an area of ​​an exemplary integrated assembly at successive process stages of an exemplary method. [Figure 3A] 3A-3C are diagrams of regions of an exemplary integrated assembly at successive process stages of an exemplary method; [Figure 4] 4 is a schematic top view of an area of ​​an exemplary integrated assembly at successive process stages of an exemplary method. [Figure 4A] 4A-4C are diagrams of regions of an exemplary integrated assembly at successive process stages of an exemplary method. [Figure 5] 5 is a schematic top view of an area of ​​an exemplary integrated assembly at successive process stages of an exemplary method. [Figure 5A]5A-5C are diagrams of regions of an exemplary integrated assembly at successive process stages of an exemplary method. [Figure 6] 1 is a schematic cross-sectional side view of a region of an exemplary integrated assembly. [Figure 7] 1A-1C are schematic cross-sectional side views of regions of an exemplary integrated assembly at successive process stages of an exemplary method. [Figure 8] 1A-1C are schematic cross-sectional side views of regions of an exemplary integrated assembly at successive process stages of an exemplary method. [Figure 9] 1A-1C are schematic cross-sectional side views of regions of an exemplary integrated assembly at successive process stages of an exemplary method. [Figure 10] 10 is a schematic top view of an area of ​​an exemplary integrated assembly at successive process stages of an exemplary method. [Figure 10A] 10A-10C are diagrams of regions of an exemplary integrated assembly at successive process stages of an exemplary method. [Figure 10B] 10A and 10B are diagrams of regions of an exemplary integrated assembly at successive process stages of an exemplary method. [Figure 11] 11 is a schematic top view of an area of ​​an exemplary integrated assembly at successive process stages of an exemplary method. [Figure 11A] 11A-11C are diagrams of regions of an exemplary integrated assembly at successive process stages of an exemplary method. [Figure 11B] 11A and 11B are diagrams of regions of an exemplary integrated assembly at successive process stages of an exemplary method. [Figure 12] 12 is a schematic top view of an area of ​​an exemplary integrated assembly at successive process stages of an exemplary method. [Figure 12A]12A-12C are diagrams of regions of an exemplary integrated assembly at successive process stages of an exemplary method; [Figure 12B] 12A and 12B are diagrams of regions of an exemplary integrated assembly at successive process stages of an exemplary method. [Figure 13] 13 is a schematic top view of an area of ​​an exemplary integrated assembly at successive process stages of an exemplary method. [Figure 13A] 13A-13C are diagrams of regions of an exemplary integrated assembly at successive process stages of an exemplary method. [Figure 14] 1A-1C are schematic top views of regions of an exemplary integrated assembly at successive process stages of an exemplary method. [Figure 15] 1A-1C are schematic top views of regions of an exemplary integrated assembly at successive process stages of an exemplary method. [Figure 16] 1A-1C are schematic top views of regions of an exemplary integrated assembly at successive process stages of an exemplary method. [Figure 17] 1A-1C are schematic top views of regions of an exemplary integrated assembly at successive process stages of an exemplary method. [Figure 18] 1A-1C are schematic top views of regions of an exemplary integrated assembly at successive process stages of an exemplary method. [Figure 19] 1A-1C are schematic top views of regions of an exemplary integrated assembly at successive process stages of an exemplary method. [Figure 20] 1A-1C are schematic top views of regions of an exemplary integrated assembly at successive process stages of an exemplary method. [Figure 21] 21A and 21B are diagrams of areas of an exemplary integrated assembly.

[0032] Figure 21 is a schematic cross-sectional top view taken along line CC in Figures 21A and 21B. [Figure 21A] 21A is a schematic cross-sectional side view taken along line AA of FIG. 21. FIG. [Figure 21B] 21A and 21B are diagrams of regions of an exemplary integrated assembly, respectively, and are schematic cross-sectional side views taken along line BB in FIG. [Figure 22A] 1 is a schematic top view of a region of an exemplary prior art integrated circuit. [Figure 22B] FIG. 22B is a schematic diagram of the exemplary prior art integrated circuit of FIG. 22A. [Figure 23A] FIG. 22C is a schematic top view of a region of an integrated circuit of an exemplary embodiment that may include the prior art arrangement of FIG. 22B. [Figure 23B] FIG. 23B is a reproduction of the schematic diagram of FIG. 23A. [Figure 24] 1 is a schematic cross-sectional top view of an exemplary integrated assembly. [Figure 25] 1 is a schematic cross-sectional top view of an exemplary integrated assembly. DETAILED DESCRIPTION OF THE INVENTION

[0005] Some embodiments include methods of forming conductive pipes (linear structures) between features of an integrated assembly. Some embodiments include an integrated assembly including conductive pipes. Some embodiments include logic circuits (e.g., 2NFET, 2PFET circuits, where NFET refers to a field effect transistor with n-type source / drain regions and PFET refers to a field effect transistor with p-type source / drain regions). Exemplary embodiments are described with reference to FIGS. 1-25.

[0006] 1-1B, integrated assembly 10 includes a pair of features 12 and 14. The features are shown to be linear structures, and such linear structures extend along a first direction corresponding to the illustrated x-axis direction. The linear features may be straight (as shown), wavy, or curved, and are substantially parallel to one another. The term "substantially parallel" means parallel within reasonable tolerances of fabrication and measurement.

[0007] The features 12 and 14 may be supported by an underlying semiconductor base (not shown). The base may include a semiconductor material, for example, may include, consist essentially of, or consist of monocrystalline silicon. The base may be referred to as a semiconductor substrate. The term "semiconductor substrate" includes, but is not limited to, bulk semiconductor materials such as semiconductor wafers (either alone or in an assembly with other materials) and semiconductor material layers (either alone or in an assembly with other materials). The term "substrate" refers to any supporting structure, including, but not limited to, the semiconductor substrates described above. In some applications, the base may correspond to a semiconductor substrate that includes one or more materials associated with the fabrication of integrated circuits. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulating materials, etc.

[0008] Features 12 and 14 are separated from one another by intervening spaces 16. In the illustrated embodiment, spaces 16 have approximately the same width W along the illustrated y-axis as features 12 and 14. Thus, features 12 and 14 are considered to be formed along (or at) a pitch P, where the width of space 16 is approximately ½P.

[0009] Features 12 and 14 include material 18. Material 18 may include any suitable composition. While material 18 is shown as being homogeneous, in other embodiments, material 18 may be heterogeneous and include two or more distinct compositions. Furthermore, while features 12 and 14 are shown as including the same material 18, in other embodiments, the features may include different compositions from one another.

[0010] Material 18 can be conductive, insulating, semiconductive, etc. If material 18 includes two or more distinct compositions, such compositions can have different conductivities from one another. Illustratively, in some embodiments, one of the compositions is conductive while another is insulating, etc.

[0011] A conductive pipe (structure, feature, wire, etc.) 20 is located within the space 16. The conductive pipe 20 is shown in dashed (phantom) line in Figure 1 to indicate that it is underneath other material.

[0012] The conductive pipe includes a conductive material 22. The conductive material 22 may include any suitable conductive composition, such as, for example, one or more of various metals (e.g., titanium, tungsten, tantalum, cobalt, molybdenum, nickel, platinum, ruthenium, copper, aluminum, palladium, silver, gold, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). In some embodiments, the conductive material 22 may include, consist essentially of, or consist of one or more of a metal nitride, a metal carbide, a metal silicide, and a metal boride. In some embodiments, the conductive material 22 may include a tungsten core laterally surrounded by a layer including titanium nitride.

[0013] The conductive pipe 20 is substantially parallel to the features 12 and 14 and, in the embodiment shown, is approximately midway between the features 12 and 14 within the intervening space 16 .

[0014] A first conductive post (block, structure, etc.) 24 is along one side of the pipe 20, and a second conductive post (block, structure, etc.) 26 is along a second, opposite side of the pipe 20. Posts 24 and 26 include the same composition 22 as the pipe 20.

[0015] First dielectric material 28 resides within interstitial space 16, beneath conductive pipe 20, and along the sidewalls of features 12 and 14. First dielectric material 28 may comprise any suitable composition, and in some embodiments may comprise, consist essentially of, or consist of one or more of silicon nitride, silicon dioxide, aluminum oxide, hafnium oxide, tantalum oxide, and the like.

[0016] A second dielectric material 30 resides within the interstitial space 16 and above the first dielectric material 28. The second dielectric material 30 resides above and below the conductive pipe 20, and in the embodiment shown, also lines the sidewalls of the conductive pipe 20. The second dielectric material 30 may have a lower density than the first dielectric material 28. The second dielectric material 30 may comprise any suitable composition, and in some embodiments may comprise, consist essentially of, or consist of one or more of silicon nitride, silicon dioxide, porous silicon dioxide, carbon-doped silicon oxide, boron-doped silicon dioxide, silicon oxynitride, etc.

[0017] In some embodiments, the first and second dielectric materials 28 and 30 may both comprise silicon nitride, with the second dielectric material 30 having a lower density than the first dielectric material. In some embodiments, the first and second dielectric materials 28 and 30 may both comprise silicon dioxide, with the second dielectric material having a lower density than the first dielectric material. In some embodiments, the first dielectric material 28 may comprise silicon nitride, and the second dielectric material 30 may comprise silicon dioxide. In some embodiments, the first dielectric material 28 may comprise silicon nitride, and the second dielectric material 30 may comprise silicon oxynitride.

[0018] A third dielectric material 32 is above the second dielectric material 30. The third dielectric material may be denser than the second dielectric material 30 and may include any of the compositions described above as suitable for the first dielectric material 28. The first and third dielectric materials 28 and 32 may include the same composition as each other, or may include different compositions from each other.

[0019] In the embodiment shown, planarized surface 33 extends across second and third dielectric materials 30 and 32. Planarized surface 33 is separated from top surfaces 17 of features 12 and 14 by at least second dielectric material 30, and in the embodiment shown, is separated from such surfaces by both second dielectric material 30 and first dielectric material 28.

[0020] The advantages of the configurations of FIGS. 1 to 1B are that the mechanisms 12 and 14 can be formed with a very tight pitch P (e.g., a pitch corresponding to the minimum pitch achievable by the manufacturing process), and the pipe 20 can be formed within the space between such mechanisms. Thus, the conductive pipe 20 can be packed into the tight space of the integrated assembly and provide conductive interconnects within such a tight space.

[0021] The assemblies of FIGS. 1 to 1B can be formed using any suitable process. Exemplary processes are described with reference to FIGS. 2 to 5.

[0022] Referring to FIGS. 2 and 2A, the assembly 10 is shown to include the mechanisms 12 and 14 as fins extending upward from the pillars 34 of the material 18. In some embodiments, the material 18 of FIGS. 2 and 2A can be a semiconductor material. The semiconductor material can include any suitable composition and, in some embodiments, can include one or more of silicon, germanium, III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc., can consist essentially of, or can consist of, the term III / V semiconductor material refers to a semiconductor material containing elements selected from groups III and V of the periodic table (groups III and V are the old nomenclature and are now referred to as groups 13 and 15). In some embodiments, the semiconductor material 18 of FIGS. 2 and 2A can include silicon, can consist essentially of, or can consist of. Silicon can be in any suitable crystalline form (e.g., single crystal, polycrystal, amorphous, etc.).

[0023] Fins 12 and 14 may be referred to as a first fin and a second fin, respectively. The fins may have regions of any suitable conductivity type in embodiments in which material 18 is a semiconductor material. Illustratively, in some embodiments, fins 12 and 14 may include regions that are p-type (e.g., may include regions having silicon conductively doped with boron) and / or may include regions that are n-type (e.g., may include regions having silicon conductively doped with one or both of phosphorus and arsenic). In some embodiments, fin 12 may include a first region having a first conductivity type, and fin 14 may include a second region having a second conductivity type, where the second conductivity type is different from the first conductivity type (e.g., one of the first and second conductivity types is p-type while the other is n-type).

[0024] The fins 12 and 14 (ie, the first and second features 12 and 14) are separated from one another by intervening spaces 16 and extend substantially parallel to one another along the illustrated x-axis direction.

[0025] 3 and 3A, a dielectric material 28 is formed within the interstitial space 16. In the described embodiment, the dielectric material 28 conformally extends along the outer surfaces of the features 12 and 14, narrowing the interstitial space 16. The dielectric material 28 may be referred to as a first dielectric material.

[0026] A second dielectric material 30 is formed above the first dielectric material 28 and within the space 16 narrowed by the first dielectric material. The second dielectric material 30 may have a lower density than the first dielectric material 28, and thus, voids 36 may be created within the material 30 during deposition of the material 30. Specifically, an upper region 37 of the second material 30 may pinch off at the top of the intervening space 16 to prevent the material 30 from completely filling the space, thereby creating the void 36.

[0027] In the described embodiment, voids 36 correspond to tubes (as shown with respect to the top view in FIG. 3 ), and such tubes extend substantially parallel to first and second features 12 and 14. Features 12 and 14 are shown in FIG. 3 with dashed lines to indicate that the tubes and features are underneath other material.

[0028] The tube 36 has a first end 39 and an opposite second end 41 .

[0029] A third dielectric material 32 is formed above the second dielectric material 30. The third dielectric material 32 may be denser than the second dielectric material 30. In some embodiments, the third dielectric material 32 may be tailored to effectively seal voids within the second dielectric material 30. Illustratively, the third dielectric material 32 may be provided to have high conformality such that it may effectively seal voids 36 within the second dielectric material 30 to the extent that additional sealing is necessary or desired.

[0030] In some embodiments, the dielectric materials 28, 30, and 32 may all comprise the same composition (e.g., silicon dioxide or silicon nitride), but deposition conditions may be modified such that the intermediate dielectric material 30 has a lower density than the upper and lower dielectric materials 28 and 32. In some embodiments, the intermediate dielectric material 30 may comprise a different composition than the upper and lower dielectric materials 28 and 32. Illustratively, the upper and lower dielectric materials 28 and 32 may both comprise silicon nitride, while the intermediate dielectric material may comprise silicon dioxide. Alternatively, the upper and lower dielectric materials 28 and 32 may both comprise silicon dioxide, while the intermediate dielectric material may comprise silicon nitride. As another example, the upper and lower dielectric materials 28 and 32 may both comprise silicon nitride, while the intermediate dielectric material 30 may comprise silicon oxynitride.

[0031] In some embodiments, the density of the intermediate dielectric material 30 may be affected by incorporating one or more dopants (and / or other additives) into the material. Illustratively, the intermediate dielectric material 30 may include carbon-doped silicon dioxide, boron-doped silicon dioxide, etc.

[0032] The upper and lower dielectric materials 28 and 32 may comprise the same composition as each other, or may comprise different compositions from each other.

[0033] Dielectric materials 28, 30, and 32 may be formed using any suitable process, including, for example, atomic layer deposition (ALD) and / or chemical vapor deposition (CVD).

[0034] In some embodiments, one or both of the dielectric materials 28 and 32 may be omitted.

[0035] Figure 3A shows a planarized surface 33 extending across the third dielectric material 32. In other embodiments, the planarized surface 33 may be formed to extend across regions of both the third dielectric material 32 and the second dielectric material 30, as shown in Figure 1A.

[0036] 4 and 4A, openings 38 are formed along ends 39 and 41 of tube 36. The openings may be utilized to provide access to ends 39 and 41 of tube 36. Although openings are shown as being formed along both opposing ends 39 and 41 of tube 36, in other embodiments, openings may be formed along only one of the ends of the tube.

[0037] 5 and 5A, conductive material 22 is formed in openings 38 and flows through those openings into tube 36. In the described embodiment, conductive material 22 fills tube 36 to form conductive pipe 20 described above with reference to FIGS. 1-1B. Material 22 may include any of the compositions described above with reference to FIGS. 1-1B. Material 22 may be formed using any suitable process, including, for example, one or more of ALD, CVD, and physical vapor deposition (PVD).

[0038] In some embodiments, material 22 can include one or more metals and / or metal-containing compositions. Illustratively, in some embodiments, material 22 can include a metal nitride (e.g., titanium nitride, tungsten nitride, etc.) liner lining tube 36 and can include a metal core material within the lined tube. The metal core material can include, consist essentially of, or consist of, for example, tungsten, titanium, etc.

[0039] In some embodiments, the formation of conductive material 22 within tube 36 can be considered a method for patterning conductive pipe 20 within region 16 between features 12 and 14. The conductive pipe 20 described is substantially parallel to first and second features 12 and 14.

[0040] While dielectric materials 28, 30, and 32 are shown in the embodiments of Figures 1-5 as comprising a homogenous composition, in other embodiments, one or more of these other materials may comprise a stack of two or more compositions. By way of illustration, Figure 6 shows an enlarged view of space 16 between features 12 and 14 at a processing stage similar to that of Figure 5A in an exemplary embodiment in which dielectric materials 28 and 30 each comprise a stack of two or more compositions. Specifically, dielectric material 28 comprises a stack of compositions 28a, 28b, and 28c, and dielectric material 30 comprises a stack of compositions 30a and 30b. The stacks may include abrupt boundaries between adjacent compositions and / or may include gradients between adjacent compositions.

[0041] An advantage of utilizing a laminate configuration for one or more of the dielectric materials is that it may allow the dielectric material to be tailored to a particular application. Illustratively, the laminate configuration of dielectric material 30 may allow the cross-sectional shape of voids 36 to be tailored to a particular application.

[0042] Compositions 28a-c may include any of the materials described above as suitable for dielectric material 28, and compositions 30a and 30b may include any of the materials described above as suitable for dielectric material 30.

[0043] In some embodiments, one or more etchants may flow into tube 36 through openings 38 (FIG. 4) to widen the tube prior to forming conductive material 22 (FIG. 5) within such tube. By way of illustration, FIG. 7 shows an enlarged view of space 16 between features 12 and 14 at the processing stage of FIGS. 4 and 4A. FIG. 8 shows a processing stage subsequent to that of FIG. 7, showing tube 36 widened with one or more etchants flowed into the tube through openings 38 (FIG. 4). When dielectric material 30 includes silicon dioxide, the etchant may include hydrochloric acid. When dielectric material 30 includes silicon nitride, the etchant may include phosphoric acid.

[0044] The original position of tube 36 is shown by dashed line 43 in FIG. 8 so that the reader can easily see that tube 36 has been widened in the process step of FIG. 8 as compared to the process step of FIG.

[0045] Referring to FIG. 9, conductive material 22 is formed within an expanded tube 36 to form a conductive pipe 20 of the type described above with reference to FIG.

[0046] The embodiment of Figures 2-5 shows dielectric materials 28, 30, and 32 formed along the entire length of space 16 between features 12 and 14. In other embodiments, the dielectric materials may be formed only along a segment of the space, such that the resulting tube 36 does not extend the entire length of the space, but only along a segment of the space. An example of such an other embodiment is described with reference to Figures 10-13.

[0047] 10-10B, assembly 10 is shown at a process stage similar to that of FIGS. 3 and 3A, except that space 16 between features 12 and 14 has been subdivided into three segments 44, 46, and 48. Segments 44 and 48 include dielectric materials 28, 30, and 32 described above with reference to FIGS. 3 and 3A.

[0048] Segment 46 includes dielectric materials 40 and 42. Dielectric materials 40 and 42 may include any suitable composition. In some embodiments, dielectric material 40 may be the same as dielectric material 28, and dielectric material 42 may be the same as dielectric material 32. In some embodiments, dielectric materials 40 and 42 may be replaced with a single dielectric material.

[0049] The less dense (softer) material 30 is omitted from segment 46, and thus voids 36 are not formed along segment 46. The configuration of Figure 10 may be considered to have segments 44 and 48 corresponding to first regions 50 of interstitial space 16, and segment 46 corresponding to second regions 52 of interstitial space 16. Tubes 36 extend across first regions 50 of interstitial space 16 and do not extend across second regions 52 of interstitial space 16. In some articles, tubes 36 within segment 44 of interstitial space 16 may be referred to as first tubes 51, and tubes within third segment 48 may be referred to as second tubes 53.

[0050] 11-11B, openings 38 are formed using a process similar to that described above with reference to FIGS. 4 and 4A.

[0051] 12-12B, conductive material 22 is formed within opening 38 and tubes 51 and 53 using a process similar to that described above with reference to FIGS. 5 and 5A.

[0052] The conductive material 22 in the tube 51 forms a first conductive pipe 20a, and the conductive material 22 in the tube 53 forms a second conductive pipe 20b.

[0053] The conductive material 22 within the openings 38 forms blocks (posts) 24 and 26 of the type described above with reference to FIG.

[0054] In some embodiments, features 12 and 14 may be considered to extend a first distance D1 along the x-axis direction, and pipes 20a and 20b may each be considered to extend a second distance D2 along the x-axis direction, the second distance being less than the first distance. In the illustrated embodiment, second distance D2 is less than half of first distance D2. In the illustrated embodiment, pipes 20a and 20b extend approximately the same distance from each other (i.e., are approximately the same length from each other). In other embodiments, pipe 20a may be a different length than pipe 20b.

[0055] In the described embodiment, the first and second conductive pipes 20a and 20b are separated from one another by an intervening gap corresponding to segment 46. Intervening gap 46 may be considered an insulating region 46 between first and second conductive pipes 20a and 20b. Pipe 20a may be considered to have a first end 55a on one side of insulating region 46, and pipe 20b may be considered to have a second end 55b on a second, opposite side of insulating region 46.

[0056] In some embodiments, the conductive interconnect may be formed to extend downwardly to one or both of the ends 55 a and 55 b. By way of illustration, Figures 13 and 13A show an electrical interconnect 54 extending downwardly through the insulator materials 28, 30, and 32 that is electrically coupled to the ends 55 a and 55 b of the conductive pipes 20 a and 20 b.

[0057] Electrical interconnects 54 may comprise any suitable conductive composition, such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). In some embodiments, electrical interconnects 54 may comprise conductive material 22 (i.e., the same conductive material utilized in blocks 24 and 26 and in pipes 20a and 20b).

[0058] Electrical interconnects 54 may be coupled to other circuitry (not shown), which may be at any suitable elevational level and, in some embodiments, may be at an elevational level above features 12 and 14.

[0059] In some embodiments, features 12 and 14 may include segments separated by intervening gaps, and it may be desirable to form a continuous conductive structure across such intervening gaps. The methods described in Figures 14-20 may be used to fabricate such conductive structures.

[0060] 14, construct 10 includes a configuration in which feature 12 includes a pair of segments 12a and 12b, and feature 14 includes a pair of segments 14a and 14b. Segments 12a and 14a are separated from segments 12b and 14b by an intervening gap 56.

[0061] Referring to Figure 15, conductive pipes 20a and 20b are formed between features 12 and 14 using a process similar to that described above with reference to Figures 2-5. Specifically, conductive pipe 20a is formed between features 12a and 14a, and conductive pipe 20b is formed between features 12b and 14b. Insulator material 32 is shown extending across features 12a, 12b, 14a, and 14b and across pipes 20a and 20b in a configuration similar to that of Figures 5 and 5A. Pipes 20a and 20b are separated from one another by intervening gaps 56.

[0062] 16, conductive material 58 is formed in interstitial gap 56 and patterned to conductively couple first conductive pipe 20a to second conductive pipe 20b. In some embodiments, conductive material 58 can be considered to be patterned as features 59 that bridge across gap 56 to electrically couple first and second conductive pipes 20a and 20b to one another.

[0063] Conductive material 58 may comprise any suitable conductive composition, such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). In some embodiments, conductive material 58 may comprise the same composition as conductive material 22, while in other embodiments, conductive material 58 may comprise a different composition than conductive material 22.

[0064] Referring to FIG. 17, assembly 10 is shown at a process stage similar to that of FIG. 2, with features 12 and 14 extending along the x-axis direction.

[0065] Referring to Figure 18, the tube 36 is formed using a process similar to that described above with reference to Figures 3 and 3A.

[0066] 19, the patterned chops subdivide feature 12 into first and second structures 12a and 12b, feature 14 into first and second structures 14a and 14b, and tube 36 into first and second structures 36a and 36b. Interstitial gaps 56 are thus formed extending between the first structures (12a, 14a, and 36a) and the second structures (12b, 14b, and 36b).

[0067] 20 , a bridge structure 59 is formed to extend across the intervening gap 56 and connect the first tube 36 a to the second tube 36 b. The bridge structure 59 includes a conductive material 58 that may flow into the tubes 36 a and 36 b to form the pipes 20 a and 20 b extending outward from the bridge structure 59. In some embodiments, the conductive material 58 includes both a metal nitride (e.g., titanium nitride, tungsten nitride, etc.) and a relatively pure metal (e.g., tungsten). The metal nitride may flow into the tubes 36 a and 36 b to line the tubes, and the relatively pure metal may then flow into the lined tube to form a metal core surrounded by a metal nitride liner.

[0068] In some embodiments, the structures described above may be incorporated into an integrated circuit as described with reference to Figures 21-21B.

[0069] Assembly 10 of Figures 21-21B includes features 12 and 14 configured as fins of semiconductor material 18 that extend upwardly from pillars 34 of semiconductor material. Stipples are provided in semiconductor material 18 to assist the reader in identifying the semiconductor material.

[0070] Semiconductor material 18 may comprise any suitable composition and, in some embodiments, may comprise, consist essentially of, or consist of one or more of silicon, germanium, III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc., where the term III / V semiconductor material refers to semiconductor materials including elements selected from Groups III and V of the periodic table (Groups III and V are older nomenclature, now referred to as Groups 13 and 15). Illustratively, in some embodiments, semiconductor material 18 may comprise, consist essentially of, or consist of silicon. The silicon may be in any suitable crystalline form and, in some embodiments, may correspond to monocrystalline silicon.

[0071] The fin 12 is shown to include p-type source / drain regions S / D. The p-type regions of the fin 12 are at least about 10 20 atoms / cm 3 The silicon may include silicon doped with boron to a concentration of 0.1 to 1.0.

[0072] The fin 14 is shown to include n-type source / drain regions S / D. The n-type regions of the fin 14 are at least about 10 20 atoms / cm 3 The silicon may include silicon doped with one or both of phosphorus and arsenic to a total concentration of 0.1 to 1.0.

[0073] The source / drain regions S / D along the first fin 12 are referred to as first source / drain regions, and the source / drain regions S / D along the second fin 14 are referred to as second source / drain regions.

[0074] The gating structures 60a and 60b extend across the fins 12 and 14, and the gating structures extend along the illustrated y-axis direction. One of the gating structures 60a and 60b may be referred to as a first gating structure, and the other may be referred to as a second gating structure.

[0075] The gating structure includes conductive gating materials 62a-c. The gating materials 62a-c may include any suitable conductive composition, such as, for example, one of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). In some embodiments, two or more of the gating materials 62a-c may be compositionally the same as one another, while in other embodiments, two or more of the gating materials may be compositionally different from one another.

[0076] An insulator material (gate dielectric material) 62 lines the outer surfaces of the fins 12 and 14. The insulator material 62 may comprise any suitable composition, and in some embodiments may include one or more of silicon dioxide, aluminum oxide, hafnium oxide, zirconium oxide, hafnium oxide, etc.

[0077] Fin 12 includes channel regions 64a and 64b between the described source / drain regions S / D along the fin, and fin 14 includes channel regions 66a and 66b between the described source / drain regions S / D along the fin. Channel regions 64a and 66a are in operative proximity to gating structure 60a, and channel regions 64b and 66b are in operative proximity to gating structure 60b. The term "operative proximity" refers to the gating structures being in adequate proximity to the channel regions such that electrical activation / deactivation of the gating structures selectively induces an electric field on the channel regions. Selective induction of an electric field on the channel regions can be utilized to achieve controlled coupling / separation of source / drain regions S / D on opposite sides of the channel region.

[0078] Channel regions 64 and 66 may be appropriately doped to achieve a desired threshold voltage.

[0079] Circuits similar to those of Figures 21-21B can be used in logic devices.

[0080] 22A and 22B illustrate an exemplary prior art logic device that includes two NFET devices 68a and 68b (labeled transistors T1 and T2) and two PFET devices 70a and 70b (labeled transistors T3 and T4). The illustrated device also includes a capacitor 69.

[0081] FIG. 22B is a schematic diagram of a prior art device, and FIG. 22A is a schematic diagram of a region of a semiconductor assembly 72 that contains the device.

[0082] The schematic diagram of Figure 22A can be viewed as an assembly including six tracks (labeled tracks 1 through 6). The tracks are on a pitch P1, which may be the minimum lithographic pitch of the manufacturing process. The outer tracks (tracks 1 and 6) contain conductive structures (power lines, traces) 74 and 76 that provide VDD and VSS to the device (i.e., are coupled to reference nodes at VDD and VSS).

[0083] In some embodiments, logic devices similar to the logic devices of Figures 22A and 22B can be formed using processes according to one or more of the embodiments of Figures 1-22 to achieve higher integration density compared to the prior art device of Figure 22A.

[0084] 23A shows an assembly 10 including an exemplary logic cell 78 having two NFET transistors 68a and 68b and two PFET transistors 70a and 70b. The logic cell 78 may be referred to as a 2NFET-2PFET device.

[0085] Figure 23B schematically illustrates a 2NFET-2PFET logic cell 78. The schematic illustration of Figure 23B is identical to the schematic illustration of Figure 22B.

[0086] The six tracks (tracks 1-6) described above with respect to FIG. 22A are shown along the right side of logic cell 78 in FIG. 23A. However, the logic cell primarily utilizes only four of those six tracks. Accordingly, four tracks 77 are shown along the left side of FIG. 23A, and these four tracks are identified as a first track, a second track, a third track, and a fourth track. The four tracks 77 extend along a first direction corresponding to the illustrated x-axis direction. The four tracks 77 are separated from one another by intervening spaces 79. The tracks and spaces (77, 79) alternate with one another along a second direction (the illustrated y-axis direction). The second direction (y-axis direction) is shown as being orthogonal to the first direction (x-axis direction). In some embodiments, the second direction can be substantially orthogonal to the first direction, where the term "substantially orthogonal" means orthogonal within reasonable manufacturing and measurement tolerances.

[0087] The tracks 77 and intervening spaces 79 are on a pitch P1, which may be the minimum lithographic pitch of the manufacturing process.

[0088] A first semiconductor-containing feature 80 is along a first track, and a second semiconductor-containing feature 82 is along a fourth track. The first semiconductor-containing feature 80 is paired with an adjacent semiconductor-containing feature 81, and the second semiconductor feature 82 is paired with an adjacent semiconductor-containing feature 83. Features 80-83 may correspond to semiconductor fins similar to fins 12 and 14 of FIG. 21. In the described embodiment, fins 80 and 81 are paired with each other, and conductive pipe 20a is formed between them. Fins 82 and 83 are paired with each other, and conductive pipe 20b is formed between them. Conductive pipes 20a and 20b may be formed by a process similar to that described above with reference to FIGS. 2-5.

[0089] Fins 80 and 81 can be considered to be separated from each other by a first gap 16a, and fins 82 and 83 can be considered to be separated from each other by a second gap 16b. Conductive pipes 20a and 20b are located within the first and second gaps, respectively. Conductive pipe 20a is substantially parallel to fins 80 and 81, and conductive pipe 20b is substantially parallel to fins 82 and 83.

[0090] In the described embodiment, fins 80-83 are all formed on pitch P1, and conductive pipes 20a and 20b are not on such pitch. Instead, conductive pipe 20a is separated from fin 80 by a first distance D1 that is less than or equal to about half of pitch P1, and conductive pipe 20b is separated from fin 82 by a second distance D2 that is less than or equal to about half of pitch P1.

[0091] In some embodiments, the distances D1 and D2 may be the same as one another, while in other embodiments, such distances may differ from one another. In some embodiments, the first and second distances D1 and D2 may be less than or equal to about one-quarter of the pitch P1.

[0092] In the illustrated embodiment, conductive pipe 20a is on the opposite side of first semiconductor-containing feature 80 from the second track, and conductive pipe 20b is on the opposite side of semiconductor-containing feature 82 from the third track. Thus, a pair of outer edges of logic cell 78 are bounded by conductive pipes 20a and 20b.

[0093] Conductive pipe 20a is shown coupled to VDD (i.e., coupled to a reference voltage node at VDD) and conductive pipe 20b is shown coupled to VSS (i.e., coupled to a reference voltage node at VSS). In other embodiments, the conductive pipes may be coupled to other suitable supply voltages.

[0094] Semiconductor-containing feature 80 is shown to include three p-type source / drain regions (S / D-1, S / D-2, and S / D-3), and semiconductor-containing feature 82 is shown to include three n-type source / drain regions (S / D-4, S / D-5, and S / D-6). Regions S / D-1, S / D-2, and S / D-3 may be referred to as the first, second, and third source / drain regions, and regions S / D-4, S / D-5, and S / D-6 may be referred to as the fourth, fifth, and sixth source / drain regions.

[0095] The first and second gating structures 60 a and 60 b extend along the second direction (y-axis) and across the track 77 .

[0096] The first and second source / drain regions S / D-1 and S / D-2 are on opposite sides of the second gating structure 60b, the second and third source / drain regions S / D-2 and S / D-3 are on opposite sides of the first gating structure 60a, the fourth and fifth source / drain regions S / D-4 and S / D-5 are on opposite sides of the second gating structure 60b, and the fifth and sixth source / drain regions S / D-5 and S / D-6 are on opposite sides of the first gating structure 60a.

[0097] A first electrical connection 84 extends from the first source / drain region S / D-1 to the first conductive pipe 20a, a second electrical connection 86 extends from the third source / drain region S / D-3 to the first conductive pipe 20a, a third electrical connection 88 extends from the sixth source / drain region S / D-6 to the second conductive pipe 20b, and a fourth electrical connection 90 extends from the second source / drain region S / D-2 to the fourth source / drain region S / D-4.

[0098] Input / outputs (I / O) are provided to logic cell 78. In the embodiment shown, a first input / output (I / O-1) extends along the third track and has a region (interconnect) electrically coupled to first gating structure 60a through interconnect 91a.

[0099] A second input / output (I / O-2) extends along a second track and has a region (interconnect) electrically coupled to second gating structure 60b through interconnect 91b.

[0100] A third input / output (I / O-3) has a region (interconnect) extending along the third track. A fifth electrical connection 92 extends from the fourth source / drain region (S / D-4) to the interconnect associated with I / O-3.

[0101] The terms "first," "second," and "third" input / output are arbitrary. Illustratively, either of inputs / outputs I / O-1 and I / O-2 may be referred to as the "first" and "second" input / output.

[0102] Electrical connections 84, 86, 88, 90, and 92 may comprise any suitable material and may be formed at any suitable elevational level. In some embodiments, gating structures 60a and 60b may be at a first elevational level and connections 90 and 92 may be at a second elevational level higher than the first level. Electrical connections 84, 86, and 88 may be at the same elevational level as gating structures 60a and 60b or may be at a different elevational level relative to such gating structures. Electrical connections 84, 86, 88, 90, and 92 may comprise any suitable conductive material and may include any suitable structural configuration.

[0103] Capacitor 69 is shown as being electrically coupled along connection 92 and therefore electrically coupled to the fourth source / drain region (S / D-4). Capacitor 69 may be formed in any suitable location and may or may not be formed in the location described. One of the electrodes of capacitor 69 is shown as being coupled to ground voltage (GND), or in other words, to an electrical node at ground voltage. In other embodiments, the electrodes may be coupled to any other suitable voltage.

[0104] The conductive pipes 20 described herein may be provided in any suitable location and utilized in any suitable application. By way of illustration, FIG. 24 illustrates an application in which conductive features 12 are formed along a first pitch P1, and conductive pipes 20 are provided between the features and utilized to reduce the pitch. Specifically, the features 12 and pipes 20 may be alternating conductive structures formed together along a second pitch P1 that is smaller than the first pitch P1. Conventional processes utilize multiple techniques to reduce pitch. Such techniques are commonly referred to as pitch-increasing techniques, with an exemplary pitch-increasing technique being pitch-doubling. Pitch-doubling techniques effectively reduce the pitch between features by approximately half (i.e., forming twice as many features within a defined area of ​​a semiconductor substrate). The method described with reference to FIG. 24 may be considered an example of utilizing pipes 20 in pitch-increasing techniques. The structure of FIG. 24 may be utilized at any suitable level within an integrated circuit. By way of illustration, the structure may be utilized in a memory array, an electrical bus, or the like.

[0105] FIG. 25 illustrates another application of a conductive pipe 20 formed in accordance with embodiments described herein. The described embodiment has a conductive pipe 20 formed between a pair of features 12 and 14. Regions 100a-c are below the features 12 and 14 and below the conductive pipe 20. Regions 100a-c may correspond to active regions across a memory array (i.e., may include semiconductor material 102), for example. The described conductive pipe 20 is coupled to outer regions 100a and 100c through conductive blocks 24 and 26, but extends across inner region 100b without being coupled to those regions. Specifically, the conductive pipe 20 may be elevated above region 100b. Thus, the pipe 20 may be utilized as an electrical interconnect extending from region 100a to region 100c and passing above region 100b without being electrically coupled to those regions. In some embodiments, regions 100a and 100c may be referred to as first and second active regions, and region 100b may be referred to as a third active region.

[0106] The assemblies and structures discussed above may be utilized within integrated circuits (the term "integrated circuit" refers to an electronic circuit supported by a semiconductor substrate) and incorporated into electronic systems. Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communications modems, processor modules, and application-specific modules, and may include multi-layer, multi-chip modules. The electronic systems may be any of a wide range of systems, such as cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, mobile phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0107] Unless otherwise specified, the various materials, substances, compositions, etc. described herein may be formed using any suitable method, whether currently known or yet to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0108] The terms "dielectric" and "insulator" may be used to describe materials that have insulating electrical properties. The terms are considered synonymous in this disclosure. The use of the term "dielectric" in some instances and the term "insulator" (or "electrical insulator") in other instances may provide language variations within this disclosure to simplify the antecedents in the claims that follow and are not used to indicate any significant chemical or electrical differences.

[0109] The terms "electrically connected" and "electrically coupled" may both be used in this disclosure. The terms are considered synonymous. The use of one term in some instances and the other term in other instances may provide for language variations within this disclosure to simplify the antecedents in the claims that follow.

[0110] The particular orientations of the various embodiments in the drawings are for illustrative purposes only, and the embodiments may be rotated relative to the orientation shown in some applications. The description provided herein and the claims that follow relate to any structure having the described relationships between its various features, regardless of whether the structure is in a particular orientation in the drawings or rotated relative to such orientation.

[0111] To simplify the drawings, unless otherwise indicated, cross-sectional views in the accompanying figures only show features in the plane of the cross-section and not material behind the plane of the cross-section.

[0112] When a structure is referred to above as being "on," "adjacent," or "against" another structure, it may be directly on the other structure, or intervening structures may be present. In contrast, when a structure is referred to as being "directly on," "directly adjacent," or "directly in contact" with another structure, there are no intervening structures present. The terms "directly below," "directly above," etc. do not indicate direct physical contact (unless otherwise specified), but instead indicate an upright arrangement.

[0113] A structure (e.g., a layer, material, etc.) may be referred to as "vertically-extending" to indicate that the structure generally extends upward from an underlying base (e.g., substrate). A vertically-extending structure may or may not extend substantially perpendicular to the top surface of the base.

[0114] Some embodiments include an integrated assembly having a pair of substantially parallel features separated from one another by an intervening space. A conductive pipe is between the features and substantially parallel to the features. A first dielectric material is within the intervening space, below the conductive pipe, and along a sidewall of the feature. A second dielectric material is within the intervening space and above the first dielectric material. The second dielectric material is above and below the conductive pipe.

[0115] Some embodiments include an integrated circuit having first, second, third, and fourth tracks extending along a first direction and separated from one another by intervening spaces. The tracks and intervening spaces alternate with one another along a second direction substantially perpendicular to the first direction. The tracks and intervening spaces are on pitch. A first semiconductor-containing feature lies along the first track. A second semiconductor-containing feature lies along the fourth track. A first gating structure extends along the second direction and spans the first, second, third, and fourth tracks. A second gating structure extends along the second direction and spans the first, second, third, and fourth tracks. First, second, and third source / drain regions are within the first semiconductor-containing feature. The first and second source / drain regions are on opposite sides of the second gating structure, and the second and third source / drain regions are on opposite sides of the first gating structure. The fourth, fifth, and sixth source / drain regions are within the second semiconductor-containing feature. The fourth and fifth source / drain regions are on opposite sides of the second gating structure from each other, and the fifth and sixth source / drain regions are on opposite sides of the first gating structure from each other. The first conductive pipe is adjacent to the first semiconductor-containing feature and on the opposite side of the first semiconductor-containing feature from the second track. The first conductive pipe is substantially parallel to the first semiconductor-containing feature and separated from the first semiconductor-containing feature by a first distance that is less than about half the pitch. The second conductive pipe is adjacent to the second semiconductor-containing feature and on the opposite side of the second semiconductor-containing feature from the third track. The second conductive pipe is substantially parallel to the second semiconductor-containing feature and separated from the second semiconductor-containing feature by a second distance that is less than about half the pitch. A first electrical connection extends from the first source / drain region to the first conductive pipe. A second electrical connection extends from the third source / drain region to the first conductive pipe. A third electrical connection extends from the sixth source / drain region to the second conductive pipe.

[0116] Some embodiments include a method of forming an integrated assembly. First and second features are formed so as to be separated from one another by an intervening space. The first and second features are substantially parallel to one another. A dielectric material is formed within the intervening space. The dielectric material pinches off at an upper portion of the intervening space to form a tube extending substantially parallel to the first and second features. A conductive material is formed within the tube, thereby patterning a conductive pipe within the tube. The conductive pipe is substantially parallel to the first and second features.

Claims

1. first, second, third, and fourth tracks extending along a first direction and separated from one another by intervening spaces, the tracks and the intervening spaces alternating with one another along a second direction substantially perpendicular to the first direction, the tracks and the intervening spaces being on pitch; a first semiconductor-containing feature along the first track; a second semiconductor-containing feature along the fourth track; and a first gating structure extending along the second direction and spanning the first, second, third, and fourth tracks; a second gating structure extending along the second direction and spanning the first, second, third, and fourth tracks; first, second, and third source / drain regions within the first semiconductor-containing feature, the first and second source / drain regions being on opposite sides of the second gating structure, and the second and third source / drain regions being on opposite sides of the first gating structure; fourth, fifth, and sixth source / drain regions in the second semiconductor-containing feature, the fourth and fifth source / drain regions being on opposite sides of the second gating structure and the fifth and sixth source / drain regions being on opposite sides of the first gating structure; a first conductive pipe adjacent to the first semiconductor-containing feature and on an opposite side of the first semiconductor-containing feature from the second track, the first conductive pipe being substantially parallel to the first semiconductor-containing feature and separated from the first semiconductor-containing feature by a first distance that is less than about half the pitch; a second conductive pipe adjacent to the second semiconductor-containing feature and on an opposite side of the second semiconductor-containing feature from the third track, the second conductive pipe being substantially parallel to the second semiconductor-containing feature and separated from the second semiconductor-containing feature by a second distance that is less than about half the pitch; a first electrical connection extending from the first source / drain region to the first conductive pipe; a second electrical connection extending from the third source / drain region to the first conductive pipe; a third electrical connection extending from the sixth source / drain region to the second conductive pipe; An integrated circuit comprising:

2. 10. The integrated circuit of claim 1 configured as a 2NFET-2PFET logic cell.

3. 2. The integrated circuit of claim 1, wherein the first and second conductive pipes are coupled to VDD and VSS, respectively.

4. 2. The integrated circuit of claim 1, wherein the first and second distances are less than or equal to about one-quarter of the pitch.

5. 2. The integrated circuit of claim 1, wherein said first semiconductor-containing feature comprises a p-type source / drain region and said second semiconductor-containing feature comprises an n-type source / drain region.

6. 2. The integrated circuit of claim 1, further comprising a fourth electrical connection extending from said second source / drain region to said fourth source / drain region.

7. a first I / O coupled to the first gating structure; a second I / O coupled to the second gating structure; a third I / O coupled to the fourth source / drain region; and 7. The integrated circuit of claim 6, comprising:

8. 8. The integrated circuit of claim 7, wherein the first I / O is coupled to the first gating structure by an interconnect extending along the third track, and the second I / O is coupled to the second gating structure by an interconnect extending along the second track.

9. 9. The integrated circuit of claim 8, wherein the third I / O is coupled to the fourth source / drain region by an interconnect extending along the third track.

10. 8. The integrated circuit of claim 7, further comprising a capacitor coupled to said fourth source / drain region.

11. the first semiconductor-containing feature is one of a pair of first semiconductor fins separated from one another by a first gap; the second semiconductor-containing feature is one of a pair of second semiconductor fins separated from one another by a second gap; the first conductive pipe is in the first gap; the second conductive pipe is within the second gap; 10. The integrated circuit of claim 1.

12. 12. The integrated circuit of claim 11, wherein the first semiconductor fin comprises a p-type region and the second semiconductor fin comprises an n-type region.

13. The integrated circuit of claim 11 , wherein the first and second semiconductor fins are on the pitch.

14. a first dielectric material in the first and second gaps, the first dielectric material below the first and second conductive pipes; a second dielectric material in the first and second gaps and above the first dielectric material, the second dielectric material being above and below the first and second conductive pipes; 12. The integrated circuit of claim 11, comprising:

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