Integrated LC element and mounting structure

Abstract

The integrated LC element 1 includes a capacitor layer 10 having a first surface 10a and a second surface 10b opposing each other in the thickness direction, a redistribution layer 20 provided on the first surface 10a of the capacitor layer 10, and an inductor layer 30 provided on the second surface 10b of the capacitor layer 10. The capacitor layer 10 includes a capacitor portion CAP having an anode 11 and a cathode 12, a first insulating portion INS1 provided around the capacitor portion CAP, and a first via conductor portion V1 penetrating the first insulating portion INS1 in the thickness direction at a position spaced apart from the capacitor portion CAP in a plane direction perpendicular to the thickness direction. The redistribution layer 20 includes a wiring portion WR and a second insulating portion INS2 provided around the wiring portion WR. The inductor layer 30 includes an inductor portion IND and a third insulating portion INS3 provided around the inductor portion IND. The inductor portion IND is electrically connected to the anode 11 of the capacitor portion CAP located on the first surface 10a of the capacitor layer 10 through the first via conductor portion V1 and the wiring portion WR.

Description

[Technical Field]

[0001] The present invention relates to an integrated LC device and a mounting structure. [Background technology]

[0002] Patent Document 1 discloses an apparatus including a circuit board having a first surface and a second surface opposite the first surface, and a passive device integrated on the circuit board. The passive device has an input terminal configured to couple to power from a die, an output terminal electrically coupled to the input terminal, and an electrical routing mechanism disposed between the first surface and the second surface of the circuit board and coupled to the input terminal and the output terminal to route the power between the input terminal and the output terminal. The input terminal includes a surface configured to receive a solder ball connection of a die package assembly including the die. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6165866 Summary of the Invention [Problem to be solved by the invention]

[0004] Patent Document 1 discloses, as an example, an integrated circuit (IC) package assembly including a die package assembly including a package substrate on which one or more dies are mounted, and a circuit board coupled to the die package assembly. Patent Document 1 states that in some embodiments, the die may be a processor, a memory, or an ASIC (Application Specific Integrated Circuit).

[0005] Patent document 1 also describes that the circuit board may include one or more passive devices integrated into the circuit board, and that in some embodiments, the passive devices include one or more of inductors, capacitors, resistors, and the like.

[0006] For example, in the power supply line from a voltage conversion module (VRM) to a processor, a combination of inductors and capacitors is used as a passive device, and in this case, it is desirable to reduce the parasitic resistance and parasitic inductance of the current path.

[0007] The present invention has been made to solve the above problems, and aims to provide an integrated LC element that can reduce the parasitic resistance and parasitic inductance of the current path. Another aim of the present invention is to provide a mounting structure including an interposer that includes the integrated LC element. [Means for solving the problem]

[0008] The integrated LC element of the present invention includes a capacitor layer having a first surface and a second surface opposing each other in a thickness direction, a redistribution layer provided on the first surface of the capacitor layer, and an inductor layer provided on the second surface of the capacitor layer. The capacitor layer includes a capacitor section having an anode and a cathode, a first insulating section provided around the capacitor section, and a first via conductor section penetrating the first insulating section in the thickness direction at a position spaced from the capacitor section in a plane direction perpendicular to the thickness direction. The redistribution layer includes a wiring section and a second insulating section provided around the wiring section. The inductor layer includes an inductor section and a third insulating section provided around the inductor section. The inductor section is electrically connected to the anode of the capacitor section located on the first surface of the capacitor layer through the first via conductor section and the wiring section.

[0009] The mounting structure of the present invention comprises an interposer including the integrated LC element of the present invention, a package substrate arranged on a main surface of the interposer closer to the inductor layer, and a processor arranged on a main surface of the interposer closer to the capacitor layer. [Effects of the Invention]

[0010] According to the present invention, it is possible to provide an integrated LC element capable of reducing the parasitic resistance and parasitic inductance of a current path. Furthermore, according to the present invention, it is possible to provide a mounting structure including an interposer including the integrated LC element. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a cross-sectional view schematically illustrating an example of an integrated LC element according to a first embodiment of the present invention. [Figure 2] FIG. 2 is an equivalent circuit diagram of the integrated LC element 1 shown in FIG. [Figure 3] FIG. 3 is a schematic diagram showing an example of an electronic circuit including the integrated LC element 1 shown in FIG. [Figure 4] FIG. 4 is a cross-sectional view schematically showing an example of a capacitor section. [Figure 5] FIG. 5 is a cross-sectional view schematically showing an example of an MIM structure. [Figure 6] FIG. 6 is a perspective view schematically illustrating an example of an inductor section. [Figure 7] FIG. 7 is a perspective view schematically showing another example of the inductor section. [Figure 8] FIG. 8 is a perspective view schematically showing still another example of the inductor section. [Figure 9] FIG. 9 is a cross-sectional view schematically showing another example of the integrated LC element according to the first embodiment of the present invention. [Figure 10] FIG. 10 is a cross-sectional view schematically showing an example of a step of forming a capacitor layer. [Figure 11]FIG. 11 is a cross-sectional view schematically showing an example of a process for forming a rewiring layer. [Figure 12] FIG. 12 is a cross-sectional view schematically illustrating an example of a step of arranging a support member. [Figure 13] FIG. 13 is a cross-sectional view schematically showing an example of a step of removing the base material. [Figure 14] FIG. 14 is a cross-sectional view schematically illustrating an example of a step of forming a third insulating portion and a second via conductor portion. [Figure 15] FIG. 15 is a cross-sectional view schematically showing an example of a process for forming an inductor portion. [Figure 16] FIG. 16 is a cross-sectional view schematically showing an example of a step of forming a first bump. [Figure 17] FIG. 17 is a cross-sectional view schematically illustrating an example of a step of removing the support member. [Figure 18] FIG. 18 is a cross-sectional view schematically illustrating an example of an integrated LC element according to the second embodiment of the present invention. [Figure 19] FIG. 19 is a cross-sectional view schematically showing another example of the integrated LC element according to the second embodiment of the present invention. [Figure 20] FIG. 20 is a cross-sectional view schematically illustrating an example of an integrated LC element according to the third embodiment of the present invention. [Figure 21] FIG. 21 is a cross-sectional view that schematically shows an example of a mounting structure of the present invention. [Figure 22] FIG. 22 is a cross-sectional view schematically showing an example of an integrated LC element included in an interposer that constitutes the mounting structure shown in FIG. [Figure 23] FIG. 23 is a cross-sectional view that schematically shows a first modified example of the mounting structure of the present invention. [Figure 24] FIG. 24 is a cross-sectional view schematically showing an example of an integrated LC element included in an interposer that constitutes the mounting structure shown in FIG. [Figure 25] FIG. 25 is a cross-sectional view that schematically shows a second modified example of the mounting structure of the present invention. [Figure 26]FIG. 26 is a cross-sectional view schematically showing an example of an integrated LC element included in an interposer that constitutes the mounting structure shown in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0012] The integrated LC element and mounting structure of the present invention will be described below. Note that the present invention is not limited to the following embodiments and may be modified as appropriate within the scope of the present invention. Furthermore, a combination of multiple individual preferred configurations described in the following embodiments also constitutes the present invention.

[0013] The following embodiments are merely examples, and it goes without saying that partial substitution or combination of the configurations shown in different embodiments is possible. From the second embodiment onwards, descriptions of matters common to the first embodiment will be omitted, and differences will be mainly described. In particular, similar effects due to similar configurations will not be mentioned one after the other for each embodiment.

[0014] In the following description, unless there is a need to distinguish between the embodiments, they will be simply referred to as the "integrated LC element of the present invention" and the "mounting structure of the present invention." The shapes and arrangements of the integrated LC element and the mounting structure of the present invention are not limited to the examples shown in the drawings.

[0015] In this specification, terms indicating the relationship between elements (e.g., "perpendicular," "parallel," "orthogonal," etc.) and terms indicating the shape of elements are not expressions that only express a strict meaning, but are expressions that also include a range of substantial equivalence, for example, a difference of a few percent.

[0016] The drawings shown below are schematic diagrams, and the dimensions, aspect ratio, and other scales may differ from those of the actual product. In the drawings, the same or equivalent parts will be designated by the same reference numerals. In addition, the same elements will be designated by the same reference numerals in each drawing, and duplicate explanations will be omitted.

[0017] [Integrated LC element] The integrated LC element of the present invention comprises a capacitor layer having a first surface and a second surface opposite to each other in the thickness direction, a redistribution layer provided on the first surface of the capacitor layer, and an inductor layer provided on the second surface of the capacitor layer.

[0018] (First embodiment) FIG. 1 is a cross-sectional view schematically illustrating an example of an integrated LC element according to a first embodiment of the present invention.

[0019] The integrated LC element 1 shown in FIG. 1 includes a capacitor layer 10, a redistribution layer 20, and an inductor layer 30.

[0020] The capacitor layer 10 has a first surface 10a and a second surface 10b that face each other in the thickness direction (the Z-axis direction in FIG. 1).

[0021] The capacitor layer 10 includes a capacitor portion CAP having an anode 11 and a cathode 12, a first insulating portion INS1 provided around the capacitor portion CAP, and a first via conductor portion V1 penetrating the first insulating portion INS1 in the thickness direction at a position separated from the capacitor portion CAP in a plane direction perpendicular to the thickness direction (the XY plane direction in FIG. 1). The capacitor layer 10 may include a plurality of capacitor portions CAP. The configuration, shape, etc. of the capacitor portion CAP are not particularly limited. The capacitor layer 10 may also include a plurality of first via conductor portions V1. The first via conductor portion V1 may have a tapered shape.

[0022] 1, the anode 11 of the capacitor section CAP is located on the first surface 10a of the capacitor layer 10. The cathode 12 of the capacitor section CAP is preferably located on the first surface 10a of the capacitor layer 10. A via conductor penetrating the inductor layer 30 in the thickness direction may be provided below the conductor layer 60 (see FIG. 4) located below the cathode 12. In this case, the via conductor is provided in a region of the inductor layer 30 where the inductor section IND is not present (a region on the far side or near side of the page in FIG. 1).

[0023] The redistribution layer 20 is provided on the first surface 10a of the capacitor layer 10.

[0024] The redistribution layer 20 includes a wiring portion WR and a second insulating portion INS2 provided around the wiring portion WR. The wiring portion WR includes, for example, a conductor layer along the surface direction and a via conductor connecting the conductor layers together.

[0025] The inductor layer 30 is provided on the second surface 10b of the capacitor layer 10.

[0026] The inductor layer 30 includes an inductor portion IND and a third insulating portion INS3 provided around the inductor portion IND. The inductor layer 30 may include a plurality of inductor portions IND. The configuration, shape, etc. of the inductor portion IND are not particularly limited.

[0027] As shown in FIG. 1, the inductor portion IND is electrically connected to the anode 11 of the capacitor portion CAP located on the first surface 10a of the capacitor layer 10 through the first via conductor portion V1 and the wiring portion WR.

[0028] In the integrated LC element 1, the inductor portion IND is electrically connected to the anode 11 of the capacitor portion CAP located on the first surface 10a of the capacitor layer 10 through the first via conductor portion V1 and the wiring portion WR, thereby shortening the current path between the inductor portion IND and the capacitor portion CAP, thereby reducing the parasitic resistance and parasitic inductance of the current path.

[0029] Furthermore, with the above-described configuration, the integrated LC element 1 can provide a thin and high-performance (high capacitance and high inductance) integrated LC element.

[0030] FIG. 2 is an equivalent circuit diagram of the integrated LC element 1 shown in FIG.

[0031] The inductor section IND is connected between a first external terminal 41 and a second external terminal 42. In the example shown in Fig. 1, a first bump BP1 is provided as the first external terminal 41, but the form of the first external terminal 41 is not particularly limited. Similarly, the form of the second external terminal 42 is not particularly limited.

[0032] On the other hand, the capacitor section CAP is connected between the second external terminal 42 and the third external terminal 43. The form of the third external terminal 43 is not particularly limited.

[0033] FIG. 3 is a schematic diagram showing an example of an electronic circuit including the integrated LC element 1 shown in FIG.

[0034] 3, the inductor unit IND is connected to a voltage regulator VR at a first external terminal 41, and is connected to a load Load at a second external terminal 42. On the other hand, the capacitor unit CAP is connected to the load Load at the second external terminal 42, and is connected to ground GND at a third external terminal 43.

[0035] The voltage regulator VR includes an active element such as a semiconductor switching element, and adjusts the DC voltage supplied from the outside to a voltage level suitable for the load Load by controlling the duty of the active element.

[0036] The load is, for example, a semiconductor integrated circuit such as a logic operation circuit or a memory circuit.

[0037] 1, the inductor section IND preferably includes a magnetic layer 31 extending along the surface direction, which can increase the inductance.

[0038] The inductor layer 30 may further include a second via conductor V2 penetrating the third insulating portion INS3 in the thickness direction between the inductor portion IND and the first via conductor V1. In this case, the inductor portion IND is electrically connected to the first via conductor V1 through the second via conductor V2. The second via conductor V2 may have a tapered shape.

[0039] 1, in a cross section taken along the thickness direction, the center line of the second via conductor portion V2 may be offset from the center line of the first via conductor portion V1. Note that in a cross section taken along the thickness direction, the center line of the second via conductor portion V2 may coincide with the center line of the first via conductor portion V1.

[0040] The diameter of the second via conductor portion V2 may be the same as the diameter of the first via conductor portion V1, may be smaller than the diameter of the first via conductor portion V1, or may be larger than the diameter of the first via conductor portion V1.

[0041] The height of the second via conductor portion V2 may be the same as the height of the first via conductor portion V1, may be smaller than the height of the first via conductor portion V1, or may be larger than the height of the first via conductor portion V1.

[0042] The material of the second via conductor portion V2 may be the same as or different from the material of the first via conductor portion V1.

[0043] 1, the third insulating portion INS3 preferably includes one insulating layer between the capacitor portion CAP and the inductor portion IND. In other words, it is preferable that one layer of second via conductor portion V2 is provided between the capacitor portion CAP and the inductor portion IND. In this case, the current path between the inductor portion IND and the capacitor portion CAP can be shortened.

[0044] The third insulating portion INS3 is preferably made of an inorganic material containing Si. Examples of inorganic materials containing Si include silicon oxides such as SiO. The third insulating portion INS3 may include an inorganic insulating layer or an organic insulating layer.

[0045] The inductor layer 30 may further include a fourth via conductor V4 penetrating the third insulating portion INS3 in the thickness direction between the inductor portion IND and the first bump BP1. In this case, the inductor portion IND is electrically connected to the first bump BP1 via the fourth via conductor V4. The fourth via conductor V4 may have a tapered shape.

[0046] In a cross section along the thickness direction, the center line of the fourth via conductor portion V4 may be offset from or coincident with the center line of the second via conductor portion V2.

[0047] The diameter of the fourth via conductor portion V4 may be the same as the diameter of the second via conductor portion V2, may be smaller than the diameter of the second via conductor portion V2, or may be larger than the diameter of the second via conductor portion V2.

[0048] The height of the fourth via conductor portion V4 may be the same as the height of the second via conductor portion V2, may be smaller than the height of the second via conductor portion V2, or may be larger than the height of the second via conductor portion V2.

[0049] The material of the fourth via conductor portion V4 may be the same as or different from the material of the second via conductor portion V2.

[0050] The capacitor layer 10 may further include a fifth via conductor V5 penetrating the first insulating portion INS1 in the thickness direction at a position away from the capacitor portion CAP and the first via conductor V1 in the planar direction. The fifth via conductor V5 is electrically connected to the wiring portion WR of the redistribution layer 20. The fifth via conductor V5 may have a tapered shape.

[0051] The diameter of the fifth via conductor portion V5 may be the same as the diameter of the first via conductor portion V1, may be smaller than the diameter of the first via conductor portion V1, or may be larger than the diameter of the first via conductor portion V1.

[0052] The height of the fifth via conductor portion V5 may be the same as the height of the first via conductor portion V1, may be smaller than the height of the first via conductor portion V1, or may be larger than the height of the first via conductor portion V1.

[0053] The material of the fifth via conductor portion V5 may be the same as or different from the material of the first via conductor portion V1.

[0054] The inductor layer 30 may further include a sixth via conductor V6 penetrating the third insulating portion INS3 in the thickness direction at a position away from the inductor portion IND in the planar direction. The sixth via conductor V6 is electrically connected to the fifth via conductor V5. The sixth via conductor V6 may have a tapered shape. In the example shown in FIG. 1, two or more layers of sixth via conductors V6 are provided in the thickness direction.

[0055] 1, in a cross section taken along the thickness direction, the center line of the sixth via conductor portion V6 may be offset from the center line of the fifth via conductor portion V5, or may be aligned with the center line of the fifth via conductor portion V5.

[0056] The diameter of the sixth via conductor portion V6 may be the same as the diameter of the fifth via conductor portion V5, may be smaller than the diameter of the fifth via conductor portion V5, or may be larger than the diameter of the fifth via conductor portion V5.

[0057] The height of the sixth via conductor portion V6 may be the same as the height of the fifth via conductor portion V5, may be smaller than the height of the fifth via conductor portion V5, or may be larger than the height of the fifth via conductor portion V5.

[0058] The material of the sixth via conductor portion V6 may be the same as or different from the material of the fifth via conductor portion V5.

[0059] The sixth via conductor V6 may be electrically connected to the second bump BP2. In the example shown in Fig. 1, the second bump BP2 is electrically connected to the wiring portion WR of the redistribution layer 20 via the sixth via conductor V6 and the fifth via conductor V5.

[0060] The redistribution layer 20 is a layer called an RDL (Redistribution Layer). The redistribution layer 20 changes the positions, spacing, etc. of the electrodes provided on the surface of the capacitor layer 10. As a result, it becomes easier to connect semiconductor elements such as processors.

[0061] The second insulating portion INS2 of the redistribution layer 20 includes, for example, an organic insulating layer. The second insulating portion INS2 may include an inorganic insulating layer and an organic insulating layer.

[0062] Specific examples of the capacitor section will be described below, but the capacitor section is not limited to the following configuration.

[0063] The capacitor section preferably has a metal-insulator-metal structure (MIM structure) of a metal layer-dielectric layer-metal layer.

[0064] FIG. 4 is a cross-sectional view schematically showing an example of a capacitor section.

[0065] 4 includes a porous layer 50 and a conductor layer 60 provided on one surface of the porous layer 50. An MIM structure 70 and an extraction electrode 80 exist on the level of the porous layer 50.

[0066] FIG. 5 is a cross-sectional view schematically showing an example of an MIM structure.

[0067] The MIM structure 70 includes, in this order, a first metal layer 71, a dielectric layer 73, and a second metal layer 72. As shown in Fig. 5, the MIM structure 70 is preferably provided in a porous layer 50. In the example shown in Fig. 5, the porous layer 50 has a plurality of grooves extending in the thickness direction from the upper surface 50a to the lower surface 50b of the porous layer 50, and the MIM structure 70 is provided on the inner surface 50c of the grooves. The shape, diameter, etc. of the grooves of the porous layer 50 are not particularly limited.

[0068] In the example shown in FIGS. 4 and 5, the first metal layer 71 is electrically connected to the anode 11, and the second metal layer 72 is electrically connected to the cathode 12 via the conductor layer 60 and the extraction electrode 80.

[0069] The grooves in the porous layer 50 are formed by, for example, etching silicon or the like, or anodizing aluminum, silicon, cobalt, or the like.

[0070] The MIM structure 70 is formed by, for example, atomic layer deposition (ALD).

[0071] Specific examples of the inductor section will be described below, but the inductor section is not limited to the following configuration.

[0072] FIG. 6 is a perspective view schematically illustrating an example of an inductor section.

[0073] The inductor section IND1 shown in Fig. 6 includes a magnetic layer 31 and a coil conductor 32. In the inductor section IND1 shown in Fig. 6, when viewed from the planar direction, the magnetic layer 31 is wrapped around the coil conductor 32. In this case, the inductance can be increased by increasing the number of turns of the coil conductor 32.

[0074] FIG. 7 is a perspective view schematically showing another example of the inductor section.

[0075] 7, when viewed in the thickness direction, the magnetic layer 31 is surrounded by the coil conductor 32. In this case, a certain inductance can be ensured and the direct current resistance (Rdc) can be reduced.

[0076] FIG. 8 is a perspective view schematically showing still another example of the inductor section.

[0077] 8, the coil conductor 32 is surrounded by the magnetic layer 31. In this case, the direct current resistance (Rdc) can be reduced.

[0078] FIG. 9 is a cross-sectional view schematically showing another example of the integrated LC element according to the first embodiment of the present invention.

[0079] 9, the inductor section IND includes, in the thickness direction, two or more magnetic layers 31. In this case, by increasing the number of magnetic layers 31, the inductance can be increased.

[0080] 9, the inductor portion IND may include two or more magnetic layers 31 in the planar direction, or may include two or more magnetic layers 31 in both the thickness direction and the planar direction.

[0081] An example of a method for manufacturing the integrated LC element according to the first embodiment of the present invention will be described below. Figures 10 to 17 are cross-sectional views that schematically show an example of a manufacturing process for the integrated LC element according to the first embodiment of the present invention.

[0082] FIG. 10 is a cross-sectional view schematically showing an example of a step of forming a capacitor layer.

[0083] 10, a capacitor layer 10 including a capacitor portion CAP, a first insulating portion INS1, and a first via conductor portion V1 is formed on a surface of a substrate SBT such as a silicon substrate. As shown in FIG. 10, a conductor layer 60 and an insulating layer 65 may be provided between the substrate SBT and the capacitor layer 10.

[0084] The capacitor section CAP preferably has an MIM structure (see FIGS. 4 and 5). In this case, the MIM structure is preferably provided in a porous layer.

[0085] In particular, the porous layer preferably has a groove extending in the thickness direction, and the MIM structure is provided on the inner surface of the groove. The porous layer having the groove may be formed, for example, by etching silicon or the like, or by anodizing aluminum, silicon, cobalt, or the like.

[0086] The first via conductor portion V1 is formed, for example, by filling a porous layer with a conductor. Filling the porous layer with the conductor is preferably performed by electrolytic plating. Alternatively, the first via conductor portion V1 may be formed by removing a portion of the porous layer and filling it with a metal by electrolytic plating. Copper or nickel is preferably used as the conductor. Meanwhile, the portion of the porous layer that is not filled with the conductor can be used as the first insulating portion INS1.

[0087] FIG. 11 is a cross-sectional view schematically showing an example of a process for forming a rewiring layer.

[0088] 11, a redistribution layer 20 including a wiring portion WR and a second insulating portion INS2 is formed on the surface of the capacitor layer 10. At this time, an anode 11 and a cathode 12 are also formed on the surface of the capacitor portion CAP. A conductor layer may also be formed on the surface of the first via conductor portion V1.

[0089] FIG. 12 is a cross-sectional view schematically illustrating an example of a step of arranging a support member.

[0090] 12, a carrier CR is disposed on the surface of the rewiring layer 20. Examples of materials for the carrier CR include insulating materials such as glass.

[0091] FIG. 13 is a cross-sectional view schematically showing an example of a step of removing the base material.

[0092] In the step shown in Fig. 13, the base material SBT is removed by a process such as grinding etc. In the example shown in Fig. 13, the entire base material SBT is removed.

[0093] FIG. 14 is a cross-sectional view schematically illustrating an example of a step of forming a third insulating portion and a second via conductor portion.

[0094] 14, a part of the third insulating portion INS3 and the second via conductor portion V2 are formed on the surface of the capacitor layer 10 opposite to the redistribution layer 20. At this time, a conductor layer may be formed between the first via conductor portion V1 and the second via conductor portion V2.

[0095] FIG. 15 is a cross-sectional view schematically showing an example of a process for forming an inductor portion.

[0096] 15, the remaining portion of the third insulating portion INS3 and the inductor portion IND are formed. As shown in FIG. 15, a fourth via conductor portion V4 may be formed.

[0097] The inductor portion IND preferably includes a magnetic layer 31 along the surface direction.

[0098] FIG. 16 is a cross-sectional view schematically showing an example of a step of forming a first bump.

[0099] 16, a first bump BP1 electrically connected to the fourth via conductor V4 is formed as needed. At this time, a conductor layer may be formed between the first bump BP1 and the fourth via conductor V4.

[0100] FIG. 17 is a cross-sectional view schematically illustrating an example of a step of removing the support member.

[0101] In the step shown in FIG. 17, the support member CR is removed.

[0102] Through the above steps, an integrated LC element according to the first embodiment of the present invention is obtained. Note that the order of the above steps is not particularly limited, and the order may be changed as appropriate.

[0103] (Second embodiment) In the integrated LC element according to the second embodiment of the present invention, the capacitor layer includes a substrate portion and a third via conductor portion.

[0104] FIG. 18 is a cross-sectional view schematically illustrating an example of an integrated LC element according to the second embodiment of the present invention.

[0105] 18, the capacitor layer 10 further includes a substrate portion ST provided on the second surface 10b so as to cover the capacitor portion CAP, the first insulating portion INS1, and the first via conductor portion V1, and a third via conductor portion V3 penetrating the substrate portion ST in the thickness direction between the inductor portion IND and the first via conductor portion V1. The other configuration is common to the integrated LC element 1 shown in FIG.

[0106] 18, the inductor portion IND is electrically connected to the first via conductor portion V1 through the third via conductor portion V3. The third via conductor portion V3 may have a tapered shape. The third via conductor portion V3 may be one layer or two or more layers.

[0107] In the integrated LC element 2 shown in FIG. 18, the capacitor layer 10 includes the substrate portion ST, which makes it possible to suppress warping of the entire element.

[0108] Examples of materials for the substrate portion ST include silicon, glass, silicon carbide, etc., but other ceramics, etc. may also be used.

[0109] In a cross section taken along the thickness direction, the center line of the third via conductor portion V3 may be offset from or coincident with the center line of the first via conductor portion V1. Furthermore, if the inductor layer 30 includes the second via conductor portion V2, in a cross section taken along the thickness direction, the center line of the third via conductor portion V3 may be offset from or coincident with the center line of the second via conductor portion V2.

[0110] The diameter of the third via conductor portion V3 may be the same as, smaller than, or larger than the diameter of the first via conductor portion V1. Furthermore, when the inductor layer 30 includes the second via conductor portion V2, the diameter of the third via conductor portion V3 may be the same as, smaller than, or larger than the diameter of the second via conductor portion V2.

[0111] The height of the third via conductor portion V3 may be the same as, smaller than, or larger than the height of the first via conductor portion V1. Furthermore, when the inductor layer 30 includes the second via conductor portion V2, the height of the third via conductor portion V3 may be the same as, smaller than, or larger than the height of the second via conductor portion V2.

[0112] The material of the third via conductor portion V3 may be the same as or different from the material of the first via conductor portion V1. Furthermore, when the inductor layer 30 includes the second via conductor portion V2, the material of the third via conductor portion V3 may be the same as or different from the material of the second via conductor portion V2.

[0113] 18, the capacitor layer 10 preferably further includes a seventh via conductor V7 penetrating the substrate ST in the thickness direction between the fifth via conductor V5 and the sixth via conductor V6. The fifth via conductor V5 is electrically connected to the sixth via conductor V6 through the seventh via conductor V7. The seventh via conductor V7 may have a tapered shape.

[0114] In a cross section taken along the thickness direction, the center line of the seventh via conductor portion V7 may be offset from or coincident with the center line of the fifth via conductor portion V5. Also, in a cross section taken along the thickness direction, the center line of the seventh via conductor portion V7 may be offset from or coincident with the center line of the sixth via conductor portion V6.

[0115] The diameter of the seventh via conductor portion V7 may be the same as, smaller than, or larger than the diameter of the fifth via conductor portion V5. Also, the diameter of the seventh via conductor portion V7 may be the same as, smaller than, or larger than the diameter of the sixth via conductor portion V6.

[0116] The height of the seventh via conductor portion V7 may be the same as, smaller than, or larger than the height of the fifth via conductor portion V5. Also, the height of the seventh via conductor portion V7 may be the same as, smaller than, or larger than the height of the sixth via conductor portion V6.

[0117] The material of the seventh via conductor portion V7 may be the same as or different from the material of the fifth via conductor portion V5, and may also be the same as or different from the material of the sixth via conductor portion V6.

[0118] FIG. 19 is a cross-sectional view schematically showing another example of the integrated LC element according to the second embodiment of the present invention.

[0119] 19, a rewiring layer 15, which is separate from the rewiring layer 20, may be provided on the substrate ST between the third via conductor V3 and the inductor IND. Providing the rewiring layer 15 below the third via conductor V3 increases the structural freedom of the third via conductor V3.

[0120] The rewiring layer 15 provided on the base member ST may have the same thickness as the rewiring layer 20 or may have a thickness greater than the rewiring layer 20, but is preferably smaller than the rewiring layer 20.

[0121] (Third embodiment) The integrated LC element according to the third embodiment of the present invention further comprises a power management integrated circuit (power management IC).

[0122] FIG. 20 is a cross-sectional view schematically illustrating an example of an integrated LC element according to the third embodiment of the present invention.

[0123] 20 further includes a power management integrated circuit PMIC electrically connected to the inductor section IND on the surface of the inductor layer 30 opposite to the capacitor layer 10. The other configurations are the same as those of the integrated LC element 1 shown in FIG.

[0124] The integrated LC element 3 shown in FIG. 20 functions as an element with a voltage conversion module. In the configuration of FIG. 20, current can be passed through the shortest path in the power supply line from the voltage conversion module (VRM) to the processor. By shortening the current path, it is possible to reduce loss due to Joule heat when current passes, and to reduce the parasitic resistance and parasitic inductance of the current path. As a result, a voltage conversion module with high conversion efficiency can be obtained.

[0125] [Implementation structure] The mounting structure of the present invention comprises an interposer including the integrated LC element of the present invention, a package substrate arranged on a main surface of the interposer closer to the inductor layer, and a processor arranged on a main surface of the interposer closer to the capacitor layer.

[0126] Fig. 21 is a cross-sectional view schematically showing an example of a mounting structure of the present invention. Fig. 22 is a cross-sectional view schematically showing an example of an integrated LC element included in an interposer constituting the mounting structure shown in Fig. 21. Fig. 22 corresponds to the cross-sectional view of the portion surrounded by the dashed line in Fig. 21.

[0127] The mounting structure 100 shown in Fig. 21 includes an interposer IP including an integrated LC element 110 (see Fig. 22), a package substrate PS arranged on a main surface of the interposer IP closer to the inductor layer 30 (see Fig. 22), and a processor PROC arranged on a main surface of the interposer IP closer to the capacitor layer 10 (see Fig. 22). The mounting structure 100 may further include a memory MEM arranged on a main surface of the interposer IP closer to the capacitor layer 10 (see Fig. 22). In the example shown in Fig. 22, the integrated LC element 110 has a common configuration with the integrated LC element 1 shown in Fig. 1.

[0128] As shown in FIG. 21, the integrated LC element 110 is positioned so as to overlap the processor PROC in the thickness direction.

[0129] 21 includes an interposer IP including a thin, high-performance (high capacitance and high inductance) integrated LC element 110. In the mounting structure 100, the via conductor portion of the integrated LC element can be used as a current path for the power supply line from the voltage conversion module (VRM) to the processor, allowing current to flow via the shortest path to the inductor portion IND and the capacitor portion CAP. By shortening the current path, it is possible to reduce loss due to Joule heat when current passes, and to reduce the parasitic resistance and parasitic inductance of the current path.

[0130] In the mounting structure 100 shown in FIG. 21, the interposer IP further includes a resin layer 120 in which the integrated LC element 110 is embedded.

[0131] As shown in FIG. 21, it is preferable that a power management integrated circuit PMIC is disposed on the surface of the resin layer 120.

[0132] In the example shown in FIG. 21, a wiring portion called a bridge die BD is disposed inside the resin layer 120, and the processor PROC and the memory MEM are electrically connected via the bridge die BD.

[0133] When the mounting structure 100 includes a memory MEM, the interposer IP may include an integrated LC element other than the integrated LC element 110 at a position overlapping the memory MEM in the thickness direction.

[0134] For example, the interposer IP and the processor PROC, the interposer IP and the memory MEM, and the interposer IP and the power management integrated circuit PMIC are connected by bumps BP, respectively.

[0135] Similarly, for example, the package substrate PS and the interposer IP are connected by bumps BP. Bumps BP may be provided on the surface of the package substrate PS opposite to the interposer IP.

[0136] An electronic component EC may be disposed on the surface of the package substrate PS.

[0137] Fig. 23 is a cross-sectional view schematically showing a first modified example of the mounting structure of the present invention. Fig. 24 is a cross-sectional view schematically showing an example of an integrated LC element included in an interposer constituting the mounting structure shown in Fig. 23. Fig. 24 corresponds to the cross-sectional view of the part surrounded by the dashed line in Fig. 23.

[0138] The mounting structure 100A shown in FIG. 23 differs from the mounting structure 100 shown in FIG. 21 in that the bridge die BD is incorporated into the integrated LC element 110A (see FIG. 24) instead of being disposed inside the resin layer 120.

[0139] 23 and 24, the redistribution layer 20 of the integrated LC element 110A extends to a position where it overlaps with both the processor PROC and the memory MEM in the thickness direction. Furthermore, as shown in FIG. 23, a power management integrated circuit PMIC is disposed inside the processor PROC.

[0140] 23, the redistribution layer 20 of the integrated LC element 110A is used not only as a power supply line but also as a signal line. By arranging the capacitor unit CAP and the inductor unit IND near the bridge die BD, noise in the signal line between the processor PROC and the memory MEM can be reduced.

[0141] Fig. 25 is a cross-sectional view schematically showing a second modified example of the mounting structure of the present invention. Fig. 26 is a cross-sectional view schematically showing an example of an integrated LC element included in an interposer constituting the mounting structure shown in Fig. 25. Fig. 26 corresponds to the cross-sectional view of the part surrounded by the dashed line in Fig. 25.

[0142] The mounting structure 100B shown in Figure 25 differs from the mounting structure 100 shown in Figure 21 and the mounting structure 100A shown in Figure 23 in that the interposer IP does not include a resin layer 120 and is composed only of an integrated LC element 110B (see Figure 26).

[0143] In the example shown in Fig. 26, the integrated LC element 110B has a common configuration with the integrated LC element 3 shown in Fig. 20. That is, the integrated LC element 110B further includes a power management integrated circuit PMIC electrically connected to the inductor unit IND on the surface of the inductor layer 30 opposite to the capacitor layer 10.

[0144] 25, an integrated LC element 110B itself is used as an interposer IP. By arranging the capacitor unit CAP and the inductor unit IND directly below the signal wiring of the interposer IP, noise in the signal wiring can be reduced.

[0145] The present specification discloses the following:

[0146] <1> a capacitor layer having a first surface and a second surface opposed to each other in a thickness direction; a redistribution layer provided on the first surface of the capacitor layer; an inductor layer provided on the second surface of the capacitor layer; the capacitor layer includes a capacitor portion having an anode and a cathode, a first insulating portion provided around the capacitor portion, and a first via conductor portion penetrating the first insulating portion in the thickness direction at a position spaced from the capacitor portion in a plane direction perpendicular to the thickness direction; the redistribution layer includes a wiring portion and a second insulating portion provided around the wiring portion; the inductor layer includes an inductor portion and a third insulating portion provided around the inductor portion; the inductor section is electrically connected to the anode of the capacitor section located on the first surface of the capacitor layer through the first via conductor section and the wiring section. Integrated LC element.

[0147] <2> The capacitor section has an MIM structure of a metal layer, a dielectric layer, and a metal layer. <1> The integrated LC element according to claim 1.

[0148] <3> The MIM structure is provided in a porous layer. <2> The integrated LC element according to claim 1.

[0149] <4> the porous layer has a groove portion extending in the thickness direction, The MIM structure is provided on the inner surface of the groove. <3> The integrated LC element according to claim 1.

[0150] <5> the inductor layer further includes a second via conductor portion that penetrates the third insulating portion in the thickness direction between the inductor portion and the first via conductor portion; the inductor portion is electrically connected to the first via conductor portion through the second via conductor portion; <1> ~ <4> 1. The integrated LC element according to any one of the preceding claims.

[0151] <6> In the cross section along the thickness direction, the center line of the second via conductor portion is misaligned with the center line of the first via conductor portion. <5> The integrated LC element according to claim 1.

[0152] <7> the third insulating section includes one insulating layer between the capacitor section and the inductor section; <1> ~ <6> 1. The integrated LC element according to any one of the preceding claims.

[0153] <8> the inductor section includes a magnetic layer extending along the surface direction; <1> ~ <7> 1. The integrated LC element according to any one of the preceding claims.

[0154] <9> When viewed from the surface direction, the magnetic layer is wound with a coil conductor. <8> The integrated LC element according to claim 1.

[0155] <10> When viewed from the thickness direction, the magnetic layer is surrounded by a coil conductor. <8> The integrated LC element according to claim 1.

[0156] <11> the coil conductor is surrounded by the magnetic layer; <8> The integrated LC element according to claim 1.

[0157] <12> the inductor section includes two or more magnetic layers in the thickness direction, the plane direction, or both; <8> ~ <11> 1. The integrated LC element according to any one of the preceding claims.

[0158] <13> The third insulating portion is made of an inorganic material containing Si. <1> ~ <12> 1. The integrated LC element according to any one of the preceding claims.

[0159] <14> the capacitor layer further includes a substrate portion provided on the second surface so as to cover the capacitor portion, the first insulating portion, and the first via conductor portion, and a third via conductor portion penetrating the substrate portion in the thickness direction between the inductor portion and the first via conductor portion, the inductor portion is electrically connected to the first via conductor portion through the third via conductor portion; <1> ~ <13> 1. The integrated LC element according to any one of the preceding claims.

[0160] <15> the substrate portion has another rewiring layer provided between the third via conductor portion and the inductor portion; <14> The integrated LC element according to claim 1.

[0161] <16> a power management IC electrically connected to the inductor section on a surface of the inductor layer opposite to the capacitor layer; <1> ~ <15> 1. The integrated LC element according to any one of the preceding claims.

[0162] <17> <1> ~ <16> an interposer including the integrated LC element according to any one of the above items; a package substrate disposed on a main surface of the interposer that is closer to the inductor layer; a processor disposed on a main surface of the interposer that is closer to the capacitor layer; the integrated LC element is positioned so as to overlap the processor in the thickness direction; Implementation structure.

[0163] <18> the interposer further includes a resin layer in which the integrated LC element is embedded; <17> The mounting structure according to claim 1.

[0164] <19> A power management IC is disposed on the surface of the resin layer. <18> The mounting structure according to claim 1.

[0165] <20> The interposer is composed only of the integrated LC element. <17> The mounting structure according to claim 1.

[0166] <21> the integrated LC element further includes a power management IC electrically connected to the inductor portion on a surface of the inductor layer opposite to the capacitor layer. <20> The mounting structure according to claim 1.

[0167] <22> a memory disposed on a main surface of the interposer that is closer to the capacitor layer; the redistribution layer of the integrated LC element extends to a position overlapping both the processor and the memory in the thickness direction; The power management IC is located inside the processor. <18> or <20> The mounting structure according to claim 1. [Explanation of symbols]

[0168] 1, 1A, 2, 2A, 3 Integrated LC element 10 Capacitor Layer 10a 1st page 10b 2nd side 11 Anode 12 Cathode 15 Redistribution layer 20 Redistribution layer 30 inductor layer 31 Magnetic layer 32 Coil conductor 41 First external terminal 42 Second external terminal 43 Third external terminal 50 Porous layer 50a top 50b Bottom side 50c Inner surface of groove 60 Conductor Layer 65 Insulating layer 70 MIM structure 71 1st metal layer 72 Second metal layer 73 Dielectric Layer 80 Extraction electrode 100, 100A, 100B mounting structure 110, 110A, 110B Integrated LC element 120 resin layer BD Bridge Die BP Bump BP1 First Bump BP2 2nd Bump CAP, CAP1 capacitor section CR support member EC electronic parts GND Ground Load Load IND, IND1, IND2, IND3 inductor section INS1 First insulation section INS2 Second insulation section INS3 3rd insulation section IP Interposer MEM memory PMIC Power Management Integrated Circuit PROC Processor PS package substrate SBT base material ST base material part V1 First via conductor V2 Second via conductor V3 Third via conductor V4 Fourth via conductor V5 Fifth via conductor V6 6th via conductor V7 7th via conductor VR Voltage Regulator WR wiring section

Claims

1. a capacitor layer having a first surface and a second surface opposed to each other in a thickness direction; a redistribution layer provided on the first surface of the capacitor layer; an inductor layer provided on the second surface of the capacitor layer, the capacitor layer includes a capacitor portion having an anode and a cathode, a first insulating portion provided around the capacitor portion, and a first via conductor portion penetrating the first insulating portion in the thickness direction at a position spaced from the capacitor portion in a plane direction perpendicular to the thickness direction, the redistribution layer includes a wiring portion and a second insulating portion provided around the wiring portion; the inductor layer includes an inductor portion and a third insulating portion provided around the inductor portion; the inductor portion is electrically connected to an anode of the capacitor portion located on the first surface of the capacitor layer through the first via conductor portion and the wiring portion; the capacitor section has an MIM structure of a metal layer-dielectric layer-metal layer, The MIM structure is provided on a porous layer. Integrated LC element.

2. the porous layer has a groove portion extending in the thickness direction, 2. The integrated LC element according to claim 1, wherein the MIM structure is provided on an inner surface of the groove.

3. a capacitor layer having a first surface and a second surface opposed to each other in a thickness direction; a redistribution layer provided on the first surface of the capacitor layer; an inductor layer provided on the second surface of the capacitor layer, the capacitor layer includes a capacitor portion having an anode and a cathode, a first insulating portion provided around the capacitor portion, and a first via conductor portion penetrating the first insulating portion in the thickness direction at a position spaced from the capacitor portion in a plane direction perpendicular to the thickness direction, the redistribution layer includes a wiring portion and a second insulating portion provided around the wiring portion; the inductor layer includes an inductor portion and a third insulating portion provided around the inductor portion; the inductor portion is electrically connected to an anode of the capacitor portion located on the first surface of the capacitor layer through the first via conductor portion and the wiring portion; the inductor layer further includes a second via conductor portion that penetrates the third insulating portion in the thickness direction between the inductor portion and the first via conductor portion; the inductor portion is electrically connected to the first via conductor portion through the second via conductor portion; In a cross section along the thickness direction, a center line of the second via conductor portion is misaligned with a center line of the first via conductor portion. Integrated LC element.

4. a capacitor layer having a first surface and a second surface opposed to each other in a thickness direction; a redistribution layer provided on the first surface of the capacitor layer; an inductor layer provided on the second surface of the capacitor layer, the capacitor layer includes a capacitor portion having an anode and a cathode, a first insulating portion provided around the capacitor portion, and a first via conductor portion penetrating the first insulating portion in the thickness direction at a position spaced from the capacitor portion in a plane direction perpendicular to the thickness direction, the redistribution layer includes a wiring portion and a second insulating portion provided around the wiring portion; the inductor layer includes an inductor portion and a third insulating portion provided around the inductor portion; the inductor portion is electrically connected to an anode of the capacitor portion located on the first surface of the capacitor layer through the first via conductor portion and the wiring portion; a power management IC electrically connected to the inductor portion on a surface of the inductor layer opposite to the capacitor layer; Integrated LC element.

5. 5. The integrated LC element according to claim 1, wherein the third insulating section includes one insulating layer between the capacitor section and the inductor section.

6. 5. The integrated LC element according to claim 1, wherein the inductor portion includes a coil conductor and a magnetic layer extending along the surface direction.

7. 7. The integrated LC element according to claim 6, wherein the magnetic layer is wound with the coil conductor when viewed from the plane direction.

8. 7. The integrated LC element according to claim 6, wherein the magnetic layer is surrounded by the coil conductor when viewed in the thickness direction.

9. 7. The integrated LC element of claim 6, wherein the magnetic layer surrounds the coil conductor.

10. 7. The integrated LC element according to claim 6, wherein the inductor section includes two or more magnetic layers in the thickness direction, the plane direction, or both.

11. 5. The integrated LC element according to claim 1, wherein the third insulating portion is made of an inorganic material containing Si elements.

12. the capacitor layer further includes a substrate portion provided on the second surface so as to cover the capacitor portion, the first insulating portion, and the first via conductor portion, and a third via conductor portion penetrating the substrate portion in the thickness direction between the inductor portion and the first via conductor portion, 5. The integrated LC element according to claim 1, wherein the inductor portion is electrically connected to the first via conductor portion through the third via conductor portion.

13. The integrated LC element according to claim 12 , wherein the substrate portion is provided with another redistribution layer between the third via conductor portion and the inductor portion.

14. An interposer including the integrated LC element according to any one of claims 1 to 4; a package substrate disposed on a main surface of the interposer that is closer to the inductor layer; a processor disposed on a main surface of the interposer that is closer to the capacitor layer; the integrated LC element is positioned so as to overlap the processor in the thickness direction; Implementation structure.

15. The mounting structure of claim 14 , wherein the interposer further includes a resin layer in which the integrated LC element is embedded.

16. The mounting structure according to claim 15 , wherein a power management IC is disposed on the surface of the resin layer.

17. 15. The mounting structure of claim 14, wherein the interposer is composed solely of the integrated LC element.

18. a memory disposed on a main surface of the interposer that is closer to the capacitor layer; the redistribution layer of the integrated LC element extends to a position overlapping both the processor and the memory in the thickness direction; The mounting structure according to claim 15 , wherein a power management IC is disposed inside the processor.

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